1 /* 2 * This declarations of the PIC16F630 MCU. 3 * 4 * This file is part of the GNU PIC library for SDCC, originally 5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016. 6 * 7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:22:57 UTC. 8 * 9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that 10 * this license covers the code to the compiler and other executables, 11 * but explicitly does not cover any code or objects generated by sdcc. 12 * 13 * For pic device libraries and header files which are derived from 14 * Microchip header (.inc) and linker script (.lkr) files Microchip 15 * requires that "The header files should state that they are only to be 16 * used with authentic Microchip devices" which makes them incompatible 17 * with the GPL. Pic device libraries and header files are located at 18 * non-free/lib and non-free/include directories respectively. 19 * Sdcc should be run with the --use-non-free command line option in 20 * order to include non-free header files and libraries. 21 * 22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc. 23 */ 24 25 #ifndef __PIC16F630_H__ 26 #define __PIC16F630_H__ 27 28 //============================================================================== 29 // 30 // Register Addresses 31 // 32 //============================================================================== 33 34 #ifndef NO_ADDR_DEFINES 35 36 #define INDF_ADDR 0x0000 37 #define TMR0_ADDR 0x0001 38 #define PCL_ADDR 0x0002 39 #define STATUS_ADDR 0x0003 40 #define FSR_ADDR 0x0004 41 #define PORTA_ADDR 0x0005 42 #define PORTC_ADDR 0x0007 43 #define PCLATH_ADDR 0x000A 44 #define INTCON_ADDR 0x000B 45 #define PIR1_ADDR 0x000C 46 #define TMR1_ADDR 0x000E 47 #define TMR1L_ADDR 0x000E 48 #define TMR1H_ADDR 0x000F 49 #define T1CON_ADDR 0x0010 50 #define CMCON_ADDR 0x0019 51 #define OPTION_REG_ADDR 0x0081 52 #define TRISA_ADDR 0x0085 53 #define TRISC_ADDR 0x0087 54 #define PIE1_ADDR 0x008C 55 #define PCON_ADDR 0x008E 56 #define OSCCAL_ADDR 0x0090 57 #define WPU_ADDR 0x0095 58 #define WPUA_ADDR 0x0095 59 #define IOC_ADDR 0x0096 60 #define IOCA_ADDR 0x0096 61 #define VRCON_ADDR 0x0099 62 #define EEDAT_ADDR 0x009A 63 #define EEDATA_ADDR 0x009A 64 #define EEADR_ADDR 0x009B 65 #define EECON1_ADDR 0x009C 66 #define EECON2_ADDR 0x009D 67 68 #endif // #ifndef NO_ADDR_DEFINES 69 70 //============================================================================== 71 // 72 // Register Definitions 73 // 74 //============================================================================== 75 76 extern __at(0x0000) __sfr INDF; 77 extern __at(0x0001) __sfr TMR0; 78 extern __at(0x0002) __sfr PCL; 79 80 //============================================================================== 81 // STATUS Bits 82 83 extern __at(0x0003) __sfr STATUS; 84 85 typedef union 86 { 87 struct 88 { 89 unsigned C : 1; 90 unsigned DC : 1; 91 unsigned Z : 1; 92 unsigned NOT_PD : 1; 93 unsigned NOT_TO : 1; 94 unsigned RP0 : 1; 95 unsigned RP1 : 1; 96 unsigned IRP : 1; 97 }; 98 99 struct 100 { 101 unsigned : 5; 102 unsigned RP : 2; 103 unsigned : 1; 104 }; 105 } __STATUSbits_t; 106 107 extern __at(0x0003) volatile __STATUSbits_t STATUSbits; 108 109 #define _C 0x01 110 #define _DC 0x02 111 #define _Z 0x04 112 #define _NOT_PD 0x08 113 #define _NOT_TO 0x10 114 #define _RP0 0x20 115 #define _RP1 0x40 116 #define _IRP 0x80 117 118 //============================================================================== 119 120 extern __at(0x0004) __sfr FSR; 121 122 //============================================================================== 123 // PORTA Bits 124 125 extern __at(0x0005) __sfr PORTA; 126 127 typedef union 128 { 129 struct 130 { 131 unsigned RA0 : 1; 132 unsigned RA1 : 1; 133 unsigned RA2 : 1; 134 unsigned RA3 : 1; 135 unsigned RA4 : 1; 136 unsigned RA5 : 1; 137 unsigned : 1; 138 unsigned : 1; 139 }; 140 141 struct 142 { 143 unsigned RA : 6; 144 unsigned : 2; 145 }; 146 } __PORTAbits_t; 147 148 extern __at(0x0005) volatile __PORTAbits_t PORTAbits; 149 150 #define _RA0 0x01 151 #define _RA1 0x02 152 #define _RA2 0x04 153 #define _RA3 0x08 154 #define _RA4 0x10 155 #define _RA5 0x20 156 157 //============================================================================== 158 159 160 //============================================================================== 161 // PORTC Bits 162 163 extern __at(0x0007) __sfr PORTC; 164 165 typedef union 166 { 167 struct 168 { 169 unsigned RC0 : 1; 170 unsigned RC1 : 1; 171 unsigned RC2 : 1; 172 unsigned RC3 : 1; 173 unsigned RC4 : 1; 174 unsigned RC5 : 1; 175 unsigned : 1; 176 unsigned : 1; 177 }; 178 179 struct 180 { 181 unsigned RC : 6; 182 unsigned : 2; 183 }; 184 } __PORTCbits_t; 185 186 extern __at(0x0007) volatile __PORTCbits_t PORTCbits; 187 188 #define _RC0 0x01 189 #define _RC1 0x02 190 #define _RC2 0x04 191 #define _RC3 0x08 192 #define _RC4 0x10 193 #define _RC5 0x20 194 195 //============================================================================== 196 197 extern __at(0x000A) __sfr PCLATH; 198 199 //============================================================================== 200 // INTCON Bits 201 202 extern __at(0x000B) __sfr INTCON; 203 204 typedef union 205 { 206 struct 207 { 208 unsigned RAIF : 1; 209 unsigned INTF : 1; 210 unsigned T0IF : 1; 211 unsigned RAIE : 1; 212 unsigned INTE : 1; 213 unsigned T0IE : 1; 214 unsigned PEIE : 1; 215 unsigned GIE : 1; 216 }; 217 218 struct 219 { 220 unsigned : 1; 221 unsigned : 1; 222 unsigned TMR0IF : 1; 223 unsigned : 1; 224 unsigned : 1; 225 unsigned TMR0IE : 1; 226 unsigned : 1; 227 unsigned : 1; 228 }; 229 } __INTCONbits_t; 230 231 extern __at(0x000B) volatile __INTCONbits_t INTCONbits; 232 233 #define _RAIF 0x01 234 #define _INTF 0x02 235 #define _T0IF 0x04 236 #define _TMR0IF 0x04 237 #define _RAIE 0x08 238 #define _INTE 0x10 239 #define _T0IE 0x20 240 #define _TMR0IE 0x20 241 #define _PEIE 0x40 242 #define _GIE 0x80 243 244 //============================================================================== 245 246 247 //============================================================================== 248 // PIR1 Bits 249 250 extern __at(0x000C) __sfr PIR1; 251 252 typedef union 253 { 254 struct 255 { 256 unsigned TMR1IF : 1; 257 unsigned : 1; 258 unsigned : 1; 259 unsigned CMIF : 1; 260 unsigned : 1; 261 unsigned : 1; 262 unsigned : 1; 263 unsigned EEIF : 1; 264 }; 265 266 struct 267 { 268 unsigned T1IF : 1; 269 unsigned : 1; 270 unsigned : 1; 271 unsigned : 1; 272 unsigned : 1; 273 unsigned : 1; 274 unsigned : 1; 275 unsigned : 1; 276 }; 277 } __PIR1bits_t; 278 279 extern __at(0x000C) volatile __PIR1bits_t PIR1bits; 280 281 #define _TMR1IF 0x01 282 #define _T1IF 0x01 283 #define _CMIF 0x08 284 #define _EEIF 0x80 285 286 //============================================================================== 287 288 extern __at(0x000E) __sfr TMR1; 289 extern __at(0x000E) __sfr TMR1L; 290 extern __at(0x000F) __sfr TMR1H; 291 292 //============================================================================== 293 // T1CON Bits 294 295 extern __at(0x0010) __sfr T1CON; 296 297 typedef union 298 { 299 struct 300 { 301 unsigned TMR1ON : 1; 302 unsigned TMR1CS : 1; 303 unsigned NOT_T1SYNC : 1; 304 unsigned T1OSCEN : 1; 305 unsigned T1CKPS0 : 1; 306 unsigned T1CKPS1 : 1; 307 unsigned TMR1GE : 1; 308 unsigned : 1; 309 }; 310 311 struct 312 { 313 unsigned : 4; 314 unsigned T1CKPS : 2; 315 unsigned : 2; 316 }; 317 } __T1CONbits_t; 318 319 extern __at(0x0010) volatile __T1CONbits_t T1CONbits; 320 321 #define _TMR1ON 0x01 322 #define _TMR1CS 0x02 323 #define _NOT_T1SYNC 0x04 324 #define _T1OSCEN 0x08 325 #define _T1CKPS0 0x10 326 #define _T1CKPS1 0x20 327 #define _TMR1GE 0x40 328 329 //============================================================================== 330 331 332 //============================================================================== 333 // CMCON Bits 334 335 extern __at(0x0019) __sfr CMCON; 336 337 typedef union 338 { 339 struct 340 { 341 unsigned CM0 : 1; 342 unsigned CM1 : 1; 343 unsigned CM2 : 1; 344 unsigned CIS : 1; 345 unsigned CINV : 1; 346 unsigned : 1; 347 unsigned COUT : 1; 348 unsigned : 1; 349 }; 350 351 struct 352 { 353 unsigned CM : 3; 354 unsigned : 5; 355 }; 356 } __CMCONbits_t; 357 358 extern __at(0x0019) volatile __CMCONbits_t CMCONbits; 359 360 #define _CM0 0x01 361 #define _CM1 0x02 362 #define _CM2 0x04 363 #define _CIS 0x08 364 #define _CINV 0x10 365 #define _COUT 0x40 366 367 //============================================================================== 368 369 370 //============================================================================== 371 // OPTION_REG Bits 372 373 extern __at(0x0081) __sfr OPTION_REG; 374 375 typedef union 376 { 377 struct 378 { 379 unsigned PS0 : 1; 380 unsigned PS1 : 1; 381 unsigned PS2 : 1; 382 unsigned PSA : 1; 383 unsigned T0SE : 1; 384 unsigned T0CS : 1; 385 unsigned INTEDG : 1; 386 unsigned NOT_RAPU : 1; 387 }; 388 389 struct 390 { 391 unsigned : 1; 392 unsigned : 1; 393 unsigned : 1; 394 unsigned : 1; 395 unsigned : 1; 396 unsigned : 1; 397 unsigned : 1; 398 unsigned NOT_GPPU : 1; 399 }; 400 401 struct 402 { 403 unsigned PS : 3; 404 unsigned : 5; 405 }; 406 } __OPTION_REGbits_t; 407 408 extern __at(0x0081) volatile __OPTION_REGbits_t OPTION_REGbits; 409 410 #define _PS0 0x01 411 #define _PS1 0x02 412 #define _PS2 0x04 413 #define _PSA 0x08 414 #define _T0SE 0x10 415 #define _T0CS 0x20 416 #define _INTEDG 0x40 417 #define _NOT_RAPU 0x80 418 #define _NOT_GPPU 0x80 419 420 //============================================================================== 421 422 423 //============================================================================== 424 // TRISA Bits 425 426 extern __at(0x0085) __sfr TRISA; 427 428 typedef union 429 { 430 struct 431 { 432 unsigned TRISA0 : 1; 433 unsigned TRISA1 : 1; 434 unsigned TRISA2 : 1; 435 unsigned TRISA3 : 1; 436 unsigned TRISA4 : 1; 437 unsigned TRISA5 : 1; 438 unsigned : 1; 439 unsigned : 1; 440 }; 441 442 struct 443 { 444 unsigned TRISA : 6; 445 unsigned : 2; 446 }; 447 } __TRISAbits_t; 448 449 extern __at(0x0085) volatile __TRISAbits_t TRISAbits; 450 451 #define _TRISA0 0x01 452 #define _TRISA1 0x02 453 #define _TRISA2 0x04 454 #define _TRISA3 0x08 455 #define _TRISA4 0x10 456 #define _TRISA5 0x20 457 458 //============================================================================== 459 460 461 //============================================================================== 462 // TRISC Bits 463 464 extern __at(0x0087) __sfr TRISC; 465 466 typedef union 467 { 468 struct 469 { 470 unsigned TRISC0 : 1; 471 unsigned TRISC1 : 1; 472 unsigned TRISC2 : 1; 473 unsigned TRISC3 : 1; 474 unsigned TRISC4 : 1; 475 unsigned TRISC5 : 1; 476 unsigned : 1; 477 unsigned : 1; 478 }; 479 480 struct 481 { 482 unsigned TRISC : 6; 483 unsigned : 2; 484 }; 485 } __TRISCbits_t; 486 487 extern __at(0x0087) volatile __TRISCbits_t TRISCbits; 488 489 #define _TRISC0 0x01 490 #define _TRISC1 0x02 491 #define _TRISC2 0x04 492 #define _TRISC3 0x08 493 #define _TRISC4 0x10 494 #define _TRISC5 0x20 495 496 //============================================================================== 497 498 499 //============================================================================== 500 // PIE1 Bits 501 502 extern __at(0x008C) __sfr PIE1; 503 504 typedef union 505 { 506 struct 507 { 508 unsigned TMR1IE : 1; 509 unsigned : 1; 510 unsigned : 1; 511 unsigned CMIE : 1; 512 unsigned : 1; 513 unsigned : 1; 514 unsigned : 1; 515 unsigned EEIE : 1; 516 }; 517 518 struct 519 { 520 unsigned T1IE : 1; 521 unsigned : 1; 522 unsigned : 1; 523 unsigned : 1; 524 unsigned : 1; 525 unsigned : 1; 526 unsigned : 1; 527 unsigned : 1; 528 }; 529 } __PIE1bits_t; 530 531 extern __at(0x008C) volatile __PIE1bits_t PIE1bits; 532 533 #define _TMR1IE 0x01 534 #define _T1IE 0x01 535 #define _CMIE 0x08 536 #define _EEIE 0x80 537 538 //============================================================================== 539 540 541 //============================================================================== 542 // PCON Bits 543 544 extern __at(0x008E) __sfr PCON; 545 546 typedef union 547 { 548 struct 549 { 550 unsigned NOT_BOR : 1; 551 unsigned NOT_POR : 1; 552 unsigned : 1; 553 unsigned : 1; 554 unsigned : 1; 555 unsigned : 1; 556 unsigned : 1; 557 unsigned : 1; 558 }; 559 560 struct 561 { 562 unsigned NOT_BOD : 1; 563 unsigned : 1; 564 unsigned : 1; 565 unsigned : 1; 566 unsigned : 1; 567 unsigned : 1; 568 unsigned : 1; 569 unsigned : 1; 570 }; 571 } __PCONbits_t; 572 573 extern __at(0x008E) volatile __PCONbits_t PCONbits; 574 575 #define _NOT_BOR 0x01 576 #define _NOT_BOD 0x01 577 #define _NOT_POR 0x02 578 579 //============================================================================== 580 581 582 //============================================================================== 583 // OSCCAL Bits 584 585 extern __at(0x0090) __sfr OSCCAL; 586 587 typedef union 588 { 589 struct 590 { 591 unsigned : 1; 592 unsigned : 1; 593 unsigned CAL0 : 1; 594 unsigned CAL1 : 1; 595 unsigned CAL2 : 1; 596 unsigned CAL3 : 1; 597 unsigned CAL4 : 1; 598 unsigned CAL5 : 1; 599 }; 600 601 struct 602 { 603 unsigned : 2; 604 unsigned CAL : 6; 605 }; 606 } __OSCCALbits_t; 607 608 extern __at(0x0090) volatile __OSCCALbits_t OSCCALbits; 609 610 #define _CAL0 0x04 611 #define _CAL1 0x08 612 #define _CAL2 0x10 613 #define _CAL3 0x20 614 #define _CAL4 0x40 615 #define _CAL5 0x80 616 617 //============================================================================== 618 619 620 //============================================================================== 621 // WPU Bits 622 623 extern __at(0x0095) __sfr WPU; 624 625 typedef struct 626 { 627 unsigned WPUA0 : 1; 628 unsigned WPUA1 : 1; 629 unsigned WPUA2 : 1; 630 unsigned : 1; 631 unsigned WPUA4 : 1; 632 unsigned WPUA5 : 1; 633 unsigned : 1; 634 unsigned : 1; 635 } __WPUbits_t; 636 637 extern __at(0x0095) volatile __WPUbits_t WPUbits; 638 639 #define _WPUA0 0x01 640 #define _WPUA1 0x02 641 #define _WPUA2 0x04 642 #define _WPUA4 0x10 643 #define _WPUA5 0x20 644 645 //============================================================================== 646 647 648 //============================================================================== 649 // WPUA Bits 650 651 extern __at(0x0095) __sfr WPUA; 652 653 typedef struct 654 { 655 unsigned WPUA0 : 1; 656 unsigned WPUA1 : 1; 657 unsigned WPUA2 : 1; 658 unsigned : 1; 659 unsigned WPUA4 : 1; 660 unsigned WPUA5 : 1; 661 unsigned : 1; 662 unsigned : 1; 663 } __WPUAbits_t; 664 665 extern __at(0x0095) volatile __WPUAbits_t WPUAbits; 666 667 #define _WPUA_WPUA0 0x01 668 #define _WPUA_WPUA1 0x02 669 #define _WPUA_WPUA2 0x04 670 #define _WPUA_WPUA4 0x10 671 #define _WPUA_WPUA5 0x20 672 673 //============================================================================== 674 675 676 //============================================================================== 677 // IOC Bits 678 679 extern __at(0x0096) __sfr IOC; 680 681 typedef union 682 { 683 struct 684 { 685 unsigned IOCA0 : 1; 686 unsigned IOCA1 : 1; 687 unsigned IOCA2 : 1; 688 unsigned IOCA3 : 1; 689 unsigned IOCA4 : 1; 690 unsigned IOCA5 : 1; 691 unsigned : 1; 692 unsigned : 1; 693 }; 694 695 struct 696 { 697 unsigned IOCA : 6; 698 unsigned : 2; 699 }; 700 } __IOCbits_t; 701 702 extern __at(0x0096) volatile __IOCbits_t IOCbits; 703 704 #define _IOCA0 0x01 705 #define _IOCA1 0x02 706 #define _IOCA2 0x04 707 #define _IOCA3 0x08 708 #define _IOCA4 0x10 709 #define _IOCA5 0x20 710 711 //============================================================================== 712 713 714 //============================================================================== 715 // IOCA Bits 716 717 extern __at(0x0096) __sfr IOCA; 718 719 typedef union 720 { 721 struct 722 { 723 unsigned IOCA0 : 1; 724 unsigned IOCA1 : 1; 725 unsigned IOCA2 : 1; 726 unsigned IOCA3 : 1; 727 unsigned IOCA4 : 1; 728 unsigned IOCA5 : 1; 729 unsigned : 1; 730 unsigned : 1; 731 }; 732 733 struct 734 { 735 unsigned IOCA : 6; 736 unsigned : 2; 737 }; 738 } __IOCAbits_t; 739 740 extern __at(0x0096) volatile __IOCAbits_t IOCAbits; 741 742 #define _IOCA_IOCA0 0x01 743 #define _IOCA_IOCA1 0x02 744 #define _IOCA_IOCA2 0x04 745 #define _IOCA_IOCA3 0x08 746 #define _IOCA_IOCA4 0x10 747 #define _IOCA_IOCA5 0x20 748 749 //============================================================================== 750 751 752 //============================================================================== 753 // VRCON Bits 754 755 extern __at(0x0099) __sfr VRCON; 756 757 typedef union 758 { 759 struct 760 { 761 unsigned VR0 : 1; 762 unsigned VR1 : 1; 763 unsigned VR2 : 1; 764 unsigned VR3 : 1; 765 unsigned : 1; 766 unsigned VRR : 1; 767 unsigned : 1; 768 unsigned VREN : 1; 769 }; 770 771 struct 772 { 773 unsigned VR : 4; 774 unsigned : 4; 775 }; 776 } __VRCONbits_t; 777 778 extern __at(0x0099) volatile __VRCONbits_t VRCONbits; 779 780 #define _VR0 0x01 781 #define _VR1 0x02 782 #define _VR2 0x04 783 #define _VR3 0x08 784 #define _VRR 0x20 785 #define _VREN 0x80 786 787 //============================================================================== 788 789 extern __at(0x009A) __sfr EEDAT; 790 extern __at(0x009A) __sfr EEDATA; 791 extern __at(0x009B) __sfr EEADR; 792 793 //============================================================================== 794 // EECON1 Bits 795 796 extern __at(0x009C) __sfr EECON1; 797 798 typedef struct 799 { 800 unsigned RD : 1; 801 unsigned WR : 1; 802 unsigned WREN : 1; 803 unsigned WRERR : 1; 804 unsigned : 1; 805 unsigned : 1; 806 unsigned : 1; 807 unsigned : 1; 808 } __EECON1bits_t; 809 810 extern __at(0x009C) volatile __EECON1bits_t EECON1bits; 811 812 #define _RD 0x01 813 #define _WR 0x02 814 #define _WREN 0x04 815 #define _WRERR 0x08 816 817 //============================================================================== 818 819 extern __at(0x009D) __sfr EECON2; 820 821 //============================================================================== 822 // 823 // Configuration Bits 824 // 825 //============================================================================== 826 827 #define _CONFIG 0x2007 828 829 //----------------------------- CONFIG Options ------------------------------- 830 831 #define _FOSC_LP 0x3FF8 // LP oscillator: Low power crystal on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN. 832 #define _LP_OSC 0x3FF8 // LP oscillator: Low power crystal on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN. 833 #define _FOSC_XT 0x3FF9 // XT oscillator: Crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN. 834 #define _XT_OSC 0x3FF9 // XT oscillator: Crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN. 835 #define _FOSC_HS 0x3FFA // HS oscillator: High speed crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN. 836 #define _HS_OSC 0x3FFA // HS oscillator: High speed crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN. 837 #define _FOSC_EC 0x3FFB // EC: I/O function on RA4/OSC2/CLKOUT pin, CLKIN on RA5/OSC1/CLKIN. 838 #define _EC_OSC 0x3FFB // EC: I/O function on RA4/OSC2/CLKOUT pin, CLKIN on RA5/OSC1/CLKIN. 839 #define _FOSC_INTRCIO 0x3FFC // INTOSC oscillator: I/O function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN. 840 #define _INTRC_OSC_NOCLKOUT 0x3FFC // INTOSC oscillator: I/O function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN. 841 #define _FOSC_INTRCCLK 0x3FFD // INTOSC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN. 842 #define _INTRC_OSC_CLKOUT 0x3FFD // INTOSC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN. 843 #define _FOSC_EXTRCIO 0x3FFE // RC oscillator: I/O function on RA4/OSC2/CLKOUT pin, RC on RA5/OSC1/CLKIN. 844 #define _EXTRC_OSC_NOCLKOUT 0x3FFE // RC oscillator: I/O function on RA4/OSC2/CLKOUT pin, RC on RA5/OSC1/CLKIN. 845 #define _FOSC_EXTRCCLK 0x3FFF // RC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, RC on RA5/OSC1/CLKIN. 846 #define _EXTRC_OSC_CLKOUT 0x3FFF // RC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, RC on RA5/OSC1/CLKIN. 847 #define _WDTE_OFF 0x3FF7 // WDT disabled. 848 #define _WDT_OFF 0x3FF7 // WDT disabled. 849 #define _WDTE_ON 0x3FFF // WDT enabled. 850 #define _WDT_ON 0x3FFF // WDT enabled. 851 #define _PWRTE_ON 0x3FEF // PWRT enabled. 852 #define _PWRTE_OFF 0x3FFF // PWRT disabled. 853 #define _MCLRE_OFF 0x3FDF // RA3/MCLR pin function is digital I/O, MCLR internally tied to VDD. 854 #define _MCLRE_ON 0x3FFF // RA3/MCLR pin function is MCLR. 855 #define _BOREN_OFF 0x3FBF // BOD disabled. 856 #define _BODEN_OFF 0x3FBF // BOD disabled. 857 #define _BOREN_ON 0x3FFF // BOD enabled. 858 #define _BODEN 0x3FFF // BOD enabled. 859 #define _CP_ON 0x3F7F // Program Memory code protection is enabled. 860 #define _CP 0x3F7F // Program Memory code protection is enabled. 861 #define _CP_OFF 0x3FFF // Program Memory code protection is disabled. 862 #define _CPD_ON 0x3EFF // Data memory code protection is enabled. 863 #define _CPD 0x3EFF // Data memory code protection is enabled. 864 #define _CPD_OFF 0x3FFF // Data memory code protection is disabled. 865 866 //============================================================================== 867 868 #define _DEVID1 0x2006 869 870 #define _IDLOC0 0x2000 871 #define _IDLOC1 0x2001 872 #define _IDLOC2 0x2002 873 #define _IDLOC3 0x2003 874 875 //============================================================================== 876 877 #ifndef NO_BIT_DEFINES 878 879 #define CM0 CMCONbits.CM0 // bit 0 880 #define CM1 CMCONbits.CM1 // bit 1 881 #define CM2 CMCONbits.CM2 // bit 2 882 #define CIS CMCONbits.CIS // bit 3 883 #define CINV CMCONbits.CINV // bit 4 884 #define COUT CMCONbits.COUT // bit 6 885 886 #define RD EECON1bits.RD // bit 0 887 #define WR EECON1bits.WR // bit 1 888 #define WREN EECON1bits.WREN // bit 2 889 #define WRERR EECON1bits.WRERR // bit 3 890 891 #define RAIF INTCONbits.RAIF // bit 0 892 #define INTF INTCONbits.INTF // bit 1 893 #define T0IF INTCONbits.T0IF // bit 2, shadows bit in INTCONbits 894 #define TMR0IF INTCONbits.TMR0IF // bit 2, shadows bit in INTCONbits 895 #define RAIE INTCONbits.RAIE // bit 3 896 #define INTE INTCONbits.INTE // bit 4 897 #define T0IE INTCONbits.T0IE // bit 5, shadows bit in INTCONbits 898 #define TMR0IE INTCONbits.TMR0IE // bit 5, shadows bit in INTCONbits 899 #define PEIE INTCONbits.PEIE // bit 6 900 #define GIE INTCONbits.GIE // bit 7 901 902 #define IOCA0 IOCbits.IOCA0 // bit 0 903 #define IOCA1 IOCbits.IOCA1 // bit 1 904 #define IOCA2 IOCbits.IOCA2 // bit 2 905 #define IOCA3 IOCbits.IOCA3 // bit 3 906 #define IOCA4 IOCbits.IOCA4 // bit 4 907 #define IOCA5 IOCbits.IOCA5 // bit 5 908 909 #define PS0 OPTION_REGbits.PS0 // bit 0 910 #define PS1 OPTION_REGbits.PS1 // bit 1 911 #define PS2 OPTION_REGbits.PS2 // bit 2 912 #define PSA OPTION_REGbits.PSA // bit 3 913 #define T0SE OPTION_REGbits.T0SE // bit 4 914 #define T0CS OPTION_REGbits.T0CS // bit 5 915 #define INTEDG OPTION_REGbits.INTEDG // bit 6 916 #define NOT_RAPU OPTION_REGbits.NOT_RAPU // bit 7, shadows bit in OPTION_REGbits 917 #define NOT_GPPU OPTION_REGbits.NOT_GPPU // bit 7, shadows bit in OPTION_REGbits 918 919 #define CAL0 OSCCALbits.CAL0 // bit 2 920 #define CAL1 OSCCALbits.CAL1 // bit 3 921 #define CAL2 OSCCALbits.CAL2 // bit 4 922 #define CAL3 OSCCALbits.CAL3 // bit 5 923 #define CAL4 OSCCALbits.CAL4 // bit 6 924 #define CAL5 OSCCALbits.CAL5 // bit 7 925 926 #define NOT_BOR PCONbits.NOT_BOR // bit 0, shadows bit in PCONbits 927 #define NOT_BOD PCONbits.NOT_BOD // bit 0, shadows bit in PCONbits 928 #define NOT_POR PCONbits.NOT_POR // bit 1 929 930 #define TMR1IE PIE1bits.TMR1IE // bit 0, shadows bit in PIE1bits 931 #define T1IE PIE1bits.T1IE // bit 0, shadows bit in PIE1bits 932 #define CMIE PIE1bits.CMIE // bit 3 933 #define EEIE PIE1bits.EEIE // bit 7 934 935 #define TMR1IF PIR1bits.TMR1IF // bit 0, shadows bit in PIR1bits 936 #define T1IF PIR1bits.T1IF // bit 0, shadows bit in PIR1bits 937 #define CMIF PIR1bits.CMIF // bit 3 938 #define EEIF PIR1bits.EEIF // bit 7 939 940 #define RA0 PORTAbits.RA0 // bit 0 941 #define RA1 PORTAbits.RA1 // bit 1 942 #define RA2 PORTAbits.RA2 // bit 2 943 #define RA3 PORTAbits.RA3 // bit 3 944 #define RA4 PORTAbits.RA4 // bit 4 945 #define RA5 PORTAbits.RA5 // bit 5 946 947 #define RC0 PORTCbits.RC0 // bit 0 948 #define RC1 PORTCbits.RC1 // bit 1 949 #define RC2 PORTCbits.RC2 // bit 2 950 #define RC3 PORTCbits.RC3 // bit 3 951 #define RC4 PORTCbits.RC4 // bit 4 952 #define RC5 PORTCbits.RC5 // bit 5 953 954 #define C STATUSbits.C // bit 0 955 #define DC STATUSbits.DC // bit 1 956 #define Z STATUSbits.Z // bit 2 957 #define NOT_PD STATUSbits.NOT_PD // bit 3 958 #define NOT_TO STATUSbits.NOT_TO // bit 4 959 #define RP0 STATUSbits.RP0 // bit 5 960 #define RP1 STATUSbits.RP1 // bit 6 961 #define IRP STATUSbits.IRP // bit 7 962 963 #define TMR1ON T1CONbits.TMR1ON // bit 0 964 #define TMR1CS T1CONbits.TMR1CS // bit 1 965 #define NOT_T1SYNC T1CONbits.NOT_T1SYNC // bit 2 966 #define T1OSCEN T1CONbits.T1OSCEN // bit 3 967 #define T1CKPS0 T1CONbits.T1CKPS0 // bit 4 968 #define T1CKPS1 T1CONbits.T1CKPS1 // bit 5 969 #define TMR1GE T1CONbits.TMR1GE // bit 6 970 971 #define TRISA0 TRISAbits.TRISA0 // bit 0 972 #define TRISA1 TRISAbits.TRISA1 // bit 1 973 #define TRISA2 TRISAbits.TRISA2 // bit 2 974 #define TRISA3 TRISAbits.TRISA3 // bit 3 975 #define TRISA4 TRISAbits.TRISA4 // bit 4 976 #define TRISA5 TRISAbits.TRISA5 // bit 5 977 978 #define TRISC0 TRISCbits.TRISC0 // bit 0 979 #define TRISC1 TRISCbits.TRISC1 // bit 1 980 #define TRISC2 TRISCbits.TRISC2 // bit 2 981 #define TRISC3 TRISCbits.TRISC3 // bit 3 982 #define TRISC4 TRISCbits.TRISC4 // bit 4 983 #define TRISC5 TRISCbits.TRISC5 // bit 5 984 985 #define VR0 VRCONbits.VR0 // bit 0 986 #define VR1 VRCONbits.VR1 // bit 1 987 #define VR2 VRCONbits.VR2 // bit 2 988 #define VR3 VRCONbits.VR3 // bit 3 989 #define VRR VRCONbits.VRR // bit 5 990 #define VREN VRCONbits.VREN // bit 7 991 992 #define WPUA0 WPUbits.WPUA0 // bit 0 993 #define WPUA1 WPUbits.WPUA1 // bit 1 994 #define WPUA2 WPUbits.WPUA2 // bit 2 995 #define WPUA4 WPUbits.WPUA4 // bit 4 996 #define WPUA5 WPUbits.WPUA5 // bit 5 997 998 #endif // #ifndef NO_BIT_DEFINES 999 1000 #endif // #ifndef __PIC16F630_H__ 1001