1 /* 2 * This definitions of the PIC18F8490 MCU. 3 * 4 * This file is part of the GNU PIC library for SDCC, originally 5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016. 6 * 7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:51 UTC. 8 * 9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that 10 * this license covers the code to the compiler and other executables, 11 * but explicitly does not cover any code or objects generated by sdcc. 12 * 13 * For pic device libraries and header files which are derived from 14 * Microchip header (.inc) and linker script (.lkr) files Microchip 15 * requires that "The header files should state that they are only to be 16 * used with authentic Microchip devices" which makes them incompatible 17 * with the GPL. Pic device libraries and header files are located at 18 * non-free/lib and non-free/include directories respectively. 19 * Sdcc should be run with the --use-non-free command line option in 20 * order to include non-free header files and libraries. 21 * 22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc. 23 */ 24 25 #include <pic18f8490.h> 26 27 //============================================================================== 28 29 __at(0x0F58) __sfr LCDPS; 30 __at(0x0F58) volatile __LCDPSbits_t LCDPSbits; 31 32 __at(0x0F59) __sfr LCDCON; 33 __at(0x0F59) volatile __LCDCONbits_t LCDCONbits; 34 35 __at(0x0F5A) __sfr LCDSE0; 36 __at(0x0F5A) volatile __LCDSE0bits_t LCDSE0bits; 37 38 __at(0x0F5B) __sfr LCDSE1; 39 __at(0x0F5B) volatile __LCDSE1bits_t LCDSE1bits; 40 41 __at(0x0F5C) __sfr LCDSE2; 42 __at(0x0F5C) volatile __LCDSE2bits_t LCDSE2bits; 43 44 __at(0x0F5D) __sfr LCDSE3; 45 __at(0x0F5D) volatile __LCDSE3bits_t LCDSE3bits; 46 47 __at(0x0F5E) __sfr LCDSE4; 48 __at(0x0F5E) volatile __LCDSE4bits_t LCDSE4bits; 49 50 __at(0x0F5F) __sfr LCDSE5; 51 __at(0x0F5F) volatile __LCDSE5bits_t LCDSE5bits; 52 53 __at(0x0F60) __sfr LCDDATA0; 54 __at(0x0F60) volatile __LCDDATA0bits_t LCDDATA0bits; 55 56 __at(0x0F61) __sfr LCDDATA1; 57 __at(0x0F61) volatile __LCDDATA1bits_t LCDDATA1bits; 58 59 __at(0x0F62) __sfr LCDDATA2; 60 __at(0x0F62) volatile __LCDDATA2bits_t LCDDATA2bits; 61 62 __at(0x0F63) __sfr LCDDATA3; 63 __at(0x0F63) volatile __LCDDATA3bits_t LCDDATA3bits; 64 65 __at(0x0F64) __sfr LCDDATA4; 66 __at(0x0F64) volatile __LCDDATA4bits_t LCDDATA4bits; 67 68 __at(0x0F65) __sfr LCDDATA5; 69 __at(0x0F65) volatile __LCDDATA5bits_t LCDDATA5bits; 70 71 __at(0x0F66) __sfr LCDDATA6; 72 __at(0x0F66) volatile __LCDDATA6bits_t LCDDATA6bits; 73 74 __at(0x0F67) __sfr LCDDATA7; 75 __at(0x0F67) volatile __LCDDATA7bits_t LCDDATA7bits; 76 77 __at(0x0F68) __sfr LCDDATA8; 78 __at(0x0F68) volatile __LCDDATA8bits_t LCDDATA8bits; 79 80 __at(0x0F69) __sfr LCDDATA9; 81 __at(0x0F69) volatile __LCDDATA9bits_t LCDDATA9bits; 82 83 __at(0x0F6A) __sfr LCDDATA10; 84 __at(0x0F6A) volatile __LCDDATA10bits_t LCDDATA10bits; 85 86 __at(0x0F6B) __sfr RCSTA2; 87 __at(0x0F6B) volatile __RCSTA2bits_t RCSTA2bits; 88 89 __at(0x0F6C) __sfr TXSTA2; 90 __at(0x0F6C) volatile __TXSTA2bits_t TXSTA2bits; 91 92 __at(0x0F6D) __sfr TXREG2; 93 94 __at(0x0F6E) __sfr RCREG2; 95 96 __at(0x0F6F) __sfr SPBRG2; 97 98 __at(0x0F70) __sfr LCDDATA11; 99 __at(0x0F70) volatile __LCDDATA11bits_t LCDDATA11bits; 100 101 __at(0x0F71) __sfr LCDDATA12; 102 __at(0x0F71) volatile __LCDDATA12bits_t LCDDATA12bits; 103 104 __at(0x0F72) __sfr LCDDATA13; 105 __at(0x0F72) volatile __LCDDATA13bits_t LCDDATA13bits; 106 107 __at(0x0F73) __sfr LCDDATA14; 108 __at(0x0F73) volatile __LCDDATA14bits_t LCDDATA14bits; 109 110 __at(0x0F74) __sfr LCDDATA15; 111 __at(0x0F74) volatile __LCDDATA15bits_t LCDDATA15bits; 112 113 __at(0x0F75) __sfr LCDDATA16; 114 __at(0x0F75) volatile __LCDDATA16bits_t LCDDATA16bits; 115 116 __at(0x0F76) __sfr LCDDATA17; 117 __at(0x0F76) volatile __LCDDATA17bits_t LCDDATA17bits; 118 119 __at(0x0F77) __sfr LCDDATA18; 120 __at(0x0F77) volatile __LCDDATA18bits_t LCDDATA18bits; 121 122 __at(0x0F78) __sfr LCDDATA19; 123 __at(0x0F78) volatile __LCDDATA19bits_t LCDDATA19bits; 124 125 __at(0x0F79) __sfr LCDDATA20; 126 __at(0x0F79) volatile __LCDDATA20bits_t LCDDATA20bits; 127 128 __at(0x0F7A) __sfr LCDDATA21; 129 __at(0x0F7A) volatile __LCDDATA21bits_t LCDDATA21bits; 130 131 __at(0x0F7B) __sfr LCDDATA22; 132 __at(0x0F7B) volatile __LCDDATA22bits_t LCDDATA22bits; 133 134 __at(0x0F7C) __sfr LCDDATA23; 135 __at(0x0F7C) volatile __LCDDATA23bits_t LCDDATA23bits; 136 137 __at(0x0F7E) __sfr BAUDCON1; 138 __at(0x0F7E) volatile __BAUDCON1bits_t BAUDCON1bits; 139 140 __at(0x0F7E) __sfr BAUDCTL1; 141 __at(0x0F7E) volatile __BAUDCTL1bits_t BAUDCTL1bits; 142 143 __at(0x0F7F) __sfr SPBRGH1; 144 145 __at(0x0F80) __sfr PORTA; 146 __at(0x0F80) volatile __PORTAbits_t PORTAbits; 147 148 __at(0x0F81) __sfr PORTB; 149 __at(0x0F81) volatile __PORTBbits_t PORTBbits; 150 151 __at(0x0F82) __sfr PORTC; 152 __at(0x0F82) volatile __PORTCbits_t PORTCbits; 153 154 __at(0x0F83) __sfr PORTD; 155 __at(0x0F83) volatile __PORTDbits_t PORTDbits; 156 157 __at(0x0F84) __sfr PORTE; 158 __at(0x0F84) volatile __PORTEbits_t PORTEbits; 159 160 __at(0x0F85) __sfr PORTF; 161 __at(0x0F85) volatile __PORTFbits_t PORTFbits; 162 163 __at(0x0F86) __sfr PORTG; 164 __at(0x0F86) volatile __PORTGbits_t PORTGbits; 165 166 __at(0x0F87) __sfr PORTH; 167 __at(0x0F87) volatile __PORTHbits_t PORTHbits; 168 169 __at(0x0F88) __sfr PORTJ; 170 __at(0x0F88) volatile __PORTJbits_t PORTJbits; 171 172 __at(0x0F89) __sfr LATA; 173 __at(0x0F89) volatile __LATAbits_t LATAbits; 174 175 __at(0x0F8A) __sfr LATB; 176 __at(0x0F8A) volatile __LATBbits_t LATBbits; 177 178 __at(0x0F8B) __sfr LATC; 179 __at(0x0F8B) volatile __LATCbits_t LATCbits; 180 181 __at(0x0F8C) __sfr LATD; 182 __at(0x0F8C) volatile __LATDbits_t LATDbits; 183 184 __at(0x0F8D) __sfr LATE; 185 __at(0x0F8D) volatile __LATEbits_t LATEbits; 186 187 __at(0x0F8E) __sfr LATF; 188 __at(0x0F8E) volatile __LATFbits_t LATFbits; 189 190 __at(0x0F8F) __sfr LATG; 191 __at(0x0F8F) volatile __LATGbits_t LATGbits; 192 193 __at(0x0F90) __sfr LATH; 194 __at(0x0F90) volatile __LATHbits_t LATHbits; 195 196 __at(0x0F91) __sfr LATJ; 197 __at(0x0F91) volatile __LATJbits_t LATJbits; 198 199 __at(0x0F92) __sfr DDRA; 200 __at(0x0F92) volatile __DDRAbits_t DDRAbits; 201 202 __at(0x0F92) __sfr TRISA; 203 __at(0x0F92) volatile __TRISAbits_t TRISAbits; 204 205 __at(0x0F93) __sfr DDRB; 206 __at(0x0F93) volatile __DDRBbits_t DDRBbits; 207 208 __at(0x0F93) __sfr TRISB; 209 __at(0x0F93) volatile __TRISBbits_t TRISBbits; 210 211 __at(0x0F94) __sfr DDRC; 212 __at(0x0F94) volatile __DDRCbits_t DDRCbits; 213 214 __at(0x0F94) __sfr TRISC; 215 __at(0x0F94) volatile __TRISCbits_t TRISCbits; 216 217 __at(0x0F95) __sfr DDRD; 218 __at(0x0F95) volatile __DDRDbits_t DDRDbits; 219 220 __at(0x0F95) __sfr TRISD; 221 __at(0x0F95) volatile __TRISDbits_t TRISDbits; 222 223 __at(0x0F96) __sfr DDRE; 224 __at(0x0F96) volatile __DDREbits_t DDREbits; 225 226 __at(0x0F96) __sfr TRISE; 227 __at(0x0F96) volatile __TRISEbits_t TRISEbits; 228 229 __at(0x0F97) __sfr DDRF; 230 __at(0x0F97) volatile __DDRFbits_t DDRFbits; 231 232 __at(0x0F97) __sfr TRISF; 233 __at(0x0F97) volatile __TRISFbits_t TRISFbits; 234 235 __at(0x0F98) __sfr DDRG; 236 __at(0x0F98) volatile __DDRGbits_t DDRGbits; 237 238 __at(0x0F98) __sfr TRISG; 239 __at(0x0F98) volatile __TRISGbits_t TRISGbits; 240 241 __at(0x0F99) __sfr DDRH; 242 __at(0x0F99) volatile __DDRHbits_t DDRHbits; 243 244 __at(0x0F99) __sfr TRISH; 245 __at(0x0F99) volatile __TRISHbits_t TRISHbits; 246 247 __at(0x0F9A) __sfr DDRJ; 248 __at(0x0F9A) volatile __DDRJbits_t DDRJbits; 249 250 __at(0x0F9A) __sfr TRISJ; 251 __at(0x0F9A) volatile __TRISJbits_t TRISJbits; 252 253 __at(0x0F9B) __sfr OSCTUNE; 254 __at(0x0F9B) volatile __OSCTUNEbits_t OSCTUNEbits; 255 256 __at(0x0F9C) __sfr MEMCON; 257 __at(0x0F9C) volatile __MEMCONbits_t MEMCONbits; 258 259 __at(0x0F9D) __sfr PIE1; 260 __at(0x0F9D) volatile __PIE1bits_t PIE1bits; 261 262 __at(0x0F9E) __sfr PIR1; 263 __at(0x0F9E) volatile __PIR1bits_t PIR1bits; 264 265 __at(0x0F9F) __sfr IPR1; 266 __at(0x0F9F) volatile __IPR1bits_t IPR1bits; 267 268 __at(0x0FA0) __sfr PIE2; 269 __at(0x0FA0) volatile __PIE2bits_t PIE2bits; 270 271 __at(0x0FA1) __sfr PIR2; 272 __at(0x0FA1) volatile __PIR2bits_t PIR2bits; 273 274 __at(0x0FA2) __sfr IPR2; 275 __at(0x0FA2) volatile __IPR2bits_t IPR2bits; 276 277 __at(0x0FA3) __sfr PIE3; 278 __at(0x0FA3) volatile __PIE3bits_t PIE3bits; 279 280 __at(0x0FA4) __sfr PIR3; 281 __at(0x0FA4) volatile __PIR3bits_t PIR3bits; 282 283 __at(0x0FA5) __sfr IPR3; 284 __at(0x0FA5) volatile __IPR3bits_t IPR3bits; 285 286 __at(0x0FAB) __sfr RCSTA; 287 __at(0x0FAB) volatile __RCSTAbits_t RCSTAbits; 288 289 __at(0x0FAB) __sfr RCSTA1; 290 __at(0x0FAB) volatile __RCSTA1bits_t RCSTA1bits; 291 292 __at(0x0FAC) __sfr TXSTA; 293 __at(0x0FAC) volatile __TXSTAbits_t TXSTAbits; 294 295 __at(0x0FAC) __sfr TXSTA1; 296 __at(0x0FAC) volatile __TXSTA1bits_t TXSTA1bits; 297 298 __at(0x0FAD) __sfr TXREG; 299 300 __at(0x0FAD) __sfr TXREG1; 301 302 __at(0x0FAE) __sfr RCREG; 303 304 __at(0x0FAE) __sfr RCREG1; 305 306 __at(0x0FAF) __sfr SPBRG; 307 308 __at(0x0FAF) __sfr SPBRG1; 309 310 __at(0x0FB1) __sfr T3CON; 311 __at(0x0FB1) volatile __T3CONbits_t T3CONbits; 312 313 __at(0x0FB2) __sfr TMR3; 314 315 __at(0x0FB2) __sfr TMR3L; 316 317 __at(0x0FB3) __sfr TMR3H; 318 319 __at(0x0FB4) __sfr CMCON; 320 __at(0x0FB4) volatile __CMCONbits_t CMCONbits; 321 322 __at(0x0FB5) __sfr CVRCON; 323 __at(0x0FB5) volatile __CVRCONbits_t CVRCONbits; 324 325 __at(0x0FBA) __sfr CCP2CON; 326 __at(0x0FBA) volatile __CCP2CONbits_t CCP2CONbits; 327 328 __at(0x0FBB) __sfr CCPR2; 329 330 __at(0x0FBB) __sfr CCPR2L; 331 332 __at(0x0FBC) __sfr CCPR2H; 333 334 __at(0x0FBD) __sfr CCP1CON; 335 __at(0x0FBD) volatile __CCP1CONbits_t CCP1CONbits; 336 337 __at(0x0FBE) __sfr CCPR1; 338 339 __at(0x0FBE) __sfr CCPR1L; 340 341 __at(0x0FBF) __sfr CCPR1H; 342 343 __at(0x0FC0) __sfr ADCON2; 344 __at(0x0FC0) volatile __ADCON2bits_t ADCON2bits; 345 346 __at(0x0FC1) __sfr ADCON1; 347 __at(0x0FC1) volatile __ADCON1bits_t ADCON1bits; 348 349 __at(0x0FC2) __sfr ADCON0; 350 __at(0x0FC2) volatile __ADCON0bits_t ADCON0bits; 351 352 __at(0x0FC3) __sfr ADRES; 353 354 __at(0x0FC3) __sfr ADRESL; 355 356 __at(0x0FC4) __sfr ADRESH; 357 358 __at(0x0FC5) __sfr SSPCON2; 359 __at(0x0FC5) volatile __SSPCON2bits_t SSPCON2bits; 360 361 __at(0x0FC6) __sfr SSPCON1; 362 __at(0x0FC6) volatile __SSPCON1bits_t SSPCON1bits; 363 364 __at(0x0FC7) __sfr SSPSTAT; 365 __at(0x0FC7) volatile __SSPSTATbits_t SSPSTATbits; 366 367 __at(0x0FC8) __sfr SSPADD; 368 369 __at(0x0FC9) __sfr SSPBUF; 370 371 __at(0x0FCA) __sfr T2CON; 372 __at(0x0FCA) volatile __T2CONbits_t T2CONbits; 373 374 __at(0x0FCB) __sfr PR2; 375 376 __at(0x0FCC) __sfr TMR2; 377 378 __at(0x0FCD) __sfr T1CON; 379 __at(0x0FCD) volatile __T1CONbits_t T1CONbits; 380 381 __at(0x0FCE) __sfr TMR1; 382 383 __at(0x0FCE) __sfr TMR1L; 384 385 __at(0x0FCF) __sfr TMR1H; 386 387 __at(0x0FD0) __sfr RCON; 388 __at(0x0FD0) volatile __RCONbits_t RCONbits; 389 390 __at(0x0FD1) __sfr WDTCON; 391 __at(0x0FD1) volatile __WDTCONbits_t WDTCONbits; 392 393 __at(0x0FD2) __sfr HLVDCON; 394 __at(0x0FD2) volatile __HLVDCONbits_t HLVDCONbits; 395 396 __at(0x0FD2) __sfr LVDCON; 397 __at(0x0FD2) volatile __LVDCONbits_t LVDCONbits; 398 399 __at(0x0FD3) __sfr OSCCON; 400 __at(0x0FD3) volatile __OSCCONbits_t OSCCONbits; 401 402 __at(0x0FD5) __sfr T0CON; 403 __at(0x0FD5) volatile __T0CONbits_t T0CONbits; 404 405 __at(0x0FD6) __sfr TMR0; 406 407 __at(0x0FD6) __sfr TMR0L; 408 409 __at(0x0FD7) __sfr TMR0H; 410 411 __at(0x0FD8) __sfr STATUS; 412 __at(0x0FD8) volatile __STATUSbits_t STATUSbits; 413 414 __at(0x0FD9) __sfr FSR2L; 415 416 __at(0x0FDA) __sfr FSR2H; 417 418 __at(0x0FDB) __sfr PLUSW2; 419 420 __at(0x0FDC) __sfr PREINC2; 421 422 __at(0x0FDD) __sfr POSTDEC2; 423 424 __at(0x0FDE) __sfr POSTINC2; 425 426 __at(0x0FDF) __sfr INDF2; 427 428 __at(0x0FE0) __sfr BSR; 429 430 __at(0x0FE1) __sfr FSR1L; 431 432 __at(0x0FE2) __sfr FSR1H; 433 434 __at(0x0FE3) __sfr PLUSW1; 435 436 __at(0x0FE4) __sfr PREINC1; 437 438 __at(0x0FE5) __sfr POSTDEC1; 439 440 __at(0x0FE6) __sfr POSTINC1; 441 442 __at(0x0FE7) __sfr INDF1; 443 444 __at(0x0FE8) __sfr WREG; 445 446 __at(0x0FE9) __sfr FSR0L; 447 448 __at(0x0FEA) __sfr FSR0H; 449 450 __at(0x0FEB) __sfr PLUSW0; 451 452 __at(0x0FEC) __sfr PREINC0; 453 454 __at(0x0FED) __sfr POSTDEC0; 455 456 __at(0x0FEE) __sfr POSTINC0; 457 458 __at(0x0FEF) __sfr INDF0; 459 460 __at(0x0FF0) __sfr INTCON3; 461 __at(0x0FF0) volatile __INTCON3bits_t INTCON3bits; 462 463 __at(0x0FF1) __sfr INTCON2; 464 __at(0x0FF1) volatile __INTCON2bits_t INTCON2bits; 465 466 __at(0x0FF2) __sfr INTCON; 467 __at(0x0FF2) volatile __INTCONbits_t INTCONbits; 468 469 __at(0x0FF3) __sfr PROD; 470 471 __at(0x0FF3) __sfr PRODL; 472 473 __at(0x0FF4) __sfr PRODH; 474 475 __at(0x0FF5) __sfr TABLAT; 476 477 __at(0x0FF6) __sfr TBLPTR; 478 479 __at(0x0FF6) __sfr TBLPTRL; 480 481 __at(0x0FF7) __sfr TBLPTRH; 482 483 __at(0x0FF8) __sfr TBLPTRU; 484 485 __at(0x0FF9) __sfr PC; 486 487 __at(0x0FF9) __sfr PCL; 488 489 __at(0x0FFA) __sfr PCLATH; 490 491 __at(0x0FFB) __sfr PCLATU; 492 493 __at(0x0FFC) __sfr STKPTR; 494 __at(0x0FFC) volatile __STKPTRbits_t STKPTRbits; 495 496 __at(0x0FFD) __sfr TOS; 497 498 __at(0x0FFD) __sfr TOSL; 499 500 __at(0x0FFE) __sfr TOSH; 501 502 __at(0x0FFF) __sfr TOSU; 503