1 /* 2 * This definitions of the PIC18LF4550 MCU. 3 * 4 * This file is part of the GNU PIC library for SDCC, originally 5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016. 6 * 7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:24:04 UTC. 8 * 9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that 10 * this license covers the code to the compiler and other executables, 11 * but explicitly does not cover any code or objects generated by sdcc. 12 * 13 * For pic device libraries and header files which are derived from 14 * Microchip header (.inc) and linker script (.lkr) files Microchip 15 * requires that "The header files should state that they are only to be 16 * used with authentic Microchip devices" which makes them incompatible 17 * with the GPL. Pic device libraries and header files are located at 18 * non-free/lib and non-free/include directories respectively. 19 * Sdcc should be run with the --use-non-free command line option in 20 * order to include non-free header files and libraries. 21 * 22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc. 23 */ 24 25 #include <pic18lf4550.h> 26 27 //============================================================================== 28 29 __at(0x0F62) __sfr SPPDATA; 30 31 __at(0x0F63) __sfr SPPCFG; 32 __at(0x0F63) volatile __SPPCFGbits_t SPPCFGbits; 33 34 __at(0x0F64) __sfr SPPEPS; 35 __at(0x0F64) volatile __SPPEPSbits_t SPPEPSbits; 36 37 __at(0x0F65) __sfr SPPCON; 38 __at(0x0F65) volatile __SPPCONbits_t SPPCONbits; 39 40 __at(0x0F66) __sfr UFRM; 41 42 __at(0x0F66) __sfr UFRML; 43 __at(0x0F66) volatile __UFRMLbits_t UFRMLbits; 44 45 __at(0x0F67) __sfr UFRMH; 46 __at(0x0F67) volatile __UFRMHbits_t UFRMHbits; 47 48 __at(0x0F68) __sfr UIR; 49 __at(0x0F68) volatile __UIRbits_t UIRbits; 50 51 __at(0x0F69) __sfr UIE; 52 __at(0x0F69) volatile __UIEbits_t UIEbits; 53 54 __at(0x0F6A) __sfr UEIR; 55 __at(0x0F6A) volatile __UEIRbits_t UEIRbits; 56 57 __at(0x0F6B) __sfr UEIE; 58 __at(0x0F6B) volatile __UEIEbits_t UEIEbits; 59 60 __at(0x0F6C) __sfr USTAT; 61 __at(0x0F6C) volatile __USTATbits_t USTATbits; 62 63 __at(0x0F6D) __sfr UCON; 64 __at(0x0F6D) volatile __UCONbits_t UCONbits; 65 66 __at(0x0F6E) __sfr UADDR; 67 __at(0x0F6E) volatile __UADDRbits_t UADDRbits; 68 69 __at(0x0F6F) __sfr UCFG; 70 __at(0x0F6F) volatile __UCFGbits_t UCFGbits; 71 72 __at(0x0F70) __sfr UEP0; 73 __at(0x0F70) volatile __UEP0bits_t UEP0bits; 74 75 __at(0x0F71) __sfr UEP1; 76 __at(0x0F71) volatile __UEP1bits_t UEP1bits; 77 78 __at(0x0F72) __sfr UEP2; 79 __at(0x0F72) volatile __UEP2bits_t UEP2bits; 80 81 __at(0x0F73) __sfr UEP3; 82 __at(0x0F73) volatile __UEP3bits_t UEP3bits; 83 84 __at(0x0F74) __sfr UEP4; 85 __at(0x0F74) volatile __UEP4bits_t UEP4bits; 86 87 __at(0x0F75) __sfr UEP5; 88 __at(0x0F75) volatile __UEP5bits_t UEP5bits; 89 90 __at(0x0F76) __sfr UEP6; 91 __at(0x0F76) volatile __UEP6bits_t UEP6bits; 92 93 __at(0x0F77) __sfr UEP7; 94 __at(0x0F77) volatile __UEP7bits_t UEP7bits; 95 96 __at(0x0F78) __sfr UEP8; 97 __at(0x0F78) volatile __UEP8bits_t UEP8bits; 98 99 __at(0x0F79) __sfr UEP9; 100 __at(0x0F79) volatile __UEP9bits_t UEP9bits; 101 102 __at(0x0F7A) __sfr UEP10; 103 __at(0x0F7A) volatile __UEP10bits_t UEP10bits; 104 105 __at(0x0F7B) __sfr UEP11; 106 __at(0x0F7B) volatile __UEP11bits_t UEP11bits; 107 108 __at(0x0F7C) __sfr UEP12; 109 __at(0x0F7C) volatile __UEP12bits_t UEP12bits; 110 111 __at(0x0F7D) __sfr UEP13; 112 __at(0x0F7D) volatile __UEP13bits_t UEP13bits; 113 114 __at(0x0F7E) __sfr UEP14; 115 __at(0x0F7E) volatile __UEP14bits_t UEP14bits; 116 117 __at(0x0F7F) __sfr UEP15; 118 __at(0x0F7F) volatile __UEP15bits_t UEP15bits; 119 120 __at(0x0F80) __sfr PORTA; 121 __at(0x0F80) volatile __PORTAbits_t PORTAbits; 122 123 __at(0x0F81) __sfr PORTB; 124 __at(0x0F81) volatile __PORTBbits_t PORTBbits; 125 126 __at(0x0F82) __sfr PORTC; 127 __at(0x0F82) volatile __PORTCbits_t PORTCbits; 128 129 __at(0x0F83) __sfr PORTD; 130 __at(0x0F83) volatile __PORTDbits_t PORTDbits; 131 132 __at(0x0F84) __sfr PORTE; 133 __at(0x0F84) volatile __PORTEbits_t PORTEbits; 134 135 __at(0x0F89) __sfr LATA; 136 __at(0x0F89) volatile __LATAbits_t LATAbits; 137 138 __at(0x0F8A) __sfr LATB; 139 __at(0x0F8A) volatile __LATBbits_t LATBbits; 140 141 __at(0x0F8B) __sfr LATC; 142 __at(0x0F8B) volatile __LATCbits_t LATCbits; 143 144 __at(0x0F8C) __sfr LATD; 145 __at(0x0F8C) volatile __LATDbits_t LATDbits; 146 147 __at(0x0F8D) __sfr LATE; 148 __at(0x0F8D) volatile __LATEbits_t LATEbits; 149 150 __at(0x0F92) __sfr DDRA; 151 __at(0x0F92) volatile __DDRAbits_t DDRAbits; 152 153 __at(0x0F92) __sfr TRISA; 154 __at(0x0F92) volatile __TRISAbits_t TRISAbits; 155 156 __at(0x0F93) __sfr DDRB; 157 __at(0x0F93) volatile __DDRBbits_t DDRBbits; 158 159 __at(0x0F93) __sfr TRISB; 160 __at(0x0F93) volatile __TRISBbits_t TRISBbits; 161 162 __at(0x0F94) __sfr DDRC; 163 __at(0x0F94) volatile __DDRCbits_t DDRCbits; 164 165 __at(0x0F94) __sfr TRISC; 166 __at(0x0F94) volatile __TRISCbits_t TRISCbits; 167 168 __at(0x0F95) __sfr DDRD; 169 __at(0x0F95) volatile __DDRDbits_t DDRDbits; 170 171 __at(0x0F95) __sfr TRISD; 172 __at(0x0F95) volatile __TRISDbits_t TRISDbits; 173 174 __at(0x0F96) __sfr DDRE; 175 __at(0x0F96) volatile __DDREbits_t DDREbits; 176 177 __at(0x0F96) __sfr TRISE; 178 __at(0x0F96) volatile __TRISEbits_t TRISEbits; 179 180 __at(0x0F9B) __sfr OSCTUNE; 181 __at(0x0F9B) volatile __OSCTUNEbits_t OSCTUNEbits; 182 183 __at(0x0F9D) __sfr PIE1; 184 __at(0x0F9D) volatile __PIE1bits_t PIE1bits; 185 186 __at(0x0F9E) __sfr PIR1; 187 __at(0x0F9E) volatile __PIR1bits_t PIR1bits; 188 189 __at(0x0F9F) __sfr IPR1; 190 __at(0x0F9F) volatile __IPR1bits_t IPR1bits; 191 192 __at(0x0FA0) __sfr PIE2; 193 __at(0x0FA0) volatile __PIE2bits_t PIE2bits; 194 195 __at(0x0FA1) __sfr PIR2; 196 __at(0x0FA1) volatile __PIR2bits_t PIR2bits; 197 198 __at(0x0FA2) __sfr IPR2; 199 __at(0x0FA2) volatile __IPR2bits_t IPR2bits; 200 201 __at(0x0FA6) __sfr EECON1; 202 __at(0x0FA6) volatile __EECON1bits_t EECON1bits; 203 204 __at(0x0FA7) __sfr EECON2; 205 206 __at(0x0FA8) __sfr EEDATA; 207 208 __at(0x0FA9) __sfr EEADR; 209 210 __at(0x0FAB) __sfr RCSTA; 211 __at(0x0FAB) volatile __RCSTAbits_t RCSTAbits; 212 213 __at(0x0FAC) __sfr TXSTA; 214 __at(0x0FAC) volatile __TXSTAbits_t TXSTAbits; 215 216 __at(0x0FAD) __sfr TXREG; 217 218 __at(0x0FAE) __sfr RCREG; 219 220 __at(0x0FAF) __sfr SPBRG; 221 222 __at(0x0FB0) __sfr SPBRGH; 223 224 __at(0x0FB1) __sfr T3CON; 225 __at(0x0FB1) volatile __T3CONbits_t T3CONbits; 226 227 __at(0x0FB2) __sfr TMR3; 228 229 __at(0x0FB2) __sfr TMR3L; 230 231 __at(0x0FB3) __sfr TMR3H; 232 233 __at(0x0FB4) __sfr CMCON; 234 __at(0x0FB4) volatile __CMCONbits_t CMCONbits; 235 236 __at(0x0FB5) __sfr CVRCON; 237 __at(0x0FB5) volatile __CVRCONbits_t CVRCONbits; 238 239 __at(0x0FB6) __sfr CCP1AS; 240 __at(0x0FB6) volatile __CCP1ASbits_t CCP1ASbits; 241 242 __at(0x0FB6) __sfr ECCP1AS; 243 __at(0x0FB6) volatile __ECCP1ASbits_t ECCP1ASbits; 244 245 __at(0x0FB7) __sfr CCP1DEL; 246 __at(0x0FB7) volatile __CCP1DELbits_t CCP1DELbits; 247 248 __at(0x0FB7) __sfr ECCP1DEL; 249 __at(0x0FB7) volatile __ECCP1DELbits_t ECCP1DELbits; 250 251 __at(0x0FB8) __sfr BAUDCON; 252 __at(0x0FB8) volatile __BAUDCONbits_t BAUDCONbits; 253 254 __at(0x0FB8) __sfr BAUDCTL; 255 __at(0x0FB8) volatile __BAUDCTLbits_t BAUDCTLbits; 256 257 __at(0x0FBA) __sfr CCP2CON; 258 __at(0x0FBA) volatile __CCP2CONbits_t CCP2CONbits; 259 260 __at(0x0FBB) __sfr CCPR2; 261 262 __at(0x0FBB) __sfr CCPR2L; 263 264 __at(0x0FBC) __sfr CCPR2H; 265 266 __at(0x0FBD) __sfr CCP1CON; 267 __at(0x0FBD) volatile __CCP1CONbits_t CCP1CONbits; 268 269 __at(0x0FBD) __sfr ECCP1CON; 270 __at(0x0FBD) volatile __ECCP1CONbits_t ECCP1CONbits; 271 272 __at(0x0FBE) __sfr CCPR1; 273 274 __at(0x0FBE) __sfr CCPR1L; 275 276 __at(0x0FBF) __sfr CCPR1H; 277 278 __at(0x0FC0) __sfr ADCON2; 279 __at(0x0FC0) volatile __ADCON2bits_t ADCON2bits; 280 281 __at(0x0FC1) __sfr ADCON1; 282 __at(0x0FC1) volatile __ADCON1bits_t ADCON1bits; 283 284 __at(0x0FC2) __sfr ADCON0; 285 __at(0x0FC2) volatile __ADCON0bits_t ADCON0bits; 286 287 __at(0x0FC3) __sfr ADRES; 288 289 __at(0x0FC3) __sfr ADRESL; 290 291 __at(0x0FC4) __sfr ADRESH; 292 293 __at(0x0FC5) __sfr SSPCON2; 294 __at(0x0FC5) volatile __SSPCON2bits_t SSPCON2bits; 295 296 __at(0x0FC6) __sfr SSPCON1; 297 __at(0x0FC6) volatile __SSPCON1bits_t SSPCON1bits; 298 299 __at(0x0FC7) __sfr SSPSTAT; 300 __at(0x0FC7) volatile __SSPSTATbits_t SSPSTATbits; 301 302 __at(0x0FC8) __sfr SSPADD; 303 304 __at(0x0FC9) __sfr SSPBUF; 305 306 __at(0x0FCA) __sfr T2CON; 307 __at(0x0FCA) volatile __T2CONbits_t T2CONbits; 308 309 __at(0x0FCB) __sfr PR2; 310 311 __at(0x0FCC) __sfr TMR2; 312 313 __at(0x0FCD) __sfr T1CON; 314 __at(0x0FCD) volatile __T1CONbits_t T1CONbits; 315 316 __at(0x0FCE) __sfr TMR1; 317 318 __at(0x0FCE) __sfr TMR1L; 319 320 __at(0x0FCF) __sfr TMR1H; 321 322 __at(0x0FD0) __sfr RCON; 323 __at(0x0FD0) volatile __RCONbits_t RCONbits; 324 325 __at(0x0FD1) __sfr WDTCON; 326 __at(0x0FD1) volatile __WDTCONbits_t WDTCONbits; 327 328 __at(0x0FD2) __sfr HLVDCON; 329 __at(0x0FD2) volatile __HLVDCONbits_t HLVDCONbits; 330 331 __at(0x0FD2) __sfr LVDCON; 332 __at(0x0FD2) volatile __LVDCONbits_t LVDCONbits; 333 334 __at(0x0FD3) __sfr OSCCON; 335 __at(0x0FD3) volatile __OSCCONbits_t OSCCONbits; 336 337 __at(0x0FD5) __sfr T0CON; 338 __at(0x0FD5) volatile __T0CONbits_t T0CONbits; 339 340 __at(0x0FD6) __sfr TMR0; 341 342 __at(0x0FD6) __sfr TMR0L; 343 344 __at(0x0FD7) __sfr TMR0H; 345 346 __at(0x0FD8) __sfr STATUS; 347 __at(0x0FD8) volatile __STATUSbits_t STATUSbits; 348 349 __at(0x0FD9) __sfr FSR2L; 350 351 __at(0x0FDA) __sfr FSR2H; 352 353 __at(0x0FDB) __sfr PLUSW2; 354 355 __at(0x0FDC) __sfr PREINC2; 356 357 __at(0x0FDD) __sfr POSTDEC2; 358 359 __at(0x0FDE) __sfr POSTINC2; 360 361 __at(0x0FDF) __sfr INDF2; 362 363 __at(0x0FE0) __sfr BSR; 364 365 __at(0x0FE1) __sfr FSR1L; 366 367 __at(0x0FE2) __sfr FSR1H; 368 369 __at(0x0FE3) __sfr PLUSW1; 370 371 __at(0x0FE4) __sfr PREINC1; 372 373 __at(0x0FE5) __sfr POSTDEC1; 374 375 __at(0x0FE6) __sfr POSTINC1; 376 377 __at(0x0FE7) __sfr INDF1; 378 379 __at(0x0FE8) __sfr WREG; 380 381 __at(0x0FE9) __sfr FSR0L; 382 383 __at(0x0FEA) __sfr FSR0H; 384 385 __at(0x0FEB) __sfr PLUSW0; 386 387 __at(0x0FEC) __sfr PREINC0; 388 389 __at(0x0FED) __sfr POSTDEC0; 390 391 __at(0x0FEE) __sfr POSTINC0; 392 393 __at(0x0FEF) __sfr INDF0; 394 395 __at(0x0FF0) __sfr INTCON3; 396 __at(0x0FF0) volatile __INTCON3bits_t INTCON3bits; 397 398 __at(0x0FF1) __sfr INTCON2; 399 __at(0x0FF1) volatile __INTCON2bits_t INTCON2bits; 400 401 __at(0x0FF2) __sfr INTCON; 402 __at(0x0FF2) volatile __INTCONbits_t INTCONbits; 403 404 __at(0x0FF3) __sfr PROD; 405 406 __at(0x0FF3) __sfr PRODL; 407 408 __at(0x0FF4) __sfr PRODH; 409 410 __at(0x0FF5) __sfr TABLAT; 411 412 __at(0x0FF6) __sfr TBLPTR; 413 414 __at(0x0FF6) __sfr TBLPTRL; 415 416 __at(0x0FF7) __sfr TBLPTRH; 417 418 __at(0x0FF8) __sfr TBLPTRU; 419 420 __at(0x0FF9) __sfr PC; 421 422 __at(0x0FF9) __sfr PCL; 423 424 __at(0x0FFA) __sfr PCLATH; 425 426 __at(0x0FFB) __sfr PCLATU; 427 428 __at(0x0FFC) __sfr STKPTR; 429 __at(0x0FFC) volatile __STKPTRbits_t STKPTRbits; 430 431 __at(0x0FFD) __sfr TOS; 432 433 __at(0x0FFD) __sfr TOSL; 434 435 __at(0x0FFE) __sfr TOSH; 436 437 __at(0x0FFF) __sfr TOSU; 438