1 /* 2 * This definitions of the PIC18LF6621 MCU. 3 * 4 * This file is part of the GNU PIC library for SDCC, originally 5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016. 6 * 7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:24:06 UTC. 8 * 9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that 10 * this license covers the code to the compiler and other executables, 11 * but explicitly does not cover any code or objects generated by sdcc. 12 * 13 * For pic device libraries and header files which are derived from 14 * Microchip header (.inc) and linker script (.lkr) files Microchip 15 * requires that "The header files should state that they are only to be 16 * used with authentic Microchip devices" which makes them incompatible 17 * with the GPL. Pic device libraries and header files are located at 18 * non-free/lib and non-free/include directories respectively. 19 * Sdcc should be run with the --use-non-free command line option in 20 * order to include non-free header files and libraries. 21 * 22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc. 23 */ 24 25 #include <pic18lf6621.h> 26 27 //============================================================================== 28 29 __at(0x0F67) __sfr ECCP2DEL; 30 __at(0x0F67) volatile __ECCP2DELbits_t ECCP2DELbits; 31 32 __at(0x0F67) __sfr PWM2CON; 33 __at(0x0F67) volatile __PWM2CONbits_t PWM2CONbits; 34 35 __at(0x0F68) __sfr ECCP2AS; 36 __at(0x0F68) volatile __ECCP2ASbits_t ECCP2ASbits; 37 38 __at(0x0F69) __sfr ECCP3DEL; 39 __at(0x0F69) volatile __ECCP3DELbits_t ECCP3DELbits; 40 41 __at(0x0F69) __sfr PWM3CON; 42 __at(0x0F69) volatile __PWM3CONbits_t PWM3CONbits; 43 44 __at(0x0F6A) __sfr ECCP3AS; 45 __at(0x0F6A) volatile __ECCP3ASbits_t ECCP3ASbits; 46 47 __at(0x0F6B) __sfr RCSTA2; 48 __at(0x0F6B) volatile __RCSTA2bits_t RCSTA2bits; 49 50 __at(0x0F6C) __sfr TXSTA2; 51 __at(0x0F6C) volatile __TXSTA2bits_t TXSTA2bits; 52 53 __at(0x0F6D) __sfr TXREG2; 54 55 __at(0x0F6E) __sfr RCREG2; 56 57 __at(0x0F6F) __sfr SPBRG2; 58 59 __at(0x0F70) __sfr CCP5CON; 60 __at(0x0F70) volatile __CCP5CONbits_t CCP5CONbits; 61 62 __at(0x0F71) __sfr CCPR5; 63 64 __at(0x0F71) __sfr CCPR5L; 65 66 __at(0x0F72) __sfr CCPR5H; 67 68 __at(0x0F73) __sfr CCP4CON; 69 __at(0x0F73) volatile __CCP4CONbits_t CCP4CONbits; 70 71 __at(0x0F74) __sfr CCPR4; 72 73 __at(0x0F74) __sfr CCPR4L; 74 75 __at(0x0F75) __sfr CCPR4H; 76 77 __at(0x0F76) __sfr T4CON; 78 __at(0x0F76) volatile __T4CONbits_t T4CONbits; 79 80 __at(0x0F77) __sfr PR4; 81 82 __at(0x0F78) __sfr TMR4; 83 84 __at(0x0F79) __sfr ECCP1DEL; 85 __at(0x0F79) volatile __ECCP1DELbits_t ECCP1DELbits; 86 87 __at(0x0F79) __sfr PWM1CON; 88 __at(0x0F79) volatile __PWM1CONbits_t PWM1CONbits; 89 90 __at(0x0F7C) __sfr BAUDCON2; 91 __at(0x0F7C) volatile __BAUDCON2bits_t BAUDCON2bits; 92 93 __at(0x0F7C) __sfr BAUDCTL2; 94 __at(0x0F7C) volatile __BAUDCTL2bits_t BAUDCTL2bits; 95 96 __at(0x0F7D) __sfr SPBRGH2; 97 98 __at(0x0F7E) __sfr BAUDCON; 99 __at(0x0F7E) volatile __BAUDCONbits_t BAUDCONbits; 100 101 __at(0x0F7E) __sfr BAUDCON1; 102 __at(0x0F7E) volatile __BAUDCON1bits_t BAUDCON1bits; 103 104 __at(0x0F7E) __sfr BAUDCTL1; 105 __at(0x0F7E) volatile __BAUDCTL1bits_t BAUDCTL1bits; 106 107 __at(0x0F7F) __sfr SPBRGH; 108 109 __at(0x0F7F) __sfr SPBRGH1; 110 111 __at(0x0F80) __sfr PORTA; 112 __at(0x0F80) volatile __PORTAbits_t PORTAbits; 113 114 __at(0x0F81) __sfr PORTB; 115 __at(0x0F81) volatile __PORTBbits_t PORTBbits; 116 117 __at(0x0F82) __sfr PORTC; 118 __at(0x0F82) volatile __PORTCbits_t PORTCbits; 119 120 __at(0x0F83) __sfr PORTD; 121 __at(0x0F83) volatile __PORTDbits_t PORTDbits; 122 123 __at(0x0F84) __sfr PORTE; 124 __at(0x0F84) volatile __PORTEbits_t PORTEbits; 125 126 __at(0x0F85) __sfr PORTF; 127 __at(0x0F85) volatile __PORTFbits_t PORTFbits; 128 129 __at(0x0F86) __sfr PORTG; 130 __at(0x0F86) volatile __PORTGbits_t PORTGbits; 131 132 __at(0x0F89) __sfr LATA; 133 __at(0x0F89) volatile __LATAbits_t LATAbits; 134 135 __at(0x0F8A) __sfr LATB; 136 __at(0x0F8A) volatile __LATBbits_t LATBbits; 137 138 __at(0x0F8B) __sfr LATC; 139 __at(0x0F8B) volatile __LATCbits_t LATCbits; 140 141 __at(0x0F8C) __sfr LATD; 142 __at(0x0F8C) volatile __LATDbits_t LATDbits; 143 144 __at(0x0F8D) __sfr LATE; 145 __at(0x0F8D) volatile __LATEbits_t LATEbits; 146 147 __at(0x0F8E) __sfr LATF; 148 __at(0x0F8E) volatile __LATFbits_t LATFbits; 149 150 __at(0x0F8F) __sfr LATG; 151 __at(0x0F8F) volatile __LATGbits_t LATGbits; 152 153 __at(0x0F92) __sfr DDRA; 154 __at(0x0F92) volatile __DDRAbits_t DDRAbits; 155 156 __at(0x0F92) __sfr TRISA; 157 __at(0x0F92) volatile __TRISAbits_t TRISAbits; 158 159 __at(0x0F93) __sfr DDRB; 160 __at(0x0F93) volatile __DDRBbits_t DDRBbits; 161 162 __at(0x0F93) __sfr TRISB; 163 __at(0x0F93) volatile __TRISBbits_t TRISBbits; 164 165 __at(0x0F94) __sfr DDRC; 166 __at(0x0F94) volatile __DDRCbits_t DDRCbits; 167 168 __at(0x0F94) __sfr TRISC; 169 __at(0x0F94) volatile __TRISCbits_t TRISCbits; 170 171 __at(0x0F95) __sfr DDRD; 172 __at(0x0F95) volatile __DDRDbits_t DDRDbits; 173 174 __at(0x0F95) __sfr TRISD; 175 __at(0x0F95) volatile __TRISDbits_t TRISDbits; 176 177 __at(0x0F96) __sfr DDRE; 178 __at(0x0F96) volatile __DDREbits_t DDREbits; 179 180 __at(0x0F96) __sfr TRISE; 181 __at(0x0F96) volatile __TRISEbits_t TRISEbits; 182 183 __at(0x0F97) __sfr DDRF; 184 __at(0x0F97) volatile __DDRFbits_t DDRFbits; 185 186 __at(0x0F97) __sfr TRISF; 187 __at(0x0F97) volatile __TRISFbits_t TRISFbits; 188 189 __at(0x0F98) __sfr DDRG; 190 __at(0x0F98) volatile __DDRGbits_t DDRGbits; 191 192 __at(0x0F98) __sfr TRISG; 193 __at(0x0F98) volatile __TRISGbits_t TRISGbits; 194 195 __at(0x0F9D) __sfr PIE1; 196 __at(0x0F9D) volatile __PIE1bits_t PIE1bits; 197 198 __at(0x0F9E) __sfr PIR1; 199 __at(0x0F9E) volatile __PIR1bits_t PIR1bits; 200 201 __at(0x0F9F) __sfr IPR1; 202 __at(0x0F9F) volatile __IPR1bits_t IPR1bits; 203 204 __at(0x0FA0) __sfr PIE2; 205 __at(0x0FA0) volatile __PIE2bits_t PIE2bits; 206 207 __at(0x0FA1) __sfr PIR2; 208 __at(0x0FA1) volatile __PIR2bits_t PIR2bits; 209 210 __at(0x0FA2) __sfr IPR2; 211 __at(0x0FA2) volatile __IPR2bits_t IPR2bits; 212 213 __at(0x0FA3) __sfr PIE3; 214 __at(0x0FA3) volatile __PIE3bits_t PIE3bits; 215 216 __at(0x0FA4) __sfr PIR3; 217 __at(0x0FA4) volatile __PIR3bits_t PIR3bits; 218 219 __at(0x0FA5) __sfr IPR3; 220 __at(0x0FA5) volatile __IPR3bits_t IPR3bits; 221 222 __at(0x0FA6) __sfr EECON1; 223 __at(0x0FA6) volatile __EECON1bits_t EECON1bits; 224 225 __at(0x0FA7) __sfr EECON2; 226 227 __at(0x0FA8) __sfr EEDATA; 228 229 __at(0x0FA9) __sfr EEADR; 230 231 __at(0x0FAA) __sfr EEADRH; 232 233 __at(0x0FAB) __sfr RCSTA; 234 __at(0x0FAB) volatile __RCSTAbits_t RCSTAbits; 235 236 __at(0x0FAB) __sfr RCSTA1; 237 __at(0x0FAB) volatile __RCSTA1bits_t RCSTA1bits; 238 239 __at(0x0FAC) __sfr TXSTA; 240 __at(0x0FAC) volatile __TXSTAbits_t TXSTAbits; 241 242 __at(0x0FAC) __sfr TXSTA1; 243 __at(0x0FAC) volatile __TXSTA1bits_t TXSTA1bits; 244 245 __at(0x0FAD) __sfr TXREG; 246 247 __at(0x0FAD) __sfr TXREG1; 248 249 __at(0x0FAE) __sfr RCREG; 250 251 __at(0x0FAE) __sfr RCREG1; 252 253 __at(0x0FAF) __sfr SPBRG; 254 255 __at(0x0FAF) __sfr SPBRG1; 256 257 __at(0x0FB0) __sfr PSPCON; 258 __at(0x0FB0) volatile __PSPCONbits_t PSPCONbits; 259 260 __at(0x0FB1) __sfr T3CON; 261 __at(0x0FB1) volatile __T3CONbits_t T3CONbits; 262 263 __at(0x0FB2) __sfr TMR3; 264 265 __at(0x0FB2) __sfr TMR3L; 266 267 __at(0x0FB3) __sfr TMR3H; 268 269 __at(0x0FB4) __sfr CMCON; 270 __at(0x0FB4) volatile __CMCONbits_t CMCONbits; 271 272 __at(0x0FB5) __sfr CVRCON; 273 __at(0x0FB5) volatile __CVRCONbits_t CVRCONbits; 274 275 __at(0x0FB6) __sfr ECCP1AS; 276 __at(0x0FB6) volatile __ECCP1ASbits_t ECCP1ASbits; 277 278 __at(0x0FB7) __sfr CCP3CON; 279 __at(0x0FB7) volatile __CCP3CONbits_t CCP3CONbits; 280 281 __at(0x0FB8) __sfr CCPR3; 282 283 __at(0x0FB8) __sfr CCPR3L; 284 285 __at(0x0FB9) __sfr CCPR3H; 286 287 __at(0x0FBA) __sfr CCP2CON; 288 __at(0x0FBA) volatile __CCP2CONbits_t CCP2CONbits; 289 290 __at(0x0FBB) __sfr CCPR2; 291 292 __at(0x0FBB) __sfr CCPR2L; 293 294 __at(0x0FBC) __sfr CCPR2H; 295 296 __at(0x0FBD) __sfr CCP1CON; 297 __at(0x0FBD) volatile __CCP1CONbits_t CCP1CONbits; 298 299 __at(0x0FBE) __sfr CCPR1; 300 301 __at(0x0FBE) __sfr CCPR1L; 302 303 __at(0x0FBF) __sfr CCPR1H; 304 305 __at(0x0FC0) __sfr ADCON2; 306 __at(0x0FC0) volatile __ADCON2bits_t ADCON2bits; 307 308 __at(0x0FC1) __sfr ADCON1; 309 __at(0x0FC1) volatile __ADCON1bits_t ADCON1bits; 310 311 __at(0x0FC2) __sfr ADCON0; 312 __at(0x0FC2) volatile __ADCON0bits_t ADCON0bits; 313 314 __at(0x0FC3) __sfr ADRES; 315 316 __at(0x0FC3) __sfr ADRESL; 317 318 __at(0x0FC4) __sfr ADRESH; 319 320 __at(0x0FC5) __sfr SSPCON2; 321 __at(0x0FC5) volatile __SSPCON2bits_t SSPCON2bits; 322 323 __at(0x0FC6) __sfr SSPCON1; 324 __at(0x0FC6) volatile __SSPCON1bits_t SSPCON1bits; 325 326 __at(0x0FC7) __sfr SSPSTAT; 327 __at(0x0FC7) volatile __SSPSTATbits_t SSPSTATbits; 328 329 __at(0x0FC8) __sfr SSPADD; 330 331 __at(0x0FC9) __sfr SSPBUF; 332 333 __at(0x0FCA) __sfr T2CON; 334 __at(0x0FCA) volatile __T2CONbits_t T2CONbits; 335 336 __at(0x0FCB) __sfr PR2; 337 338 __at(0x0FCC) __sfr TMR2; 339 340 __at(0x0FCD) __sfr T1CON; 341 __at(0x0FCD) volatile __T1CONbits_t T1CONbits; 342 343 __at(0x0FCE) __sfr TMR1; 344 345 __at(0x0FCE) __sfr TMR1L; 346 347 __at(0x0FCF) __sfr TMR1H; 348 349 __at(0x0FD0) __sfr RCON; 350 __at(0x0FD0) volatile __RCONbits_t RCONbits; 351 352 __at(0x0FD1) __sfr WDTCON; 353 __at(0x0FD1) volatile __WDTCONbits_t WDTCONbits; 354 355 __at(0x0FD2) __sfr LVDCON; 356 __at(0x0FD2) volatile __LVDCONbits_t LVDCONbits; 357 358 __at(0x0FD3) __sfr OSCCON; 359 __at(0x0FD3) volatile __OSCCONbits_t OSCCONbits; 360 361 __at(0x0FD5) __sfr T0CON; 362 __at(0x0FD5) volatile __T0CONbits_t T0CONbits; 363 364 __at(0x0FD6) __sfr TMR0; 365 366 __at(0x0FD6) __sfr TMR0L; 367 368 __at(0x0FD7) __sfr TMR0H; 369 370 __at(0x0FD8) __sfr STATUS; 371 __at(0x0FD8) volatile __STATUSbits_t STATUSbits; 372 373 __at(0x0FD9) __sfr FSR2L; 374 375 __at(0x0FDA) __sfr FSR2H; 376 377 __at(0x0FDB) __sfr PLUSW2; 378 379 __at(0x0FDC) __sfr PREINC2; 380 381 __at(0x0FDD) __sfr POSTDEC2; 382 383 __at(0x0FDE) __sfr POSTINC2; 384 385 __at(0x0FDF) __sfr INDF2; 386 387 __at(0x0FE0) __sfr BSR; 388 389 __at(0x0FE1) __sfr FSR1L; 390 391 __at(0x0FE2) __sfr FSR1H; 392 393 __at(0x0FE3) __sfr PLUSW1; 394 395 __at(0x0FE4) __sfr PREINC1; 396 397 __at(0x0FE5) __sfr POSTDEC1; 398 399 __at(0x0FE6) __sfr POSTINC1; 400 401 __at(0x0FE7) __sfr INDF1; 402 403 __at(0x0FE8) __sfr WREG; 404 405 __at(0x0FE9) __sfr FSR0L; 406 407 __at(0x0FEA) __sfr FSR0H; 408 409 __at(0x0FEB) __sfr PLUSW0; 410 411 __at(0x0FEC) __sfr PREINC0; 412 413 __at(0x0FED) __sfr POSTDEC0; 414 415 __at(0x0FEE) __sfr POSTINC0; 416 417 __at(0x0FEF) __sfr INDF0; 418 419 __at(0x0FF0) __sfr INTCON3; 420 __at(0x0FF0) volatile __INTCON3bits_t INTCON3bits; 421 422 __at(0x0FF1) __sfr INTCON2; 423 __at(0x0FF1) volatile __INTCON2bits_t INTCON2bits; 424 425 __at(0x0FF2) __sfr INTCON; 426 __at(0x0FF2) volatile __INTCONbits_t INTCONbits; 427 428 __at(0x0FF3) __sfr PROD; 429 430 __at(0x0FF3) __sfr PRODL; 431 432 __at(0x0FF4) __sfr PRODH; 433 434 __at(0x0FF5) __sfr TABLAT; 435 436 __at(0x0FF6) __sfr TBLPTR; 437 438 __at(0x0FF6) __sfr TBLPTRL; 439 440 __at(0x0FF7) __sfr TBLPTRH; 441 442 __at(0x0FF8) __sfr TBLPTRU; 443 444 __at(0x0FF9) __sfr PC; 445 446 __at(0x0FF9) __sfr PCL; 447 448 __at(0x0FFA) __sfr PCLATH; 449 450 __at(0x0FFB) __sfr PCLATU; 451 452 __at(0x0FFC) __sfr STKPTR; 453 __at(0x0FFC) volatile __STKPTRbits_t STKPTRbits; 454 455 __at(0x0FFD) __sfr TOS; 456 457 __at(0x0FFD) __sfr TOSL; 458 459 __at(0x0FFE) __sfr TOSH; 460 461 __at(0x0FFF) __sfr TOSU; 462