1 use crate::cdsl::settings::{SettingGroup, SettingGroupBuilder};
2
define() -> SettingGroup3 pub(crate) fn define() -> SettingGroup {
4 let mut settings = SettingGroupBuilder::new("shared");
5
6 settings.add_enum(
7 "regalloc",
8 r#"Register allocator to use with the MachInst backend.
9
10 This selects the register allocator as an option among those offered by the `regalloc.rs`
11 crate. Please report register allocation bugs to the maintainers of this crate whenever
12 possible.
13
14 Note: this only applies to target that use the MachInst backend. As of 2020-04-17, this
15 means the x86_64 backend doesn't use this yet.
16
17 Possible values:
18
19 - `backtracking` is a greedy, backtracking register allocator as implemented in
20 Spidermonkey's optimizing tier IonMonkey. It may take more time to allocate registers, but
21 it should generate better code in general, resulting in better throughput of generated
22 code.
23 - `backtracking_checked` is the backtracking allocator with additional self checks that may
24 take some time to run, and thus these checks are disabled by default.
25 - `experimental_linear_scan` is an experimental linear scan allocator. It may take less
26 time to allocate registers, but generated code's quality may be inferior. As of
27 2020-04-17, it is still experimental and it should not be used in production settings.
28 "#,
29 vec![
30 "backtracking",
31 "backtracking_checked",
32 "experimental_linear_scan",
33 ],
34 );
35
36 settings.add_enum(
37 "opt_level",
38 r#"
39 Optimization level:
40
41 - none: Minimise compile time by disabling most optimizations.
42 - speed: Generate the fastest possible code
43 - speed_and_size: like "speed", but also perform transformations
44 aimed at reducing code size.
45 "#,
46 vec!["none", "speed", "speed_and_size"],
47 );
48
49 settings.add_bool(
50 "enable_verifier",
51 r#"
52 Run the Cranelift IR verifier at strategic times during compilation.
53
54 This makes compilation slower but catches many bugs. The verifier is always enabled by
55 default, which is useful during development.
56 "#,
57 true,
58 );
59
60 // Note that Cranelift doesn't currently need an is_pie flag, because PIE is
61 // just PIC where symbols can't be pre-empted, which can be expressed with the
62 // `colocated` flag on external functions and global values.
63 settings.add_bool(
64 "is_pic",
65 "Enable Position-Independent Code generation",
66 false,
67 );
68
69 settings.add_bool(
70 "use_colocated_libcalls",
71 r#"
72 Use colocated libcalls.
73
74 Generate code that assumes that libcalls can be declared "colocated",
75 meaning they will be defined along with the current function, such that
76 they can use more efficient addressing.
77 "#,
78 false,
79 );
80
81 settings.add_bool(
82 "avoid_div_traps",
83 r#"
84 Generate explicit checks around native division instructions to avoid
85 their trapping.
86
87 This is primarily used by SpiderMonkey which doesn't install a signal
88 handler for SIGFPE, but expects a SIGILL trap for division by zero.
89
90 On ISAs like ARM where the native division instructions don't trap,
91 this setting has no effect - explicit checks are always inserted.
92 "#,
93 false,
94 );
95
96 settings.add_bool(
97 "enable_float",
98 r#"
99 Enable the use of floating-point instructions
100
101 Disabling use of floating-point instructions is not yet implemented.
102 "#,
103 true,
104 );
105
106 settings.add_bool(
107 "enable_nan_canonicalization",
108 r#"
109 Enable NaN canonicalization
110
111 This replaces NaNs with a single canonical value, for users requiring
112 entirely deterministic WebAssembly computation. This is not required
113 by the WebAssembly spec, so it is not enabled by default.
114 "#,
115 false,
116 );
117
118 settings.add_bool(
119 "enable_pinned_reg",
120 r#"Enable the use of the pinned register.
121
122 This register is excluded from register allocation, and is completely under the control of
123 the end-user. It is possible to read it via the get_pinned_reg instruction, and to set it
124 with the set_pinned_reg instruction.
125 "#,
126 false,
127 );
128
129 settings.add_bool(
130 "use_pinned_reg_as_heap_base",
131 r#"Use the pinned register as the heap base.
132
133 Enabling this requires the enable_pinned_reg setting to be set to true. It enables a custom
134 legalization of the `heap_addr` instruction so it will use the pinned register as the heap
135 base, instead of fetching it from a global value.
136
137 Warning! Enabling this means that the pinned register *must* be maintained to contain the
138 heap base address at all times, during the lifetime of a function. Using the pinned
139 register for other purposes when this is set is very likely to cause crashes.
140 "#,
141 false,
142 );
143
144 settings.add_bool("enable_simd", "Enable the use of SIMD instructions.", false);
145
146 settings.add_bool(
147 "enable_atomics",
148 "Enable the use of atomic instructions",
149 true,
150 );
151
152 settings.add_bool(
153 "enable_safepoints",
154 r#"
155 Enable safepoint instruction insertions.
156
157 This will allow the emit_stackmaps() function to insert the safepoint
158 instruction on top of calls and interrupt traps in order to display the
159 live reference values at that point in the program.
160 "#,
161 false,
162 );
163
164 settings.add_enum(
165 "tls_model",
166 r#"
167 Defines the model used to perform TLS accesses.
168 "#,
169 vec!["none", "elf_gd", "macho", "coff"],
170 );
171
172 // Settings specific to the `baldrdash` calling convention.
173
174 settings.add_enum(
175 "libcall_call_conv",
176 r#"
177 Defines the calling convention to use for LibCalls call expansion,
178 since it may be different from the ISA default calling convention.
179
180 The default value is to use the same calling convention as the ISA
181 default calling convention.
182
183 This list should be kept in sync with the list of calling
184 conventions available in isa/call_conv.rs.
185 "#,
186 vec![
187 "isa_default",
188 "fast",
189 "cold",
190 "system_v",
191 "windows_fastcall",
192 "baldrdash_system_v",
193 "baldrdash_windows",
194 "probestack",
195 ],
196 );
197
198 settings.add_num(
199 "baldrdash_prologue_words",
200 r#"
201 Number of pointer-sized words pushed by the baldrdash prologue.
202
203 Functions with the `baldrdash` calling convention don't generate their
204 own prologue and epilogue. They depend on externally generated code
205 that pushes a fixed number of words in the prologue and restores them
206 in the epilogue.
207
208 This setting configures the number of pointer-sized words pushed on the
209 stack when the Cranelift-generated code is entered. This includes the
210 pushed return address on x86.
211 "#,
212 0,
213 );
214
215 // BaldrMonkey requires that not-yet-relocated function addresses be encoded
216 // as all-ones bitpatterns.
217 settings.add_bool(
218 "emit_all_ones_funcaddrs",
219 "Emit not-yet-relocated function addresses as all-ones bit patterns.",
220 false,
221 );
222
223 // Stack probing options.
224
225 settings.add_bool(
226 "enable_probestack",
227 r#"
228 Enable the use of stack probes, for calling conventions which support this
229 functionality.
230 "#,
231 true,
232 );
233
234 settings.add_bool(
235 "probestack_func_adjusts_sp",
236 r#"
237 Set this to true of the stack probe function modifies the stack pointer
238 itself.
239 "#,
240 false,
241 );
242
243 settings.add_num(
244 "probestack_size_log2",
245 r#"
246 The log2 of the size of the stack guard region.
247
248 Stack frames larger than this size will have stack overflow checked
249 by calling the probestack function.
250
251 The default is 12, which translates to a size of 4096.
252 "#,
253 12,
254 );
255
256 // Jump table options.
257
258 settings.add_bool(
259 "enable_jump_tables",
260 "Enable the use of jump tables in generated machine code.",
261 true,
262 );
263
264 settings.build()
265 }
266