1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ 2 /* 3 * linux/drivers/char/serial_core.h 4 * 5 * Copyright (C) 2000 Deep Blue Solutions Ltd. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 */ 21 #ifndef LINUX_SERIAL_CORE_H 22 #define LINUX_SERIAL_CORE_H 23 24 #include <linux/serial.h> 25 26 /* 27 * The type definitions. These are from Ted Ts'o's serial.h 28 */ 29 #define PORT_NS16550A 14 30 #define PORT_XSCALE 15 31 #define PORT_RM9000 16 /* PMC-Sierra RM9xxx internal UART */ 32 #define PORT_OCTEON 17 /* Cavium OCTEON internal UART */ 33 #define PORT_AR7 18 /* Texas Instruments AR7 internal UART */ 34 #define PORT_U6_16550A 19 /* ST-Ericsson U6xxx internal UART */ 35 #define PORT_TEGRA 20 /* NVIDIA Tegra internal UART */ 36 #define PORT_XR17D15X 21 /* Exar XR17D15x UART */ 37 #define PORT_LPC3220 22 /* NXP LPC32xx SoC "Standard" UART */ 38 #define PORT_8250_CIR 23 /* CIR infrared port, has its own driver */ 39 #define PORT_XR17V35X 24 /* Exar XR17V35x UARTs */ 40 #define PORT_BRCM_TRUMANAGE 25 41 #define PORT_ALTR_16550_F32 26 /* Altera 16550 UART with 32 FIFOs */ 42 #define PORT_ALTR_16550_F64 27 /* Altera 16550 UART with 64 FIFOs */ 43 #define PORT_ALTR_16550_F128 28 /* Altera 16550 UART with 128 FIFOs */ 44 #define PORT_RT2880 29 /* Ralink RT2880 internal UART */ 45 #define PORT_16550A_FSL64 30 /* Freescale 16550 UART with 64 FIFOs */ 46 47 /* 48 * ARM specific type numbers. These are not currently guaranteed 49 * to be implemented, and will change in the future. These are 50 * separate so any additions to the old serial.c that occur before 51 * we are merged can be easily merged here. 52 */ 53 #define PORT_PXA 31 54 #define PORT_AMBA 32 55 #define PORT_CLPS711X 33 56 #define PORT_SA1100 34 57 #define PORT_UART00 35 58 #define PORT_OWL 36 59 #define PORT_21285 37 60 61 /* Sparc type numbers. */ 62 #define PORT_SUNZILOG 38 63 #define PORT_SUNSAB 39 64 65 /* Nuvoton UART */ 66 #define PORT_NPCM 40 67 68 /* NVIDIA Tegra Combined UART */ 69 #define PORT_TEGRA_TCU 41 70 71 /* Intel EG20 */ 72 #define PORT_PCH_8LINE 44 73 #define PORT_PCH_2LINE 45 74 75 /* DEC */ 76 #define PORT_DZ 46 77 #define PORT_ZS 47 78 79 /* Parisc type numbers. */ 80 #define PORT_MUX 48 81 82 /* Atmel AT91 SoC */ 83 #define PORT_ATMEL 49 84 85 /* Macintosh Zilog type numbers */ 86 #define PORT_MAC_ZILOG 50 /* m68k : not yet implemented */ 87 #define PORT_PMAC_ZILOG 51 88 89 /* SH-SCI */ 90 #define PORT_SCI 52 91 #define PORT_SCIF 53 92 #define PORT_IRDA 54 93 94 /* Samsung S3C2410 SoC and derivatives thereof */ 95 #define PORT_S3C2410 55 96 97 /* SGI IP22 aka Indy / Challenge S / Indigo 2 */ 98 #define PORT_IP22ZILOG 56 99 100 /* Sharp LH7a40x -- an ARM9 SoC series */ 101 #define PORT_LH7A40X 57 102 103 /* PPC CPM type number */ 104 #define PORT_CPM 58 105 106 /* MPC52xx (and MPC512x) type numbers */ 107 #define PORT_MPC52xx 59 108 109 /* IBM icom */ 110 #define PORT_ICOM 60 111 112 /* Samsung S3C2440 SoC */ 113 #define PORT_S3C2440 61 114 115 /* Motorola i.MX SoC */ 116 #define PORT_IMX 62 117 118 /* Marvell MPSC (obsolete unused) */ 119 #define PORT_MPSC 63 120 121 /* TXX9 type number */ 122 #define PORT_TXX9 64 123 124 /* NEC VR4100 series SIU/DSIU */ 125 #define PORT_VR41XX_SIU 65 126 #define PORT_VR41XX_DSIU 66 127 128 /* Samsung S3C2400 SoC */ 129 #define PORT_S3C2400 67 130 131 /* M32R SIO */ 132 #define PORT_M32R_SIO 68 133 134 /*Digi jsm */ 135 #define PORT_JSM 69 136 137 /* SUN4V Hypervisor Console */ 138 #define PORT_SUNHV 72 139 140 #define PORT_S3C2412 73 141 142 /* Xilinx uartlite */ 143 #define PORT_UARTLITE 74 144 145 /* Blackfin bf5xx */ 146 #define PORT_BFIN 75 147 148 /* Broadcom SB1250, etc. SOC */ 149 #define PORT_SB1250_DUART 77 150 151 /* Freescale ColdFire */ 152 #define PORT_MCF 78 153 154 /* Blackfin SPORT */ 155 #define PORT_BFIN_SPORT 79 156 157 /* MN10300 on-chip UART numbers */ 158 #define PORT_MN10300 80 159 #define PORT_MN10300_CTS 81 160 161 #define PORT_SC26XX 82 162 163 /* SH-SCI */ 164 #define PORT_SCIFA 83 165 166 #define PORT_S3C6400 84 167 168 /* NWPSERIAL, now removed */ 169 #define PORT_NWPSERIAL 85 170 171 /* MAX3100 */ 172 #define PORT_MAX3100 86 173 174 /* Timberdale UART */ 175 #define PORT_TIMBUART 87 176 177 /* Qualcomm MSM SoCs */ 178 #define PORT_MSM 88 179 180 /* BCM63xx family SoCs */ 181 #define PORT_BCM63XX 89 182 183 /* Aeroflex Gaisler GRLIB APBUART */ 184 #define PORT_APBUART 90 185 186 /* Altera UARTs */ 187 #define PORT_ALTERA_JTAGUART 91 188 #define PORT_ALTERA_UART 92 189 190 /* SH-SCI */ 191 #define PORT_SCIFB 93 192 193 /* MAX310X */ 194 #define PORT_MAX310X 94 195 196 /* TI DA8xx/66AK2x */ 197 #define PORT_DA830 95 198 199 /* TI OMAP-UART */ 200 #define PORT_OMAP 96 201 202 /* VIA VT8500 SoC */ 203 #define PORT_VT8500 97 204 205 /* Cadence (Xilinx Zynq) UART */ 206 #define PORT_XUARTPS 98 207 208 /* Atheros AR933X SoC */ 209 #define PORT_AR933X 99 210 211 /* ARC (Synopsys) on-chip UART */ 212 #define PORT_ARC 101 213 214 /* Rocketport EXPRESS/INFINITY */ 215 #define PORT_RP2 102 216 217 /* Freescale lpuart */ 218 #define PORT_LPUART 103 219 220 /* SH-SCI */ 221 #define PORT_HSCIF 104 222 223 /* ST ASC type numbers */ 224 #define PORT_ASC 105 225 226 /* Tilera TILE-Gx UART */ 227 #define PORT_TILEGX 106 228 229 /* MEN 16z135 UART */ 230 #define PORT_MEN_Z135 107 231 232 /* SC16IS74xx */ 233 #define PORT_SC16IS7XX 108 234 235 /* MESON */ 236 #define PORT_MESON 109 237 238 /* Conexant Digicolor */ 239 #define PORT_DIGICOLOR 110 240 241 /* SPRD SERIAL */ 242 #define PORT_SPRD 111 243 244 /* Cris v10 / v32 SoC */ 245 #define PORT_CRIS 112 246 247 /* STM32 USART */ 248 #define PORT_STM32 113 249 250 /* MVEBU UART */ 251 #define PORT_MVEBU 114 252 253 /* Microchip PIC32 UART */ 254 #define PORT_PIC32 115 255 256 /* MPS2 UART */ 257 #define PORT_MPS2UART 116 258 259 /* MediaTek BTIF */ 260 #define PORT_MTK_BTIF 117 261 262 /* RDA UART */ 263 #define PORT_RDA 118 264 265 /* Socionext Milbeaut UART */ 266 #define PORT_MLB_USIO 119 267 268 /* SiFive UART */ 269 #define PORT_SIFIVE_V0 120 270 271 /* Sunix UART */ 272 #define PORT_SUNIX 121 273 274 /* Freescale LINFlexD UART */ 275 #define PORT_LINFLEXUART 122 276 277 #endif /* LINUX_SERIAL_CORE_H */