1 /*
2 * Copyright (c) 2010 The WebM project authors. All Rights Reserved.
3 *
4 * Use of this source code is governed by a BSD-style license
5 * that can be found in the LICENSE file in the root of the source
6 * tree. An additional intellectual property rights grant can be found
7 * in the file PATENTS. All contributing project authors may
8 * be found in the AUTHORS file in the root of the source tree.
9 */
10
11 #ifndef VPX_VPX_PORTS_X86_H_
12 #define VPX_VPX_PORTS_X86_H_
13 #include <stdlib.h>
14
15 #if defined(_MSC_VER)
16 #include <intrin.h> /* For __cpuidex, __rdtsc */
17 #endif
18
19 #include "vpx_config.h"
20 #include "vpx/vpx_integer.h"
21
22 #ifdef __cplusplus
23 extern "C" {
24 #endif
25
26 typedef enum {
27 VPX_CPU_UNKNOWN = -1,
28 VPX_CPU_AMD,
29 VPX_CPU_AMD_OLD,
30 VPX_CPU_CENTAUR,
31 VPX_CPU_CYRIX,
32 VPX_CPU_INTEL,
33 VPX_CPU_NEXGEN,
34 VPX_CPU_NSC,
35 VPX_CPU_RISE,
36 VPX_CPU_SIS,
37 VPX_CPU_TRANSMETA,
38 VPX_CPU_TRANSMETA_OLD,
39 VPX_CPU_UMC,
40 VPX_CPU_VIA,
41
42 VPX_CPU_LAST
43 } vpx_cpu_t;
44
45 #if defined(__GNUC__) && __GNUC__ || defined(__ANDROID__)
46 #if VPX_ARCH_X86_64
47 #define cpuid(func, func2, ax, bx, cx, dx) \
48 __asm__ __volatile__("cpuid \n\t" \
49 : "=a"(ax), "=b"(bx), "=c"(cx), "=d"(dx) \
50 : "a"(func), "c"(func2));
51 #else
52 #define cpuid(func, func2, ax, bx, cx, dx) \
53 __asm__ __volatile__( \
54 "mov %%ebx, %%edi \n\t" \
55 "cpuid \n\t" \
56 "xchg %%edi, %%ebx \n\t" \
57 : "=a"(ax), "=D"(bx), "=c"(cx), "=d"(dx) \
58 : "a"(func), "c"(func2));
59 #endif
60 #elif defined(__SUNPRO_C) || \
61 defined(__SUNPRO_CC) /* end __GNUC__ or __ANDROID__*/
62 #if VPX_ARCH_X86_64
63 #define cpuid(func, func2, ax, bx, cx, dx) \
64 asm volatile( \
65 "xchg %rsi, %rbx \n\t" \
66 "cpuid \n\t" \
67 "movl %ebx, %edi \n\t" \
68 "xchg %rsi, %rbx \n\t" \
69 : "=a"(ax), "=D"(bx), "=c"(cx), "=d"(dx) \
70 : "a"(func), "c"(func2));
71 #else
72 #define cpuid(func, func2, ax, bx, cx, dx) \
73 asm volatile( \
74 "pushl %ebx \n\t" \
75 "cpuid \n\t" \
76 "movl %ebx, %edi \n\t" \
77 "popl %ebx \n\t" \
78 : "=a"(ax), "=D"(bx), "=c"(cx), "=d"(dx) \
79 : "a"(func), "c"(func2));
80 #endif
81 #else /* end __SUNPRO__ */
82 #if VPX_ARCH_X86_64
83 #if defined(_MSC_VER) && _MSC_VER > 1500
84 #define cpuid(func, func2, a, b, c, d) \
85 do { \
86 int regs[4]; \
87 __cpuidex(regs, func, func2); \
88 a = regs[0]; \
89 b = regs[1]; \
90 c = regs[2]; \
91 d = regs[3]; \
92 } while (0)
93 #else
94 #define cpuid(func, func2, a, b, c, d) \
95 do { \
96 int regs[4]; \
97 __cpuid(regs, func); \
98 a = regs[0]; \
99 b = regs[1]; \
100 c = regs[2]; \
101 d = regs[3]; \
102 } while (0)
103 #endif
104 #else
105 #define cpuid(func, func2, a, b, c, d) \
106 __asm mov eax, func __asm mov ecx, func2 __asm cpuid __asm mov a, \
107 eax __asm mov b, ebx __asm mov c, ecx __asm mov d, edx
108 #endif
109 #endif /* end others */
110
111 // NaCl has no support for xgetbv or the raw opcode.
112 #if !defined(__native_client__) && (defined(__i386__) || defined(__x86_64__))
xgetbv(void)113 static INLINE uint64_t xgetbv(void) {
114 const uint32_t ecx = 0;
115 uint32_t eax, edx;
116 // Use the raw opcode for xgetbv for compatibility with older toolchains.
117 __asm__ volatile(".byte 0x0f, 0x01, 0xd0\n"
118 : "=a"(eax), "=d"(edx)
119 : "c"(ecx));
120 return ((uint64_t)edx << 32) | eax;
121 }
122 #elif (defined(_M_X64) || defined(_M_IX86)) && defined(_MSC_FULL_VER) && \
123 _MSC_FULL_VER >= 160040219 // >= VS2010 SP1
124 #include <immintrin.h>
125 #define xgetbv() _xgetbv(0)
126 #elif defined(_MSC_VER) && defined(_M_IX86)
xgetbv(void)127 static INLINE uint64_t xgetbv(void) {
128 uint32_t eax_, edx_;
129 __asm {
130 xor ecx, ecx // ecx = 0
131 // Use the raw opcode for xgetbv for compatibility with older toolchains.
132 __asm _emit 0x0f __asm _emit 0x01 __asm _emit 0xd0
133 mov eax_, eax
134 mov edx_, edx
135 }
136 return ((uint64_t)edx_ << 32) | eax_;
137 }
138 #else
139 #define xgetbv() 0U // no AVX for older x64 or unrecognized toolchains.
140 #endif
141
142 #if defined(_MSC_VER) && _MSC_VER >= 1700
143 #undef NOMINMAX
144 #define NOMINMAX
145 #ifndef WIN32_LEAN_AND_MEAN
146 #define WIN32_LEAN_AND_MEAN
147 #endif
148 #include <windows.h>
149 #if WINAPI_FAMILY_PARTITION(WINAPI_FAMILY_APP)
150 #define getenv(x) NULL
151 #endif
152 #endif
153
154 #define HAS_MMX 0x001
155 #define HAS_SSE 0x002
156 #define HAS_SSE2 0x004
157 #define HAS_SSE3 0x008
158 #define HAS_SSSE3 0x010
159 #define HAS_SSE4_1 0x020
160 #define HAS_AVX 0x040
161 #define HAS_AVX2 0x080
162 #define HAS_AVX512 0x100
163 #ifndef BIT
164 #define BIT(n) (1u << (n))
165 #endif
166
x86_simd_caps(void)167 static INLINE int x86_simd_caps(void) {
168 unsigned int flags = 0;
169 unsigned int mask = ~0;
170 unsigned int max_cpuid_val, reg_eax, reg_ebx, reg_ecx, reg_edx;
171 char *env;
172 (void)reg_ebx;
173
174 /* See if the CPU capabilities are being overridden by the environment */
175 env = getenv("VPX_SIMD_CAPS");
176
177 if (env && *env) return (int)strtol(env, NULL, 0);
178
179 env = getenv("VPX_SIMD_CAPS_MASK");
180
181 if (env && *env) mask = (unsigned int)strtoul(env, NULL, 0);
182
183 /* Ensure that the CPUID instruction supports extended features */
184 cpuid(0, 0, max_cpuid_val, reg_ebx, reg_ecx, reg_edx);
185
186 if (max_cpuid_val < 1) return 0;
187
188 /* Get the standard feature flags */
189 cpuid(1, 0, reg_eax, reg_ebx, reg_ecx, reg_edx);
190
191 if (reg_edx & BIT(23)) flags |= HAS_MMX;
192
193 if (reg_edx & BIT(25)) flags |= HAS_SSE; /* aka xmm */
194
195 if (reg_edx & BIT(26)) flags |= HAS_SSE2; /* aka wmt */
196
197 if (reg_ecx & BIT(0)) flags |= HAS_SSE3;
198
199 if (reg_ecx & BIT(9)) flags |= HAS_SSSE3;
200
201 if (reg_ecx & BIT(19)) flags |= HAS_SSE4_1;
202
203 // bits 27 (OSXSAVE) & 28 (256-bit AVX)
204 if ((reg_ecx & (BIT(27) | BIT(28))) == (BIT(27) | BIT(28))) {
205 // Check for OS-support of YMM state. Necessary for AVX and AVX2.
206 if ((xgetbv() & 0x6) == 0x6) {
207 flags |= HAS_AVX;
208
209 if (max_cpuid_val >= 7) {
210 /* Get the leaf 7 feature flags. Needed to check for AVX2 support */
211 cpuid(7, 0, reg_eax, reg_ebx, reg_ecx, reg_edx);
212
213 if (reg_ebx & BIT(5)) flags |= HAS_AVX2;
214
215 // bits 16 (AVX-512F) & 17 (AVX-512DQ) & 28 (AVX-512CD) &
216 // 30 (AVX-512BW) & 32 (AVX-512VL)
217 if ((reg_ebx & (BIT(16) | BIT(17) | BIT(28) | BIT(30) | BIT(31))) ==
218 (BIT(16) | BIT(17) | BIT(28) | BIT(30) | BIT(31))) {
219 // Check for OS-support of ZMM and YMM state. Necessary for AVX-512.
220 if ((xgetbv() & 0xe6) == 0xe6) flags |= HAS_AVX512;
221 }
222 }
223 }
224 }
225
226 return flags & mask;
227 }
228
229 // Fine-Grain Measurement Functions
230 //
231 // If you are timing a small region of code, access the timestamp counter
232 // (TSC) via:
233 //
234 // unsigned int start = x86_tsc_start();
235 // ...
236 // unsigned int end = x86_tsc_end();
237 // unsigned int diff = end - start;
238 //
239 // The start/end functions introduce a few more instructions than using
240 // x86_readtsc directly, but prevent the CPU's out-of-order execution from
241 // affecting the measurement (by having earlier/later instructions be evaluated
242 // in the time interval). See the white paper, "How to Benchmark Code
243 // Execution Times on Intel® IA-32 and IA-64 Instruction Set Architectures" by
244 // Gabriele Paoloni for more information.
245 //
246 // If you are timing a large function (CPU time > a couple of seconds), use
247 // x86_readtsc64 to read the timestamp counter in a 64-bit integer. The
248 // out-of-order leakage that can occur is minimal compared to total runtime.
x86_readtsc(void)249 static INLINE unsigned int x86_readtsc(void) {
250 #if defined(__GNUC__) && __GNUC__
251 unsigned int tsc;
252 __asm__ __volatile__("rdtsc\n\t" : "=a"(tsc) :);
253 return tsc;
254 #elif defined(__SUNPRO_C) || defined(__SUNPRO_CC)
255 unsigned int tsc;
256 asm volatile("rdtsc\n\t" : "=a"(tsc) :);
257 return tsc;
258 #else
259 #if VPX_ARCH_X86_64
260 return (unsigned int)__rdtsc();
261 #else
262 __asm rdtsc;
263 #endif
264 #endif
265 }
266 // 64-bit CPU cycle counter
x86_readtsc64(void)267 static INLINE uint64_t x86_readtsc64(void) {
268 #if defined(__GNUC__) && __GNUC__
269 uint32_t hi, lo;
270 __asm__ __volatile__("rdtsc" : "=a"(lo), "=d"(hi));
271 return ((uint64_t)hi << 32) | lo;
272 #elif defined(__SUNPRO_C) || defined(__SUNPRO_CC)
273 uint_t hi, lo;
274 asm volatile("rdtsc\n\t" : "=a"(lo), "=d"(hi));
275 return ((uint64_t)hi << 32) | lo;
276 #else
277 #if VPX_ARCH_X86_64
278 return (uint64_t)__rdtsc();
279 #else
280 __asm rdtsc;
281 #endif
282 #endif
283 }
284
285 // 32-bit CPU cycle counter with a partial fence against out-of-order execution.
x86_readtscp(void)286 static INLINE unsigned int x86_readtscp(void) {
287 #if defined(__GNUC__) && __GNUC__
288 unsigned int tscp;
289 __asm__ __volatile__("rdtscp\n\t" : "=a"(tscp) :);
290 return tscp;
291 #elif defined(__SUNPRO_C) || defined(__SUNPRO_CC)
292 unsigned int tscp;
293 asm volatile("rdtscp\n\t" : "=a"(tscp) :);
294 return tscp;
295 #elif defined(_MSC_VER)
296 unsigned int ui;
297 return (unsigned int)__rdtscp(&ui);
298 #else
299 #if VPX_ARCH_X86_64
300 return (unsigned int)__rdtscp();
301 #else
302 __asm rdtscp;
303 #endif
304 #endif
305 }
306
x86_tsc_start(void)307 static INLINE unsigned int x86_tsc_start(void) {
308 unsigned int reg_eax, reg_ebx, reg_ecx, reg_edx;
309 cpuid(0, 0, reg_eax, reg_ebx, reg_ecx, reg_edx);
310 return x86_readtsc();
311 }
312
x86_tsc_end(void)313 static INLINE unsigned int x86_tsc_end(void) {
314 uint32_t v = x86_readtscp();
315 unsigned int reg_eax, reg_ebx, reg_ecx, reg_edx;
316 cpuid(0, 0, reg_eax, reg_ebx, reg_ecx, reg_edx);
317 return v;
318 }
319
320 #if defined(__GNUC__) && __GNUC__
321 #define x86_pause_hint() __asm__ __volatile__("pause \n\t")
322 #elif defined(__SUNPRO_C) || defined(__SUNPRO_CC)
323 #define x86_pause_hint() asm volatile("pause \n\t")
324 #else
325 #if VPX_ARCH_X86_64
326 #define x86_pause_hint() _mm_pause();
327 #else
328 #define x86_pause_hint() __asm pause
329 #endif
330 #endif
331
332 #if defined(__GNUC__) && __GNUC__
x87_set_control_word(unsigned short mode)333 static void x87_set_control_word(unsigned short mode) {
334 __asm__ __volatile__("fldcw %0" : : "m"(*&mode));
335 }
x87_get_control_word(void)336 static unsigned short x87_get_control_word(void) {
337 unsigned short mode;
338 __asm__ __volatile__("fstcw %0\n\t" : "=m"(*&mode) :);
339 return mode;
340 }
341 #elif defined(__SUNPRO_C) || defined(__SUNPRO_CC)
x87_set_control_word(unsigned short mode)342 static void x87_set_control_word(unsigned short mode) {
343 asm volatile("fldcw %0" : : "m"(*&mode));
344 }
x87_get_control_word(void)345 static unsigned short x87_get_control_word(void) {
346 unsigned short mode;
347 asm volatile("fstcw %0\n\t" : "=m"(*&mode) :);
348 return mode;
349 }
350 #elif VPX_ARCH_X86_64
351 /* No fldcw intrinsics on Windows x64, punt to external asm */
352 extern void vpx_winx64_fldcw(unsigned short mode);
353 extern unsigned short vpx_winx64_fstcw(void);
354 #define x87_set_control_word vpx_winx64_fldcw
355 #define x87_get_control_word vpx_winx64_fstcw
356 #else
x87_set_control_word(unsigned short mode)357 static void x87_set_control_word(unsigned short mode) {
358 __asm { fldcw mode }
359 }
x87_get_control_word(void)360 static unsigned short x87_get_control_word(void) {
361 unsigned short mode;
362 __asm { fstcw mode }
363 return mode;
364 }
365 #endif
366
x87_set_double_precision(void)367 static INLINE unsigned int x87_set_double_precision(void) {
368 unsigned int mode = x87_get_control_word();
369 // Intel 64 and IA-32 Architectures Developer's Manual: Vol. 1
370 // https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-1-manual.pdf
371 // 8.1.5.2 Precision Control Field
372 // Bits 8 and 9 (0x300) of the x87 FPU Control Word ("Precision Control")
373 // determine the number of bits used in floating point calculations. To match
374 // later SSE instructions restrict x87 operations to Double Precision (0x200).
375 // Precision PC Field
376 // Single Precision (24-Bits) 00B
377 // Reserved 01B
378 // Double Precision (53-Bits) 10B
379 // Extended Precision (64-Bits) 11B
380 x87_set_control_word((mode & ~0x300) | 0x200);
381 return mode;
382 }
383
384 #ifdef __cplusplus
385 } // extern "C"
386 #endif
387
388 #endif // VPX_VPX_PORTS_X86_H_
389