1 /**************************************************************************
2 *
3 * Copyright 2007 VMware, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28
29 /**
30 * @file
31 *
32 * Abstract graphics pipe state objects.
33 *
34 * Basic notes:
35 * 1. Want compact representations, so we use bitfields.
36 * 2. Put bitfields before other (GLfloat) fields.
37 * 3. enum bitfields need to be at least one bit extra in size so the most
38 * significant bit is zero. MSVC treats enums as signed so if the high
39 * bit is set, the value will be interpreted as a negative number.
40 * That causes trouble in various places.
41 */
42
43
44 #ifndef PIPE_STATE_H
45 #define PIPE_STATE_H
46
47 #include "p_compiler.h"
48 #include "p_defines.h"
49 #include "p_format.h"
50
51
52 #ifdef __cplusplus
53 extern "C" {
54 #endif
55
56
57 /**
58 * Implementation limits
59 */
60 #define PIPE_MAX_ATTRIBS 32
61 #define PIPE_MAX_CLIP_PLANES 8
62 #define PIPE_MAX_COLOR_BUFS 8
63 #define PIPE_MAX_CONSTANT_BUFFERS 32
64 #define PIPE_MAX_SAMPLERS 32
65 #define PIPE_MAX_SHADER_INPUTS 80 /* 32 GENERIC + 32 PATCH + 16 others */
66 #define PIPE_MAX_SHADER_OUTPUTS 80 /* 32 GENERIC + 32 PATCH + 16 others */
67 #define PIPE_MAX_SHADER_SAMPLER_VIEWS 128
68 #define PIPE_MAX_SHADER_BUFFERS 32
69 #define PIPE_MAX_SHADER_IMAGES 32
70 #define PIPE_MAX_TEXTURE_LEVELS 16
71 #define PIPE_MAX_SO_BUFFERS 4
72 #define PIPE_MAX_SO_OUTPUTS 64
73 #define PIPE_MAX_VIEWPORTS 16
74 #define PIPE_MAX_CLIP_OR_CULL_DISTANCE_COUNT 8
75 #define PIPE_MAX_CLIP_OR_CULL_DISTANCE_ELEMENT_COUNT 2
76 #define PIPE_MAX_WINDOW_RECTANGLES 8
77 #define PIPE_MAX_SAMPLE_LOCATION_GRID_SIZE 4
78
79 #define PIPE_MAX_HW_ATOMIC_BUFFERS 32
80 #define PIPE_MAX_VERTEX_STREAMS 4
81
82 struct pipe_reference
83 {
84 int32_t count; /* atomic */
85 };
86
87
88
89 /**
90 * Primitive (point/line/tri) rasterization info
91 */
92 struct pipe_rasterizer_state
93 {
94 unsigned flatshade:1;
95 unsigned light_twoside:1;
96 unsigned clamp_vertex_color:1;
97 unsigned clamp_fragment_color:1;
98 unsigned front_ccw:1;
99 unsigned cull_face:2; /**< PIPE_FACE_x */
100 unsigned fill_front:2; /**< PIPE_POLYGON_MODE_x */
101 unsigned fill_back:2; /**< PIPE_POLYGON_MODE_x */
102 unsigned offset_point:1;
103 unsigned offset_line:1;
104 unsigned offset_tri:1;
105 unsigned scissor:1;
106 unsigned poly_smooth:1;
107 unsigned poly_stipple_enable:1;
108 unsigned point_smooth:1;
109 unsigned sprite_coord_mode:1; /**< PIPE_SPRITE_COORD_ */
110 unsigned point_quad_rasterization:1; /** points rasterized as quads or points */
111 unsigned point_tri_clip:1; /** large points clipped as tris or points */
112 unsigned point_size_per_vertex:1; /**< size computed in vertex shader */
113 unsigned multisample:1; /* XXX maybe more ms state in future */
114 unsigned force_persample_interp:1;
115 unsigned line_smooth:1;
116 unsigned line_stipple_enable:1;
117 unsigned line_last_pixel:1;
118 unsigned conservative_raster_mode:2; /**< PIPE_CONSERVATIVE_RASTER_x */
119
120 /**
121 * Use the first vertex of a primitive as the provoking vertex for
122 * flat shading.
123 */
124 unsigned flatshade_first:1;
125
126 unsigned half_pixel_center:1;
127 unsigned bottom_edge_rule:1;
128
129 /*
130 * Conservative rasterization subpixel precision bias in bits
131 */
132 unsigned subpixel_precision_x:4;
133 unsigned subpixel_precision_y:4;
134
135 /**
136 * When true, rasterization is disabled and no pixels are written.
137 * This only makes sense with the Stream Out functionality.
138 */
139 unsigned rasterizer_discard:1;
140
141 /**
142 * Exposed by PIPE_CAP_TILE_RASTER_ORDER. When true,
143 * tile_raster_order_increasing_* indicate the order that the rasterizer
144 * should render tiles, to meet the requirements of
145 * GL_MESA_tile_raster_order.
146 */
147 unsigned tile_raster_order_fixed:1;
148 unsigned tile_raster_order_increasing_x:1;
149 unsigned tile_raster_order_increasing_y:1;
150
151 /**
152 * When false, depth clipping is disabled and the depth value will be
153 * clamped later at the per-pixel level before depth testing.
154 * This depends on PIPE_CAP_DEPTH_CLIP_DISABLE.
155 *
156 * If PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE is unsupported, depth_clip_near
157 * is equal to depth_clip_far.
158 */
159 unsigned depth_clip_near:1;
160 unsigned depth_clip_far:1;
161
162 /**
163 * When true clip space in the z axis goes from [0..1] (D3D). When false
164 * [-1, 1] (GL).
165 *
166 * NOTE: D3D will always use depth clamping.
167 */
168 unsigned clip_halfz:1;
169
170 /**
171 * When true do not scale offset_units and use same rules for unorm and
172 * float depth buffers (D3D9). When false use GL/D3D1X behaviour.
173 * This depends on PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED.
174 */
175 unsigned offset_units_unscaled:1;
176
177 /**
178 * Enable bits for clipping half-spaces.
179 * This applies to both user clip planes and shader clip distances.
180 * Note that if the bound shader exports any clip distances, these
181 * replace all user clip planes, and clip half-spaces enabled here
182 * but not written by the shader count as disabled.
183 */
184 unsigned clip_plane_enable:PIPE_MAX_CLIP_PLANES;
185
186 unsigned line_stipple_factor:8; /**< [1..256] actually */
187 unsigned line_stipple_pattern:16;
188
189 /**
190 * Replace the given TEXCOORD inputs with point coordinates, max. 8 inputs.
191 * If TEXCOORD (including PCOORD) are unsupported, replace GENERIC inputs
192 * instead. Max. 9 inputs: 8x GENERIC to emulate TEXCOORD, and 1x GENERIC
193 * to emulate PCOORD.
194 */
195 uint16_t sprite_coord_enable; /* 0-7: TEXCOORD/GENERIC, 8: PCOORD */
196
197 float line_width;
198 float point_size; /**< used when no per-vertex size */
199 float offset_units;
200 float offset_scale;
201 float offset_clamp;
202 float conservative_raster_dilate;
203 };
204
205
206 struct pipe_poly_stipple
207 {
208 unsigned stipple[32];
209 };
210
211
212 struct pipe_viewport_state
213 {
214 float scale[3];
215 float translate[3];
216 enum pipe_viewport_swizzle swizzle_x:3;
217 enum pipe_viewport_swizzle swizzle_y:3;
218 enum pipe_viewport_swizzle swizzle_z:3;
219 enum pipe_viewport_swizzle swizzle_w:3;
220 };
221
222
223 struct pipe_scissor_state
224 {
225 unsigned minx:16;
226 unsigned miny:16;
227 unsigned maxx:16;
228 unsigned maxy:16;
229 };
230
231
232 struct pipe_clip_state
233 {
234 float ucp[PIPE_MAX_CLIP_PLANES][4];
235 };
236
237 /**
238 * A single output for vertex transform feedback.
239 */
240 struct pipe_stream_output
241 {
242 unsigned register_index:6; /**< 0 to 63 (OUT index) */
243 unsigned start_component:2; /** 0 to 3 */
244 unsigned num_components:3; /** 1 to 4 */
245 unsigned output_buffer:3; /**< 0 to PIPE_MAX_SO_BUFFERS */
246 unsigned dst_offset:16; /**< offset into the buffer in dwords */
247 unsigned stream:2; /**< 0 to 3 */
248 };
249
250 /**
251 * Stream output for vertex transform feedback.
252 */
253 struct pipe_stream_output_info
254 {
255 unsigned num_outputs;
256 /** stride for an entire vertex for each buffer in dwords */
257 uint16_t stride[PIPE_MAX_SO_BUFFERS];
258
259 /**
260 * Array of stream outputs, in the order they are to be written in.
261 * Selected components are tightly packed into the output buffer.
262 */
263 struct pipe_stream_output output[PIPE_MAX_SO_OUTPUTS];
264 };
265
266 /**
267 * The 'type' parameter identifies whether the shader state contains TGSI
268 * tokens, etc. If the driver returns 'PIPE_SHADER_IR_TGSI' for the
269 * 'PIPE_SHADER_CAP_PREFERRED_IR' shader param, the ir will *always* be
270 * 'PIPE_SHADER_IR_TGSI' and the tokens ptr will be valid. If the driver
271 * requests a different 'pipe_shader_ir' type, then it must check the 'type'
272 * enum to see if it is getting TGSI tokens or its preferred IR.
273 *
274 * TODO pipe_compute_state should probably get similar treatment to handle
275 * multiple IR's in a cleaner way..
276 *
277 * NOTE: since it is expected that the consumer will want to perform
278 * additional passes on the nir_shader, the driver takes ownership of
279 * the nir_shader. If state trackers need to hang on to the IR (for
280 * example, variant management), it should use nir_shader_clone().
281 */
282 struct pipe_shader_state
283 {
284 enum pipe_shader_ir type;
285 /* TODO move tokens into union. */
286 const struct tgsi_token *tokens;
287 union {
288 void *native;
289 void *nir;
290 } ir;
291 struct pipe_stream_output_info stream_output;
292 };
293
294 static inline void
pipe_shader_state_from_tgsi(struct pipe_shader_state * state,const struct tgsi_token * tokens)295 pipe_shader_state_from_tgsi(struct pipe_shader_state *state,
296 const struct tgsi_token *tokens)
297 {
298 state->type = PIPE_SHADER_IR_TGSI;
299 state->tokens = tokens;
300 memset(&state->stream_output, 0, sizeof(state->stream_output));
301 }
302
303 struct pipe_depth_state
304 {
305 unsigned enabled:1; /**< depth test enabled? */
306 unsigned writemask:1; /**< allow depth buffer writes? */
307 unsigned func:3; /**< depth test func (PIPE_FUNC_x) */
308 unsigned bounds_test:1; /**< depth bounds test enabled? */
309 float bounds_min; /**< minimum depth bound */
310 float bounds_max; /**< maximum depth bound */
311 };
312
313
314 struct pipe_stencil_state
315 {
316 unsigned enabled:1; /**< stencil[0]: stencil enabled, stencil[1]: two-side enabled */
317 unsigned func:3; /**< PIPE_FUNC_x */
318 unsigned fail_op:3; /**< PIPE_STENCIL_OP_x */
319 unsigned zpass_op:3; /**< PIPE_STENCIL_OP_x */
320 unsigned zfail_op:3; /**< PIPE_STENCIL_OP_x */
321 unsigned valuemask:8;
322 unsigned writemask:8;
323 };
324
325
326 struct pipe_alpha_state
327 {
328 unsigned enabled:1;
329 unsigned func:3; /**< PIPE_FUNC_x */
330 float ref_value; /**< reference value */
331 };
332
333
334 struct pipe_depth_stencil_alpha_state
335 {
336 struct pipe_depth_state depth;
337 struct pipe_stencil_state stencil[2]; /**< [0] = front, [1] = back */
338 struct pipe_alpha_state alpha;
339 };
340
341
342 struct pipe_rt_blend_state
343 {
344 unsigned blend_enable:1;
345
346 unsigned rgb_func:3; /**< PIPE_BLEND_x */
347 unsigned rgb_src_factor:5; /**< PIPE_BLENDFACTOR_x */
348 unsigned rgb_dst_factor:5; /**< PIPE_BLENDFACTOR_x */
349
350 unsigned alpha_func:3; /**< PIPE_BLEND_x */
351 unsigned alpha_src_factor:5; /**< PIPE_BLENDFACTOR_x */
352 unsigned alpha_dst_factor:5; /**< PIPE_BLENDFACTOR_x */
353
354 unsigned colormask:4; /**< bitmask of PIPE_MASK_R/G/B/A */
355 };
356
357
358 struct pipe_blend_state
359 {
360 unsigned independent_blend_enable:1;
361 unsigned logicop_enable:1;
362 unsigned logicop_func:4; /**< PIPE_LOGICOP_x */
363 unsigned dither:1;
364 unsigned alpha_to_coverage:1;
365 unsigned alpha_to_coverage_dither:1;
366 unsigned alpha_to_one:1;
367 unsigned max_rt:3; /* index of max rt, Ie. # of cbufs minus 1 */
368 struct pipe_rt_blend_state rt[PIPE_MAX_COLOR_BUFS];
369 };
370
371
372 struct pipe_blend_color
373 {
374 float color[4];
375 };
376
377
378 struct pipe_stencil_ref
379 {
380 ubyte ref_value[2];
381 };
382
383
384 /**
385 * Note that pipe_surfaces are "texture views for rendering"
386 * and so in the case of ARB_framebuffer_no_attachment there
387 * is no pipe_surface state available such that we may
388 * extract the number of samples and layers.
389 */
390 struct pipe_framebuffer_state
391 {
392 uint16_t width, height;
393 uint16_t layers; /**< Number of layers in a no-attachment framebuffer */
394 ubyte samples; /**< Number of samples in a no-attachment framebuffer */
395
396 /** multiple color buffers for multiple render targets */
397 ubyte nr_cbufs;
398 struct pipe_surface *cbufs[PIPE_MAX_COLOR_BUFS];
399
400 struct pipe_surface *zsbuf; /**< Z/stencil buffer */
401 };
402
403
404 /**
405 * Texture sampler state.
406 */
407 struct pipe_sampler_state
408 {
409 unsigned wrap_s:3; /**< PIPE_TEX_WRAP_x */
410 unsigned wrap_t:3; /**< PIPE_TEX_WRAP_x */
411 unsigned wrap_r:3; /**< PIPE_TEX_WRAP_x */
412 unsigned min_img_filter:1; /**< PIPE_TEX_FILTER_x */
413 unsigned min_mip_filter:2; /**< PIPE_TEX_MIPFILTER_x */
414 unsigned mag_img_filter:1; /**< PIPE_TEX_FILTER_x */
415 unsigned compare_mode:1; /**< PIPE_TEX_COMPARE_x */
416 unsigned compare_func:3; /**< PIPE_FUNC_x */
417 unsigned normalized_coords:1; /**< Are coords normalized to [0,1]? */
418 unsigned max_anisotropy:5;
419 unsigned seamless_cube_map:1;
420 float lod_bias; /**< LOD/lambda bias */
421 float min_lod, max_lod; /**< LOD clamp range, after bias */
422 union pipe_color_union border_color;
423 };
424
425 union pipe_surface_desc {
426 struct {
427 unsigned level;
428 unsigned first_layer:16;
429 unsigned last_layer:16;
430 } tex;
431 struct {
432 unsigned first_element;
433 unsigned last_element;
434 } buf;
435 };
436
437 /**
438 * A view into a texture that can be bound to a color render target /
439 * depth stencil attachment point.
440 */
441 struct pipe_surface
442 {
443 struct pipe_reference reference;
444 enum pipe_format format:16;
445 unsigned writable:1; /**< writable shader resource */
446 struct pipe_resource *texture; /**< resource into which this is a view */
447 struct pipe_context *context; /**< context this surface belongs to */
448
449 /* XXX width/height should be removed */
450 uint16_t width; /**< logical width in pixels */
451 uint16_t height; /**< logical height in pixels */
452
453 /**
454 * Number of samples for the surface. This will be 0 if rendering
455 * should use the resource's nr_samples, or another value if the resource
456 * is bound using FramebufferTexture2DMultisampleEXT.
457 */
458 unsigned nr_samples:8;
459
460 union pipe_surface_desc u;
461 };
462
463
464 /**
465 * A view into a texture that can be bound to a shader stage.
466 */
467 struct pipe_sampler_view
468 {
469 struct pipe_reference reference;
470 enum pipe_format format:15; /**< typed PIPE_FORMAT_x */
471 enum pipe_texture_target target:5; /**< PIPE_TEXTURE_x */
472 unsigned swizzle_r:3; /**< PIPE_SWIZZLE_x for red component */
473 unsigned swizzle_g:3; /**< PIPE_SWIZZLE_x for green component */
474 unsigned swizzle_b:3; /**< PIPE_SWIZZLE_x for blue component */
475 unsigned swizzle_a:3; /**< PIPE_SWIZZLE_x for alpha component */
476 struct pipe_resource *texture; /**< texture into which this is a view */
477 struct pipe_context *context; /**< context this view belongs to */
478 union {
479 struct {
480 unsigned first_layer:16; /**< first layer to use for array textures */
481 unsigned last_layer:16; /**< last layer to use for array textures */
482 unsigned first_level:8; /**< first mipmap level to use */
483 unsigned last_level:8; /**< last mipmap level to use */
484 } tex;
485 struct {
486 unsigned offset; /**< offset in bytes */
487 unsigned size; /**< size of the readable sub-range in bytes */
488 } buf;
489 } u;
490 };
491
492
493 /**
494 * A description of a buffer or texture image that can be bound to a shader
495 * stage.
496 */
497 struct pipe_image_view
498 {
499 struct pipe_resource *resource; /**< resource into which this is a view */
500 enum pipe_format format; /**< typed PIPE_FORMAT_x */
501 uint16_t access; /**< PIPE_IMAGE_ACCESS_x */
502 uint16_t shader_access; /**< PIPE_IMAGE_ACCESS_x */
503
504 union {
505 struct {
506 unsigned first_layer:16; /**< first layer to use for array textures */
507 unsigned last_layer:16; /**< last layer to use for array textures */
508 unsigned level:8; /**< mipmap level to use */
509 } tex;
510 struct {
511 unsigned offset; /**< offset in bytes */
512 unsigned size; /**< size of the accessible sub-range in bytes */
513 } buf;
514 } u;
515 };
516
517
518 /**
519 * Subregion of 1D/2D/3D image resource.
520 */
521 struct pipe_box
522 {
523 /* Fields only used by textures use int16_t instead of int.
524 * x and width are used by buffers, so they need the full 32-bit range.
525 */
526 int x;
527 int16_t y;
528 int16_t z;
529 int width;
530 int16_t height;
531 int16_t depth;
532 };
533
534
535 /**
536 * A memory object/resource such as a vertex buffer or texture.
537 */
538 struct pipe_resource
539 {
540 struct pipe_reference reference;
541
542 unsigned width0; /**< Used by both buffers and textures. */
543 uint16_t height0; /* Textures: The maximum height/depth/array_size is 16k. */
544 uint16_t depth0;
545 uint16_t array_size;
546
547 enum pipe_format format:16; /**< PIPE_FORMAT_x */
548 enum pipe_texture_target target:8; /**< PIPE_TEXTURE_x */
549 unsigned last_level:8; /**< Index of last mipmap level present/defined */
550
551 /** Number of samples determining quality, driving rasterizer, shading,
552 * and framebuffer.
553 */
554 unsigned nr_samples:8;
555
556 /** Multiple samples within a pixel can have the same value.
557 * nr_storage_samples determines how many slots for different values
558 * there are per pixel. Only color buffers can set this lower than
559 * nr_samples.
560 */
561 unsigned nr_storage_samples:8;
562
563 unsigned usage:8; /**< PIPE_USAGE_x (not a bitmask) */
564 unsigned bind; /**< bitmask of PIPE_BIND_x */
565 unsigned flags; /**< bitmask of PIPE_RESOURCE_FLAG_x */
566
567 /**
568 * For planar images, ie. YUV EGLImage external, etc, pointer to the
569 * next plane.
570 */
571 struct pipe_resource *next;
572 /* The screen pointer should be last for optimal structure packing. */
573 struct pipe_screen *screen; /**< screen that this texture belongs to */
574 };
575
576
577 /**
578 * Transfer object. For data transfer to/from a resource.
579 */
580 struct pipe_transfer
581 {
582 struct pipe_resource *resource; /**< resource to transfer to/from */
583 unsigned level; /**< texture mipmap level */
584 enum pipe_transfer_usage usage;
585 struct pipe_box box; /**< region of the resource to access */
586 unsigned stride; /**< row stride in bytes */
587 unsigned layer_stride; /**< image/layer stride in bytes */
588 };
589
590
591 /**
592 * A vertex buffer. Typically, all the vertex data/attributes for
593 * drawing something will be in one buffer. But it's also possible, for
594 * example, to put colors in one buffer and texcoords in another.
595 */
596 struct pipe_vertex_buffer
597 {
598 uint16_t stride; /**< stride to same attrib in next vertex, in bytes */
599 bool is_user_buffer;
600 unsigned buffer_offset; /**< offset to start of data in buffer, in bytes */
601
602 union {
603 struct pipe_resource *resource; /**< the actual buffer */
604 const void *user; /**< pointer to a user buffer */
605 } buffer;
606 };
607
608
609 /**
610 * A constant buffer. A subrange of an existing buffer can be set
611 * as a constant buffer.
612 */
613 struct pipe_constant_buffer
614 {
615 struct pipe_resource *buffer; /**< the actual buffer */
616 unsigned buffer_offset; /**< offset to start of data in buffer, in bytes */
617 unsigned buffer_size; /**< how much data can be read in shader */
618 const void *user_buffer; /**< pointer to a user buffer if buffer == NULL */
619 };
620
621
622 /**
623 * An untyped shader buffer supporting loads, stores, and atomics.
624 */
625 struct pipe_shader_buffer {
626 struct pipe_resource *buffer; /**< the actual buffer */
627 unsigned buffer_offset; /**< offset to start of data in buffer, in bytes */
628 unsigned buffer_size; /**< how much data can be read in shader */
629 };
630
631
632 /**
633 * A stream output target. The structure specifies the range vertices can
634 * be written to.
635 *
636 * In addition to that, the structure should internally maintain the offset
637 * into the buffer, which should be incremented everytime something is written
638 * (appended) to it. The internal offset is buffer_offset + how many bytes
639 * have been written. The internal offset can be stored on the device
640 * and the CPU actually doesn't have to query it.
641 *
642 * Note that the buffer_size variable is actually specifying the available
643 * space in the buffer, not the size of the attached buffer.
644 * In other words in majority of cases buffer_size would simply be
645 * 'buffer->width0 - buffer_offset', so buffer_size refers to the size
646 * of the buffer left, after accounting for buffer offset, for stream output
647 * to write to.
648 *
649 * Use PIPE_QUERY_SO_STATISTICS to know how many primitives have
650 * actually been written.
651 */
652 struct pipe_stream_output_target
653 {
654 struct pipe_reference reference;
655 struct pipe_resource *buffer; /**< the output buffer */
656 struct pipe_context *context; /**< context this SO target belongs to */
657
658 unsigned buffer_offset; /**< offset where data should be written, in bytes */
659 unsigned buffer_size; /**< how much data is allowed to be written */
660 };
661
662
663 /**
664 * Information to describe a vertex attribute (position, color, etc)
665 */
666 struct pipe_vertex_element
667 {
668 /** Offset of this attribute, in bytes, from the start of the vertex */
669 unsigned src_offset:16;
670
671 /** Which vertex_buffer (as given to pipe->set_vertex_buffer()) does
672 * this attribute live in?
673 */
674 unsigned vertex_buffer_index:5;
675
676 enum pipe_format src_format:11;
677
678 /** Instance data rate divisor. 0 means this is per-vertex data,
679 * n means per-instance data used for n consecutive instances (n > 0).
680 */
681 unsigned instance_divisor;
682 };
683
684
685 struct pipe_draw_indirect_info
686 {
687 unsigned offset; /**< must be 4 byte aligned */
688 unsigned stride; /**< must be 4 byte aligned */
689 unsigned draw_count; /**< number of indirect draws */
690 unsigned indirect_draw_count_offset; /**< must be 4 byte aligned */
691
692 /* Indirect draw parameters resource is laid out as follows:
693 *
694 * if using indexed drawing:
695 * struct {
696 * uint32_t count;
697 * uint32_t instance_count;
698 * uint32_t start;
699 * int32_t index_bias;
700 * uint32_t start_instance;
701 * };
702 * otherwise:
703 * struct {
704 * uint32_t count;
705 * uint32_t instance_count;
706 * uint32_t start;
707 * uint32_t start_instance;
708 * };
709 */
710 struct pipe_resource *buffer;
711
712 /* Indirect draw count resource: If not NULL, contains a 32-bit value which
713 * is to be used as the real draw_count.
714 */
715 struct pipe_resource *indirect_draw_count;
716 };
717
718
719 /**
720 * Information to describe a draw_vbo call.
721 */
722 struct pipe_draw_info
723 {
724 ubyte index_size; /**< if 0, the draw is not indexed. */
725 enum pipe_prim_type mode:8; /**< the mode of the primitive */
726 unsigned primitive_restart:1;
727 unsigned has_user_indices:1; /**< if true, use index.user_buffer */
728 ubyte vertices_per_patch; /**< the number of vertices per patch */
729
730 /**
731 * Direct draws: start is the index of the first vertex
732 * Non-indexed indirect draws: not used
733 * Indexed indirect draws: start is added to the indirect start.
734 */
735 unsigned start;
736 unsigned count; /**< number of vertices */
737
738 unsigned start_instance; /**< first instance id */
739 unsigned instance_count; /**< number of instances */
740
741 unsigned drawid; /**< id of this draw in a multidraw */
742
743 /**
744 * For indexed drawing, these fields apply after index lookup.
745 */
746 int index_bias; /**< a bias to be added to each index */
747 unsigned min_index; /**< the min index */
748 unsigned max_index; /**< the max index */
749
750 /**
751 * Primitive restart enable/index (only applies to indexed drawing)
752 */
753 unsigned restart_index;
754
755 /* Pointers must be at the end for an optimal structure layout on 64-bit. */
756
757 /**
758 * An index buffer. When an index buffer is bound, all indices to vertices
759 * will be looked up from the buffer.
760 *
761 * If has_user_indices, use index.user, else use index.resource.
762 */
763 union {
764 struct pipe_resource *resource; /**< real buffer */
765 const void *user; /**< pointer to a user buffer */
766 } index;
767
768 struct pipe_draw_indirect_info *indirect; /**< Indirect draw. */
769
770 /**
771 * Stream output target. If not NULL, it's used to provide the 'count'
772 * parameter based on the number vertices captured by the stream output
773 * stage. (or generally, based on the number of bytes captured)
774 *
775 * Only 'mode', 'start_instance', and 'instance_count' are taken into
776 * account, all the other variables from pipe_draw_info are ignored.
777 *
778 * 'start' is implicitly 0 and 'count' is set as discussed above.
779 * The draw command is non-indexed.
780 *
781 * Note that this only provides the count. The vertex buffers must
782 * be set via set_vertex_buffers manually.
783 */
784 struct pipe_stream_output_target *count_from_stream_output;
785 };
786
787
788 /**
789 * Information to describe a blit call.
790 */
791 struct pipe_blit_info
792 {
793 struct {
794 struct pipe_resource *resource;
795 unsigned level;
796 struct pipe_box box; /**< negative width, height only legal for src */
797 /* For pipe_surface-like format casting: */
798 enum pipe_format format; /**< must be supported for sampling (src)
799 or rendering (dst), ZS is always supported */
800 } dst, src;
801
802 unsigned mask; /**< bitmask of PIPE_MASK_R/G/B/A/Z/S */
803 unsigned filter; /**< PIPE_TEX_FILTER_* */
804
805 bool scissor_enable;
806 struct pipe_scissor_state scissor;
807
808 /* Window rectangles can either be inclusive or exclusive. */
809 bool window_rectangle_include;
810 unsigned num_window_rectangles;
811 struct pipe_scissor_state window_rectangles[PIPE_MAX_WINDOW_RECTANGLES];
812
813 bool render_condition_enable; /**< whether the blit should honor the
814 current render condition */
815 bool alpha_blend; /* dst.rgb = src.rgb * src.a + dst.rgb * (1 - src.a) */
816 };
817
818 /**
819 * Information to describe a launch_grid call.
820 */
821 struct pipe_grid_info
822 {
823 /**
824 * For drivers that use PIPE_SHADER_IR_NATIVE as their prefered IR, this
825 * value will be the index of the kernel in the opencl.kernels metadata
826 * list.
827 */
828 uint32_t pc;
829
830 /**
831 * Will be used to initialize the INPUT resource, and it should point to a
832 * buffer of at least pipe_compute_state::req_input_mem bytes.
833 */
834 void *input;
835
836 /**
837 * Grid number of dimensions, 1-3, e.g. the work_dim parameter passed to
838 * clEnqueueNDRangeKernel. Note block[] and grid[] must be padded with
839 * 1 for non-used dimensions.
840 */
841 uint work_dim;
842
843 /**
844 * Determine the layout of the working block (in thread units) to be used.
845 */
846 uint block[3];
847
848 /**
849 * last_block allows disabling threads at the farthermost grid boundary.
850 * Full blocks as specified by "block" are launched, but the threads
851 * outside of "last_block" dimensions are disabled.
852 *
853 * If a block touches the grid boundary in the i-th axis, threads with
854 * THREAD_ID[i] >= last_block[i] are disabled.
855 *
856 * If last_block[i] is 0, it has the same behavior as last_block[i] = block[i],
857 * meaning no effect.
858 *
859 * It's equivalent to doing this at the beginning of the compute shader:
860 *
861 * for (i = 0; i < 3; i++) {
862 * if (block_id[i] == grid[i] - 1 &&
863 * last_block[i] && thread_id[i] >= last_block[i])
864 * return;
865 * }
866 */
867 uint last_block[3];
868
869 /**
870 * Determine the layout of the grid (in block units) to be used.
871 */
872 uint grid[3];
873
874 /* Indirect compute parameters resource: If not NULL, block sizes are taken
875 * from this buffer instead, which is laid out as follows:
876 *
877 * struct {
878 * uint32_t num_blocks_x;
879 * uint32_t num_blocks_y;
880 * uint32_t num_blocks_z;
881 * };
882 */
883 struct pipe_resource *indirect;
884 unsigned indirect_offset; /**< must be 4 byte aligned */
885 };
886
887 /**
888 * Structure used as a header for serialized compute programs.
889 */
890 struct pipe_binary_program_header
891 {
892 uint32_t num_bytes; /**< Number of bytes in the LLVM bytecode program. */
893 char blob[];
894 };
895
896 struct pipe_compute_state
897 {
898 enum pipe_shader_ir ir_type; /**< IR type contained in prog. */
899 const void *prog; /**< Compute program to be executed. */
900 unsigned req_local_mem; /**< Required size of the LOCAL resource. */
901 unsigned req_private_mem; /**< Required size of the PRIVATE resource. */
902 unsigned req_input_mem; /**< Required size of the INPUT resource. */
903 };
904
905 /**
906 * Structure that contains a callback for debug messages from the driver back
907 * to the state tracker.
908 */
909 struct pipe_debug_callback
910 {
911 /**
912 * When set to \c true, the callback may be called asynchronously from a
913 * driver-created thread.
914 */
915 bool async;
916
917 /**
918 * Callback for the driver to report debug/performance/etc information back
919 * to the state tracker.
920 *
921 * \param data user-supplied data pointer
922 * \param id message type identifier, if pointed value is 0, then a
923 * new id is assigned
924 * \param type PIPE_DEBUG_TYPE_*
925 * \param format printf-style format string
926 * \param args args for format string
927 */
928 void (*debug_message)(void *data,
929 unsigned *id,
930 enum pipe_debug_type type,
931 const char *fmt,
932 va_list args);
933 void *data;
934 };
935
936 /**
937 * Structure that contains a callback for device reset messages from the driver
938 * back to the state tracker.
939 *
940 * The callback must not be called from driver-created threads.
941 */
942 struct pipe_device_reset_callback
943 {
944 /**
945 * Callback for the driver to report when a device reset is detected.
946 *
947 * \param data user-supplied data pointer
948 * \param status PIPE_*_RESET
949 */
950 void (*reset)(void *data, enum pipe_reset_status status);
951
952 void *data;
953 };
954
955 /**
956 * Information about memory usage. All sizes are in kilobytes.
957 */
958 struct pipe_memory_info
959 {
960 unsigned total_device_memory; /**< size of device memory, e.g. VRAM */
961 unsigned avail_device_memory; /**< free device memory at the moment */
962 unsigned total_staging_memory; /**< size of staging memory, e.g. GART */
963 unsigned avail_staging_memory; /**< free staging memory at the moment */
964 unsigned device_memory_evicted; /**< size of memory evicted (monotonic counter) */
965 unsigned nr_device_memory_evictions; /**< # of evictions (monotonic counter) */
966 };
967
968 /**
969 * Structure that contains information about external memory
970 */
971 struct pipe_memory_object
972 {
973 bool dedicated;
974 };
975
976 #ifdef __cplusplus
977 }
978 #endif
979
980 #endif
981