1 /*********************************************************************/
2 /* Copyright 2009, 2010 The University of Texas at Austin.           */
3 /* All rights reserved.                                              */
4 /*                                                                   */
5 /* Redistribution and use in source and binary forms, with or        */
6 /* without modification, are permitted provided that the following   */
7 /* conditions are met:                                               */
8 /*                                                                   */
9 /*   1. Redistributions of source code must retain the above         */
10 /*      copyright notice, this list of conditions and the following  */
11 /*      disclaimer.                                                  */
12 /*                                                                   */
13 /*   2. Redistributions in binary form must reproduce the above      */
14 /*      copyright notice, this list of conditions and the following  */
15 /*      disclaimer in the documentation and/or other materials       */
16 /*      provided with the distribution.                              */
17 /*                                                                   */
18 /*    THIS  SOFTWARE IS PROVIDED  BY THE  UNIVERSITY OF  TEXAS AT    */
19 /*    AUSTIN  ``AS IS''  AND ANY  EXPRESS OR  IMPLIED WARRANTIES,    */
20 /*    INCLUDING, BUT  NOT LIMITED  TO, THE IMPLIED  WARRANTIES OF    */
21 /*    MERCHANTABILITY  AND FITNESS FOR  A PARTICULAR  PURPOSE ARE    */
22 /*    DISCLAIMED.  IN  NO EVENT SHALL THE UNIVERSITY  OF TEXAS AT    */
23 /*    AUSTIN OR CONTRIBUTORS BE  LIABLE FOR ANY DIRECT, INDIRECT,    */
24 /*    INCIDENTAL,  SPECIAL, EXEMPLARY,  OR  CONSEQUENTIAL DAMAGES    */
25 /*    (INCLUDING, BUT  NOT LIMITED TO,  PROCUREMENT OF SUBSTITUTE    */
26 /*    GOODS  OR  SERVICES; LOSS  OF  USE,  DATA,  OR PROFITS;  OR    */
27 /*    BUSINESS INTERRUPTION) HOWEVER CAUSED  AND ON ANY THEORY OF    */
28 /*    LIABILITY, WHETHER  IN CONTRACT, STRICT  LIABILITY, OR TORT    */
29 /*    (INCLUDING NEGLIGENCE OR OTHERWISE)  ARISING IN ANY WAY OUT    */
30 /*    OF  THE  USE OF  THIS  SOFTWARE,  EVEN  IF ADVISED  OF  THE    */
31 /*    POSSIBILITY OF SUCH DAMAGE.                                    */
32 /*                                                                   */
33 /* The views and conclusions contained in the software and           */
34 /* documentation are those of the authors and should not be          */
35 /* interpreted as representing official policies, either expressed   */
36 /* or implied, of The University of Texas at Austin.                 */
37 /*********************************************************************/
38 
39 #ifndef COMMON_POWER
40 #define COMMON_POWER
41 
42 #define MB		__asm__ __volatile__ ("sync")
43 #define WMB		__asm__ __volatile__ ("sync")
44 
45 #define INLINE inline
46 
47 #ifdef PPC440
48 #define STDERR stdout
49 #define QNONCACHE 0x1
50 #define QCOMMS    0x2
51 #define QFAST     0x4
52 #endif
53 
54 #ifndef ASSEMBLER
55 
56 void *qalloc(int flags, size_t bytes);
57 
blas_lock(volatile unsigned long * address)58 static void INLINE blas_lock(volatile unsigned long *address){
59 
60   long int ret, val = 1;
61 
62   do {
63     while (*address) {YIELDING;};
64 
65 #if defined(OS_LINUX) || defined(OS_DARWIN)
66   __asm__ __volatile__ (
67 	   "0:	lwarx %0, 0, %1\n"
68 	   "	cmpwi %0, 0\n"
69 	   "	bne- 1f\n"
70 	   "	stwcx. %2,0, %1\n"
71 	   "	bne- 0b\n"
72 	   "1:    "
73 	: "=&r"(ret)
74 	: "r"(address), "r" (val)
75 	: "cr0", "memory");
76 #else
77   __asm__ __volatile__ (
78 	   ".machine \"any\"\n"
79 	   "	lwarx %0, 0, %1\n"
80 	   "	cmpwi  %0, 0\n"
81 	   "	bne-  $+12\n"
82 	   "	stwcx. %2,0, %1\n"
83 	   "	bne-  $-16\n"
84 	: "=&r"(ret)
85 	: "r"(address), "r" (val)
86 	: "cr0", "memory");
87 #endif
88   } while (ret);
89 }
90 
rpcc(void)91 static inline unsigned long rpcc(void){
92   unsigned long ret;
93 
94 #ifdef OS_AIX
95   __asm__ __volatile__(".machine \"any\" ;");
96 #endif
97   __asm__ __volatile__ ("mftb %0" : "=r" (ret) : );
98 
99 #if defined(POWER5) || defined(PPC970)
100   return (ret << 6);
101 #else
102   return (ret << 3);
103 #endif
104 
105 }
106 
107 #ifdef __64BIT__
108 #define RPCC64BIT
109 #endif
110 
getstackaddr(void)111 static inline unsigned long getstackaddr(void){
112   unsigned long addr;
113 
114   __asm__ __volatile__ ("mr %0, 1"
115 			 : "=r"(addr) : : "memory");
116 
117   return addr;
118 };
119 
120 #if defined(OS_LINUX) || defined(OS_AIX)
121 #define GET_IMAGE(res)  __asm__ __volatile__("fmr %0, 2" : "=f"(res)  : : "memory")
122 #else
123 #define GET_IMAGE(res)  __asm__ __volatile__("fmr %0, f2" : "=f"(res)  : : "memory")
124 
125 #define GET_IMAGE_CANCEL
126 
127 #endif
128 
129 #ifdef SMP
blas_quickdivide(blasint x,blasint y)130 static inline int blas_quickdivide(blasint x, blasint y){
131   return x / y;
132 }
133 #endif
134 
135 #endif
136 
137 
138 #ifdef ASSEMBLER
139 
140 #ifdef DOUBLE
141 #define LFD	lfd
142 #define LFDX	lfdx
143 #define LFPDX	lfpdx
144 #define LFSDX	lfsdx
145 #define LFXDX	lfxdx
146 #define LFDU	lfdu
147 #define LFDUX	lfdux
148 #define LFPDUX	lfpdux
149 #define LFSDUX	lfsdux
150 #define LFXDUX	lfxdux
151 #define STFD	stfd
152 #define STFDX	stfdx
153 #define STFPDX	stfpdx
154 #define STFSDX	stfsdx
155 #define STFXDX	stfxdx
156 #define STFDU	stfdu
157 #define STFDUX	stfdux
158 #define STFPDUX	stfpdux
159 #define STFSDUX	stfsdux
160 #define STFXDUX	stfxdux
161 #define FMADD	fmadd
162 #define FMSUB	fmsub
163 #define FNMADD	fnmadd
164 #define FNMSUB	fnmsub
165 #define FMUL	fmul
166 #define FADD	fadd
167 #define FSUB	fsub
168 #else
169 #define LFD	lfs
170 #define LFDX	lfsx
171 #define LFPDX	lfpsx
172 #define LFSDX	lfssx
173 #define LFXDX	lfxsx
174 #define LFDU	lfsu
175 #define LFDUX	lfsux
176 #define LFPDUX	lfpsux
177 #define LFSDUX	lfssux
178 #define LFXDUX	lfxsux
179 #define STFD	stfs
180 #define STFDX	stfsx
181 #define STFPDX	stfpsx
182 #define STFSDX	stfssx
183 #define STFXDX	stfxsx
184 #define STFDU	stfsu
185 #define STFDUX	stfsux
186 #define STFPDUX	stfpsux
187 #define STFSDUX	stfssux
188 #define STFXDUX	stfxsux
189 #define FMADD	fmadds
190 #define FMSUB	fmsubs
191 #define FNMADD	fnmadds
192 #define FNMSUB	fnmsubs
193 #define FMUL	fmuls
194 #define FADD	fadds
195 #define FSUB	fsubs
196 #endif
197 
198 #ifdef __64BIT__
199 #define LDLONG	ld
200 #else
201 #define LDLONG	lwz
202 #endif
203 
204 #ifdef OS_DARWIN
205 #define LL(x)	L##x
206 #endif
207 
208 #ifdef OS_LINUX
209 #define LL(x)	.L##x
210 #endif
211 
212 #ifndef LL
213 #define LL(x)	__L##x
214 #endif
215 
216 
217 #if   defined(__64BIT__) &&  defined(USE64BITINT)
218 #define LDINT	ld
219 #elif defined(__64BIT__) && !defined(USE64BITINT)
220 #define LDINT	lwa
221 #else
222 #define LDINT	lwz
223 #endif
224 
225 /*
226 #define DCBT(REGA, REGB, NUM) .long (0x7c00022c | (REGA << 16) | (REGB << 11) | ((NUM) << 21))
227 #define DCBTST(REGA, REGB, NUM) .long (0x7c0001ec | (REGA << 16) | (REGB << 11) | ((NUM) << 21))
228 */
229 
230 #define DSTATTR_H(SIZE, COUNT, STRIDE) ((SIZE << 8) | (COUNT))
231 #define DSTATTR_L(SIZE, COUNT, STRIDE) (STRIDE)
232 
233 #if defined(PPC970) || defined(POWER3) || defined(POWER4) || defined(POWER5) || defined(PPCG4)
234 #define HAVE_PREFETCH
235 #endif
236 
237 #if defined(POWER3) || defined(POWER6) || defined(PPCG4) || defined(CELL)
238 #define DCBT_ARG	0
239 #else
240 #define DCBT_ARG	8
241 #endif
242 
243 #ifdef CELL
244 #define L1_DUALFETCH
245 #define L1_PREFETCHSIZE (64 + 128 * 13)
246 #endif
247 
248 #if defined(POWER3) || defined(POWER4) || defined(POWER5)
249 #define L1_DUALFETCH
250 #define L1_PREFETCHSIZE (96 + 128 * 12)
251 #endif
252 
253 #if defined(POWER6)
254 #define L1_DUALFETCH
255 #define L1_PREFETCHSIZE (16 + 128 * 100)
256 #define L1_PREFETCH	dcbtst
257 #endif
258 
259 #ifndef L1_PREFETCH
260 #define L1_PREFETCH	dcbt
261 #endif
262 
263 #ifndef L1_PREFETCHW
264 #define L1_PREFETCHW	dcbtst
265 #endif
266 
267 #if DCBT_ARG == 0
268 #define DCBT(REGA, REGB)	L1_PREFETCH	REGB, REGA
269 #define DCBTST(REGA, REGB)	L1_PREFETCHW	REGB, REGA
270 #else
271 #define DCBT(REGA, REGB)	L1_PREFETCH	DCBT_ARG, REGB, REGA
272 #define DCBTST(REGA, REGB)	L1_PREFETCHW	DCBT_ARG, REGB, REGA
273 #endif
274 
275 
276 #ifndef L1_PREFETCHSIZE
277 #define L1_PREFETCHSIZE (96 + 128 * 12)
278 #endif
279 
280 #if !defined(OS_DARWIN) || defined(NEEDPARAM)
281 #define f0	0
282 #define f1	1
283 #define f2	2
284 #define f3	3
285 #define f4	4
286 #define f5	5
287 #define f6	6
288 #define f7	7
289 #define f8	8
290 #define f9	9
291 #define f10	10
292 #define f11	11
293 #define f12	12
294 #define f13	13
295 #define f14	14
296 #define f15	15
297 #define f16	16
298 #define f17	17
299 #define f18	18
300 #define f19	19
301 #define f20	20
302 #define f21	21
303 #define f22	22
304 #define f23	23
305 #define f24	24
306 #define f25	25
307 #define f26	26
308 #define f27	27
309 #define f28	28
310 #define f29	29
311 #define f30	30
312 #define f31	31
313 
314 #define r0	0
315 #define r1	1
316 #define r2	2
317 #define r3	3
318 #define r4	4
319 #define r5	5
320 #define r6	6
321 #define r7	7
322 #define r8	8
323 #define r9	9
324 #define r10	10
325 #define r11	11
326 #define r12	12
327 #define r13	13
328 #define r14	14
329 #define r15	15
330 #define r16	16
331 #define r17	17
332 #define r18	18
333 #define r19	19
334 #define r20	20
335 #define r21	21
336 #define r22	22
337 #define r23	23
338 #define r24	24
339 #define r25	25
340 #define r26	26
341 #define r27	27
342 #define r28	28
343 #define r29	29
344 #define r30	30
345 #define r31	31
346 
347 #define v0	0
348 #define v1	1
349 #define v2	2
350 #define v3	3
351 #define v4	4
352 #define v5	5
353 #define v6	6
354 #define v7	7
355 #define v8	8
356 #define v9	9
357 #define v10	10
358 #define v11	11
359 #define v12	12
360 #define v13	13
361 #define v14	14
362 #define v15	15
363 #define v16	16
364 #define v17	17
365 #define v18	18
366 #define v19	19
367 #define v20	20
368 #define v21	21
369 #define v22	22
370 #define v23	23
371 #define v24	24
372 #define v25	25
373 #define v26	26
374 #define v27	27
375 #define v28	28
376 #define v29	29
377 #define v30	30
378 #define v31	31
379 
380 #define BO_dCTR_NZERO_AND_NOT	0
381 #define BO_dCTR_NZERO_AND_NOT_1	1
382 #define BO_dCTR_ZERO_AND_NOT	2
383 #define BO_dCTR_ZERO_AND_NOT_1	3
384 #define BO_IF_NOT	4
385 #define BO_IF_NOT_1	5
386 #define BO_IF_NOT_2	6
387 #define BO_IF_NOT_3	7
388 #define BO_dCTR_NZERO_AND	8
389 #define BO_dCTR_NZERO_AND_1	9
390 #define BO_dCTR_ZERO_AND	10
391 #define BO_dCTR_ZERO_AND_1	11
392 #define BO_IF	12
393 #define BO_IF_1	13
394 #define BO_IF_2	14
395 #define BO_IF_3	15
396 #define BO_dCTR_NZERO	16
397 #define BO_dCTR_NZERO_1	17
398 #define BO_dCTR_ZERO	18
399 #define BO_dCTR_ZERO_1	19
400 #define BO_ALWAYS	20
401 #define BO_ALWAYS_1	21
402 #define BO_ALWAYS_2	22
403 #define BO_ALWAYS_3	23
404 #define BO_dCTR_NZERO_8	24
405 #define BO_dCTR_NZERO_9	25
406 #define BO_dCTR_ZERO_8	26
407 #define BO_dCTR_ZERO_9	27
408 #define BO_ALWAYS_8	28
409 #define BO_ALWAYS_9	29
410 #define BO_ALWAYS_10	30
411 #define BO_ALWAYS_11	31
412 
413 #define CR0_LT	0
414 #define CR0_GT	1
415 #define CR0_EQ	2
416 #define CR0_SO	3
417 #define CR1_FX	4
418 #define CR1_FEX	5
419 #define CR1_VX	6
420 #define CR1_OX	7
421 #define CR2_LT	8
422 #define CR2_GT	9
423 #define CR2_EQ	10
424 #define CR2_SO	11
425 #define CR3_LT	12
426 #define CR3_GT	13
427 #define CR3_EQ	14
428 #define CR3_SO	15
429 #define CR4_LT	16
430 #define CR4_GT	17
431 #define CR4_EQ	18
432 #define CR4_SO	19
433 #define CR5_LT	20
434 #define CR5_GT	21
435 #define CR5_EQ	22
436 #define CR5_SO	23
437 #define CR6_LT	24
438 #define CR6_GT	25
439 #define CR6_EQ	26
440 #define CR6_SO	27
441 #define CR7_LT	28
442 #define CR7_GT	29
443 #define CR7_EQ	30
444 #define CR7_SO	31
445 #define TO_LT	16
446 #define TO_GT	8
447 #define TO_EQ	4
448 #define TO_LLT	2
449 #define TO_LGT	1
450 #define CR0	 0
451 #define CR1	 1
452 #define CR2	 2
453 #define CR3	 3
454 #define CR4	 4
455 #define CR5	 5
456 #define CR6	 6
457 #define CR7	 7
458 #define cr0	 0
459 #define cr1	 1
460 #define cr2	 2
461 #define cr3	 3
462 #define cr4	 4
463 #define cr5	 5
464 #define cr6	 6
465 #define cr7	 7
466 #define VRsave	256
467 
468 #endif
469 
470 #define CTR 9
471 #define SP r1
472 
473 #ifdef __64BIT__
474 #define	slwi	sldi
475 #define cmpwi	cmpdi
476 #define srawi	sradi
477 #define mullw	mulld
478 #endif
479 
480 #ifndef F_INTERFACE
481 #define REALNAME ASMNAME
482 #else
483 #define REALNAME ASMFNAME
484 #endif
485 
486 #if defined(ASSEMBLER) && !defined(NEEDPARAM)
487 
488 #ifdef OS_LINUX
489 #ifndef __64BIT__
490 #define PROLOGUE \
491 	.section .text;\
492 	.align 6;\
493 	.globl	REALNAME;\
494 	.type	REALNAME, @function;\
495 REALNAME:
496 #define EPILOGUE	.size	REALNAME, .-REALNAME
497 #else
498 #define PROLOGUE \
499 	.section .text;\
500 	.align 5;\
501 	.globl REALNAME;\
502 	.section	".opd","aw";\
503 	.align 3;\
504 REALNAME:;\
505 	.quad	.REALNAME, .TOC.@tocbase, 0;\
506 	.previous;\
507 	.size	REALNAME, 24;\
508 	.type	.REALNAME, @function;\
509 	.globl	.REALNAME;\
510 .REALNAME:
511 #define EPILOGUE \
512 	.long 0 ; \
513 	.byte 0,0,0,1,128,0,0,0 ; \
514 	.size	.REALNAME, .-.REALNAME; \
515 	.section	.note.GNU-stack,"",@progbits
516 #endif
517 
518 #ifdef PROFILE
519 #ifndef __64BIT__
520 #define PROFCODE ;\
521 	.section	".data";\
522 	.align 2;\
523 .LP3:;\
524 	.long	0;\
525 	.section	".text";\
526 	mflr	r0;\
527 	stw	r0,   4(SP);\
528 	lis	r12, .LP3@ha;\
529 	la	r0, .LP3@l(r12);\
530 	bl	_mcount;\
531 	lwz	r0,   4(SP);\
532 	mtlr	r0
533 #else
534 #define PROFCODE \
535 	.globl	 _mcount; \
536 	mflr	r0; \
537 	std	r0,    16(SP); \
538 	mr	r11, SP; \
539 	addi	SP, SP, -256; \
540 	std	r11,    0(SP); \
541 	std	r3,   128(SP); \
542 	std	r4,   136(SP); \
543 	std	r5,   144(SP); \
544 	std	r6,   152(SP); \
545 	std	r7,   160(SP); \
546 	std	r8,   168(SP); \
547 	std	r9,   176(SP); \
548 	std	r10,  184(SP); \
549 	stfd	f3,   192(SP); \
550 	stfd	f4,   200(SP); \
551 	bl	._mcount; \
552 	nop; \
553 	ld	r3,   128(SP);\
554 	ld	r4,   136(SP);\
555 	ld	r5,   144(SP);\
556 	ld	r6,   152(SP);\
557 	ld	r7,   160(SP);\
558 	ld	r8,   168(SP);\
559 	ld	r9,   176(SP);\
560 	ld	r10,  184(SP);\
561 	lfd	f3,   192(SP);\
562 	lfd	f4,   200(SP);\
563 	addi	SP, SP,  256;\
564 	ld	r0,    16(SP);\
565 	mtlr	r0
566 #endif
567 #else
568 #define PROFCODE
569 #endif
570 
571 #endif
572 
573 #if OS_AIX
574 #ifndef __64BIT__
575 #define PROLOGUE \
576 	.machine "any";\
577 	.globl .REALNAME;\
578 	.csect .text[PR],5;\
579 .REALNAME:;
580 
581 #define EPILOGUE \
582 _section_.text:;\
583 	.csect .data[RW],4;\
584 	.long _section_.text;
585 
586 #else
587 
588 #define PROLOGUE \
589 	.machine "any";\
590 	.globl .REALNAME;\
591 	.csect .text[PR], 5;\
592 .REALNAME:;
593 
594 #define EPILOGUE \
595 _section_.text:;\
596 	.csect .data[RW],4;\
597 	.llong _section_.text;
598 #endif
599 
600 #define PROFCODE
601 
602 #endif
603 
604 #ifdef OS_DARWIN
605 #ifndef __64BIT__
606 	.macro PROLOGUE
607 	.section __TEXT,__text,regular,pure_instructions
608 	.section __TEXT,__picsymbolstub1,symbol_stubs,pure_instructions,32
609 	.machine ppc
610 	.text
611 	.align 4
612 	.globl REALNAME
613 REALNAME:
614 	.endmacro
615 #else
616 	.macro PROLOGUE
617 	.section __TEXT,__text,regular,pure_instructions
618 	.section __TEXT,__picsymbolstub1,symbol_stubs,pure_instructions,32
619 	.machine ppc64
620 	.text
621 	.align 4
622 	.globl REALNAME
623 REALNAME:
624 	.endmacro
625 #endif
626 
627 #ifndef PROFILE
628 #define PROFCODE
629 #define EPILOGUE	.subsections_via_symbols
630 #else
631 #ifndef __64BIT__
632 
633 	.macro PROFCODE
634 	mflr	r0
635 	stw	r0,     8(SP)
636 	addi	SP, SP, -64
637 	stw	SP,     0(SP)
638 	stw	r3,    12(SP)
639 	stw	r4,    16(SP)
640 	stw	r5,    20(SP)
641 	stw	r6,    24(SP)
642 	stw	r7,    28(SP)
643 	stw	r8,    32(SP)
644 	stw	r9,    36(SP)
645 	stw	r10,   40(SP)
646 	stfd	f1,    48(SP)
647 	stfd	f2,    56(SP)
648 	mr	r3, r0
649 	bl	Lmcount$stub
650 	nop
651 	lwz	r3,    12(SP)
652 	lwz	r4,    16(SP)
653 	lwz	r5,    20(SP)
654 	lwz	r6,    24(SP)
655 	lwz	r7,    28(SP)
656 	lwz	r8,    32(SP)
657 	lwz	r9,    36(SP)
658 	lwz	r10,   40(SP)
659 	lfd	f1,    48(SP)
660 	lfd	f2,    56(SP)
661 	addi	SP, SP,  64
662 	lwz	r0,     8(SP)
663 	mtlr	r0
664 	.endmacro
665 
666 	.macro EPILOGUE
667 	.section __TEXT,__picsymbolstub1,symbol_stubs,pure_instructions,32
668 	.align 5
669 Lmcount$stub:
670 	.indirect_symbol mcount
671 	mflr r0
672 	bcl 20,31,L00000000001$spb
673 L00000000001$spb:
674 	mflr r11
675 	addis r11,r11,ha16(Lmcount$lazy_ptr-L00000000001$spb)
676 	mtlr r0
677 	lwzu r12,lo16(Lmcount$lazy_ptr-L00000000001$spb)(r11)
678 	mtctr r12
679 	bctr
680 	.lazy_symbol_pointer
681 Lmcount$lazy_ptr:
682 	.indirect_symbol mcount
683 	.long	dyld_stub_binding_helper
684 	.subsections_via_symbols
685 	.endmacro
686 
687 #else
688 	.macro PROFCODE
689 	mflr	r0
690 	std	r0,    16(SP)
691 	addi	SP, SP, -128
692 	std	SP,     0(SP)
693 	std	r3,    24(SP)
694 	std	r4,    32(SP)
695 	std	r5,    40(SP)
696 	std	r6,    48(SP)
697 	std	r7,    56(SP)
698 	std	r8,    64(SP)
699 	std	r9,    72(SP)
700 	std	r10,   80(SP)
701 	stfd	f1,    88(SP)
702 	stfd	f2,    96(SP)
703 	mr	r3, r0
704 	bl	Lmcount$stub
705 	nop
706 	ld	r3,    24(SP)
707 	ld	r4,    32(SP)
708 	ld	r5,    40(SP)
709 	ld	r6,    48(SP)
710 	ld	r7,    56(SP)
711 	ld	r8,    64(SP)
712 	ld	r9,    72(SP)
713 	ld	r10,   80(SP)
714 	lfd	f1,    88(SP)
715 	lfd	f2,    86(SP)
716 	addi	SP, SP,  128
717 	ld	r0,    16(SP)
718 	mtlr	r0
719 	.endmacro
720 
721 	.macro EPILOGUE
722 	.data
723 	.section __TEXT,__picsymbolstub1,symbol_stubs,pure_instructions,32
724 	.align 5
725 Lmcount$stub:
726 	.indirect_symbol mcount
727 	mflr r0
728 	bcl 20,31,L00000000001$spb
729 L00000000001$spb:
730 	mflr r11
731 	addis r11,r11,ha16(Lmcount$lazy_ptr-L00000000001$spb)
732 	mtlr r0
733 	ld r12,lo16(Lmcount$lazy_ptr-L00000000001$spb)(r11)
734 	mtctr r12
735 	bctr
736 	.lazy_symbol_pointer
737 Lmcount$lazy_ptr:
738 	.indirect_symbol mcount
739 	.quad	dyld_stub_binding_helper
740 	.subsections_via_symbols
741 	.endmacro
742 #endif
743 
744 #endif
745 
746 #endif
747 #endif
748 
749 #endif
750 
751 #define HALT		mfspr	r0, 1023
752 
753 #ifdef OS_LINUX
754 #if defined(PPC440) || defined(PPC440FP2)
755 #undef  MAX_CPU_NUMBER
756 #define MAX_CPU_NUMBER 1
757 #endif
758 #if !defined(__64BIT__) && !defined(PROFILE) && !defined(PPC440) && !defined(PPC440FP2)
759 #define START_ADDRESS (0x0b000000UL)
760 #else
761 #define SEEK_ADDRESS
762 #endif
763 #endif
764 
765 #ifdef OS_AIX
766 #ifndef __64BIT__
767 #define START_ADDRESS (0xf0000000UL)
768 #else
769 #define SEEK_ADDRESS
770 #endif
771 #endif
772 
773 #ifdef OS_DARWIN
774 #define SEEK_ADDRESS
775 #endif
776 
777 #if defined(PPC440)
778 #define BUFFER_SIZE     (  2 << 20)
779 #elif defined(PPC440FP2)
780 #define BUFFER_SIZE     ( 16 << 20)
781 #else
782 #define BUFFER_SIZE     ( 16 << 20)
783 #endif
784 
785 #ifndef PAGESIZE
786 #define PAGESIZE	( 4 << 10)
787 #endif
788 #define HUGE_PAGESIZE	(16 << 20)
789 
790 #define BASE_ADDRESS (START_ADDRESS - BUFFER_SIZE * MAX_CPU_NUMBER)
791 
792 #ifndef MAP_ANONYMOUS
793 #define MAP_ANONYMOUS MAP_ANON
794 #endif
795 #endif
796