1 /* IA-32 common hooks.
2    Copyright (C) 1988-2021 Free Software Foundation, Inc.
3 
4 This file is part of GCC.
5 
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10 
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14 GNU General Public License for more details.
15 
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3.  If not see
18 <http://www.gnu.org/licenses/>.  */
19 
20 #include "config.h"
21 #include "system.h"
22 #include "coretypes.h"
23 #include "diagnostic-core.h"
24 #include "tm.h"
25 #include "memmodel.h"
26 #include "tm_p.h"
27 #include "common/common-target.h"
28 #include "common/common-target-def.h"
29 #include "opts.h"
30 #include "flags.h"
31 
32 /* Define a set of ISAs which are available when a given ISA is
33    enabled.  MMX and SSE ISAs are handled separately.  */
34 
35 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
36 #define OPTION_MASK_ISA_3DNOW_SET \
37   (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
38 #define OPTION_MASK_ISA_3DNOW_A_SET \
39   (OPTION_MASK_ISA_3DNOW_A | OPTION_MASK_ISA_3DNOW_SET)
40 
41 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
42 #define OPTION_MASK_ISA_SSE2_SET \
43   (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
44 #define OPTION_MASK_ISA_SSE3_SET \
45   (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
46 #define OPTION_MASK_ISA_SSSE3_SET \
47   (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
48 #define OPTION_MASK_ISA_SSE4_1_SET \
49   (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
50 #define OPTION_MASK_ISA_SSE4_2_SET \
51   (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
52 #define OPTION_MASK_ISA_AVX_SET \
53   (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET \
54    | OPTION_MASK_ISA_XSAVE_SET)
55 #define OPTION_MASK_ISA_FMA_SET \
56   (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
57 #define OPTION_MASK_ISA_AVX2_SET \
58   (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX_SET)
59 #define OPTION_MASK_ISA_FXSR_SET OPTION_MASK_ISA_FXSR
60 #define OPTION_MASK_ISA_XSAVE_SET OPTION_MASK_ISA_XSAVE
61 #define OPTION_MASK_ISA_XSAVEOPT_SET \
62   (OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_XSAVE_SET)
63 #define OPTION_MASK_ISA_AVX512F_SET \
64   (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX2_SET)
65 #define OPTION_MASK_ISA_AVX512CD_SET \
66   (OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512F_SET)
67 #define OPTION_MASK_ISA_AVX512PF_SET \
68   (OPTION_MASK_ISA_AVX512PF | OPTION_MASK_ISA_AVX512F_SET)
69 #define OPTION_MASK_ISA_AVX512ER_SET \
70   (OPTION_MASK_ISA_AVX512ER | OPTION_MASK_ISA_AVX512F_SET)
71 #define OPTION_MASK_ISA_AVX512DQ_SET \
72   (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512F_SET)
73 #define OPTION_MASK_ISA_AVX512BW_SET \
74   (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512F_SET)
75 #define OPTION_MASK_ISA_AVX512VL_SET \
76   (OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512F_SET)
77 #define OPTION_MASK_ISA_AVX512IFMA_SET \
78   (OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512F_SET)
79 #define OPTION_MASK_ISA_AVX512VBMI_SET \
80   (OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512BW_SET)
81 #define OPTION_MASK_ISA2_AVX5124FMAPS_SET OPTION_MASK_ISA2_AVX5124FMAPS
82 #define OPTION_MASK_ISA2_AVX5124VNNIW_SET OPTION_MASK_ISA2_AVX5124VNNIW
83 #define OPTION_MASK_ISA_AVX512VBMI2_SET \
84   (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512F_SET)
85 #define OPTION_MASK_ISA_AVX512VNNI_SET \
86   (OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512F_SET)
87 #define OPTION_MASK_ISA2_AVXVNNI_SET OPTION_MASK_ISA2_AVXVNNI
88 #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET \
89   (OPTION_MASK_ISA_AVX512VPOPCNTDQ | OPTION_MASK_ISA_AVX512F_SET)
90 #define OPTION_MASK_ISA_AVX512BITALG_SET \
91   (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512F_SET)
92 #define OPTION_MASK_ISA2_AVX512BF16_SET OPTION_MASK_ISA2_AVX512BF16
93 #define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM
94 #define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW
95 #define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED
96 #define OPTION_MASK_ISA_ADX_SET OPTION_MASK_ISA_ADX
97 #define OPTION_MASK_ISA_PREFETCHWT1_SET OPTION_MASK_ISA_PREFETCHWT1
98 #define OPTION_MASK_ISA_CLFLUSHOPT_SET OPTION_MASK_ISA_CLFLUSHOPT
99 #define OPTION_MASK_ISA_XSAVES_SET \
100   (OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_XSAVE_SET)
101 #define OPTION_MASK_ISA_XSAVEC_SET \
102   (OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_XSAVE_SET)
103 #define OPTION_MASK_ISA_CLWB_SET OPTION_MASK_ISA_CLWB
104 #define OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET OPTION_MASK_ISA2_AVX512VP2INTERSECT
105 #define OPTION_MASK_ISA2_AMX_TILE_SET OPTION_MASK_ISA2_AMX_TILE
106 #define OPTION_MASK_ISA2_AMX_INT8_SET OPTION_MASK_ISA2_AMX_INT8
107 #define OPTION_MASK_ISA2_AMX_BF16_SET OPTION_MASK_ISA2_AMX_BF16
108 
109 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
110    as -msse4.2.  */
111 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
112 
113 #define OPTION_MASK_ISA_SSE4A_SET \
114   (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
115 #define OPTION_MASK_ISA_FMA4_SET \
116   (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_SSE4A_SET \
117    | OPTION_MASK_ISA_AVX_SET)
118 #define OPTION_MASK_ISA_XOP_SET \
119   (OPTION_MASK_ISA_XOP | OPTION_MASK_ISA_FMA4_SET)
120 #define OPTION_MASK_ISA_LWP_SET \
121   OPTION_MASK_ISA_LWP
122 
123 /* AES, SHA and PCLMUL need SSE2 because they use xmm registers.  */
124 #define OPTION_MASK_ISA_AES_SET \
125   (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
126 #define OPTION_MASK_ISA_SHA_SET \
127   (OPTION_MASK_ISA_SHA | OPTION_MASK_ISA_SSE2_SET)
128 #define OPTION_MASK_ISA_PCLMUL_SET \
129   (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
130 
131 #define OPTION_MASK_ISA_ABM_SET \
132   (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
133 
134 #define OPTION_MASK_ISA2_PCONFIG_SET OPTION_MASK_ISA2_PCONFIG
135 #define OPTION_MASK_ISA2_WBNOINVD_SET OPTION_MASK_ISA2_WBNOINVD
136 #define OPTION_MASK_ISA2_SGX_SET OPTION_MASK_ISA2_SGX
137 #define OPTION_MASK_ISA_BMI_SET OPTION_MASK_ISA_BMI
138 #define OPTION_MASK_ISA_BMI2_SET OPTION_MASK_ISA_BMI2
139 #define OPTION_MASK_ISA_LZCNT_SET OPTION_MASK_ISA_LZCNT
140 #define OPTION_MASK_ISA_TBM_SET OPTION_MASK_ISA_TBM
141 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
142 #define OPTION_MASK_ISA2_CX16_SET OPTION_MASK_ISA2_CX16
143 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
144 #define OPTION_MASK_ISA2_MOVBE_SET OPTION_MASK_ISA2_MOVBE
145 #define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32
146 
147 #define OPTION_MASK_ISA_FSGSBASE_SET OPTION_MASK_ISA_FSGSBASE
148 #define OPTION_MASK_ISA_RDRND_SET OPTION_MASK_ISA_RDRND
149 #define OPTION_MASK_ISA2_PTWRITE_SET OPTION_MASK_ISA2_PTWRITE
150 #define OPTION_MASK_ISA_F16C_SET \
151   (OPTION_MASK_ISA_F16C | OPTION_MASK_ISA_AVX_SET)
152 #define OPTION_MASK_ISA2_MWAITX_SET OPTION_MASK_ISA2_MWAITX
153 #define OPTION_MASK_ISA2_CLZERO_SET OPTION_MASK_ISA2_CLZERO
154 #define OPTION_MASK_ISA_PKU_SET OPTION_MASK_ISA_PKU
155 #define OPTION_MASK_ISA2_RDPID_SET OPTION_MASK_ISA2_RDPID
156 #define OPTION_MASK_ISA_GFNI_SET OPTION_MASK_ISA_GFNI
157 #define OPTION_MASK_ISA_SHSTK_SET OPTION_MASK_ISA_SHSTK
158 #define OPTION_MASK_ISA2_VAES_SET OPTION_MASK_ISA2_VAES
159 #define OPTION_MASK_ISA_VPCLMULQDQ_SET OPTION_MASK_ISA_VPCLMULQDQ
160 #define OPTION_MASK_ISA_MOVDIRI_SET OPTION_MASK_ISA_MOVDIRI
161 #define OPTION_MASK_ISA2_MOVDIR64B_SET OPTION_MASK_ISA2_MOVDIR64B
162 #define OPTION_MASK_ISA2_WAITPKG_SET OPTION_MASK_ISA2_WAITPKG
163 #define OPTION_MASK_ISA2_CLDEMOTE_SET OPTION_MASK_ISA2_CLDEMOTE
164 #define OPTION_MASK_ISA2_ENQCMD_SET OPTION_MASK_ISA2_ENQCMD
165 #define OPTION_MASK_ISA2_SERIALIZE_SET OPTION_MASK_ISA2_SERIALIZE
166 #define OPTION_MASK_ISA2_TSXLDTRK_SET OPTION_MASK_ISA2_TSXLDTRK
167 #define OPTION_MASK_ISA2_UINTR_SET OPTION_MASK_ISA2_UINTR
168 #define OPTION_MASK_ISA2_HRESET_SET OPTION_MASK_ISA2_HRESET
169 #define OPTION_MASK_ISA2_KL_SET OPTION_MASK_ISA2_KL
170 #define OPTION_MASK_ISA2_WIDEKL_SET \
171   (OPTION_MASK_ISA2_WIDEKL | OPTION_MASK_ISA2_KL_SET)
172 
173 /* Define a set of ISAs which aren't available when a given ISA is
174    disabled.  MMX and SSE ISAs are handled separately.  */
175 
176 #define OPTION_MASK_ISA_MMX_UNSET \
177   (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
178 #define OPTION_MASK_ISA_3DNOW_UNSET \
179   (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
180 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
181 
182 #define OPTION_MASK_ISA_SSE_UNSET \
183   (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
184 #define OPTION_MASK_ISA_SSE2_UNSET \
185   (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
186 #define OPTION_MASK_ISA_SSE3_UNSET \
187   (OPTION_MASK_ISA_SSE3 \
188    | OPTION_MASK_ISA_SSSE3_UNSET \
189    | OPTION_MASK_ISA_SSE4A_UNSET )
190 #define OPTION_MASK_ISA_SSSE3_UNSET \
191   (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
192 #define OPTION_MASK_ISA_SSE4_1_UNSET \
193   (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
194 #define OPTION_MASK_ISA_SSE4_2_UNSET \
195   (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
196 #define OPTION_MASK_ISA_AVX_UNSET \
197   (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \
198    | OPTION_MASK_ISA_FMA4_UNSET | OPTION_MASK_ISA_F16C_UNSET \
199    | OPTION_MASK_ISA_AVX2_UNSET )
200 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
201 #define OPTION_MASK_ISA_FXSR_UNSET OPTION_MASK_ISA_FXSR
202 #define OPTION_MASK_ISA_XSAVE_UNSET \
203   (OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_XSAVEOPT_UNSET \
204    | OPTION_MASK_ISA_XSAVES_UNSET | OPTION_MASK_ISA_XSAVEC_UNSET \
205    | OPTION_MASK_ISA_AVX_UNSET)
206 #define OPTION_MASK_ISA2_XSAVE_UNSET OPTION_MASK_ISA2_AMX_TILE_UNSET
207 #define OPTION_MASK_ISA_XSAVEOPT_UNSET OPTION_MASK_ISA_XSAVEOPT
208 #define OPTION_MASK_ISA_AVX2_UNSET \
209   (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX512F_UNSET)
210 #define OPTION_MASK_ISA2_AVX2_UNSET \
211   (OPTION_MASK_ISA2_AVXVNNI_UNSET | OPTION_MASK_ISA2_AVX512F_UNSET)
212 #define OPTION_MASK_ISA_AVX512F_UNSET \
213   (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \
214    | OPTION_MASK_ISA_AVX512PF_UNSET | OPTION_MASK_ISA_AVX512ER_UNSET \
215    | OPTION_MASK_ISA_AVX512DQ_UNSET | OPTION_MASK_ISA_AVX512BW_UNSET \
216    | OPTION_MASK_ISA_AVX512VL_UNSET | OPTION_MASK_ISA_AVX512IFMA_UNSET \
217    | OPTION_MASK_ISA_AVX512VBMI2_UNSET \
218    | OPTION_MASK_ISA_AVX512VNNI_UNSET \
219    | OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET \
220    | OPTION_MASK_ISA_AVX512BITALG_UNSET)
221 #define OPTION_MASK_ISA_AVX512CD_UNSET OPTION_MASK_ISA_AVX512CD
222 #define OPTION_MASK_ISA_AVX512PF_UNSET OPTION_MASK_ISA_AVX512PF
223 #define OPTION_MASK_ISA_AVX512ER_UNSET OPTION_MASK_ISA_AVX512ER
224 #define OPTION_MASK_ISA_AVX512DQ_UNSET OPTION_MASK_ISA_AVX512DQ
225 #define OPTION_MASK_ISA_AVX512BW_UNSET \
226   (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VBMI_UNSET)
227 #define OPTION_MASK_ISA_AVX512VL_UNSET OPTION_MASK_ISA_AVX512VL
228 #define OPTION_MASK_ISA_AVX512IFMA_UNSET OPTION_MASK_ISA_AVX512IFMA
229 #define OPTION_MASK_ISA_AVX512VBMI_UNSET OPTION_MASK_ISA_AVX512VBMI
230 #define OPTION_MASK_ISA2_AVX5124FMAPS_UNSET OPTION_MASK_ISA2_AVX5124FMAPS
231 #define OPTION_MASK_ISA2_AVX5124VNNIW_UNSET OPTION_MASK_ISA2_AVX5124VNNIW
232 #define OPTION_MASK_ISA_AVX512VBMI2_UNSET OPTION_MASK_ISA_AVX512VBMI2
233 #define OPTION_MASK_ISA_AVX512VNNI_UNSET OPTION_MASK_ISA_AVX512VNNI
234 #define OPTION_MASK_ISA2_AVXVNNI_UNSET OPTION_MASK_ISA2_AVXVNNI
235 #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET OPTION_MASK_ISA_AVX512VPOPCNTDQ
236 #define OPTION_MASK_ISA_AVX512BITALG_UNSET OPTION_MASK_ISA_AVX512BITALG
237 #define OPTION_MASK_ISA2_AVX512BF16_UNSET OPTION_MASK_ISA2_AVX512BF16
238 #define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM
239 #define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW
240 #define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED
241 #define OPTION_MASK_ISA_ADX_UNSET OPTION_MASK_ISA_ADX
242 #define OPTION_MASK_ISA_PREFETCHWT1_UNSET OPTION_MASK_ISA_PREFETCHWT1
243 #define OPTION_MASK_ISA_CLFLUSHOPT_UNSET OPTION_MASK_ISA_CLFLUSHOPT
244 #define OPTION_MASK_ISA_XSAVEC_UNSET OPTION_MASK_ISA_XSAVEC
245 #define OPTION_MASK_ISA_XSAVES_UNSET OPTION_MASK_ISA_XSAVES
246 #define OPTION_MASK_ISA_CLWB_UNSET OPTION_MASK_ISA_CLWB
247 #define OPTION_MASK_ISA2_MWAITX_UNSET OPTION_MASK_ISA2_MWAITX
248 #define OPTION_MASK_ISA2_CLZERO_UNSET OPTION_MASK_ISA2_CLZERO
249 #define OPTION_MASK_ISA_PKU_UNSET OPTION_MASK_ISA_PKU
250 #define OPTION_MASK_ISA2_RDPID_UNSET OPTION_MASK_ISA2_RDPID
251 #define OPTION_MASK_ISA_GFNI_UNSET OPTION_MASK_ISA_GFNI
252 #define OPTION_MASK_ISA_SHSTK_UNSET OPTION_MASK_ISA_SHSTK
253 #define OPTION_MASK_ISA2_VAES_UNSET OPTION_MASK_ISA2_VAES
254 #define OPTION_MASK_ISA_VPCLMULQDQ_UNSET OPTION_MASK_ISA_VPCLMULQDQ
255 #define OPTION_MASK_ISA_MOVDIRI_UNSET OPTION_MASK_ISA_MOVDIRI
256 #define OPTION_MASK_ISA2_MOVDIR64B_UNSET OPTION_MASK_ISA2_MOVDIR64B
257 #define OPTION_MASK_ISA2_WAITPKG_UNSET OPTION_MASK_ISA2_WAITPKG
258 #define OPTION_MASK_ISA2_CLDEMOTE_UNSET OPTION_MASK_ISA2_CLDEMOTE
259 #define OPTION_MASK_ISA2_ENQCMD_UNSET OPTION_MASK_ISA2_ENQCMD
260 #define OPTION_MASK_ISA2_SERIALIZE_UNSET OPTION_MASK_ISA2_SERIALIZE
261 #define OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET OPTION_MASK_ISA2_AVX512VP2INTERSECT
262 #define OPTION_MASK_ISA2_TSXLDTRK_UNSET OPTION_MASK_ISA2_TSXLDTRK
263 #define OPTION_MASK_ISA2_AMX_TILE_UNSET OPTION_MASK_ISA2_AMX_TILE
264 #define OPTION_MASK_ISA2_AMX_INT8_UNSET OPTION_MASK_ISA2_AMX_INT8
265 #define OPTION_MASK_ISA2_AMX_BF16_UNSET OPTION_MASK_ISA2_AMX_BF16
266 #define OPTION_MASK_ISA2_UINTR_UNSET OPTION_MASK_ISA2_UINTR
267 #define OPTION_MASK_ISA2_HRESET_UNSET OPTION_MASK_ISA2_HRESET
268 #define OPTION_MASK_ISA2_KL_UNSET \
269   (OPTION_MASK_ISA2_KL | OPTION_MASK_ISA2_WIDEKL_UNSET)
270 #define OPTION_MASK_ISA2_WIDEKL_UNSET OPTION_MASK_ISA2_WIDEKL
271 
272 /* SSE4 includes both SSE4.1 and SSE4.2.  -mno-sse4 should the same
273    as -mno-sse4.1. */
274 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
275 
276 #define OPTION_MASK_ISA_SSE4A_UNSET \
277   (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_FMA4_UNSET)
278 
279 #define OPTION_MASK_ISA_FMA4_UNSET \
280   (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_XOP_UNSET)
281 #define OPTION_MASK_ISA_XOP_UNSET OPTION_MASK_ISA_XOP
282 #define OPTION_MASK_ISA_LWP_UNSET OPTION_MASK_ISA_LWP
283 
284 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
285 #define OPTION_MASK_ISA_SHA_UNSET OPTION_MASK_ISA_SHA
286 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
287 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
288 #define OPTION_MASK_ISA2_PCONFIG_UNSET OPTION_MASK_ISA2_PCONFIG
289 #define OPTION_MASK_ISA2_WBNOINVD_UNSET OPTION_MASK_ISA2_WBNOINVD
290 #define OPTION_MASK_ISA2_SGX_UNSET OPTION_MASK_ISA2_SGX
291 #define OPTION_MASK_ISA_BMI_UNSET OPTION_MASK_ISA_BMI
292 #define OPTION_MASK_ISA_BMI2_UNSET OPTION_MASK_ISA_BMI2
293 #define OPTION_MASK_ISA_LZCNT_UNSET OPTION_MASK_ISA_LZCNT
294 #define OPTION_MASK_ISA_TBM_UNSET OPTION_MASK_ISA_TBM
295 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
296 #define OPTION_MASK_ISA2_CX16_UNSET OPTION_MASK_ISA2_CX16
297 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
298 #define OPTION_MASK_ISA2_MOVBE_UNSET OPTION_MASK_ISA2_MOVBE
299 #define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32
300 
301 #define OPTION_MASK_ISA_FSGSBASE_UNSET OPTION_MASK_ISA_FSGSBASE
302 #define OPTION_MASK_ISA_RDRND_UNSET OPTION_MASK_ISA_RDRND
303 #define OPTION_MASK_ISA2_PTWRITE_UNSET OPTION_MASK_ISA2_PTWRITE
304 #define OPTION_MASK_ISA_F16C_UNSET OPTION_MASK_ISA_F16C
305 
306 #define OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET \
307   (OPTION_MASK_ISA_MMX_UNSET \
308    | OPTION_MASK_ISA_SSE_UNSET)
309 
310 #define OPTION_MASK_ISA2_AVX512F_UNSET \
311   (OPTION_MASK_ISA2_AVX512BF16_UNSET \
312    | OPTION_MASK_ISA2_AVX5124FMAPS_UNSET \
313    | OPTION_MASK_ISA2_AVX5124VNNIW_UNSET \
314    | OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET)
315 #define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \
316   (OPTION_MASK_ISA2_AVX512F_UNSET)
317 #define OPTION_MASK_ISA2_AVX_UNSET OPTION_MASK_ISA2_AVX2_UNSET
318 #define OPTION_MASK_ISA2_SSE4_2_UNSET OPTION_MASK_ISA2_AVX_UNSET
319 #define OPTION_MASK_ISA2_SSE4_1_UNSET OPTION_MASK_ISA2_SSE4_2_UNSET
320 #define OPTION_MASK_ISA2_SSE4_UNSET OPTION_MASK_ISA2_SSE4_1_UNSET
321 #define OPTION_MASK_ISA2_SSSE3_UNSET OPTION_MASK_ISA2_SSE4_1_UNSET
322 #define OPTION_MASK_ISA2_SSE3_UNSET OPTION_MASK_ISA2_SSSE3_UNSET
323 #define OPTION_MASK_ISA2_SSE2_UNSET \
324   (OPTION_MASK_ISA2_SSE3_UNSET | OPTION_MASK_ISA2_KL_UNSET)
325 #define OPTION_MASK_ISA2_SSE_UNSET OPTION_MASK_ISA2_SSE2_UNSET
326 
327 #define OPTION_MASK_ISA2_AVX512BW_UNSET OPTION_MASK_ISA2_AVX512BF16_UNSET
328 
329 /* Set 1 << value as value of -malign-FLAG option.  */
330 
331 static void
set_malign_value(const char ** flag,unsigned value)332 set_malign_value (const char **flag, unsigned value)
333 {
334   char *r = XNEWVEC (char, 6);
335   sprintf (r, "%d", 1 << value);
336   *flag = r;
337 }
338 
339 /* Implement TARGET_HANDLE_OPTION.  */
340 
341 bool
ix86_handle_option(struct gcc_options * opts,struct gcc_options * opts_set ATTRIBUTE_UNUSED,const struct cl_decoded_option * decoded,location_t loc)342 ix86_handle_option (struct gcc_options *opts,
343 		    struct gcc_options *opts_set ATTRIBUTE_UNUSED,
344 		    const struct cl_decoded_option *decoded,
345 		    location_t loc)
346 {
347   size_t code = decoded->opt_index;
348   int value = decoded->value;
349 
350   switch (code)
351     {
352     case OPT_mgeneral_regs_only:
353       if (value)
354 	{
355 	  /* Disable MMX, SSE and x87 instructions if only
356 	     general registers are allowed.  */
357 	  opts->x_ix86_isa_flags
358 	    &= ~OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET;
359 	  opts->x_ix86_isa_flags2
360 	    &= ~OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET;
361 	  opts->x_ix86_isa_flags_explicit
362 	    |= OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET;
363 	  opts->x_ix86_isa_flags2_explicit
364 	    |= OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET;
365 
366 	  opts->x_target_flags &= ~MASK_80387;
367 	}
368       else
369 	gcc_unreachable ();
370       return true;
371 
372     case OPT_mmmx:
373       if (value)
374 	{
375 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
376 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
377 	}
378       else
379 	{
380 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
381 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
382 	}
383       return true;
384 
385     case OPT_m3dnow:
386       if (value)
387 	{
388 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
389 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
390 	}
391       else
392 	{
393 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
394 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
395 	}
396       return true;
397 
398     case OPT_m3dnowa:
399       if (value)
400 	{
401 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A_SET;
402 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_A_SET;
403 	}
404       else
405 	{
406 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_A_UNSET;
407 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_A_UNSET;
408 	}
409       return true;
410 
411     case OPT_msse:
412       if (value)
413 	{
414 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
415 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
416 	}
417       else
418 	{
419 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
420 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
421 	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE_UNSET;
422 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE_UNSET;
423 	}
424       return true;
425 
426     case OPT_msse2:
427       if (value)
428 	{
429 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
430 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
431 	}
432       else
433 	{
434 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
435 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
436 	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE2_UNSET;
437 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE2_UNSET;
438 	}
439       return true;
440 
441     case OPT_msse3:
442       if (value)
443 	{
444 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
445 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
446 	}
447       else
448 	{
449 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
450 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
451 	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE3_UNSET;
452 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE3_UNSET;
453 	}
454       return true;
455 
456     case OPT_mssse3:
457       if (value)
458 	{
459 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
460 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
461 	}
462       else
463 	{
464 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
465 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
466 	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSSE3_UNSET;
467 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSSE3_UNSET;
468 	}
469       return true;
470 
471     case OPT_msse4_1:
472       if (value)
473 	{
474 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
475 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
476 	}
477       else
478 	{
479 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
480 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
481 	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE4_1_UNSET;
482 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE4_1_UNSET;
483 	}
484       return true;
485 
486     case OPT_msse4_2:
487       if (value)
488 	{
489 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
490 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
491 	}
492       else
493 	{
494 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
495 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
496 	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE4_2_UNSET;
497 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE4_2_UNSET;
498 	}
499       return true;
500 
501     case OPT_mavx:
502       if (value)
503 	{
504 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
505 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
506 	}
507       else
508 	{
509 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET;
510 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET;
511 	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX_UNSET;
512 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX_UNSET;
513 	}
514       return true;
515 
516     case OPT_mavx2:
517       if (value)
518 	{
519 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
520 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
521 	}
522       else
523 	{
524 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX2_UNSET;
525 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_UNSET;
526 	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX2_UNSET;
527 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX2_UNSET;
528 	}
529       return true;
530 
531     case OPT_mavx512f:
532       if (value)
533 	{
534 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
535 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
536 	}
537       else
538 	{
539 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512F_UNSET;
540 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_UNSET;
541 	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
542 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
543 	}
544       return true;
545 
546     case OPT_mavx512cd:
547       if (value)
548 	{
549 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512CD_SET;
550 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_SET;
551 	}
552       else
553 	{
554 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512CD_UNSET;
555 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_UNSET;
556 	}
557       return true;
558 
559     case OPT_mavx512pf:
560       if (value)
561 	{
562 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512PF_SET;
563 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512PF_SET;
564 	}
565       else
566 	{
567 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512PF_UNSET;
568 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512PF_UNSET;
569 	}
570       return true;
571 
572     case OPT_mavx512er:
573       if (value)
574 	{
575 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512ER_SET;
576 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512ER_SET;
577 	}
578       else
579 	{
580 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512ER_UNSET;
581 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512ER_UNSET;
582 	}
583       return true;
584 
585     case OPT_mrdpid:
586       if (value)
587 	{
588 	  opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_RDPID_SET;
589 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RDPID_SET;
590 	}
591       else
592 	{
593 	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_RDPID_UNSET;
594 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RDPID_UNSET;
595 	}
596       return true;
597 
598     case OPT_mgfni:
599       if (value)
600 	{
601 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_GFNI_SET;
602 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_GFNI_SET;
603 	}
604       else
605 	{
606 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_GFNI_UNSET;
607 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_GFNI_UNSET;
608 	}
609       return true;
610 
611     case OPT_mshstk:
612       if (value)
613 	{
614 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SHSTK_SET;
615 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHSTK_SET;
616 	}
617       else
618 	{
619 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SHSTK_UNSET;
620 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHSTK_UNSET;
621 	}
622       return true;
623 
624     case OPT_mvaes:
625       if (value)
626 	{
627 	  opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_VAES_SET;
628 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_VAES_SET;
629 	}
630       else
631 	{
632 	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_VAES_UNSET;
633 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_VAES_UNSET;
634 	}
635       return true;
636 
637     case OPT_mvpclmulqdq:
638       if (value)
639 	{
640 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_VPCLMULQDQ_SET;
641 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_VPCLMULQDQ_SET;
642 	}
643       else
644 	{
645 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_VPCLMULQDQ_UNSET;
646 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_VPCLMULQDQ_UNSET;
647 	}
648       return true;
649 
650     case OPT_mmovdiri:
651       if (value)
652 	{
653 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MOVDIRI_SET;
654 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVDIRI_SET;
655 	}
656       else
657 	{
658 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MOVDIRI_UNSET;
659 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVDIRI_UNSET;
660 	}
661       return true;
662 
663     case OPT_mmovdir64b:
664       if (value)
665 	{
666 	  opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MOVDIR64B_SET;
667 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVDIR64B_SET;
668 	}
669       else
670 	{
671 	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MOVDIR64B_UNSET;
672 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVDIR64B_UNSET;
673 	}
674 	return true;
675 
676     case OPT_mcldemote:
677       if (value)
678 	{
679 	  opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CLDEMOTE_SET;
680 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLDEMOTE_SET;
681 	}
682       else
683 	{
684 	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CLDEMOTE_UNSET;
685 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLDEMOTE_UNSET;
686 	}
687       return true;
688 
689     case OPT_mwaitpkg:
690       if (value)
691 	{
692 	  opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_WAITPKG_SET;
693 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WAITPKG_SET;
694 	}
695       else
696 	{
697 	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_WAITPKG_UNSET;
698 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WAITPKG_UNSET;
699 	}
700       return true;
701 
702     case OPT_menqcmd:
703       if (value)
704 	{
705 	  opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_ENQCMD_SET;
706 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_ENQCMD_SET;
707 	}
708       else
709 	{
710 	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_ENQCMD_UNSET;
711 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_ENQCMD_UNSET;
712 	}
713 	return true;
714 
715     case OPT_mkl:
716       if (value)
717 	{
718 	  opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_KL_SET;
719 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_KL_SET;
720 
721 	  /* The Keylocker instructions need XMM registers from SSE2.  */
722 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
723 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
724 	}
725       else
726 	{
727 	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_KL_UNSET;
728 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_KL_UNSET;
729 	}
730       return true;
731 
732     case OPT_mwidekl:
733       if (value)
734 	{
735 	  opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_WIDEKL_SET;
736 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WIDEKL_SET;
737 
738 	  /* The Widekl instructions need XMM registers from SSE2.  */
739 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
740 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
741 	}
742       else
743 	{
744 	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_WIDEKL_UNSET;
745 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WIDEKL_UNSET;
746 	}
747       return true;
748 
749     case OPT_mserialize:
750       if (value)
751 	{
752 	  opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SERIALIZE_SET;
753 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SERIALIZE_SET;
754 	}
755       else
756 	{
757 	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SERIALIZE_UNSET;
758 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SERIALIZE_UNSET;
759 	}
760       return true;
761 
762     case OPT_muintr:
763       if (value)
764 	{
765 	  opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_UINTR_SET;
766 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_UINTR_SET;
767 	}
768       else
769 	{
770 	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_UINTR_UNSET;
771 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_UINTR_UNSET;
772 	}
773       return true;
774 
775     case OPT_mhreset:
776       if (value)
777 	{
778 	  opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_HRESET_SET;
779 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_HRESET_SET;
780 	}
781       else
782 	{
783 	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_HRESET_UNSET;
784 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_HRESET_UNSET;
785 	}
786       return true;
787 
788     case OPT_mavx5124fmaps:
789       if (value)
790 	{
791 	  opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX5124FMAPS_SET;
792 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX5124FMAPS_SET;
793 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
794 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
795 	}
796       else
797 	{
798 	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX5124FMAPS_UNSET;
799 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX5124FMAPS_UNSET;
800 	}
801       return true;
802 
803     case OPT_mavx5124vnniw:
804       if (value)
805 	{
806 	  opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX5124VNNIW_SET;
807 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX5124VNNIW_SET;
808 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
809 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
810 	}
811       else
812 	{
813 	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX5124VNNIW_UNSET;
814 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX5124VNNIW_UNSET;
815 	}
816       return true;
817 
818     case OPT_mavx512vbmi2:
819       if (value)
820 	{
821 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI2_SET;
822 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_SET;
823 	}
824       else
825 	{
826 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI2_UNSET;
827 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_UNSET;
828 	}
829       return true;
830 
831     case OPT_mavx512vnni:
832       if (value)
833 	{
834 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VNNI_SET;
835 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_SET;
836 	}
837       else
838 	{
839 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VNNI_UNSET;
840 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_UNSET;
841 	}
842       return true;
843 
844     case OPT_mavx512vpopcntdq:
845       if (value)
846 	{
847 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET;
848 	  opts->x_ix86_isa_flags_explicit
849 	    |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET;
850 	}
851       else
852 	{
853 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
854 	  opts->x_ix86_isa_flags_explicit
855 	    |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
856 	}
857       return true;
858 
859     case OPT_mavx512bitalg:
860       if (value)
861 	{
862 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BITALG_SET;
863 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BITALG_SET;
864 	}
865       else
866 	{
867 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BITALG_UNSET;
868 	  opts->x_ix86_isa_flags_explicit
869 		|= OPTION_MASK_ISA_AVX512BITALG_UNSET;
870 	}
871       return true;
872 
873     case OPT_mavx512bf16:
874       if (value)
875 	{
876 	  opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512BF16_SET;
877 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BF16_SET;
878 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW_SET;
879 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_SET;
880 	}
881       else
882 	{
883 	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BF16_UNSET;
884 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BF16_UNSET;
885 	}
886       return true;
887 
888     case OPT_mavxvnni:
889       if (value)
890 	{
891 	  opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVXVNNI_SET;
892 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXVNNI_SET;
893 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
894 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
895 	}
896       else
897 	{
898 	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVXVNNI_UNSET;
899 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXVNNI_UNSET;
900 	}
901       return true;
902 
903     case OPT_msgx:
904       if (value)
905 	{
906 	  opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SGX_SET;
907 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SGX_SET;
908 	}
909       else
910 	{
911 	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SGX_UNSET;
912 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SGX_UNSET;
913 	}
914       return true;
915 
916     case OPT_mpconfig:
917       if (value)
918 	{
919 	  opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_PCONFIG_SET;
920 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PCONFIG_SET;
921 	}
922       else
923 	{
924 	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_PCONFIG_UNSET;
925 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PCONFIG_UNSET;
926 	}
927       return true;
928 
929     case OPT_mwbnoinvd:
930       if (value)
931 	{
932 	  opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_WBNOINVD_SET;
933 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WBNOINVD_SET;
934 	}
935       else
936 	{
937 	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_WBNOINVD_UNSET;
938 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WBNOINVD_UNSET;
939 	}
940       return true;
941 
942     case OPT_mavx512dq:
943       if (value)
944 	{
945 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512DQ_SET;
946 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_SET;
947 	}
948       else
949 	{
950 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512DQ_UNSET;
951 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_UNSET;
952 	}
953       return true;
954 
955     case OPT_mavx512bw:
956       if (value)
957 	{
958 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW_SET;
959 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_SET;
960 	}
961       else
962 	{
963 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BW_UNSET;
964 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_UNSET;
965 	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BW_UNSET;
966 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BW_UNSET;
967 	}
968       return true;
969 
970     case OPT_mavx512vl:
971       if (value)
972 	{
973 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VL_SET;
974 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_SET;
975 	}
976       else
977 	{
978 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VL_UNSET;
979 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_UNSET;
980 	}
981       return true;
982 
983     case OPT_mavx512ifma:
984       if (value)
985 	{
986 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512IFMA_SET;
987 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_SET;
988 	}
989       else
990 	{
991 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512IFMA_UNSET;
992 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_UNSET;
993 	}
994       return true;
995 
996     case OPT_mavx512vbmi:
997       if (value)
998 	{
999 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI_SET;
1000 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_SET;
1001 	}
1002       else
1003 	{
1004 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI_UNSET;
1005 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_UNSET;
1006 	}
1007       return true;
1008 
1009     case OPT_mavx512vp2intersect:
1010       if (value)
1011 	{
1012 	  opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET;
1013 	  opts->x_ix86_isa_flags2_explicit |=
1014 	    OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET;
1015 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512DQ_SET;
1016 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_SET;
1017 	}
1018       else
1019 	{
1020 	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET;
1021 	  opts->x_ix86_isa_flags2_explicit |=
1022 	    OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET;
1023 	}
1024       return true;
1025 
1026     case OPT_mtsxldtrk:
1027       if (value)
1028 	{
1029 	  opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_TSXLDTRK_SET;
1030 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_TSXLDTRK_SET;
1031 	}
1032       else
1033 	{
1034 	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_TSXLDTRK_UNSET;
1035 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_TSXLDTRK_UNSET;
1036 	}
1037       return true;
1038 
1039     case OPT_mamx_tile:
1040       if (value)
1041 	{
1042 	  opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_TILE_SET;
1043 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_TILE_SET;
1044 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVE_SET;
1045 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_SET;
1046 	}
1047       else
1048 	{
1049 	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_TILE_UNSET;
1050 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_TILE_UNSET;
1051 	}
1052       return true;
1053 
1054     case OPT_mamx_int8:
1055       if (value)
1056 	{
1057 	  opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_INT8_SET;
1058 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_INT8_SET;
1059 	}
1060       else
1061 	{
1062 	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_INT8_UNSET;
1063 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_INT8_UNSET;
1064 	}
1065       return true;
1066 
1067     case OPT_mamx_bf16:
1068       if (value)
1069 	{
1070 	  opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_BF16_SET;
1071 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_BF16_SET;
1072 	}
1073       else
1074 	{
1075 	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_BF16_UNSET;
1076 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_BF16_UNSET;
1077 	}
1078       return true;
1079 
1080     case OPT_mfma:
1081       if (value)
1082 	{
1083 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA_SET;
1084 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_SET;
1085 	}
1086       else
1087 	{
1088 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA_UNSET;
1089 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_UNSET;
1090 	}
1091       return true;
1092 
1093     case OPT_mrtm:
1094       if (value)
1095 	{
1096 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RTM_SET;
1097 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_SET;
1098 	}
1099       else
1100 	{
1101 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RTM_UNSET;
1102 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_UNSET;
1103 	}
1104       return true;
1105 
1106     case OPT_msse4:
1107       opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
1108       opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
1109       return true;
1110 
1111     case OPT_mno_sse4:
1112       opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
1113       opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
1114       opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE4_UNSET;
1115       opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE4_UNSET;
1116       return true;
1117 
1118     case OPT_msse4a:
1119       if (value)
1120 	{
1121 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
1122 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
1123 	}
1124       else
1125 	{
1126 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
1127 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
1128 	}
1129       return true;
1130 
1131     case OPT_mfma4:
1132       if (value)
1133 	{
1134 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA4_SET;
1135 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_SET;
1136 	}
1137       else
1138 	{
1139 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA4_UNSET;
1140 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_UNSET;
1141 	}
1142       return true;
1143 
1144    case OPT_mxop:
1145       if (value)
1146 	{
1147 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XOP_SET;
1148 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_SET;
1149 	}
1150       else
1151 	{
1152 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XOP_UNSET;
1153 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_UNSET;
1154 	}
1155       return true;
1156 
1157    case OPT_mlwp:
1158       if (value)
1159 	{
1160 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LWP_SET;
1161 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_SET;
1162 	}
1163       else
1164 	{
1165 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_LWP_UNSET;
1166 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_UNSET;
1167 	}
1168       return true;
1169 
1170     case OPT_mabm:
1171       if (value)
1172 	{
1173 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ABM_SET;
1174 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_SET;
1175 	}
1176       else
1177 	{
1178 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_ABM_UNSET;
1179 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_UNSET;
1180 	}
1181       return true;
1182 
1183     case OPT_mbmi:
1184       if (value)
1185 	{
1186 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI_SET;
1187 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_SET;
1188 	}
1189       else
1190 	{
1191 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI_UNSET;
1192 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_UNSET;
1193 	}
1194       return true;
1195 
1196     case OPT_mbmi2:
1197       if (value)
1198 	{
1199 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI2_SET;
1200 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_SET;
1201 	}
1202       else
1203 	{
1204 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI2_UNSET;
1205 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_UNSET;
1206 	}
1207       return true;
1208 
1209     case OPT_mlzcnt:
1210       if (value)
1211 	{
1212 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LZCNT_SET;
1213 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LZCNT_SET;
1214 	}
1215       else
1216 	{
1217 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_LZCNT_UNSET;
1218 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LZCNT_UNSET;
1219 	}
1220       return true;
1221 
1222     case OPT_mtbm:
1223       if (value)
1224 	{
1225 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_TBM_SET;
1226 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_SET;
1227 	}
1228       else
1229 	{
1230 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_TBM_UNSET;
1231 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_UNSET;
1232 	}
1233       return true;
1234 
1235     case OPT_mpopcnt:
1236       if (value)
1237 	{
1238 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_POPCNT_SET;
1239 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_SET;
1240 	}
1241       else
1242 	{
1243 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_POPCNT_UNSET;
1244 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_UNSET;
1245 	}
1246       return true;
1247 
1248     case OPT_msahf:
1249       if (value)
1250 	{
1251 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SAHF_SET;
1252 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_SET;
1253 	}
1254       else
1255 	{
1256 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SAHF_UNSET;
1257 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_UNSET;
1258 	}
1259       return true;
1260 
1261     case OPT_mcx16:
1262       if (value)
1263 	{
1264 	  opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CX16_SET;
1265 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CX16_SET;
1266 	}
1267       else
1268 	{
1269 	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CX16_UNSET;
1270 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CX16_UNSET;
1271 	}
1272       return true;
1273 
1274     case OPT_mmovbe:
1275       if (value)
1276 	{
1277 	  opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MOVBE_SET;
1278 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVBE_SET;
1279 	}
1280       else
1281 	{
1282 	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MOVBE_UNSET;
1283 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVBE_UNSET;
1284 	}
1285       return true;
1286 
1287     case OPT_mcrc32:
1288       if (value)
1289 	{
1290 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CRC32_SET;
1291 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_SET;
1292 	}
1293       else
1294 	{
1295 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CRC32_UNSET;
1296 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_UNSET;
1297 	}
1298       return true;
1299 
1300     case OPT_maes:
1301       if (value)
1302 	{
1303 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AES_SET;
1304 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_SET;
1305 	}
1306       else
1307 	{
1308 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AES_UNSET;
1309 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_UNSET;
1310 	}
1311       return true;
1312 
1313     case OPT_msha:
1314       if (value)
1315 	{
1316 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SHA_SET;
1317 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHA_SET;
1318 	}
1319       else
1320 	{
1321 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SHA_UNSET;
1322 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHA_UNSET;
1323 	}
1324       return true;
1325 
1326     case OPT_mpclmul:
1327       if (value)
1328 	{
1329 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL_SET;
1330 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_SET;
1331 	}
1332       else
1333 	{
1334 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PCLMUL_UNSET;
1335 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_UNSET;
1336 	}
1337       return true;
1338 
1339     case OPT_mfsgsbase:
1340       if (value)
1341 	{
1342 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FSGSBASE_SET;
1343 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_SET;
1344 	}
1345       else
1346 	{
1347 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FSGSBASE_UNSET;
1348 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_UNSET;
1349 	}
1350       return true;
1351 
1352     case OPT_mrdrnd:
1353       if (value)
1354 	{
1355 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDRND_SET;
1356 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_SET;
1357 	}
1358       else
1359 	{
1360 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDRND_UNSET;
1361 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_UNSET;
1362 	}
1363       return true;
1364 
1365     case OPT_mptwrite:
1366       if (value)
1367 	{
1368 	  opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_PTWRITE_SET;
1369 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PTWRITE_SET;
1370 	}
1371       else
1372 	{
1373 	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_PTWRITE_UNSET;
1374 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PTWRITE_UNSET;
1375 	}
1376       return true;
1377 
1378     case OPT_mf16c:
1379       if (value)
1380 	{
1381 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_F16C_SET;
1382 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_SET;
1383 	}
1384       else
1385 	{
1386 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_F16C_UNSET;
1387 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_UNSET;
1388 	}
1389       return true;
1390 
1391     case OPT_mfxsr:
1392       if (value)
1393 	{
1394 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FXSR_SET;
1395 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FXSR_SET;
1396 	}
1397       else
1398 	{
1399 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FXSR_UNSET;
1400 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FXSR_UNSET;
1401 	}
1402       return true;
1403 
1404     case OPT_mxsave:
1405       if (value)
1406 	{
1407 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVE_SET;
1408 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_SET;
1409 	}
1410       else
1411 	{
1412 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVE_UNSET;
1413 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_UNSET;
1414 	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_XSAVE_UNSET;
1415 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_XSAVE_UNSET;
1416 	}
1417       return true;
1418 
1419     case OPT_mxsaveopt:
1420       if (value)
1421 	{
1422 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEOPT_SET;
1423 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEOPT_SET;
1424 	}
1425       else
1426 	{
1427 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVEOPT_UNSET;
1428 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEOPT_UNSET;
1429 	}
1430       return true;
1431 
1432     case OPT_mxsavec:
1433       if (value)
1434 	{
1435 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEC_SET;
1436 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEC_SET;
1437 	}
1438       else
1439 	{
1440 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVEC_UNSET;
1441 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEC_UNSET;
1442 	}
1443       return true;
1444 
1445     case OPT_mxsaves:
1446       if (value)
1447 	{
1448 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVES_SET;
1449 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVES_SET;
1450 	}
1451       else
1452 	{
1453 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVES_UNSET;
1454 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVES_UNSET;
1455 	}
1456       return true;
1457 
1458     case OPT_mrdseed:
1459       if (value)
1460 	{
1461 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDSEED_SET;
1462 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_SET;
1463 	}
1464       else
1465 	{
1466 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDSEED_UNSET;
1467 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_UNSET;
1468 	}
1469       return true;
1470 
1471     case OPT_mprfchw:
1472       if (value)
1473 	{
1474 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PRFCHW_SET;
1475 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_SET;
1476 	}
1477       else
1478 	{
1479 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PRFCHW_UNSET;
1480 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_UNSET;
1481 	}
1482       return true;
1483 
1484     case OPT_madx:
1485       if (value)
1486 	{
1487 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ADX_SET;
1488 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ADX_SET;
1489 	}
1490       else
1491 	{
1492 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_ADX_UNSET;
1493 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ADX_UNSET;
1494 	}
1495       return true;
1496 
1497     case OPT_mprefetchwt1:
1498       if (value)
1499 	{
1500 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PREFETCHWT1_SET;
1501 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PREFETCHWT1_SET;
1502 	}
1503       else
1504 	{
1505 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PREFETCHWT1_UNSET;
1506 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PREFETCHWT1_UNSET;
1507 	}
1508       return true;
1509 
1510     case OPT_mclflushopt:
1511       if (value)
1512 	{
1513 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLFLUSHOPT_SET;
1514 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLFLUSHOPT_SET;
1515 	}
1516       else
1517 	{
1518 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLFLUSHOPT_UNSET;
1519 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLFLUSHOPT_UNSET;
1520 	}
1521       return true;
1522 
1523     case OPT_mclwb:
1524       if (value)
1525 	{
1526 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLWB_SET;
1527 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_SET;
1528 	}
1529       else
1530 	{
1531 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLWB_UNSET;
1532 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_UNSET;
1533 	}
1534       return true;
1535 
1536     case OPT_mmwaitx:
1537       if (value)
1538 	{
1539 	  opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MWAITX_SET;
1540 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAITX_SET;
1541 	}
1542       else
1543 	{
1544 	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MWAITX_UNSET;
1545 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAITX_UNSET;
1546 	}
1547       return true;
1548 
1549     case OPT_mclzero:
1550       if (value)
1551 	{
1552 	  opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CLZERO_SET;
1553 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLZERO_SET;
1554 	}
1555       else
1556 	{
1557 	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CLZERO_UNSET;
1558 	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLZERO_UNSET;
1559 	}
1560       return true;
1561 
1562     case OPT_mpku:
1563       if (value)
1564 	{
1565 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PKU_SET;
1566 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PKU_SET;
1567 	}
1568       else
1569 	{
1570 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PKU_UNSET;
1571 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PKU_UNSET;
1572 	}
1573       return true;
1574 
1575 
1576     case OPT_malign_loops_:
1577       warning_at (loc, 0, "%<-malign-loops%> is obsolete, "
1578 		  "use %<-falign-loops%>");
1579       if (value > MAX_CODE_ALIGN)
1580 	error_at (loc, "%<-malign-loops=%d%> is not between 0 and %d",
1581 		  value, MAX_CODE_ALIGN);
1582       else
1583 	set_malign_value (&opts->x_str_align_loops, value);
1584       return true;
1585 
1586     case OPT_malign_jumps_:
1587       warning_at (loc, 0, "%<-malign-jumps%> is obsolete, "
1588 		  "use %<-falign-jumps%>");
1589       if (value > MAX_CODE_ALIGN)
1590 	error_at (loc, "%<-malign-jumps=%d%> is not between 0 and %d",
1591 		  value, MAX_CODE_ALIGN);
1592       else
1593 	set_malign_value (&opts->x_str_align_jumps, value);
1594       return true;
1595 
1596     case OPT_malign_functions_:
1597       warning_at (loc, 0,
1598 		  "%<-malign-functions%> is obsolete, "
1599 		  "use %<-falign-functions%>");
1600       if (value > MAX_CODE_ALIGN)
1601 	error_at (loc, "%<-malign-functions=%d%> is not between 0 and %d",
1602 		  value, MAX_CODE_ALIGN);
1603       else
1604 	set_malign_value (&opts->x_str_align_functions, value);
1605       return true;
1606 
1607     case OPT_mbranch_cost_:
1608       if (value > 5)
1609 	{
1610 	  error_at (loc, "%<-mbranch-cost=%d%> is not between 0 and 5", value);
1611 	  opts->x_ix86_branch_cost = 5;
1612 	}
1613       return true;
1614 
1615     default:
1616       return true;
1617     }
1618 }
1619 
1620 static const struct default_options ix86_option_optimization_table[] =
1621   {
1622     /* Enable redundant extension instructions removal at -O2 and higher.  */
1623     { OPT_LEVELS_2_PLUS, OPT_free, NULL, 1 },
1624     /* Enable function splitting at -O2 and higher.  */
1625     { OPT_LEVELS_2_PLUS, OPT_freorder_blocks_and_partition, NULL, 1 },
1626     /* The STC algorithm produces the smallest code at -Os, for x86.  */
1627     { OPT_LEVELS_2_PLUS, OPT_freorder_blocks_algorithm_, NULL,
1628       REORDER_BLOCKS_ALGORITHM_STC },
1629     /* Turn off -fschedule-insns by default.  It tends to make the
1630        problem with not enough registers even worse.  */
1631     { OPT_LEVELS_ALL, OPT_fschedule_insns, NULL, 0 },
1632 
1633 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
1634     SUBTARGET_OPTIMIZATION_OPTIONS,
1635 #endif
1636     { OPT_LEVELS_NONE, 0, NULL, 0 }
1637   };
1638 
1639 /* Implement TARGET_OPTION_INIT_STRUCT.  */
1640 
1641 static void
ix86_option_init_struct(struct gcc_options * opts)1642 ix86_option_init_struct (struct gcc_options *opts)
1643 {
1644   if (TARGET_MACHO)
1645     /* The Darwin libraries never set errno, so we might as well
1646        avoid calling them when that's the only reason we would.  */
1647     opts->x_flag_errno_math = 0;
1648 
1649   opts->x_flag_pcc_struct_return = 2;
1650   opts->x_flag_asynchronous_unwind_tables = 2;
1651 }
1652 
1653 /* On the x86 -fsplit-stack and -fstack-protector both use the same
1654    field in the TCB, so they cannot be used together.  */
1655 
1656 static bool
ix86_supports_split_stack(bool report ATTRIBUTE_UNUSED,struct gcc_options * opts ATTRIBUTE_UNUSED)1657 ix86_supports_split_stack (bool report ATTRIBUTE_UNUSED,
1658 			   struct gcc_options *opts ATTRIBUTE_UNUSED)
1659 {
1660   bool ret = true;
1661 
1662 #ifndef TARGET_THREAD_SPLIT_STACK_OFFSET
1663   if (report)
1664     error ("%<-fsplit-stack%> currently only supported on GNU/Linux");
1665   ret = false;
1666 #else
1667   if (!HAVE_GAS_CFI_PERSONALITY_DIRECTIVE)
1668     {
1669       if (report)
1670 	error ("%<-fsplit-stack%> requires "
1671 	       "assembler support for CFI directives");
1672       ret = false;
1673     }
1674 #endif
1675 
1676   return ret;
1677 }
1678 
1679 /* Implement TARGET_EXCEPT_UNWIND_INFO.  */
1680 
1681 static enum unwind_info_type
i386_except_unwind_info(struct gcc_options * opts)1682 i386_except_unwind_info (struct gcc_options *opts)
1683 {
1684   /* Honor the --enable-sjlj-exceptions configure switch.  */
1685 #ifdef CONFIG_SJLJ_EXCEPTIONS
1686   if (CONFIG_SJLJ_EXCEPTIONS)
1687     return UI_SJLJ;
1688 #endif
1689 
1690   /* On windows 64, prefer SEH exceptions over anything else.  */
1691   if (TARGET_64BIT && DEFAULT_ABI == MS_ABI && opts->x_flag_unwind_tables)
1692     return UI_SEH;
1693 
1694   if (DWARF2_UNWIND_INFO)
1695     return UI_DWARF2;
1696 
1697   return UI_SJLJ;
1698 }
1699 
1700 #undef  TARGET_EXCEPT_UNWIND_INFO
1701 #define TARGET_EXCEPT_UNWIND_INFO  i386_except_unwind_info
1702 
1703 #undef TARGET_DEFAULT_TARGET_FLAGS
1704 #define TARGET_DEFAULT_TARGET_FLAGS	\
1705   (TARGET_DEFAULT			\
1706    | TARGET_SUBTARGET_DEFAULT		\
1707    | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
1708 
1709 #undef TARGET_HANDLE_OPTION
1710 #define TARGET_HANDLE_OPTION ix86_handle_option
1711 
1712 #undef TARGET_OPTION_OPTIMIZATION_TABLE
1713 #define TARGET_OPTION_OPTIMIZATION_TABLE ix86_option_optimization_table
1714 #undef TARGET_OPTION_INIT_STRUCT
1715 #define TARGET_OPTION_INIT_STRUCT ix86_option_init_struct
1716 
1717 #undef TARGET_SUPPORTS_SPLIT_STACK
1718 #define TARGET_SUPPORTS_SPLIT_STACK ix86_supports_split_stack
1719 
1720 /* This table must be in sync with enum processor_type in i386.h.  */
1721 const char *const processor_names[] =
1722 {
1723   "generic",
1724   "i386",
1725   "i486",
1726   "pentium",
1727   "lakemont",
1728   "pentiumpro",
1729   "pentium4",
1730   "nocona",
1731   "core2",
1732   "nehalem",
1733   "sandybridge",
1734   "haswell",
1735   "bonnell",
1736   "silvermont",
1737   "goldmont",
1738   "goldmont-plus",
1739   "tremont",
1740   "knl",
1741   "knm",
1742   "skylake",
1743   "skylake-avx512",
1744   "cannonlake",
1745   "icelake-client",
1746   "icelake-server",
1747   "cascadelake",
1748   "tigerlake",
1749   "cooperlake",
1750   "sapphirerapids",
1751   "alderlake",
1752   "rocketlake",
1753   "intel",
1754   "geode",
1755   "k6",
1756   "athlon",
1757   "k8",
1758   "amdfam10",
1759   "bdver1",
1760   "bdver2",
1761   "bdver3",
1762   "bdver4",
1763   "btver1",
1764   "btver2",
1765   "znver1",
1766   "znver2",
1767   "znver3"
1768 };
1769 
1770 /* Guarantee that the array is aligned with enum processor_type.  */
1771 STATIC_ASSERT (ARRAY_SIZE (processor_names) == PROCESSOR_max);
1772 
1773 const pta processor_alias_table[] =
1774 {
1775   {"i386", PROCESSOR_I386, CPU_NONE, 0, 0, P_NONE},
1776   {"i486", PROCESSOR_I486, CPU_NONE, 0, 0, P_NONE},
1777   {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0, 0, P_NONE},
1778   {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0, 0, P_NONE},
1779   {"lakemont", PROCESSOR_LAKEMONT, CPU_PENTIUM, PTA_NO_80387,
1780     0, P_NONE},
1781   {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX, 0, P_NONE},
1782   {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX, 0, P_NONE},
1783   {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW,
1784     0, P_NONE},
1785   {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW, 0, P_NONE},
1786   {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW,
1787     0, P_NONE},
1788   {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
1789     PTA_MMX | PTA_SSE | PTA_FXSR, 0, P_NONE},
1790   {"nehemiah", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
1791     PTA_MMX | PTA_SSE | PTA_FXSR, 0, P_NONE},
1792   {"c7", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
1793     PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR, 0, P_NONE},
1794   {"esther", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
1795     PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR, 0, P_NONE},
1796   {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0, 0, P_NONE},
1797   {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0, 0, P_NONE},
1798   {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_FXSR,
1799     0, P_NONE},
1800   {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
1801     PTA_MMX | PTA_SSE | PTA_FXSR, 0, P_NONE},
1802   {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
1803     PTA_MMX | PTA_SSE | PTA_FXSR, 0, P_NONE},
1804   {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
1805     PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR, 0, P_NONE},
1806   {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
1807     PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR, 0, P_NONE},
1808   {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
1809     PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR, 0, P_NONE},
1810   {"prescott", PROCESSOR_NOCONA, CPU_NONE,
1811     PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR, 0, P_NONE},
1812   {"nocona", PROCESSOR_NOCONA, CPU_NONE,
1813     PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1814       | PTA_CX16 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
1815   {"core2", PROCESSOR_CORE2, CPU_CORE2, PTA_CORE2,
1816    M_CPU_TYPE (INTEL_CORE2), P_PROC_SSSE3},
1817   {"nehalem", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM,
1818     M_CPU_SUBTYPE (INTEL_COREI7_NEHALEM), P_PROC_DYNAMIC},
1819   {"corei7", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM,
1820     M_CPU_TYPE (INTEL_COREI7), P_PROC_DYNAMIC},
1821   {"westmere", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_WESTMERE,
1822     M_CPU_SUBTYPE (INTEL_COREI7_WESTMERE), P_PROC_DYNAMIC},
1823   {"sandybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
1824     PTA_SANDYBRIDGE,
1825     M_CPU_SUBTYPE (INTEL_COREI7_SANDYBRIDGE), P_PROC_DYNAMIC},
1826   {"corei7-avx", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
1827     PTA_SANDYBRIDGE, 0, P_PROC_DYNAMIC},
1828   {"ivybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
1829     PTA_IVYBRIDGE,
1830     M_CPU_SUBTYPE (INTEL_COREI7_IVYBRIDGE), P_PROC_DYNAMIC},
1831   {"core-avx-i", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
1832     PTA_IVYBRIDGE, 0, P_PROC_DYNAMIC},
1833   {"haswell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL,
1834     M_CPU_SUBTYPE (INTEL_COREI7_HASWELL), P_PROC_DYNAMIC},
1835   {"core-avx2", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL,
1836     0, P_PROC_DYNAMIC},
1837   {"broadwell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_BROADWELL,
1838     M_CPU_SUBTYPE (INTEL_COREI7_BROADWELL), P_PROC_DYNAMIC},
1839   {"skylake", PROCESSOR_SKYLAKE, CPU_HASWELL, PTA_SKYLAKE,
1840     M_CPU_SUBTYPE (INTEL_COREI7_SKYLAKE), P_PROC_AVX2},
1841   {"skylake-avx512", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL,
1842     PTA_SKYLAKE_AVX512,
1843     M_CPU_SUBTYPE (INTEL_COREI7_SKYLAKE_AVX512), P_PROC_AVX512F},
1844   {"cannonlake", PROCESSOR_CANNONLAKE, CPU_HASWELL, PTA_CANNONLAKE,
1845     M_CPU_SUBTYPE (INTEL_COREI7_CANNONLAKE), P_PROC_AVX512F},
1846   {"icelake-client", PROCESSOR_ICELAKE_CLIENT, CPU_HASWELL,
1847     PTA_ICELAKE_CLIENT,
1848     M_CPU_SUBTYPE (INTEL_COREI7_ICELAKE_CLIENT), P_PROC_AVX512F},
1849   {"rocketlake", PROCESSOR_ROCKETLAKE, CPU_HASWELL,
1850     PTA_ROCKETLAKE,
1851     M_CPU_SUBTYPE (INTEL_COREI7_ROCKETLAKE), P_PROC_AVX512F},
1852   {"icelake-server", PROCESSOR_ICELAKE_SERVER, CPU_HASWELL,
1853     PTA_ICELAKE_SERVER,
1854     M_CPU_SUBTYPE (INTEL_COREI7_ICELAKE_SERVER), P_PROC_AVX512F},
1855   {"cascadelake", PROCESSOR_CASCADELAKE, CPU_HASWELL,
1856     PTA_CASCADELAKE,
1857     M_CPU_SUBTYPE (INTEL_COREI7_CASCADELAKE), P_PROC_AVX512F},
1858   {"tigerlake", PROCESSOR_TIGERLAKE, CPU_HASWELL, PTA_TIGERLAKE,
1859     M_CPU_SUBTYPE (INTEL_COREI7_TIGERLAKE), P_PROC_AVX512F},
1860   {"cooperlake", PROCESSOR_COOPERLAKE, CPU_HASWELL, PTA_COOPERLAKE,
1861     M_CPU_SUBTYPE (INTEL_COREI7_COOPERLAKE), P_PROC_AVX512F},
1862   {"sapphirerapids", PROCESSOR_SAPPHIRERAPIDS, CPU_HASWELL, PTA_SAPPHIRERAPIDS,
1863     M_CPU_SUBTYPE (INTEL_COREI7_SAPPHIRERAPIDS), P_PROC_AVX512F},
1864   {"alderlake", PROCESSOR_ALDERLAKE, CPU_HASWELL, PTA_ALDERLAKE,
1865     M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE), P_PROC_AVX2},
1866   {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL,
1867     M_CPU_TYPE (INTEL_BONNELL), P_PROC_SSSE3},
1868   {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL,
1869     M_CPU_TYPE (INTEL_BONNELL), P_PROC_SSSE3},
1870   {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT,
1871     M_CPU_TYPE (INTEL_SILVERMONT), P_PROC_SSE4_2},
1872   {"slm", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT,
1873     M_CPU_TYPE (INTEL_SILVERMONT), P_PROC_SSE4_2},
1874   {"goldmont", PROCESSOR_GOLDMONT, CPU_GLM, PTA_GOLDMONT,
1875     M_CPU_TYPE (INTEL_GOLDMONT), P_PROC_SSE4_2},
1876   {"goldmont-plus", PROCESSOR_GOLDMONT_PLUS, CPU_GLM, PTA_GOLDMONT_PLUS,
1877     M_CPU_TYPE (INTEL_GOLDMONT_PLUS), P_PROC_SSE4_2},
1878   {"tremont", PROCESSOR_TREMONT, CPU_GLM, PTA_TREMONT,
1879     M_CPU_TYPE (INTEL_TREMONT), P_PROC_SSE4_2},
1880   {"knl", PROCESSOR_KNL, CPU_SLM, PTA_KNL,
1881     M_CPU_TYPE (INTEL_KNL), P_PROC_AVX512F},
1882   {"knm", PROCESSOR_KNM, CPU_SLM, PTA_KNM,
1883    M_CPU_TYPE (INTEL_KNM), P_PROC_AVX512F},
1884   {"intel", PROCESSOR_INTEL, CPU_SLM, PTA_NEHALEM,
1885     M_VENDOR (VENDOR_INTEL), P_NONE},
1886   {"geode", PROCESSOR_GEODE, CPU_GEODE,
1887     PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE, 0, P_NONE},
1888   {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX, 0, P_NONE},
1889   {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW, 0, P_NONE},
1890   {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW, 0, P_NONE},
1891   {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
1892     PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE, 0, P_NONE},
1893   {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
1894     PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE, 0, P_NONE},
1895   {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
1896     PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR, 0, P_NONE},
1897   {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
1898     PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR, 0, P_NONE},
1899   {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
1900     PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR, 0, P_NONE},
1901   {"x86-64", PROCESSOR_K8, CPU_K8, PTA_X86_64_BASELINE, 0, P_NONE},
1902   {"x86-64-v2", PROCESSOR_K8, CPU_GENERIC, PTA_X86_64_V2 | PTA_NO_TUNE,
1903    0, P_NONE},
1904   {"x86-64-v3", PROCESSOR_K8, CPU_GENERIC, PTA_X86_64_V3 | PTA_NO_TUNE,
1905    0, P_NONE},
1906   {"x86-64-v4", PROCESSOR_K8, CPU_GENERIC, PTA_X86_64_V4 | PTA_NO_TUNE,
1907    0, P_NONE},
1908   {"eden-x2", PROCESSOR_K8, CPU_K8,
1909     PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR,
1910     0, P_NONE},
1911   {"nano", PROCESSOR_K8, CPU_K8,
1912     PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1913       | PTA_SSSE3 | PTA_FXSR, 0, P_NONE},
1914   {"nano-1000", PROCESSOR_K8, CPU_K8,
1915     PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1916       | PTA_SSSE3 | PTA_FXSR, 0, P_NONE},
1917   {"nano-2000", PROCESSOR_K8, CPU_K8,
1918     PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1919       | PTA_SSSE3 | PTA_FXSR, 0, P_NONE},
1920   {"nano-3000", PROCESSOR_K8, CPU_K8,
1921     PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1922       | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
1923   {"nano-x2", PROCESSOR_K8, CPU_K8,
1924     PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1925       | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
1926   {"eden-x4", PROCESSOR_K8, CPU_K8,
1927     PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1928       | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
1929   {"nano-x4", PROCESSOR_K8, CPU_K8,
1930     PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1931       | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
1932   {"k8", PROCESSOR_K8, CPU_K8,
1933     PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
1934       | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
1935   {"k8-sse3", PROCESSOR_K8, CPU_K8,
1936     PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
1937       | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
1938   {"opteron", PROCESSOR_K8, CPU_K8,
1939     PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
1940       | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
1941   {"opteron-sse3", PROCESSOR_K8, CPU_K8,
1942     PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
1943       | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
1944   {"athlon64", PROCESSOR_K8, CPU_K8,
1945     PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
1946       | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
1947   {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
1948     PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
1949       | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
1950   {"athlon-fx", PROCESSOR_K8, CPU_K8,
1951     PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
1952       | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
1953   {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
1954     PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
1955       | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR,
1956     0, P_PROC_DYNAMIC},
1957   {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
1958     PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
1959       | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR,
1960     M_CPU_SUBTYPE (AMDFAM10H_BARCELONA), P_PROC_DYNAMIC},
1961   {"bdver1", PROCESSOR_BDVER1, CPU_BDVER1,
1962     PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1963       | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
1964       | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
1965       | PTA_XOP | PTA_LWP | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE,
1966     M_CPU_TYPE (AMDFAM15H_BDVER1), P_PROC_XOP},
1967   {"bdver2", PROCESSOR_BDVER2, CPU_BDVER2,
1968     PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1969       | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
1970       | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
1971       | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
1972       | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE,
1973     M_CPU_TYPE (AMDFAM15H_BDVER2), P_PROC_FMA},
1974   {"bdver3", PROCESSOR_BDVER3, CPU_BDVER3,
1975     PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1976       | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
1977       | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
1978       | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
1979       | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE
1980       | PTA_XSAVEOPT | PTA_FSGSBASE,
1981     M_CPU_SUBTYPE (AMDFAM15H_BDVER3), P_PROC_FMA},
1982   {"bdver4", PROCESSOR_BDVER4, CPU_BDVER4,
1983     PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1984       | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
1985       | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
1986       | PTA_FMA4 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_BMI2
1987       | PTA_TBM | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR
1988       | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE | PTA_RDRND
1989       | PTA_MOVBE | PTA_MWAITX,
1990     M_CPU_SUBTYPE (AMDFAM15H_BDVER4), P_PROC_AVX2},
1991   {"znver1", PROCESSOR_ZNVER1, CPU_ZNVER1,
1992     PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1993       | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
1994       | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
1995       | PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_PRFCHW
1996       | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE
1997       | PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX | PTA_RDSEED
1998       | PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES
1999       | PTA_SHA | PTA_LZCNT | PTA_POPCNT,
2000     M_CPU_SUBTYPE (AMDFAM17H_ZNVER1), P_PROC_AVX2},
2001   {"znver2", PROCESSOR_ZNVER2, CPU_ZNVER2,
2002     PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2003       | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
2004       | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
2005       | PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_PRFCHW
2006       | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE
2007       | PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX | PTA_RDSEED
2008       | PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES
2009       | PTA_SHA | PTA_LZCNT | PTA_POPCNT | PTA_CLWB | PTA_RDPID
2010       | PTA_WBNOINVD,
2011     M_CPU_SUBTYPE (AMDFAM17H_ZNVER2), P_PROC_AVX2},
2012   {"znver3", PROCESSOR_ZNVER3, CPU_ZNVER3,
2013     PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2014       | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
2015       | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
2016       | PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_PRFCHW
2017       | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE
2018       | PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX | PTA_RDSEED
2019       | PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES
2020       | PTA_SHA | PTA_LZCNT | PTA_POPCNT | PTA_CLWB | PTA_RDPID
2021       | PTA_WBNOINVD | PTA_VAES | PTA_VPCLMULQDQ | PTA_PKU,
2022     M_CPU_SUBTYPE (AMDFAM19H_ZNVER3), P_PROC_AVX2},
2023   {"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
2024     PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2025       | PTA_SSSE3 | PTA_SSE4A | PTA_ABM | PTA_CX16 | PTA_PRFCHW
2026       | PTA_FXSR | PTA_XSAVE,
2027    M_CPU_SUBTYPE (AMDFAM15H_BDVER1), P_PROC_SSE4_A},
2028   {"btver2", PROCESSOR_BTVER2, CPU_BTVER2,
2029     PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2030       | PTA_SSSE3 | PTA_SSE4A | PTA_ABM | PTA_CX16 | PTA_SSE4_1
2031       | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
2032       | PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW
2033       | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT,
2034     M_CPU_TYPE (AMD_BTVER2), P_PROC_BMI},
2035 
2036   {"generic", PROCESSOR_GENERIC, CPU_GENERIC,
2037     PTA_64BIT
2038       | PTA_HLE /* flags are only used for -march switch.  */,
2039     0, P_NONE},
2040 
2041   {"amd", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2042    M_VENDOR (VENDOR_AMD), P_NONE},
2043   {"amdfam10h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2044     M_CPU_TYPE (AMDFAM10H), P_NONE},
2045   {"amdfam15h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2046     M_CPU_TYPE (AMDFAM15H), P_NONE},
2047   {"amdfam17h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2048     M_CPU_TYPE (AMDFAM17H), P_NONE},
2049   {"amdfam19h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2050     M_CPU_TYPE (AMDFAM19H), P_NONE},
2051   {"shanghai", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2052     M_CPU_TYPE (AMDFAM10H_SHANGHAI), P_NONE},
2053   {"istanbul", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2054     M_CPU_TYPE (AMDFAM10H_ISTANBUL), P_NONE},
2055 };
2056 
2057 /* NB: processor_alias_table stops at the "generic" entry.  */
2058 unsigned int const pta_size = ARRAY_SIZE (processor_alias_table) - 7;
2059 unsigned int const num_arch_names = ARRAY_SIZE (processor_alias_table);
2060 
2061 /* Provide valid option values for -march and -mtune options.  */
2062 
2063 vec<const char *>
ix86_get_valid_option_values(int option_code,const char * prefix ATTRIBUTE_UNUSED)2064 ix86_get_valid_option_values (int option_code,
2065 			      const char *prefix ATTRIBUTE_UNUSED)
2066 {
2067   vec<const char *> v;
2068   v.create (0);
2069   opt_code opt = (opt_code) option_code;
2070 
2071   switch (opt)
2072     {
2073     case OPT_march_:
2074       for (unsigned i = 0; i < pta_size; i++)
2075 	{
2076 	  const char *name = processor_alias_table[i].name;
2077 	  gcc_checking_assert (name != NULL);
2078 	  v.safe_push (name);
2079 	}
2080 #ifdef HAVE_LOCAL_CPU_DETECT
2081       /* Add also "native" as possible value.  */
2082       v.safe_push ("native");
2083 #endif
2084 
2085       break;
2086     case OPT_mtune_:
2087       for (unsigned i = 0; i < PROCESSOR_max; i++)
2088 	{
2089 	  const char *name = processor_names[i];
2090 	  gcc_checking_assert (name != NULL);
2091 	  v.safe_push (name);
2092 	}
2093       break;
2094     default:
2095       break;
2096     }
2097 
2098   return v;
2099 }
2100 
2101 #undef  TARGET_GET_VALID_OPTION_VALUES
2102 #define TARGET_GET_VALID_OPTION_VALUES ix86_get_valid_option_values
2103 
2104 struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
2105