1;; ARM Cortex-A17 pipeline description
2;; Copyright (C) 2014-2021 Free Software Foundation, Inc.
3;;
4;; Contributed by ARM Ltd.
5;;
6;; This file is part of GCC.
7;;
8;; GCC is free software; you can redistribute it and/or modify it
9;; under the terms of the GNU General Public License as published by
10;; the Free Software Foundation; either version 3, or (at your option)
11;; any later version.
12;;
13;; GCC is distributed in the hope that it will be useful, but
14;; WITHOUT ANY WARRANTY; without even the implied warranty of
15;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
16;; General Public License for more details.
17;;
18;; You should have received a copy of the GNU General Public License
19;; along with GCC; see the file COPYING3.  If not see
20;; <http://www.gnu.org/licenses/>.
21
22
23(define_automaton "cortex_a17")
24
25(define_cpu_unit "ca17_ls0, ca17_ls1" "cortex_a17")
26(define_cpu_unit "ca17_alu0, ca17_alu1" "cortex_a17")
27(define_cpu_unit "ca17_mac" "cortex_a17")
28(define_cpu_unit "ca17_idiv" "cortex_a17")
29(define_cpu_unit "ca17_bx" "cortex_a17")
30
31(define_reservation "ca17_alu" "(ca17_alu0|ca17_alu1)")
32
33
34
35;; Simple Execution Unit:
36;;
37;; Simple ALU
38(define_insn_reservation "cortex_a17_alu" 1
39  (and (eq_attr "tune" "cortexa17")
40       (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
41                        alu_sreg,alus_sreg,logic_reg,logics_reg,\
42                        adc_imm,adcs_imm,adc_reg,adcs_reg,\
43                        adr, mov_imm,mov_reg,\
44                        mvn_imm,mvn_reg,extend,\
45                        mrs,multiple"))
46  "ca17_alu")
47
48(define_insn_reservation "cortex_a17_alu_shiftimm" 2
49  (and (eq_attr "tune" "cortexa17")
50       (eq_attr "type" "bfm,clz,rev,rbit, alu_shift_imm_lsl_1to4,alu_shift_imm_other, alus_shift_imm,
51                        logic_shift_imm,alu_dsp_reg, logics_shift_imm,shift_imm,\
52                        shift_reg, mov_shift,mvn_shift"))
53  "ca17_alu")
54
55
56;; ALU ops with register controlled shift.
57(define_insn_reservation "cortex_a17_alu_shift_reg" 2
58  (and (eq_attr "tune" "cortexa17")
59       (eq_attr "type" "alu_shift_reg,alus_shift_reg,\
60                        logic_shift_reg,logics_shift_reg"))
61  "ca17_alu0")
62
63
64;; Multiply Execution Unit:
65
66;; 32-bit multiplies
67(define_insn_reservation "cortex_a17_mult32" 4
68  (and (eq_attr "tune" "cortexa17")
69       (eq_attr "type" "mul,muls,smmul,smmulr"))
70  "ca17_alu0+ca17_mac")
71
72(define_insn_reservation "cortex_a17_mac32" 4
73  (and (eq_attr "tune" "cortexa17")
74       (eq_attr "type" "mla,mlas,smmla"))
75  "ca17_alu0+ca17_mac,ca17_mac")
76
77(define_insn_reservation "cortex_a17_mac32_other" 3
78  (and (eq_attr "tune" "cortexa17")
79       (eq_attr "type" "smlad,smladx,smlsd,smlsdx,smuad,smuadx,smusd,smusdx"))
80  "ca17_alu0+ca17_mac,ca17_mac")
81
82;; 64-bit multiplies
83(define_insn_reservation "cortex_a17_mac64" 4
84  (and (eq_attr "tune" "cortexa17")
85       (eq_attr "type" "smlal,smlals,umaal,umlal,umlals"))
86  "ca17_alu0+ca17_mac,ca17_mac")
87
88(define_insn_reservation "cortex_a17_mac64_other" 3
89  (and (eq_attr "tune" "cortexa17")
90       (eq_attr "type" "smlald,smlalxy,smlsld"))
91  "ca17_alu0+ca17_mac,ca17_mac")
92
93(define_insn_reservation "cortex_a17_mult64" 4
94  (and (eq_attr "tune" "cortexa17")
95       (eq_attr "type" "smull,smulls,umull,umulls"))
96  "ca17_alu0+ca17_mac,ca17_mac")
97
98
99(define_bypass 2 "cortex_a17_mult*, cortex_a17_mac*"
100                 "cortex_a17_mult*, cortex_a17_mac*"
101                 "arm_mac_accumulator_is_result")
102
103;; Integer divide
104(define_insn_reservation "cortex_a17_udiv" 19
105  (and (eq_attr "tune" "cortexa17")
106       (eq_attr "type" "udiv"))
107  "ca17_alu1+ca17_idiv*10")
108
109(define_insn_reservation "cortex_a17_sdiv" 20
110  (and (eq_attr "tune" "cortexa17")
111       (eq_attr "type" "sdiv"))
112  "ca17_alu1+ca17_idiv*11")
113
114
115
116;; Branch execution Unit
117;;
118;; Branches take one issue slot.
119;; No latency as there is no result
120(define_insn_reservation "cortex_a17_branch" 0
121  (and (eq_attr "tune" "cortexa17")
122       (eq_attr "type" "branch"))
123  "ca17_bx")
124
125;; Load-store execution Unit
126;;
127;; Loads of up to two words.
128(define_insn_reservation "cortex_a17_load1" 4
129  (and (eq_attr "tune" "cortexa17")
130       (eq_attr "type" "load_byte,load_4,load_8"))
131  "ca17_ls0|ca17_ls1")
132
133;; Loads of three words.
134(define_insn_reservation "cortex_a17_load3" 4
135  (and (eq_attr "tune" "cortexa17")
136       (eq_attr "type" "load_12"))
137  "ca17_ls0+ca17_ls1")
138
139;; Loads of four words.
140(define_insn_reservation "cortex_a17_load4" 4
141  (and (eq_attr "tune" "cortexa17")
142       (eq_attr "type" "load_16"))
143  "ca17_ls0+ca17_ls1")
144
145;; Stores of up to two words.
146(define_insn_reservation "cortex_a17_store1" 0
147  (and (eq_attr "tune" "cortexa17")
148       (eq_attr "type" "store_4,store_8"))
149  "ca17_ls0|ca17_ls1")
150
151;; Stores of three words
152(define_insn_reservation "cortex_a17_store3" 0
153  (and (eq_attr "tune" "cortexa17")
154       (eq_attr "type" "store_12"))
155  "ca17_ls0+ca17_ls1")
156
157;; Stores of four words.
158(define_insn_reservation "cortex_a17_store4" 0
159  (and (eq_attr "tune" "cortexa17")
160       (eq_attr "type" "store_16"))
161  "ca17_ls0+ca17_ls1")
162
163(define_insn_reservation "cortex_a17_call" 0
164  (and (eq_attr "tune" "cortexa17")
165       (eq_attr "type" "call"))
166  "ca17_bx")
167
168
169(include "../arm/cortex-a17-neon.md")
170