1 // Tencent is pleased to support the open source community by making ncnn available. 2 // 3 // Copyright (C) 2017 THL A29 Limited, a Tencent company. All rights reserved. 4 // 5 // Licensed under the BSD 3-Clause License (the "License"); you may not use this file except 6 // in compliance with the License. You may obtain a copy of the License at 7 // 8 // https://opensource.org/licenses/BSD-3-Clause 9 // 10 // Unless required by applicable law or agreed to in writing, software distributed 11 // under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR 12 // CONDITIONS OF ANY KIND, either express or implied. See the License for the 13 // specific language governing permissions and limitations under the License. 14 15 #ifndef NCNN_CPU_H 16 #define NCNN_CPU_H 17 18 #include <stddef.h> 19 20 #if defined __ANDROID__ || defined __linux__ 21 #include <sched.h> // cpu_set_t 22 #endif 23 24 #include "platform.h" 25 26 namespace ncnn { 27 28 class NCNN_EXPORT CpuSet 29 { 30 public: 31 CpuSet(); 32 void enable(int cpu); 33 void disable(int cpu); 34 void disable_all(); 35 bool is_enabled(int cpu) const; 36 int num_enabled() const; 37 38 public: 39 #if defined __ANDROID__ || defined __linux__ 40 cpu_set_t cpu_set; 41 #endif 42 #if __APPLE__ 43 unsigned int policy; 44 #endif 45 }; 46 47 // test optional cpu features 48 // neon = armv7 neon or aarch64 asimd 49 NCNN_EXPORT int cpu_support_arm_neon(); 50 // vfpv4 = armv7 fp16 + fma 51 NCNN_EXPORT int cpu_support_arm_vfpv4(); 52 // asimdhp = aarch64 asimd half precision 53 NCNN_EXPORT int cpu_support_arm_asimdhp(); 54 // asimddp = aarch64 asimd dot product 55 NCNN_EXPORT int cpu_support_arm_asimddp(); 56 57 // avx2 = x86_64 avx2 + fma + f16c 58 NCNN_EXPORT int cpu_support_x86_avx2(); 59 60 // avx = x86_64 avx 61 NCNN_EXPORT int cpu_support_x86_avx(); 62 63 // msa = mips mas 64 NCNN_EXPORT int cpu_support_mips_msa(); 65 // mmi = loongson mmi 66 NCNN_EXPORT int cpu_support_loongson_mmi(); 67 68 // v = riscv vector 69 NCNN_EXPORT int cpu_support_riscv_v(); 70 // zfh = riscv half-precision float 71 NCNN_EXPORT int cpu_support_riscv_zfh(); 72 // vlenb = riscv vector length in bytes 73 NCNN_EXPORT int cpu_riscv_vlenb(); 74 75 // cpu info 76 NCNN_EXPORT int get_cpu_count(); 77 NCNN_EXPORT int get_little_cpu_count(); 78 NCNN_EXPORT int get_big_cpu_count(); 79 80 // bind all threads on little clusters if powersave enabled 81 // affects HMP arch cpu like ARM big.LITTLE 82 // only implemented on android at the moment 83 // switching powersave is expensive and not thread-safe 84 // 0 = all cores enabled(default) 85 // 1 = only little clusters enabled 86 // 2 = only big clusters enabled 87 // return 0 if success for setter function 88 NCNN_EXPORT int get_cpu_powersave(); 89 NCNN_EXPORT int set_cpu_powersave(int powersave); 90 91 // convenient wrapper 92 NCNN_EXPORT const CpuSet& get_cpu_thread_affinity_mask(int powersave); 93 94 // set explicit thread affinity 95 NCNN_EXPORT int set_cpu_thread_affinity(const CpuSet& thread_affinity_mask); 96 97 // misc function wrapper for openmp routines 98 NCNN_EXPORT int get_omp_num_threads(); 99 NCNN_EXPORT void set_omp_num_threads(int num_threads); 100 101 NCNN_EXPORT int get_omp_dynamic(); 102 NCNN_EXPORT void set_omp_dynamic(int dynamic); 103 104 NCNN_EXPORT int get_omp_thread_num(); 105 106 NCNN_EXPORT int get_kmp_blocktime(); 107 NCNN_EXPORT void set_kmp_blocktime(int time_ms); 108 109 // need to flush denormals on Intel Chipset. 110 // Other architectures such as ARM can be added as needed. 111 // 0 = DAZ OFF, FTZ OFF 112 // 1 = DAZ ON , FTZ OFF 113 // 2 = DAZ OFF, FTZ ON 114 // 3 = DAZ ON, FTZ ON 115 NCNN_EXPORT int get_flush_denormals(); 116 NCNN_EXPORT int set_flush_denormals(int flush_denormals); 117 118 } // namespace ncnn 119 120 #endif // NCNN_CPU_H 121