1/* 2 * Licensed to the Apache Software Foundation (ASF) under one 3 * or more contributor license agreements. See the NOTICE file 4 * distributed with this work for additional information 5 * regarding copyright ownership. The ASF licenses this file 6 * to you under the Apache License, Version 2.0 (the 7 * "License"); you may not use this file except in compliance 8 * with the License. You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, 13 * software distributed under the License is distributed on an 14 * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 15 * KIND, either express or implied. See the License for the 16 * specific language governing permissions and limitations 17 * under the License. 18 */ 19 20package vta.core 21 22import chisel3._ 23import chisel3.util._ 24import vta.util.config._ 25import vta.shell._ 26 27/** EventCounters. 28 * 29 * This unit contains all the event counting logic. One common event tracked in 30 * hardware is the number of clock cycles taken to achieve certain task. We 31 * can count the total number of clock cycles spent in a VTA run by checking 32 * launch and finish signals. 33 * 34 * The event counter value is passed to the VCR module via the ecnt port, so 35 * they can be accessed by the host. The number of event counters (nECnt) is 36 * defined in the Shell VCR module as a parameter, see VCRParams. 37 * 38 * If one would like to add an event counter, then the value of nECnt must be 39 * changed in VCRParams together with the corresponding counting logic here. 40 */ 41class EventCounters(debug: Boolean = false)(implicit p: Parameters) 42 extends Module { 43 val vp = p(ShellKey).vcrParams 44 val io = IO(new Bundle { 45 val launch = Input(Bool()) 46 val finish = Input(Bool()) 47 val ecnt = Vec(vp.nECnt, ValidIO(UInt(vp.regBits.W))) 48 }) 49 val cycle_cnt = RegInit(0.U(vp.regBits.W)) 50 when(io.launch && !io.finish) { 51 cycle_cnt := cycle_cnt + 1.U 52 }.otherwise { 53 cycle_cnt := 0.U 54 } 55 io.ecnt(0).valid := io.finish 56 io.ecnt(0).bits := cycle_cnt 57} 58