1 /* $NetBSD: dbcool.c,v 1.46 2016/07/11 14:44:49 msaitoh Exp $ */
2
3 /*-
4 * Copyright (c) 2008 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Paul Goyette
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 /*
33 * a driver for the dbCool(tm) family of environmental controllers
34 *
35 * Data sheets for the various supported chips are available at
36 *
37 * http://www.onsemi.com/pub/Collateral/ADM1027-D.PDF
38 * http://www.onsemi.com/pub/Collateral/ADM1030-D.PDF
39 * http://www.onsemi.com/pub/Collateral/ADT7463-D.PDF
40 * http://www.onsemi.com/pub/Collateral/ADT7466.PDF
41 * http://www.onsemi.com/pub/Collateral/ADT7467-D.PDF
42 * http://www.onsemi.com/pub/Collateral/ADT7468-D.PDF
43 * http://www.onsemi.com/pub/Collateral/ADT7473-D.PDF
44 * http://www.onsemi.com/pub/Collateral/ADT7475-D.PDF
45 * http://www.onsemi.com/pub/Collateral/ADT7476-D.PDF
46 * http://www.onsemi.com/pub/Collateral/ADT7490-D.PDF
47 * http://www.smsc.com/media/Downloads_Public/Data_Sheets/6d103s.pdf
48 *
49 * (URLs are correct as of October 5, 2008)
50 */
51
52 #include <sys/cdefs.h>
53 __KERNEL_RCSID(0, "$NetBSD: dbcool.c,v 1.46 2016/07/11 14:44:49 msaitoh Exp $");
54
55 #include <sys/param.h>
56 #include <sys/systm.h>
57 #include <sys/kernel.h>
58 #include <sys/device.h>
59 #include <sys/malloc.h>
60 #include <sys/sysctl.h>
61 #include <sys/module.h>
62
63 #include <dev/i2c/dbcool_var.h>
64 #include <dev/i2c/dbcool_reg.h>
65
66 /* Config interface */
67 static int dbcool_match(device_t, cfdata_t, void *);
68 static void dbcool_attach(device_t, device_t, void *);
69 static int dbcool_detach(device_t, int);
70
71 /* Device attributes */
72 static int dbcool_supply_voltage(struct dbcool_softc *);
73 static bool dbcool_islocked(struct dbcool_softc *);
74
75 /* Sensor read functions */
76 static void dbcool_refresh(struct sysmon_envsys *, envsys_data_t *);
77 static int dbcool_read_rpm(struct dbcool_softc *, uint8_t);
78 static int dbcool_read_temp(struct dbcool_softc *, uint8_t, bool);
79 static int dbcool_read_volt(struct dbcool_softc *, uint8_t, int, bool);
80
81 /* Sensor get/set limit functions */
82 static void dbcool_get_limits(struct sysmon_envsys *, envsys_data_t *,
83 sysmon_envsys_lim_t *, uint32_t *);
84 static void dbcool_get_temp_limits(struct dbcool_softc *, int,
85 sysmon_envsys_lim_t *, uint32_t *);
86 static void dbcool_get_volt_limits(struct dbcool_softc *, int,
87 sysmon_envsys_lim_t *, uint32_t *);
88 static void dbcool_get_fan_limits(struct dbcool_softc *, int,
89 sysmon_envsys_lim_t *, uint32_t *);
90
91 static void dbcool_set_limits(struct sysmon_envsys *, envsys_data_t *,
92 sysmon_envsys_lim_t *, uint32_t *);
93 static void dbcool_set_temp_limits(struct dbcool_softc *, int,
94 sysmon_envsys_lim_t *, uint32_t *);
95 static void dbcool_set_volt_limits(struct dbcool_softc *, int,
96 sysmon_envsys_lim_t *, uint32_t *);
97 static void dbcool_set_fan_limits(struct dbcool_softc *, int,
98 sysmon_envsys_lim_t *, uint32_t *);
99
100 /* SYSCTL Helpers */
101 SYSCTL_SETUP_PROTO(sysctl_dbcoolsetup);
102 static int sysctl_dbcool_temp(SYSCTLFN_PROTO);
103 static int sysctl_adm1030_temp(SYSCTLFN_PROTO);
104 static int sysctl_adm1030_trange(SYSCTLFN_PROTO);
105 static int sysctl_dbcool_duty(SYSCTLFN_PROTO);
106 static int sysctl_dbcool_behavior(SYSCTLFN_PROTO);
107 static int sysctl_dbcool_slope(SYSCTLFN_PROTO);
108 static int sysctl_dbcool_thyst(SYSCTLFN_PROTO);
109
110 /* Set-up subroutines */
111 static void dbcool_setup_controllers(struct dbcool_softc *);
112 static int dbcool_setup_sensors(struct dbcool_softc *);
113 static int dbcool_attach_sensor(struct dbcool_softc *, int);
114 static int dbcool_attach_temp_control(struct dbcool_softc *, int,
115 struct chip_id *);
116
117 #ifdef DBCOOL_DEBUG
118 static int sysctl_dbcool_reg_select(SYSCTLFN_PROTO);
119 static int sysctl_dbcool_reg_access(SYSCTLFN_PROTO);
120 #endif /* DBCOOL_DEBUG */
121
122 /*
123 * Descriptions for SYSCTL entries
124 */
125 struct dbc_sysctl_info {
126 const char *name;
127 const char *desc;
128 bool lockable;
129 int (*helper)(SYSCTLFN_PROTO);
130 };
131
132 static struct dbc_sysctl_info dbc_sysctl_table[] = {
133 /*
134 * The first several entries must remain in the same order as the
135 * corresponding entries in enum dbc_pwm_params
136 */
137 { "behavior", "operating behavior and temp selector",
138 true, sysctl_dbcool_behavior },
139 { "min_duty", "minimum fan controller PWM duty cycle",
140 true, sysctl_dbcool_duty },
141 { "max_duty", "maximum fan controller PWM duty cycle",
142 true, sysctl_dbcool_duty },
143 { "cur_duty", "current fan controller PWM duty cycle",
144 false, sysctl_dbcool_duty },
145
146 /*
147 * The rest of these should be in the order in which they
148 * are to be stored in the sysctl tree; the table index is
149 * used as the high-order bits of the sysctl_num to maintain
150 * the sequence.
151 *
152 * If you rearrange the order of these items, be sure to
153 * update the sysctl_index in the XXX_sensor_table[] for
154 * the various chips!
155 */
156 { "Trange", "temp slope/range to reach 100% duty cycle",
157 true, sysctl_dbcool_slope },
158 { "Tmin", "temp at which to start fan controller",
159 true, sysctl_dbcool_temp },
160 { "Ttherm", "temp at which THERM is asserted",
161 true, sysctl_dbcool_temp },
162 { "Thyst", "temp hysteresis for stopping fan controller",
163 true, sysctl_dbcool_thyst },
164 { "Tmin", "temp at which to start fan controller",
165 true, sysctl_adm1030_temp },
166 { "Trange", "temp slope/range to reach 100% duty cycle",
167 true, sysctl_adm1030_trange },
168 };
169
170 static const char *dbc_sensor_names[] = {
171 "l_temp", "r1_temp", "r2_temp", "Vccp", "Vcc", "fan1",
172 "fan2", "fan3", "fan4", "AIN1", "AIN2", "V2dot5",
173 "V5", "V12", "Vtt", "Imon", "VID"
174 };
175
176 /*
177 * Following table derived from product data-sheets
178 */
179 static int64_t nominal_voltages[] = {
180 -1, /* Vcc can be either 3.3 or 5.0V
181 at 3/4 scale */
182 2249939, /* Vccp 2.25V 3/4 scale */
183 2497436, /* 2.5VIN 2.5V 3/4 scale */
184 5002466, /* 5VIN 5V 3/4 scale */
185 12000000, /* 12VIN 12V 3/4 scale */
186 1690809, /* Vtt, Imon 2.25V full scale */
187 1689600, /* AIN1, AIN2 2.25V full scale */
188 0
189 };
190
191 /*
192 * Sensor-type, { val-reg, hilim-reg, lolim-reg}, name-idx, sysctl-table-idx,
193 * nom-voltage-index
194 */
195 struct dbcool_sensor ADT7490_sensor_table[] = {
196 { DBC_TEMP, { DBCOOL_LOCAL_TEMP,
197 DBCOOL_LOCAL_HIGHLIM,
198 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 },
199 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP,
200 DBCOOL_REMOTE1_HIGHLIM,
201 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 },
202 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP,
203 DBCOOL_REMOTE2_HIGHLIM,
204 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 },
205 { DBC_VOLT, { DBCOOL_VCCP,
206 DBCOOL_VCCP_HIGHLIM,
207 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 },
208 { DBC_VOLT, { DBCOOL_VCC,
209 DBCOOL_VCC_HIGHLIM,
210 DBCOOL_VCC_LOWLIM }, 4, 0, 0 },
211 { DBC_VOLT, { DBCOOL_25VIN,
212 DBCOOL_25VIN_HIGHLIM,
213 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 },
214 { DBC_VOLT, { DBCOOL_5VIN,
215 DBCOOL_5VIN_HIGHLIM,
216 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 },
217 { DBC_VOLT, { DBCOOL_12VIN,
218 DBCOOL_12VIN_HIGHLIM,
219 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 },
220 { DBC_VOLT, { DBCOOL_VTT,
221 DBCOOL_VTT_HIGHLIM,
222 DBCOOL_VTT_LOWLIM }, 14, 0, 5 },
223 { DBC_VOLT, { DBCOOL_IMON,
224 DBCOOL_IMON_HIGHLIM,
225 DBCOOL_IMON_LOWLIM }, 15, 0, 5 },
226 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB,
227 DBCOOL_NO_REG,
228 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 },
229 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB,
230 DBCOOL_NO_REG,
231 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 },
232 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB,
233 DBCOOL_NO_REG,
234 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 },
235 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB,
236 DBCOOL_NO_REG,
237 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 },
238 { DBC_VID, { DBCOOL_VID_REG,
239 DBCOOL_NO_REG,
240 DBCOOL_NO_REG }, 16, 0, 0 },
241 { DBC_CTL, { DBCOOL_LOCAL_TMIN,
242 DBCOOL_NO_REG,
243 DBCOOL_NO_REG }, 0, 5, 0 },
244 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH,
245 DBCOOL_NO_REG,
246 DBCOOL_NO_REG }, 0, 6, 0 },
247 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80,
248 DBCOOL_NO_REG,
249 DBCOOL_NO_REG }, 0, 7, 0 },
250 { DBC_CTL, { DBCOOL_REMOTE1_TMIN,
251 DBCOOL_NO_REG,
252 DBCOOL_NO_REG }, 1, 5, 0 },
253 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH,
254 DBCOOL_NO_REG,
255 DBCOOL_NO_REG }, 1, 6, 0 },
256 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST,
257 DBCOOL_NO_REG,
258 DBCOOL_NO_REG }, 1, 7, 0 },
259 { DBC_CTL, { DBCOOL_REMOTE2_TMIN,
260 DBCOOL_NO_REG,
261 DBCOOL_NO_REG }, 2, 5, 0 },
262 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH,
263 DBCOOL_NO_REG,
264 DBCOOL_NO_REG }, 2, 6, 0 },
265 { DBC_CTL, { DBCOOL_R2_TMIN_HYST,
266 DBCOOL_NO_REG,
267 DBCOOL_NO_REG }, 2, 7, 0 },
268 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 }
269 };
270
271 struct dbcool_sensor ADT7476_sensor_table[] = {
272 { DBC_TEMP, { DBCOOL_LOCAL_TEMP,
273 DBCOOL_LOCAL_HIGHLIM,
274 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 },
275 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP,
276 DBCOOL_REMOTE1_HIGHLIM,
277 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 },
278 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP,
279 DBCOOL_REMOTE2_HIGHLIM,
280 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 },
281 { DBC_VOLT, { DBCOOL_VCCP,
282 DBCOOL_VCCP_HIGHLIM,
283 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 },
284 { DBC_VOLT, { DBCOOL_VCC,
285 DBCOOL_VCC_HIGHLIM,
286 DBCOOL_VCC_LOWLIM }, 4, 0, 0 },
287 { DBC_VOLT, { DBCOOL_25VIN,
288 DBCOOL_25VIN_HIGHLIM,
289 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 },
290 { DBC_VOLT, { DBCOOL_5VIN,
291 DBCOOL_5VIN_HIGHLIM,
292 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 },
293 { DBC_VOLT, { DBCOOL_12VIN,
294 DBCOOL_12VIN_HIGHLIM,
295 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 },
296 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB,
297 DBCOOL_NO_REG,
298 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 },
299 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB,
300 DBCOOL_NO_REG,
301 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 },
302 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB,
303 DBCOOL_NO_REG,
304 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 },
305 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB,
306 DBCOOL_NO_REG,
307 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 },
308 { DBC_VID, { DBCOOL_VID_REG,
309 DBCOOL_NO_REG,
310 DBCOOL_NO_REG }, 16, 0, 0 },
311 { DBC_CTL, { DBCOOL_LOCAL_TMIN,
312 DBCOOL_NO_REG,
313 DBCOOL_NO_REG }, 0, 5, 0 },
314 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH,
315 DBCOOL_NO_REG,
316 DBCOOL_NO_REG }, 0, 6, 0 },
317 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80,
318 DBCOOL_NO_REG,
319 DBCOOL_NO_REG }, 0, 7, 0 },
320 { DBC_CTL, { DBCOOL_REMOTE1_TMIN,
321 DBCOOL_NO_REG,
322 DBCOOL_NO_REG }, 1, 5, 0 },
323 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH,
324 DBCOOL_NO_REG,
325 DBCOOL_NO_REG }, 1, 6, 0 },
326 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST,
327 DBCOOL_NO_REG,
328 DBCOOL_NO_REG }, 1, 7, 0 },
329 { DBC_CTL, { DBCOOL_REMOTE2_TMIN,
330 DBCOOL_NO_REG,
331 DBCOOL_NO_REG }, 2, 5, 0 },
332 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH,
333 DBCOOL_NO_REG,
334 DBCOOL_NO_REG }, 2, 6, 0 },
335 { DBC_CTL, { DBCOOL_R2_TMIN_HYST,
336 DBCOOL_NO_REG,
337 DBCOOL_NO_REG }, 2, 7, 0 },
338 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 }
339 };
340
341 struct dbcool_sensor ADT7475_sensor_table[] = {
342 { DBC_TEMP, { DBCOOL_LOCAL_TEMP,
343 DBCOOL_LOCAL_HIGHLIM,
344 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 },
345 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP,
346 DBCOOL_REMOTE1_HIGHLIM,
347 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 },
348 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP,
349 DBCOOL_REMOTE2_HIGHLIM,
350 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 },
351 { DBC_VOLT, { DBCOOL_VCCP,
352 DBCOOL_VCCP_HIGHLIM,
353 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 },
354 { DBC_VOLT, { DBCOOL_VCC,
355 DBCOOL_VCC_HIGHLIM,
356 DBCOOL_VCC_LOWLIM }, 4, 0, 0 },
357 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB,
358 DBCOOL_NO_REG,
359 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 },
360 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB,
361 DBCOOL_NO_REG,
362 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 },
363 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB,
364 DBCOOL_NO_REG,
365 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 },
366 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB,
367 DBCOOL_NO_REG,
368 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 },
369 { DBC_CTL, { DBCOOL_LOCAL_TMIN,
370 DBCOOL_NO_REG,
371 DBCOOL_NO_REG }, 0, 5, 0 },
372 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH,
373 DBCOOL_NO_REG,
374 DBCOOL_NO_REG }, 0, 6, 0 },
375 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80,
376 DBCOOL_NO_REG,
377 DBCOOL_NO_REG }, 0, 7, 0 },
378 { DBC_CTL, { DBCOOL_REMOTE1_TMIN,
379 DBCOOL_NO_REG,
380 DBCOOL_NO_REG }, 1, 5, 0 },
381 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH,
382 DBCOOL_NO_REG,
383 DBCOOL_NO_REG }, 1, 6, 0 },
384 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST,
385 DBCOOL_NO_REG,
386 DBCOOL_NO_REG }, 1, 7, 0 },
387 { DBC_CTL, { DBCOOL_REMOTE2_TMIN,
388 DBCOOL_NO_REG,
389 DBCOOL_NO_REG }, 2, 5, 0 },
390 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH,
391 DBCOOL_NO_REG,
392 DBCOOL_NO_REG }, 2, 6, 0 },
393 { DBC_CTL, { DBCOOL_R2_TMIN_HYST,
394 DBCOOL_NO_REG,
395 DBCOOL_NO_REG }, 2, 7, 0 },
396 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 }
397 };
398
399 /*
400 * The registers of dbcool_power_control must be in the same order as
401 * in enum dbc_pwm_params
402 */
403 struct dbcool_power_control ADT7475_power_table[] = {
404 { { DBCOOL_PWM1_CTL, DBCOOL_PWM1_MINDUTY,
405 DBCOOL_PWM1_MAXDUTY, DBCOOL_PWM1_CURDUTY },
406 "fan_control_1" },
407 { { DBCOOL_PWM2_CTL, DBCOOL_PWM2_MINDUTY,
408 DBCOOL_PWM2_MAXDUTY, DBCOOL_PWM2_CURDUTY },
409 "fan_control_2" },
410 { { DBCOOL_PWM3_CTL, DBCOOL_PWM3_MINDUTY,
411 DBCOOL_PWM3_MAXDUTY, DBCOOL_PWM3_CURDUTY },
412 "fan_control_3" },
413 { { 0, 0, 0, 0 }, NULL }
414 };
415
416 struct dbcool_sensor ADT7466_sensor_table[] = {
417 { DBC_TEMP, { DBCOOL_ADT7466_LCL_TEMP_MSB,
418 DBCOOL_ADT7466_LCL_TEMP_HILIM,
419 DBCOOL_ADT7466_LCL_TEMP_LOLIM }, 0, 0, 0 },
420 { DBC_TEMP, { DBCOOL_ADT7466_REM_TEMP_MSB,
421 DBCOOL_ADT7466_REM_TEMP_HILIM,
422 DBCOOL_ADT7466_REM_TEMP_LOLIM }, 1, 0, 0 },
423 { DBC_VOLT, { DBCOOL_ADT7466_VCC,
424 DBCOOL_ADT7466_VCC_HILIM,
425 DBCOOL_ADT7466_VCC_LOLIM }, 4, 0, 0 },
426 { DBC_VOLT, { DBCOOL_ADT7466_AIN1,
427 DBCOOL_ADT7466_AIN1_HILIM,
428 DBCOOL_ADT7466_AIN1_LOLIM }, 9, 0, 6 },
429 { DBC_VOLT, { DBCOOL_ADT7466_AIN2,
430 DBCOOL_ADT7466_AIN2_HILIM,
431 DBCOOL_ADT7466_AIN2_LOLIM }, 10, 0, 6 },
432 { DBC_FAN, { DBCOOL_ADT7466_FANA_LSB,
433 DBCOOL_NO_REG,
434 DBCOOL_ADT7466_FANA_LOLIM_LSB }, 5, 0, 0 },
435 { DBC_FAN, { DBCOOL_ADT7466_FANB_LSB,
436 DBCOOL_NO_REG,
437 DBCOOL_ADT7466_FANB_LOLIM_LSB }, 6, 0, 0 },
438 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 }
439 };
440
441 struct dbcool_sensor ADM1027_sensor_table[] = {
442 { DBC_TEMP, { DBCOOL_LOCAL_TEMP,
443 DBCOOL_LOCAL_HIGHLIM,
444 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 },
445 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP,
446 DBCOOL_REMOTE1_HIGHLIM,
447 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 },
448 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP,
449 DBCOOL_REMOTE2_HIGHLIM,
450 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 },
451 { DBC_VOLT, { DBCOOL_VCCP,
452 DBCOOL_VCCP_HIGHLIM,
453 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 },
454 { DBC_VOLT, { DBCOOL_VCC,
455 DBCOOL_VCC_HIGHLIM,
456 DBCOOL_VCC_LOWLIM }, 4, 0, 0 },
457 { DBC_VOLT, { DBCOOL_25VIN,
458 DBCOOL_25VIN_HIGHLIM,
459 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 },
460 { DBC_VOLT, { DBCOOL_5VIN,
461 DBCOOL_5VIN_HIGHLIM,
462 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 },
463 { DBC_VOLT, { DBCOOL_12VIN,
464 DBCOOL_12VIN_HIGHLIM,
465 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 },
466 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB,
467 DBCOOL_NO_REG,
468 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 },
469 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB,
470 DBCOOL_NO_REG,
471 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 },
472 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB,
473 DBCOOL_NO_REG,
474 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 },
475 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB,
476 DBCOOL_NO_REG,
477 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 },
478 { DBC_VID, { DBCOOL_VID_REG,
479 DBCOOL_NO_REG,
480 DBCOOL_NO_REG }, 16, 0, 0 },
481 { DBC_CTL, { DBCOOL_LOCAL_TMIN,
482 DBCOOL_NO_REG,
483 DBCOOL_NO_REG }, 0, 5, 0 },
484 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH,
485 DBCOOL_NO_REG,
486 DBCOOL_NO_REG }, 0, 6, 0 },
487 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST | 0x80,
488 DBCOOL_NO_REG,
489 DBCOOL_NO_REG }, 0, 7, 0 },
490 { DBC_CTL, { DBCOOL_REMOTE1_TMIN,
491 DBCOOL_NO_REG,
492 DBCOOL_NO_REG }, 1, 5, 0 },
493 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH,
494 DBCOOL_NO_REG,
495 DBCOOL_NO_REG }, 1, 6, 0 },
496 { DBC_CTL, { DBCOOL_R1_LCL_TMIN_HYST,
497 DBCOOL_NO_REG,
498 DBCOOL_NO_REG }, 1, 7, 0 },
499 { DBC_CTL, { DBCOOL_REMOTE2_TMIN,
500 DBCOOL_NO_REG,
501 DBCOOL_NO_REG }, 2, 5, 0 },
502 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH,
503 DBCOOL_NO_REG,
504 DBCOOL_NO_REG }, 2, 6, 0 },
505 { DBC_CTL, { DBCOOL_R2_TMIN_HYST,
506 DBCOOL_NO_REG,
507 DBCOOL_NO_REG }, 2, 7, 0 },
508 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 }
509 };
510
511 struct dbcool_sensor ADM1030_sensor_table[] = {
512 { DBC_TEMP, { DBCOOL_ADM1030_L_TEMP,
513 DBCOOL_ADM1030_L_HI_LIM,
514 DBCOOL_ADM1030_L_LO_LIM }, 0, 0, 0 },
515 { DBC_TEMP, { DBCOOL_ADM1030_R_TEMP,
516 DBCOOL_ADM1030_R_HI_LIM,
517 DBCOOL_ADM1030_R_LO_LIM }, 1, 0, 0 },
518 { DBC_FAN, { DBCOOL_ADM1030_FAN_TACH,
519 DBCOOL_NO_REG,
520 DBCOOL_ADM1030_FAN_LO_LIM }, 5, 0, 0 },
521 { DBC_CTL, { DBCOOL_ADM1030_L_TMIN,
522 DBCOOL_NO_REG,
523 DBCOOL_NO_REG }, 0, 8, 0 },
524 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH,
525 DBCOOL_NO_REG,
526 DBCOOL_NO_REG }, 0, 9, 0 },
527 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH,
528 DBCOOL_NO_REG,
529 DBCOOL_NO_REG }, 0, 6, 0 },
530 { DBC_CTL, { DBCOOL_ADM1030_R_TMIN,
531 DBCOOL_NO_REG,
532 DBCOOL_NO_REG }, 1, 8, 0 },
533 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH,
534 DBCOOL_NO_REG,
535 DBCOOL_NO_REG }, 1, 9, 0 },
536 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH,
537 DBCOOL_NO_REG,
538 DBCOOL_NO_REG }, 1, 6, 0 },
539 { DBC_EOF, {0, 0, 0 }, 0, 0, 0 }
540 };
541
542 struct dbcool_power_control ADM1030_power_table[] = {
543 { { DBCOOL_ADM1030_CFG1, DBCOOL_NO_REG, DBCOOL_NO_REG,
544 DBCOOL_ADM1030_FAN_SPEED_CFG },
545 "fan_control_1" },
546 { { 0, 0, 0, 0 }, NULL }
547 };
548
549 struct dbcool_sensor ADM1031_sensor_table[] = {
550 { DBC_TEMP, { DBCOOL_ADM1030_L_TEMP,
551 DBCOOL_ADM1030_L_HI_LIM,
552 DBCOOL_ADM1030_L_LO_LIM }, 0, 0, 0 },
553 { DBC_TEMP, { DBCOOL_ADM1030_R_TEMP,
554 DBCOOL_ADM1030_R_HI_LIM,
555 DBCOOL_ADM1030_R_LO_LIM }, 1, 0, 0 },
556 { DBC_TEMP, { DBCOOL_ADM1031_R2_TEMP,
557 DBCOOL_ADM1031_R2_HI_LIM,
558 DBCOOL_ADM1031_R2_LO_LIM }, 2, 0, 0 },
559 { DBC_FAN, { DBCOOL_ADM1030_FAN_TACH,
560 DBCOOL_NO_REG,
561 DBCOOL_ADM1030_FAN_LO_LIM }, 5, 0, 0 },
562 { DBC_FAN, { DBCOOL_ADM1031_FAN2_TACH,
563 DBCOOL_NO_REG,
564 DBCOOL_ADM1031_FAN2_LO_LIM }, 6, 0, 0 },
565 { DBC_CTL, { DBCOOL_ADM1030_L_TMIN,
566 DBCOOL_NO_REG,
567 DBCOOL_NO_REG }, 0, 8, 0 },
568 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH,
569 DBCOOL_NO_REG,
570 DBCOOL_NO_REG }, 0, 9, 0 },
571 { DBC_CTL, { DBCOOL_ADM1030_L_TTHRESH,
572 DBCOOL_NO_REG,
573 DBCOOL_NO_REG }, 0, 6, 0 },
574 { DBC_CTL, { DBCOOL_ADM1030_R_TMIN,
575 DBCOOL_NO_REG,
576 DBCOOL_NO_REG }, 1, 8, 0 },
577 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH,
578 DBCOOL_NO_REG,
579 DBCOOL_NO_REG }, 1, 9, 0 },
580 { DBC_CTL, { DBCOOL_ADM1030_R_TTHRESH,
581 DBCOOL_NO_REG,
582 DBCOOL_NO_REG }, 1, 6, 0 },
583 { DBC_CTL, { DBCOOL_ADM1031_R2_TMIN,
584 DBCOOL_NO_REG,
585 DBCOOL_NO_REG }, 2, 8, 0 },
586 { DBC_CTL, { DBCOOL_ADM1031_R2_TTHRESH,
587 DBCOOL_NO_REG,
588 DBCOOL_NO_REG }, 2, 9, 0 },
589 { DBC_CTL, { DBCOOL_ADM1031_R2_TTHRESH,
590 DBCOOL_NO_REG,
591 DBCOOL_NO_REG }, 2, 6, 0 },
592 { DBC_EOF, {0, 0, 0 }, 0, 0, 0 }
593 };
594
595 struct dbcool_power_control ADM1031_power_table[] = {
596 { { DBCOOL_ADM1030_CFG1, DBCOOL_NO_REG, DBCOOL_NO_REG,
597 DBCOOL_ADM1030_FAN_SPEED_CFG },
598 "fan_control_1" },
599 { { DBCOOL_ADM1030_CFG1, DBCOOL_NO_REG, DBCOOL_NO_REG,
600 DBCOOL_ADM1030_FAN_SPEED_CFG },
601 "fan_control_2" },
602 { { 0, 0, 0, 0 }, NULL }
603 };
604
605 struct dbcool_sensor EMC6D103S_sensor_table[] = {
606 { DBC_TEMP, { DBCOOL_LOCAL_TEMP,
607 DBCOOL_LOCAL_HIGHLIM,
608 DBCOOL_LOCAL_LOWLIM }, 0, 0, 0 },
609 { DBC_TEMP, { DBCOOL_REMOTE1_TEMP,
610 DBCOOL_REMOTE1_HIGHLIM,
611 DBCOOL_REMOTE1_LOWLIM }, 1, 0, 0 },
612 { DBC_TEMP, { DBCOOL_REMOTE2_TEMP,
613 DBCOOL_REMOTE2_HIGHLIM,
614 DBCOOL_REMOTE2_LOWLIM }, 2, 0, 0 },
615 { DBC_VOLT, { DBCOOL_VCCP,
616 DBCOOL_VCCP_HIGHLIM,
617 DBCOOL_VCCP_LOWLIM }, 3, 0, 1 },
618 { DBC_VOLT, { DBCOOL_VCC,
619 DBCOOL_VCC_HIGHLIM,
620 DBCOOL_VCC_LOWLIM }, 4, 0, 0 },
621 { DBC_VOLT, { DBCOOL_25VIN,
622 DBCOOL_25VIN_HIGHLIM,
623 DBCOOL_25VIN_LOWLIM }, 11, 0, 2 },
624 { DBC_VOLT, { DBCOOL_5VIN,
625 DBCOOL_5VIN_HIGHLIM,
626 DBCOOL_5VIN_LOWLIM }, 12, 0, 3 },
627 { DBC_VOLT, { DBCOOL_12VIN,
628 DBCOOL_12VIN_HIGHLIM,
629 DBCOOL_12VIN_LOWLIM }, 13, 0, 4 },
630 { DBC_FAN, { DBCOOL_FAN1_TACH_LSB,
631 DBCOOL_NO_REG,
632 DBCOOL_TACH1_MIN_LSB }, 5, 0, 0 },
633 { DBC_FAN, { DBCOOL_FAN2_TACH_LSB,
634 DBCOOL_NO_REG,
635 DBCOOL_TACH2_MIN_LSB }, 6, 0, 0 },
636 { DBC_FAN, { DBCOOL_FAN3_TACH_LSB,
637 DBCOOL_NO_REG,
638 DBCOOL_TACH3_MIN_LSB }, 7, 0, 0 },
639 { DBC_FAN, { DBCOOL_FAN4_TACH_LSB,
640 DBCOOL_NO_REG,
641 DBCOOL_TACH4_MIN_LSB }, 8, 0, 0 },
642 { DBC_VID, { DBCOOL_VID_REG,
643 DBCOOL_NO_REG,
644 DBCOOL_NO_REG }, 16, 0, 0 },
645 { DBC_CTL, { DBCOOL_LOCAL_TMIN,
646 DBCOOL_NO_REG,
647 DBCOOL_NO_REG }, 0, 5, 0 },
648 { DBC_CTL, { DBCOOL_LOCAL_TTHRESH,
649 DBCOOL_NO_REG,
650 DBCOOL_NO_REG }, 0, 6, 0 },
651 { DBC_CTL, { DBCOOL_REMOTE1_TMIN,
652 DBCOOL_NO_REG,
653 DBCOOL_NO_REG }, 1, 5, 0 },
654 { DBC_CTL, { DBCOOL_REMOTE1_TTHRESH,
655 DBCOOL_NO_REG,
656 DBCOOL_NO_REG }, 1, 6, 0 },
657 { DBC_CTL, { DBCOOL_REMOTE2_TMIN,
658 DBCOOL_NO_REG,
659 DBCOOL_NO_REG }, 2, 5, 0 },
660 { DBC_CTL, { DBCOOL_REMOTE2_TTHRESH,
661 DBCOOL_NO_REG,
662 DBCOOL_NO_REG }, 2, 6, 0 },
663 { DBC_EOF, { 0, 0, 0 }, 0, 0, 0 }
664 };
665
666 struct chip_id chip_table[] = {
667 { DBCOOL_COMPANYID, ADT7490_DEVICEID, ADT7490_REV_ID,
668 ADT7490_sensor_table, ADT7475_power_table,
669 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_PECI,
670 90000 * 60, "ADT7490" },
671 { DBCOOL_COMPANYID, ADT7476_DEVICEID, 0xff,
672 ADT7476_sensor_table, ADT7475_power_table,
673 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY,
674 90000 * 60, "ADT7476" },
675 { DBCOOL_COMPANYID, ADT7475_DEVICEID, 0xff,
676 ADT7475_sensor_table, ADT7475_power_table,
677 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_SHDN,
678 90000 * 60, "ADT7475" },
679 { DBCOOL_COMPANYID, ADT7473_DEVICEID, ADT7473_REV_ID1,
680 ADT7475_sensor_table, ADT7475_power_table,
681 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_SHDN,
682 90000 * 60, "ADT7460/ADT7463" },
683 { DBCOOL_COMPANYID, ADT7473_DEVICEID, ADT7473_REV_ID2,
684 ADT7475_sensor_table, ADT7475_power_table,
685 DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_MAXDUTY | DBCFLAG_HAS_SHDN,
686 90000 * 60, "ADT7463-1" },
687 { DBCOOL_COMPANYID, ADT7468_DEVICEID, 0xff,
688 ADT7476_sensor_table, ADT7475_power_table,
689 DBCFLAG_TEMPOFFSET | DBCFLAG_MULTI_VCC | DBCFLAG_HAS_MAXDUTY |
690 DBCFLAG_4BIT_VER | DBCFLAG_HAS_SHDN,
691 90000 * 60, "ADT7467/ADT7468" },
692 { DBCOOL_COMPANYID, ADT7466_DEVICEID, 0xff,
693 ADT7466_sensor_table, NULL,
694 DBCFLAG_ADT7466 | DBCFLAG_TEMPOFFSET | DBCFLAG_HAS_SHDN,
695 82000 * 60, "ADT7466" },
696 { DBCOOL_COMPANYID, ADT7463_DEVICEID, ADT7463_REV_ID1,
697 ADM1027_sensor_table, ADT7475_power_table,
698 DBCFLAG_MULTI_VCC | DBCFLAG_4BIT_VER | DBCFLAG_HAS_SHDN,
699 90000 * 60, "ADT7463" },
700 { DBCOOL_COMPANYID, ADT7463_DEVICEID, ADT7463_REV_ID2,
701 ADM1027_sensor_table, ADT7475_power_table,
702 DBCFLAG_MULTI_VCC | DBCFLAG_4BIT_VER | DBCFLAG_HAS_SHDN |
703 DBCFLAG_HAS_VID_SEL,
704 90000 * 60, "ADT7463" },
705 { DBCOOL_COMPANYID, ADM1027_DEVICEID, ADM1027_REV_ID,
706 ADM1027_sensor_table, ADT7475_power_table,
707 DBCFLAG_MULTI_VCC | DBCFLAG_4BIT_VER,
708 90000 * 60, "ADM1027" },
709 { DBCOOL_COMPANYID, ADM1030_DEVICEID, 0xff,
710 ADM1030_sensor_table, ADM1030_power_table,
711 DBCFLAG_ADM1030 | DBCFLAG_NO_READBYTE,
712 11250 * 60, "ADM1030" },
713 { DBCOOL_COMPANYID, ADM1031_DEVICEID, 0xff,
714 ADM1031_sensor_table, ADM1030_power_table,
715 DBCFLAG_ADM1030 | DBCFLAG_NO_READBYTE,
716 11250 * 60, "ADM1031" },
717 { SMSC_COMPANYID, EMC6D103S_DEVICEID, EMC6D103S_REV_ID,
718 EMC6D103S_sensor_table, ADT7475_power_table,
719 DBCFLAG_4BIT_VER,
720 90000 * 60, "EMC6D103S" },
721 { 0, 0, 0, NULL, NULL, 0, 0, NULL }
722 };
723
724 static const char *behavior[] = {
725 "remote1", "local", "remote2", "full-speed",
726 "disabled", "local+remote2","all-temps", "manual"
727 };
728
729 static char dbcool_cur_behav[16];
730
731 CFATTACH_DECL_NEW(dbcool, sizeof(struct dbcool_softc),
732 dbcool_match, dbcool_attach, dbcool_detach, NULL);
733
734 static const char * dbcool_compats[] = {
735 "i2c-adm1031",
736 NULL
737 };
738 int
dbcool_match(device_t parent,cfdata_t cf,void * aux)739 dbcool_match(device_t parent, cfdata_t cf, void *aux)
740 {
741 struct i2c_attach_args *ia = aux;
742 struct dbcool_chipset dc;
743 dc.dc_tag = ia->ia_tag;
744 dc.dc_addr = ia->ia_addr;
745 dc.dc_chip = NULL;
746 dc.dc_readreg = dbcool_readreg;
747 dc.dc_writereg = dbcool_writereg;
748
749 /* Direct config - match compats */
750 if (ia->ia_name) {
751 if (ia->ia_ncompat > 0) {
752 if (iic_compat_match(ia, dbcool_compats))
753 return 1;
754 }
755 /* Indirect config - check address and chip ID */
756 } else {
757 if ((ia->ia_addr & DBCOOL_ADDRMASK) != DBCOOL_ADDR)
758 return 0;
759 if (dbcool_chip_ident(&dc) >= 0)
760 return 1;
761 }
762 return 0;
763 }
764
765 void
dbcool_attach(device_t parent,device_t self,void * aux)766 dbcool_attach(device_t parent, device_t self, void *aux)
767 {
768 struct dbcool_softc *sc = device_private(self);
769 struct i2c_attach_args *args = aux;
770 uint8_t ver;
771
772 sc->sc_dc.dc_addr = args->ia_addr;
773 sc->sc_dc.dc_tag = args->ia_tag;
774 sc->sc_dc.dc_chip = NULL;
775 sc->sc_dc.dc_readreg = dbcool_readreg;
776 sc->sc_dc.dc_writereg = dbcool_writereg;
777 (void)dbcool_chip_ident(&sc->sc_dc);
778 sc->sc_dev = self;
779
780 aprint_naive("\n");
781 aprint_normal("\n");
782
783 ver = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_REVISION_REG);
784 if (sc->sc_dc.dc_chip->flags & DBCFLAG_4BIT_VER)
785 if (sc->sc_dc.dc_chip->company == SMSC_COMPANYID)
786 {
787 aprint_normal_dev(self, "SMSC %s Controller "
788 "(rev 0x%02x, stepping 0x%02x)\n",
789 sc->sc_dc.dc_chip->name, ver >> 4, ver & 0x0f);
790 } else {
791 aprint_normal_dev(self, "%s dBCool(tm) Controller "
792 "(rev 0x%02x, stepping 0x%02x)\n",
793 sc->sc_dc.dc_chip->name, ver >> 4, ver & 0x0f);
794 }
795 else
796 aprint_normal_dev(self, "%s dBCool(tm) Controller "
797 "(rev 0x%04x)\n", sc->sc_dc.dc_chip->name, ver);
798
799 sc->sc_sysctl_log = NULL;
800
801 #ifdef _MODULE
802 sysctl_dbcoolsetup(&sc->sc_sysctl_log);
803 #endif
804
805 dbcool_setup(self);
806
807 if (!pmf_device_register(self, dbcool_pmf_suspend, dbcool_pmf_resume))
808 aprint_error_dev(self, "couldn't establish power handler\n");
809 }
810
811 static int
dbcool_detach(device_t self,int flags)812 dbcool_detach(device_t self, int flags)
813 {
814 struct dbcool_softc *sc = device_private(self);
815
816 pmf_device_deregister(self);
817
818 sysmon_envsys_unregister(sc->sc_sme);
819
820 sysctl_teardown(&sc->sc_sysctl_log);
821
822 sc->sc_sme = NULL;
823 return 0;
824 }
825
826 /* On suspend, we save the state of the SHDN bit, then set it */
dbcool_pmf_suspend(device_t dev,const pmf_qual_t * qual)827 bool dbcool_pmf_suspend(device_t dev, const pmf_qual_t *qual)
828 {
829 struct dbcool_softc *sc = device_private(dev);
830 uint8_t reg, bit, cfg;
831
832 if ((sc->sc_dc.dc_chip->flags & DBCFLAG_HAS_SHDN) == 0)
833 return true;
834
835 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) {
836 reg = DBCOOL_ADT7466_CONFIG2;
837 bit = DBCOOL_ADT7466_CFG2_SHDN;
838 } else {
839 reg = DBCOOL_CONFIG2_REG;
840 bit = DBCOOL_CFG2_SHDN;
841 }
842 cfg = sc->sc_dc.dc_readreg(&sc->sc_dc, reg);
843 sc->sc_suspend = cfg & bit;
844 cfg |= bit;
845 sc->sc_dc.dc_writereg(&sc->sc_dc, reg, cfg);
846
847 return true;
848 }
849
850 /* On resume, we restore the previous state of the SHDN bit (which
851 we saved in sc_suspend) */
dbcool_pmf_resume(device_t dev,const pmf_qual_t * qual)852 bool dbcool_pmf_resume(device_t dev, const pmf_qual_t *qual)
853 {
854 struct dbcool_softc *sc = device_private(dev);
855 uint8_t reg, cfg;
856
857 if ((sc->sc_dc.dc_chip->flags & DBCFLAG_HAS_SHDN) == 0)
858 return true;
859
860 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) {
861 reg = DBCOOL_ADT7466_CONFIG2;
862 } else {
863 reg = DBCOOL_CONFIG2_REG;
864 }
865 cfg = sc->sc_dc.dc_readreg(&sc->sc_dc, reg);
866 cfg &= ~sc->sc_suspend;
867 sc->sc_dc.dc_writereg(&sc->sc_dc, reg, cfg);
868
869 return true;
870
871 }
872
873 uint8_t
dbcool_readreg(struct dbcool_chipset * dc,uint8_t reg)874 dbcool_readreg(struct dbcool_chipset *dc, uint8_t reg)
875 {
876 uint8_t data = 0;
877
878 if (iic_acquire_bus(dc->dc_tag, 0) != 0)
879 return data;
880
881 if (dc->dc_chip == NULL || dc->dc_chip->flags & DBCFLAG_NO_READBYTE) {
882 /* ADM1027 doesn't support i2c read_byte protocol */
883 if (iic_smbus_send_byte(dc->dc_tag, dc->dc_addr, reg, 0) != 0)
884 goto bad;
885 (void)iic_smbus_receive_byte(dc->dc_tag, dc->dc_addr, &data, 0);
886 } else
887 (void)iic_smbus_read_byte(dc->dc_tag, dc->dc_addr, reg, &data,
888 0);
889
890 bad:
891 iic_release_bus(dc->dc_tag, 0);
892 return data;
893 }
894
895 void
dbcool_writereg(struct dbcool_chipset * dc,uint8_t reg,uint8_t val)896 dbcool_writereg(struct dbcool_chipset *dc, uint8_t reg, uint8_t val)
897 {
898 if (iic_acquire_bus(dc->dc_tag, 0) != 0)
899 return;
900
901 (void)iic_smbus_write_byte(dc->dc_tag, dc->dc_addr, reg, val, 0);
902
903 iic_release_bus(dc->dc_tag, 0);
904 }
905
906 static bool
dbcool_islocked(struct dbcool_softc * sc)907 dbcool_islocked(struct dbcool_softc *sc)
908 {
909 uint8_t cfg_reg;
910
911 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030)
912 return 0;
913
914 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466)
915 cfg_reg = DBCOOL_ADT7466_CONFIG1;
916 else
917 cfg_reg = DBCOOL_CONFIG1_REG;
918
919 if (sc->sc_dc.dc_readreg(&sc->sc_dc, cfg_reg) & DBCOOL_CFG1_LOCK)
920 return 1;
921 else
922 return 0;
923 }
924
925 static int
dbcool_read_temp(struct dbcool_softc * sc,uint8_t reg,bool extres)926 dbcool_read_temp(struct dbcool_softc *sc, uint8_t reg, bool extres)
927 {
928 uint8_t t1, t2, t3, val, ext = 0;
929 int temp;
930
931 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) {
932 /*
933 * ADT7466 temps are in strange location
934 */
935 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADT7466_CONFIG1);
936 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg);
937 if (extres)
938 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, reg + 1);
939 } else if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) {
940 /*
941 * ADM1030 temps are in their own special place, too
942 */
943 if (extres) {
944 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_TEMP_EXTRES);
945 if (reg == DBCOOL_ADM1030_L_TEMP)
946 ext >>= 6;
947 else if (reg == DBCOOL_ADM1031_R2_TEMP)
948 ext >>= 4;
949 else
950 ext >>= 1;
951 ext &= 0x03;
952 }
953 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg);
954 } else if (extres) {
955 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES2_REG);
956
957 /* Read all msb regs to unlatch them */
958 t1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_12VIN);
959 t1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_REMOTE1_TEMP);
960 t2 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_REMOTE2_TEMP);
961 t3 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_LOCAL_TEMP);
962 switch (reg) {
963 case DBCOOL_REMOTE1_TEMP:
964 val = t1;
965 ext >>= 2;
966 break;
967 case DBCOOL_LOCAL_TEMP:
968 val = t3;
969 ext >>= 4;
970 break;
971 case DBCOOL_REMOTE2_TEMP:
972 val = t2;
973 ext >>= 6;
974 break;
975 default:
976 val = 0;
977 break;
978 }
979 ext &= 0x03;
980 }
981 else
982 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg);
983
984 /* Check for invalid temp values */
985 if ((sc->sc_temp_offset == 0 && val == 0x80) ||
986 (sc->sc_temp_offset != 0 && val == 0))
987 return 0;
988
989 /* If using offset mode, adjust, else treat as signed */
990 if (sc->sc_temp_offset) {
991 temp = val;
992 temp -= sc->sc_temp_offset;
993 } else
994 temp = (int8_t)val;
995
996 /* Convert degC to uK and include extended precision bits */
997 temp *= 1000000;
998 temp += 250000 * (int)ext;
999 temp += 273150000U;
1000
1001 return temp;
1002 }
1003
1004 static int
dbcool_read_rpm(struct dbcool_softc * sc,uint8_t reg)1005 dbcool_read_rpm(struct dbcool_softc *sc, uint8_t reg)
1006 {
1007 int rpm;
1008 uint8_t rpm_lo, rpm_hi;
1009
1010 rpm_lo = sc->sc_dc.dc_readreg(&sc->sc_dc, reg);
1011 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030)
1012 rpm_hi = (rpm_lo == 0xff)?0xff:0x0;
1013 else
1014 rpm_hi = sc->sc_dc.dc_readreg(&sc->sc_dc, reg + 1);
1015
1016 rpm = (rpm_hi << 8) | rpm_lo;
1017 if (rpm == 0xffff)
1018 return 0; /* 0xffff indicates stalled/failed fan */
1019
1020 /* don't divide by zero */
1021 return (rpm == 0)? 0 : (sc->sc_dc.dc_chip->rpm_dividend / rpm);
1022 }
1023
1024 /* Provide chip's supply voltage, in microvolts */
1025 static int
dbcool_supply_voltage(struct dbcool_softc * sc)1026 dbcool_supply_voltage(struct dbcool_softc *sc)
1027 {
1028 if (sc->sc_dc.dc_chip->flags & DBCFLAG_MULTI_VCC) {
1029 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_CONFIG1_REG) & DBCOOL_CFG1_Vcc)
1030 return 5002500;
1031 else
1032 return 3300000;
1033 } else if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) {
1034 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADT7466_CONFIG1) &
1035 DBCOOL_ADT7466_CFG1_Vcc)
1036 return 5000000;
1037 else
1038 return 3300000;
1039 } else
1040 return 3300000;
1041 }
1042
1043 /*
1044 * Nominal voltages are calculated in microvolts
1045 */
1046 static int
dbcool_read_volt(struct dbcool_softc * sc,uint8_t reg,int nom_idx,bool extres)1047 dbcool_read_volt(struct dbcool_softc *sc, uint8_t reg, int nom_idx, bool extres)
1048 {
1049 uint8_t ext = 0, v1, v2, v3, v4, val;
1050 int64_t ret;
1051 int64_t nom;
1052
1053 nom = nominal_voltages[nom_idx];
1054 if (nom < 0)
1055 nom = sc->sc_supply_voltage;
1056
1057 /* ADT7466 voltages are in strange locations with only 8-bits */
1058 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466)
1059 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg);
1060 else
1061 /*
1062 * It's a "normal" dbCool chip - check for regs that
1063 * share extended resolution bits since we have to
1064 * read all the MSB registers to unlatch them.
1065 */
1066 if (!extres)
1067 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg);
1068 else if (reg == DBCOOL_12VIN) {
1069 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES2_REG) & 0x03;
1070 val = sc->sc_dc.dc_readreg(&sc->sc_dc, reg);
1071 (void)dbcool_read_temp(sc, DBCOOL_LOCAL_TEMP, true);
1072 } else if (reg == DBCOOL_VTT || reg == DBCOOL_IMON) {
1073 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES_VTT_IMON);
1074 v1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_IMON);
1075 v2 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VTT);
1076 if (reg == DBCOOL_IMON) {
1077 val = v1;
1078 ext >>= 6;
1079 } else
1080 val = v2;
1081 ext >>= 4;
1082 ext &= 0x0f;
1083 } else {
1084 ext = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_EXTRES1_REG);
1085 v1 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_25VIN);
1086 v2 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VCCP);
1087 v3 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VCC);
1088 v4 = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_5VIN);
1089
1090 switch (reg) {
1091 case DBCOOL_25VIN:
1092 val = v1;
1093 break;
1094 case DBCOOL_VCCP:
1095 val = v2;
1096 ext >>= 2;
1097 break;
1098 case DBCOOL_VCC:
1099 val = v3;
1100 ext >>= 4;
1101 break;
1102 case DBCOOL_5VIN:
1103 val = v4;
1104 ext >>= 6;
1105 break;
1106 default:
1107 val = nom = 0;
1108 }
1109 ext &= 0x03;
1110 }
1111
1112 /*
1113 * Scale the nominal value by the 10-bit fraction
1114 *
1115 * Returned value is in microvolts.
1116 */
1117 ret = val;
1118 ret <<= 2;
1119 ret |= ext;
1120 ret = (ret * nom) / 0x300;
1121
1122 return ret;
1123 }
1124
1125 static int
sysctl_dbcool_temp(SYSCTLFN_ARGS)1126 sysctl_dbcool_temp(SYSCTLFN_ARGS)
1127 {
1128 struct sysctlnode node;
1129 struct dbcool_softc *sc;
1130 int reg, error;
1131 uint8_t chipreg;
1132 uint8_t newreg;
1133
1134 node = *rnode;
1135 sc = (struct dbcool_softc *)node.sysctl_data;
1136 chipreg = node.sysctl_num & 0xff;
1137
1138 if (sc->sc_temp_offset) {
1139 reg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg);
1140 reg -= sc->sc_temp_offset;
1141 } else
1142 reg = (int8_t)sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg);
1143
1144 node.sysctl_data = ®
1145 error = sysctl_lookup(SYSCTLFN_CALL(&node));
1146
1147 if (error || newp == NULL)
1148 return error;
1149
1150 /* We were asked to update the value - sanity check before writing */
1151 if (*(int *)node.sysctl_data < -64 ||
1152 *(int *)node.sysctl_data > 127 + sc->sc_temp_offset)
1153 return EINVAL;
1154
1155 newreg = *(int *)node.sysctl_data;
1156 newreg += sc->sc_temp_offset;
1157 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg);
1158 return 0;
1159 }
1160
1161 static int
sysctl_adm1030_temp(SYSCTLFN_ARGS)1162 sysctl_adm1030_temp(SYSCTLFN_ARGS)
1163 {
1164 struct sysctlnode node;
1165 struct dbcool_softc *sc;
1166 int reg, error;
1167 uint8_t chipreg, oldreg, newreg;
1168
1169 node = *rnode;
1170 sc = (struct dbcool_softc *)node.sysctl_data;
1171 chipreg = node.sysctl_num & 0xff;
1172
1173 oldreg = (int8_t)sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg);
1174 reg = (oldreg >> 1) & ~0x03;
1175
1176 node.sysctl_data = ®
1177 error = sysctl_lookup(SYSCTLFN_CALL(&node));
1178
1179 if (error || newp == NULL)
1180 return error;
1181
1182 /* We were asked to update the value - sanity check before writing */
1183 if (*(int *)node.sysctl_data < 0 || *(int *)node.sysctl_data > 127)
1184 return EINVAL;
1185
1186 newreg = *(int *)node.sysctl_data;
1187 newreg &= ~0x03;
1188 newreg <<= 1;
1189 newreg |= (oldreg & 0x07);
1190 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg);
1191 return 0;
1192 }
1193
1194 static int
sysctl_adm1030_trange(SYSCTLFN_ARGS)1195 sysctl_adm1030_trange(SYSCTLFN_ARGS)
1196 {
1197 struct sysctlnode node;
1198 struct dbcool_softc *sc;
1199 int reg, error, newval;
1200 uint8_t chipreg, oldreg, newreg;
1201
1202 node = *rnode;
1203 sc = (struct dbcool_softc *)node.sysctl_data;
1204 chipreg = node.sysctl_num & 0xff;
1205
1206 oldreg = (int8_t)sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg);
1207 reg = oldreg & 0x07;
1208
1209 node.sysctl_data = ®
1210 error = sysctl_lookup(SYSCTLFN_CALL(&node));
1211
1212 if (error || newp == NULL)
1213 return error;
1214
1215 /* We were asked to update the value - sanity check before writing */
1216 newval = *(int *)node.sysctl_data;
1217
1218 if (newval == 5)
1219 newreg = 0;
1220 else if (newval == 10)
1221 newreg = 1;
1222 else if (newval == 20)
1223 newreg = 2;
1224 else if (newval == 40)
1225 newreg = 3;
1226 else if (newval == 80)
1227 newreg = 4;
1228 else
1229 return EINVAL;
1230
1231 newreg |= (oldreg & ~0x07);
1232 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg);
1233 return 0;
1234 }
1235
1236 static int
sysctl_dbcool_duty(SYSCTLFN_ARGS)1237 sysctl_dbcool_duty(SYSCTLFN_ARGS)
1238 {
1239 struct sysctlnode node;
1240 struct dbcool_softc *sc;
1241 int reg, error;
1242 uint8_t chipreg, oldreg, newreg;
1243
1244 node = *rnode;
1245 sc = (struct dbcool_softc *)node.sysctl_data;
1246 chipreg = node.sysctl_num & 0xff;
1247
1248 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg);
1249 reg = (uint32_t)oldreg;
1250 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030)
1251 reg = ((reg & 0x0f) * 100) / 15;
1252 else
1253 reg = (reg * 100) / 255;
1254 node.sysctl_data = ®
1255 error = sysctl_lookup(SYSCTLFN_CALL(&node));
1256
1257 if (error || newp == NULL)
1258 return error;
1259
1260 /* We were asked to update the value - sanity check before writing */
1261 if (*(int *)node.sysctl_data < 0 || *(int *)node.sysctl_data > 100)
1262 return EINVAL;
1263
1264 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) {
1265 newreg = *(uint8_t *)(node.sysctl_data) * 15 / 100;
1266 newreg |= oldreg & 0xf0;
1267 } else
1268 newreg = *(uint8_t *)(node.sysctl_data) * 255 / 100;
1269 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg);
1270 return 0;
1271 }
1272
1273 static int
sysctl_dbcool_behavior(SYSCTLFN_ARGS)1274 sysctl_dbcool_behavior(SYSCTLFN_ARGS)
1275 {
1276 struct sysctlnode node;
1277 struct dbcool_softc *sc;
1278 int i, reg, error;
1279 uint8_t chipreg, oldreg, newreg;
1280
1281 node = *rnode;
1282 sc = (struct dbcool_softc *)node.sysctl_data;
1283 chipreg = node.sysctl_num & 0xff;
1284
1285 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg);
1286
1287 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) {
1288 if ((sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_CFG2) & 1) == 0)
1289 reg = 4;
1290 else if ((oldreg & 0x80) == 0)
1291 reg = 7;
1292 else if ((oldreg & 0x60) == 0)
1293 reg = 4;
1294 else
1295 reg = 6;
1296 } else
1297 reg = (oldreg >> 5) & 0x07;
1298
1299 strlcpy(dbcool_cur_behav, behavior[reg], sizeof(dbcool_cur_behav));
1300 node.sysctl_data = dbcool_cur_behav;
1301 error = sysctl_lookup(SYSCTLFN_CALL(&node));
1302
1303 if (error || newp == NULL)
1304 return error;
1305
1306 /* We were asked to update the value - convert string to value */
1307 newreg = __arraycount(behavior);
1308 for (i = 0; i < __arraycount(behavior); i++)
1309 if (strcmp(node.sysctl_data, behavior[i]) == 0)
1310 break;
1311 if (i >= __arraycount(behavior))
1312 return EINVAL;
1313
1314 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030) {
1315 /*
1316 * ADM1030 splits fan controller behavior across two
1317 * registers. We also do not support Auto-Filter mode
1318 * nor do we support Manual-RPM-feedback.
1319 */
1320 if (newreg == 4) {
1321 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_CFG2);
1322 oldreg &= ~0x01;
1323 sc->sc_dc.dc_writereg(&sc->sc_dc, DBCOOL_ADM1030_CFG2, oldreg);
1324 } else {
1325 if (newreg == 0)
1326 newreg = 4;
1327 else if (newreg == 6)
1328 newreg = 7;
1329 else if (newreg == 7)
1330 newreg = 0;
1331 else
1332 return EINVAL;
1333 newreg <<= 5;
1334 newreg |= (oldreg & 0x1f);
1335 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg);
1336 oldreg = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADM1030_CFG2) | 1;
1337 sc->sc_dc.dc_writereg(&sc->sc_dc, DBCOOL_ADM1030_CFG2, oldreg);
1338 }
1339 } else {
1340 newreg = (sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg) & 0x1f) | (i << 5);
1341 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg);
1342 }
1343 return 0;
1344 }
1345
1346 static int
sysctl_dbcool_slope(SYSCTLFN_ARGS)1347 sysctl_dbcool_slope(SYSCTLFN_ARGS)
1348 {
1349 struct sysctlnode node;
1350 struct dbcool_softc *sc;
1351 int reg, error;
1352 uint8_t chipreg;
1353 uint8_t newreg;
1354
1355 node = *rnode;
1356 sc = (struct dbcool_softc *)node.sysctl_data;
1357 chipreg = node.sysctl_num & 0xff;
1358
1359 reg = (sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg) >> 4) & 0x0f;
1360 node.sysctl_data = ®
1361 error = sysctl_lookup(SYSCTLFN_CALL(&node));
1362
1363 if (error || newp == NULL)
1364 return error;
1365
1366 /* We were asked to update the value - sanity check before writing */
1367 if (*(int *)node.sysctl_data < 0 || *(int *)node.sysctl_data > 0x0f)
1368 return EINVAL;
1369
1370 newreg = (sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg) & 0x0f) |
1371 (*(int *)node.sysctl_data << 4);
1372 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg);
1373 return 0;
1374 }
1375
1376 static int
sysctl_dbcool_thyst(SYSCTLFN_ARGS)1377 sysctl_dbcool_thyst(SYSCTLFN_ARGS)
1378 {
1379 struct sysctlnode node;
1380 struct dbcool_softc *sc;
1381 int reg, error;
1382 uint8_t chipreg;
1383 uint8_t newreg, newhyst;
1384
1385 node = *rnode;
1386 sc = (struct dbcool_softc *)node.sysctl_data;
1387 chipreg = node.sysctl_num & 0x7f;
1388
1389 /* retrieve 4-bit value */
1390 newreg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg);
1391 if ((node.sysctl_num & 0x80) == 0)
1392 reg = newreg >> 4;
1393 else
1394 reg = newreg;
1395 reg = reg & 0x0f;
1396
1397 node.sysctl_data = ®
1398 error = sysctl_lookup(SYSCTLFN_CALL(&node));
1399
1400 if (error || newp == NULL)
1401 return error;
1402
1403 /* We were asked to update the value - sanity check before writing */
1404 newhyst = *(int *)node.sysctl_data;
1405 if (newhyst > 0x0f)
1406 return EINVAL;
1407
1408 /* Insert new value into field and update register */
1409 if ((node.sysctl_num & 0x80) == 0) {
1410 newreg &= 0x0f;
1411 newreg |= (newhyst << 4);
1412 } else {
1413 newreg &= 0xf0;
1414 newreg |= newhyst;
1415 }
1416 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg);
1417 return 0;
1418 }
1419
1420 #ifdef DBCOOL_DEBUG
1421
1422 /*
1423 * These routines can be used for debugging. reg_select is used to
1424 * select any arbitrary register in the device. reg_access is used
1425 * to read (and optionally update) the selected register.
1426 *
1427 * No attempt is made to validate the data passed. If you use these
1428 * routines, you are assumed to know what you're doing!
1429 *
1430 * Caveat user
1431 */
1432 static int
sysctl_dbcool_reg_select(SYSCTLFN_ARGS)1433 sysctl_dbcool_reg_select(SYSCTLFN_ARGS)
1434 {
1435 struct sysctlnode node;
1436 struct dbcool_softc *sc;
1437 int reg, error;
1438
1439 node = *rnode;
1440 sc = (struct dbcool_softc *)node.sysctl_data;
1441
1442 reg = sc->sc_user_reg;
1443 node.sysctl_data = ®
1444 error = sysctl_lookup(SYSCTLFN_CALL(&node));
1445
1446 if (error || newp == NULL)
1447 return error;
1448
1449 sc->sc_user_reg = *(int *)node.sysctl_data;
1450 return 0;
1451 }
1452
1453 static int
sysctl_dbcool_reg_access(SYSCTLFN_ARGS)1454 sysctl_dbcool_reg_access(SYSCTLFN_ARGS)
1455 {
1456 struct sysctlnode node;
1457 struct dbcool_softc *sc;
1458 int reg, error;
1459 uint8_t chipreg;
1460 uint8_t newreg;
1461
1462 node = *rnode;
1463 sc = (struct dbcool_softc *)node.sysctl_data;
1464 chipreg = sc->sc_user_reg;
1465
1466 reg = sc->sc_dc.dc_readreg(&sc->sc_dc, chipreg);
1467 node.sysctl_data = ®
1468 error = sysctl_lookup(SYSCTLFN_CALL(&node));
1469
1470 if (error || newp == NULL)
1471 return error;
1472
1473 newreg = *(int *)node.sysctl_data;
1474 sc->sc_dc.dc_writereg(&sc->sc_dc, chipreg, newreg);
1475 return 0;
1476 }
1477 #endif /* DBCOOL_DEBUG */
1478
1479 /*
1480 * Encode an index number and register number for use as a sysctl_num
1481 * so we can select the correct device register later.
1482 */
1483 #define DBC_PWM_SYSCTL(seq, reg) ((seq << 8) | reg)
1484
1485 void
dbcool_setup(device_t self)1486 dbcool_setup(device_t self)
1487 {
1488 struct dbcool_softc *sc = device_private(self);
1489 const struct sysctlnode *me = NULL;
1490 #ifdef DBCOOL_DEBUG
1491 struct sysctlnode *node = NULL;
1492 #endif
1493 uint8_t cfg_val, cfg_reg;
1494 int ret, error;
1495
1496 /*
1497 * Some chips are capable of reporting an extended temperature range
1498 * by default. On these models, config register 5 bit 0 can be set
1499 * to 1 for compatability with other chips that report 2s complement.
1500 */
1501 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466) {
1502 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_ADT7466_CONFIG1) & 0x80)
1503 sc->sc_temp_offset = 64;
1504 else
1505 sc->sc_temp_offset = 0;
1506 } else if (sc->sc_dc.dc_chip->flags & DBCFLAG_TEMPOFFSET) {
1507 if (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_CONFIG5_REG) &
1508 DBCOOL_CFG5_TWOSCOMP)
1509 sc->sc_temp_offset = 0;
1510 else
1511 sc->sc_temp_offset = 64;
1512 } else
1513 sc->sc_temp_offset = 0;
1514
1515 /* Determine Vcc for this chip */
1516 sc->sc_supply_voltage = dbcool_supply_voltage(sc);
1517
1518 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL, &me,
1519 CTLFLAG_READWRITE,
1520 CTLTYPE_NODE, device_xname(self), NULL,
1521 NULL, 0, NULL, 0,
1522 CTL_HW, CTL_CREATE, CTL_EOL);
1523 if (ret == 0)
1524 sc->sc_root_sysctl_num = me->sysctl_num;
1525 else
1526 sc->sc_root_sysctl_num = 0;
1527
1528 aprint_debug_dev(self,
1529 "Supply voltage %"PRId64".%06"PRId64"V, %s temp range\n",
1530 sc->sc_supply_voltage / 1000000,
1531 sc->sc_supply_voltage % 1000000,
1532 sc->sc_temp_offset ? "extended" : "normal");
1533
1534 /* Create the sensors for this device */
1535 sc->sc_sme = sysmon_envsys_create();
1536 if (dbcool_setup_sensors(sc))
1537 goto out;
1538
1539 if (sc->sc_root_sysctl_num != 0) {
1540 /* If supported, create sysctl tree for fan PWM controllers */
1541 if (sc->sc_dc.dc_chip->power != NULL)
1542 dbcool_setup_controllers(sc);
1543
1544 #ifdef DBCOOL_DEBUG
1545 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL,
1546 (void *)&node,
1547 CTLFLAG_READWRITE, CTLTYPE_INT, "reg_select", NULL,
1548 sysctl_dbcool_reg_select,
1549 0, (void *)sc, sizeof(int),
1550 CTL_HW, me->sysctl_num, CTL_CREATE, CTL_EOL);
1551 if (node != NULL)
1552 node->sysctl_data = sc;
1553
1554 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL,
1555 (void *)&node,
1556 CTLFLAG_READWRITE, CTLTYPE_INT, "reg_access", NULL,
1557 sysctl_dbcool_reg_access,
1558 0, (void *)sc, sizeof(int),
1559 CTL_HW, me->sysctl_num, CTL_CREATE, CTL_EOL);
1560 if (node != NULL)
1561 node->sysctl_data = sc;
1562 #endif /* DBCOOL_DEBUG */
1563 }
1564
1565 /*
1566 * Read and rewrite config register to activate device
1567 */
1568 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030)
1569 cfg_reg = DBCOOL_ADM1030_CFG1;
1570 else if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADT7466)
1571 cfg_reg = DBCOOL_ADT7466_CONFIG1;
1572 else
1573 cfg_reg = DBCOOL_CONFIG1_REG;
1574 cfg_val = sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_CONFIG1_REG);
1575 if ((cfg_val & DBCOOL_CFG1_START) == 0) {
1576 cfg_val |= DBCOOL_CFG1_START;
1577 sc->sc_dc.dc_writereg(&sc->sc_dc, cfg_reg, cfg_val);
1578 }
1579 if (dbcool_islocked(sc))
1580 aprint_normal_dev(self, "configuration locked\n");
1581
1582 sc->sc_sme->sme_name = device_xname(self);
1583 sc->sc_sme->sme_cookie = sc;
1584 sc->sc_sme->sme_refresh = dbcool_refresh;
1585 sc->sc_sme->sme_set_limits = dbcool_set_limits;
1586 sc->sc_sme->sme_get_limits = dbcool_get_limits;
1587
1588 if ((error = sysmon_envsys_register(sc->sc_sme)) != 0) {
1589 aprint_error_dev(self,
1590 "unable to register with sysmon (%d)\n", error);
1591 goto out;
1592 }
1593
1594 return;
1595
1596 out:
1597 sysmon_envsys_destroy(sc->sc_sme);
1598 }
1599
1600 static int
dbcool_setup_sensors(struct dbcool_softc * sc)1601 dbcool_setup_sensors(struct dbcool_softc *sc)
1602 {
1603 int i;
1604 int error = 0;
1605 uint8_t vid_reg, vid_val;
1606 struct chip_id *chip = sc->sc_dc.dc_chip;
1607
1608 for (i=0; chip->table[i].type != DBC_EOF; i++) {
1609 if (i < DBCOOL_MAXSENSORS)
1610 sc->sc_sysctl_num[i] = -1;
1611 else if (chip->table[i].type != DBC_CTL) {
1612 aprint_normal_dev(sc->sc_dev, "chip table too big!\n");
1613 break;
1614 }
1615 switch (chip->table[i].type) {
1616 case DBC_TEMP:
1617 sc->sc_sensor[i].units = ENVSYS_STEMP;
1618 sc->sc_sensor[i].state = ENVSYS_SINVALID;
1619 sc->sc_sensor[i].flags |= ENVSYS_FMONLIMITS;
1620 sc->sc_sensor[i].flags |= ENVSYS_FHAS_ENTROPY;
1621 error = dbcool_attach_sensor(sc, i);
1622 break;
1623 case DBC_VOLT:
1624 /*
1625 * If 12V-In pin has been reconfigured as 6th bit
1626 * of VID code, don't create a 12V-In sensor
1627 */
1628 if ((chip->flags & DBCFLAG_HAS_VID_SEL) &&
1629 (chip->table[i].reg.val_reg == DBCOOL_12VIN) &&
1630 (sc->sc_dc.dc_readreg(&sc->sc_dc, DBCOOL_VID_REG) &
1631 0x80))
1632 break;
1633
1634 sc->sc_sensor[i].units = ENVSYS_SVOLTS_DC;
1635 sc->sc_sensor[i].state = ENVSYS_SINVALID;
1636 sc->sc_sensor[i].flags |= ENVSYS_FMONLIMITS;
1637 sc->sc_sensor[i].flags |= ENVSYS_FHAS_ENTROPY;
1638 error = dbcool_attach_sensor(sc, i);
1639 break;
1640 case DBC_FAN:
1641 sc->sc_sensor[i].units = ENVSYS_SFANRPM;
1642 sc->sc_sensor[i].state = ENVSYS_SINVALID;
1643 sc->sc_sensor[i].flags |= ENVSYS_FMONLIMITS;
1644 sc->sc_sensor[i].flags |= ENVSYS_FHAS_ENTROPY;
1645 error = dbcool_attach_sensor(sc, i);
1646 break;
1647 case DBC_VID:
1648 sc->sc_sensor[i].units = ENVSYS_INTEGER;
1649 sc->sc_sensor[i].state = ENVSYS_SINVALID;
1650 sc->sc_sensor[i].flags |= ENVSYS_FMONNOTSUPP;
1651
1652 /* retrieve 5- or 6-bit value */
1653 vid_reg = chip->table[i].reg.val_reg;
1654 vid_val = sc->sc_dc.dc_readreg(&sc->sc_dc, vid_reg);
1655 if (chip->flags & DBCFLAG_HAS_VID_SEL)
1656 vid_val &= 0x3f;
1657 else
1658 vid_val &= 0x1f;
1659 sc->sc_sensor[i].value_cur = vid_val;
1660
1661 error = dbcool_attach_sensor(sc, i);
1662 break;
1663 case DBC_CTL:
1664 error = dbcool_attach_temp_control(sc, i, chip);
1665 if (error) {
1666 aprint_error_dev(sc->sc_dev,
1667 "attach index %d failed %d\n",
1668 i, error);
1669 error = 0;
1670 }
1671 break;
1672 default:
1673 aprint_error_dev(sc->sc_dev,
1674 "sensor_table index %d has bad type %d\n",
1675 i, chip->table[i].type);
1676 break;
1677 }
1678 if (error)
1679 break;
1680 }
1681 return error;
1682 }
1683
1684 static int
dbcool_attach_sensor(struct dbcool_softc * sc,int idx)1685 dbcool_attach_sensor(struct dbcool_softc *sc, int idx)
1686 {
1687 int name_index;
1688 int error = 0;
1689
1690 name_index = sc->sc_dc.dc_chip->table[idx].name_index;
1691 strlcpy(sc->sc_sensor[idx].desc, dbc_sensor_names[name_index],
1692 sizeof(sc->sc_sensor[idx].desc));
1693 sc->sc_regs[idx] = &sc->sc_dc.dc_chip->table[idx].reg;
1694 sc->sc_nom_volt[idx] = sc->sc_dc.dc_chip->table[idx].nom_volt_index;
1695
1696 error = sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor[idx]);
1697 return error;
1698 }
1699
1700 static int
dbcool_attach_temp_control(struct dbcool_softc * sc,int idx,struct chip_id * chip)1701 dbcool_attach_temp_control(struct dbcool_softc *sc, int idx,
1702 struct chip_id *chip)
1703 {
1704 const struct sysctlnode *me2 = NULL, *node;
1705 int j, ret, sysctl_index, rw_flag;
1706 uint8_t sysctl_reg;
1707 char name[SYSCTL_NAMELEN];
1708
1709 /* Search for the corresponding temp sensor */
1710 for (j = 0; j < idx; j++) {
1711 if (j >= DBCOOL_MAXSENSORS || chip->table[j].type != DBC_TEMP)
1712 continue;
1713 if (chip->table[j].name_index == chip->table[idx].name_index)
1714 break;
1715 }
1716 if (j >= idx) /* Temp sensor not found */
1717 return ENOENT;
1718
1719 /* create sysctl node for the sensor if not one already there */
1720 if (sc->sc_sysctl_num[j] == -1) {
1721 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL, &me2,
1722 CTLFLAG_READWRITE,
1723 CTLTYPE_NODE, sc->sc_sensor[j].desc, NULL,
1724 NULL, 0, NULL, 0,
1725 CTL_HW, sc->sc_root_sysctl_num, CTL_CREATE,
1726 CTL_EOL);
1727 if (me2 != NULL)
1728 sc->sc_sysctl_num[j] = me2->sysctl_num;
1729 else
1730 return ret;
1731 }
1732 /* add sysctl leaf node for this control variable */
1733 sysctl_index = chip->table[idx].sysctl_index;
1734 sysctl_reg = chip->table[idx].reg.val_reg;
1735 strlcpy(name, dbc_sysctl_table[sysctl_index].name, sizeof(name));
1736 if (dbc_sysctl_table[sysctl_index].lockable && dbcool_islocked(sc))
1737 rw_flag = CTLFLAG_READONLY | CTLFLAG_OWNDESC;
1738 else
1739 rw_flag = CTLFLAG_READWRITE | CTLFLAG_OWNDESC;
1740 ret = sysctl_createv(&sc->sc_sysctl_log, 0, NULL, &node, rw_flag,
1741 CTLTYPE_INT, name,
1742 SYSCTL_DESCR(dbc_sysctl_table[sysctl_index].desc),
1743 dbc_sysctl_table[sysctl_index].helper,
1744 0, (void *)sc, sizeof(int),
1745 CTL_HW, sc->sc_root_sysctl_num,
1746 sc->sc_sysctl_num[j],
1747 DBC_PWM_SYSCTL(idx, sysctl_reg), CTL_EOL);
1748
1749 return ret;
1750 }
1751
1752 static void
dbcool_setup_controllers(struct dbcool_softc * sc)1753 dbcool_setup_controllers(struct dbcool_softc *sc)
1754 {
1755 int i, j, rw_flag;
1756 uint8_t sysctl_reg;
1757 struct chip_id *chip = sc->sc_dc.dc_chip;
1758 const struct sysctlnode *me2 = NULL;
1759 const struct sysctlnode *node = NULL;
1760 char name[SYSCTL_NAMELEN];
1761
1762 for (i = 0; chip->power[i].desc != NULL; i++) {
1763 snprintf(name, sizeof(name), "fan_ctl_%d", i);
1764 sysctl_createv(&sc->sc_sysctl_log, 0, NULL, &me2,
1765 CTLFLAG_READWRITE | CTLFLAG_OWNDESC,
1766 CTLTYPE_NODE, name, NULL,
1767 NULL, 0, NULL, 0,
1768 CTL_HW, sc->sc_root_sysctl_num, CTL_CREATE, CTL_EOL);
1769
1770 for (j = DBC_PWM_BEHAVIOR; j < DBC_PWM_LAST_PARAM; j++) {
1771 if (j == DBC_PWM_MAX_DUTY &&
1772 (chip->flags & DBCFLAG_HAS_MAXDUTY) == 0)
1773 continue;
1774 sysctl_reg = chip->power[i].power_regs[j];
1775 if (sysctl_reg == DBCOOL_NO_REG)
1776 continue;
1777 strlcpy(name, dbc_sysctl_table[j].name, sizeof(name));
1778 if (dbc_sysctl_table[j].lockable && dbcool_islocked(sc))
1779 rw_flag = CTLFLAG_READONLY | CTLFLAG_OWNDESC;
1780 else
1781 rw_flag = CTLFLAG_READWRITE | CTLFLAG_OWNDESC;
1782 (sysctl_createv)(&sc->sc_sysctl_log, 0, NULL,
1783 &node, rw_flag,
1784 (j == DBC_PWM_BEHAVIOR)?
1785 CTLTYPE_STRING:CTLTYPE_INT,
1786 name,
1787 SYSCTL_DESCR(dbc_sysctl_table[j].desc),
1788 dbc_sysctl_table[j].helper,
1789 0, sc,
1790 ( j == DBC_PWM_BEHAVIOR)?
1791 sizeof(dbcool_cur_behav): sizeof(int),
1792 CTL_HW, sc->sc_root_sysctl_num, me2->sysctl_num,
1793 DBC_PWM_SYSCTL(j, sysctl_reg), CTL_EOL);
1794 }
1795 }
1796 }
1797
1798 static void
dbcool_refresh(struct sysmon_envsys * sme,envsys_data_t * edata)1799 dbcool_refresh(struct sysmon_envsys *sme, envsys_data_t *edata)
1800 {
1801 struct dbcool_softc *sc=sme->sme_cookie;
1802 int i, nom_volt_idx, cur;
1803 struct reg_list *reg;
1804
1805 i = edata->sensor;
1806 reg = sc->sc_regs[i];
1807
1808 edata->state = ENVSYS_SVALID;
1809 switch (edata->units)
1810 {
1811 case ENVSYS_STEMP:
1812 cur = dbcool_read_temp(sc, reg->val_reg, true);
1813 break;
1814 case ENVSYS_SVOLTS_DC:
1815 nom_volt_idx = sc->sc_nom_volt[i];
1816 cur = dbcool_read_volt(sc, reg->val_reg, nom_volt_idx,
1817 true);
1818 break;
1819 case ENVSYS_SFANRPM:
1820 cur = dbcool_read_rpm(sc, reg->val_reg);
1821 break;
1822 case ENVSYS_INTEGER:
1823 return;
1824 default:
1825 edata->state = ENVSYS_SINVALID;
1826 return;
1827 }
1828
1829 if (cur == 0 && (edata->units != ENVSYS_SFANRPM))
1830 edata->state = ENVSYS_SINVALID;
1831
1832 /*
1833 * If fan is "stalled" but has no low limit, treat
1834 * it as though the fan is not installed.
1835 */
1836 else if (edata->units == ENVSYS_SFANRPM && cur == 0 &&
1837 !(edata->upropset & (PROP_CRITMIN | PROP_WARNMIN)))
1838 edata->state = ENVSYS_SINVALID;
1839
1840 edata->value_cur = cur;
1841 }
1842
1843 int
dbcool_chip_ident(struct dbcool_chipset * dc)1844 dbcool_chip_ident(struct dbcool_chipset *dc)
1845 {
1846 /* verify this is a supported dbCool chip */
1847 uint8_t c_id, d_id, r_id;
1848 int i;
1849
1850 c_id = dc->dc_readreg(dc, DBCOOL_COMPANYID_REG);
1851 d_id = dc->dc_readreg(dc, DBCOOL_DEVICEID_REG);
1852 r_id = dc->dc_readreg(dc, DBCOOL_REVISION_REG);
1853
1854 /* The EMC6D103S only supports read_byte and since dc->dc_chip is
1855 * NULL when we call dc->dc_readreg above we use
1856 * send_byte/receive_byte which doesn't work.
1857 *
1858 * So if we only get 0's back then try again with dc->dc_chip
1859 * set to the EMC6D103S_DEVICEID and which doesn't have
1860 * DBCFLAG_NO_READBYTE set so read_byte will be used
1861 */
1862 if ((c_id == 0) && (d_id == 0) && (r_id == 0)) {
1863 for (i = 0; chip_table[i].company != 0; i++)
1864 if ((SMSC_COMPANYID == chip_table[i].company) &&
1865 (EMC6D103S_DEVICEID == chip_table[i].device)) {
1866 dc->dc_chip = &chip_table[i];
1867 break;
1868 }
1869 c_id = dc->dc_readreg(dc, DBCOOL_COMPANYID_REG);
1870 d_id = dc->dc_readreg(dc, DBCOOL_DEVICEID_REG);
1871 r_id = dc->dc_readreg(dc, DBCOOL_REVISION_REG);
1872 }
1873
1874 for (i = 0; chip_table[i].company != 0; i++)
1875 if ((c_id == chip_table[i].company) &&
1876 (d_id == chip_table[i].device ||
1877 chip_table[i].device == 0xff) &&
1878 (r_id == chip_table[i].rev ||
1879 chip_table[i].rev == 0xff)) {
1880 dc->dc_chip = &chip_table[i];
1881 return i;
1882 }
1883
1884 aprint_verbose("dbcool_chip_ident: addr 0x%02x c_id 0x%02x d_id 0x%02x"
1885 " r_id 0x%02x: No match.\n", dc->dc_addr, c_id, d_id,
1886 r_id);
1887
1888 return -1;
1889 }
1890
1891 /*
1892 * Retrieve sensor limits from the chip registers
1893 */
1894 static void
dbcool_get_limits(struct sysmon_envsys * sme,envsys_data_t * edata,sysmon_envsys_lim_t * limits,uint32_t * props)1895 dbcool_get_limits(struct sysmon_envsys *sme, envsys_data_t *edata,
1896 sysmon_envsys_lim_t *limits, uint32_t *props)
1897 {
1898 int index = edata->sensor;
1899 struct dbcool_softc *sc = sme->sme_cookie;
1900
1901 *props &= ~(PROP_CRITMIN | PROP_CRITMAX);
1902 switch (edata->units) {
1903 case ENVSYS_STEMP:
1904 dbcool_get_temp_limits(sc, index, limits, props);
1905 break;
1906 case ENVSYS_SVOLTS_DC:
1907 dbcool_get_volt_limits(sc, index, limits, props);
1908 break;
1909 case ENVSYS_SFANRPM:
1910 dbcool_get_fan_limits(sc, index, limits, props);
1911
1912 /* FALLTHROUGH */
1913 default:
1914 break;
1915 }
1916 *props &= ~PROP_DRIVER_LIMITS;
1917
1918 /* If both limits provided, make sure they're sane */
1919 if ((*props & PROP_CRITMIN) &&
1920 (*props & PROP_CRITMAX) &&
1921 (limits->sel_critmin >= limits->sel_critmax))
1922 *props &= ~(PROP_CRITMIN | PROP_CRITMAX);
1923
1924 /*
1925 * If this is the first time through, save these values
1926 * in case user overrides them and then requests a reset.
1927 */
1928 if (sc->sc_defprops[index] == 0) {
1929 sc->sc_defprops[index] = *props | PROP_DRIVER_LIMITS;
1930 sc->sc_deflims[index] = *limits;
1931 }
1932 }
1933
1934 static void
dbcool_get_temp_limits(struct dbcool_softc * sc,int idx,sysmon_envsys_lim_t * lims,uint32_t * props)1935 dbcool_get_temp_limits(struct dbcool_softc *sc, int idx,
1936 sysmon_envsys_lim_t *lims, uint32_t *props)
1937 {
1938 struct reg_list *reg = sc->sc_regs[idx];
1939 uint8_t lo_lim, hi_lim;
1940
1941 lo_lim = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->lo_lim_reg);
1942 hi_lim = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->hi_lim_reg);
1943
1944 if (sc->sc_temp_offset) {
1945 if (lo_lim > 0x01) {
1946 lims->sel_critmin = lo_lim - sc->sc_temp_offset;
1947 *props |= PROP_CRITMIN;
1948 }
1949 if (hi_lim != 0xff) {
1950 lims->sel_critmax = hi_lim - sc->sc_temp_offset;
1951 *props |= PROP_CRITMAX;
1952 }
1953 } else {
1954 if (lo_lim != 0x80 && lo_lim != 0x81) {
1955 lims->sel_critmin = (int8_t)lo_lim;
1956 *props |= PROP_CRITMIN;
1957 }
1958
1959 if (hi_lim != 0x7f) {
1960 lims->sel_critmax = (int8_t)hi_lim;
1961 *props |= PROP_CRITMAX;
1962 }
1963 }
1964
1965 /* Convert temp limits to microKelvin */
1966 lims->sel_critmin *= 1000000;
1967 lims->sel_critmin += 273150000;
1968 lims->sel_critmax *= 1000000;
1969 lims->sel_critmax += 273150000;
1970 }
1971
1972 static void
dbcool_get_volt_limits(struct dbcool_softc * sc,int idx,sysmon_envsys_lim_t * lims,uint32_t * props)1973 dbcool_get_volt_limits(struct dbcool_softc *sc, int idx,
1974 sysmon_envsys_lim_t *lims, uint32_t *props)
1975 {
1976 struct reg_list *reg = sc->sc_regs[idx];
1977 int64_t limit;
1978 int nom;
1979
1980 nom = nominal_voltages[sc->sc_dc.dc_chip->table[idx].nom_volt_index];
1981 if (nom < 0)
1982 nom = dbcool_supply_voltage(sc);
1983 nom *= 1000000; /* scale for microvolts */
1984
1985 limit = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->lo_lim_reg);
1986 if (limit != 0x00 && limit != 0xff) {
1987 limit *= nom;
1988 limit /= 0xc0;
1989 lims->sel_critmin = limit;
1990 *props |= PROP_CRITMIN;
1991 }
1992 limit = sc->sc_dc.dc_readreg(&sc->sc_dc, reg->hi_lim_reg);
1993 if (limit != 0x00 && limit != 0xff) {
1994 limit *= nom;
1995 limit /= 0xc0;
1996 lims->sel_critmax = limit;
1997 *props |= PROP_CRITMAX;
1998 }
1999 }
2000
2001 static void
dbcool_get_fan_limits(struct dbcool_softc * sc,int idx,sysmon_envsys_lim_t * lims,uint32_t * props)2002 dbcool_get_fan_limits(struct dbcool_softc *sc, int idx,
2003 sysmon_envsys_lim_t *lims, uint32_t *props)
2004 {
2005 struct reg_list *reg = sc->sc_regs[idx];
2006 int32_t limit;
2007
2008 limit = dbcool_read_rpm(sc, reg->lo_lim_reg);
2009 if (limit) {
2010 lims->sel_critmin = limit;
2011 *props |= PROP_CRITMIN;
2012 }
2013 }
2014
2015 /*
2016 * Update sensor limits in the chip registers
2017 */
2018 static void
dbcool_set_limits(struct sysmon_envsys * sme,envsys_data_t * edata,sysmon_envsys_lim_t * limits,uint32_t * props)2019 dbcool_set_limits(struct sysmon_envsys *sme, envsys_data_t *edata,
2020 sysmon_envsys_lim_t *limits, uint32_t *props)
2021 {
2022 int index = edata->sensor;
2023 struct dbcool_softc *sc = sme->sme_cookie;
2024
2025 if (limits == NULL) {
2026 limits = &sc->sc_deflims[index];
2027 props = &sc->sc_defprops[index];
2028 }
2029 switch (edata->units) {
2030 case ENVSYS_STEMP:
2031 dbcool_set_temp_limits(sc, index, limits, props);
2032 break;
2033 case ENVSYS_SVOLTS_DC:
2034 dbcool_set_volt_limits(sc, index, limits, props);
2035 break;
2036 case ENVSYS_SFANRPM:
2037 dbcool_set_fan_limits(sc, index, limits, props);
2038
2039 /* FALLTHROUGH */
2040 default:
2041 break;
2042 }
2043 *props &= ~PROP_DRIVER_LIMITS;
2044 }
2045
2046 static void
dbcool_set_temp_limits(struct dbcool_softc * sc,int idx,sysmon_envsys_lim_t * lims,uint32_t * props)2047 dbcool_set_temp_limits(struct dbcool_softc *sc, int idx,
2048 sysmon_envsys_lim_t *lims, uint32_t *props)
2049 {
2050 struct reg_list *reg = sc->sc_regs[idx];
2051 int32_t limit;
2052
2053 if (*props & PROP_CRITMIN) {
2054 limit = lims->sel_critmin - 273150000;
2055 limit /= 1000000;
2056 if (sc->sc_temp_offset) {
2057 limit += sc->sc_temp_offset;
2058 if (limit < 0)
2059 limit = 0;
2060 else if (limit > 255)
2061 limit = 255;
2062 } else {
2063 if (limit < -127)
2064 limit = -127;
2065 else if (limit > 127)
2066 limit = 127;
2067 }
2068 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg,
2069 (uint8_t)limit);
2070 } else if (*props & PROP_DRIVER_LIMITS) {
2071 if (sc->sc_temp_offset)
2072 limit = 0x00;
2073 else
2074 limit = 0x80;
2075 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg,
2076 (uint8_t)limit);
2077 }
2078
2079 if (*props & PROP_CRITMAX) {
2080 limit = lims->sel_critmax - 273150000;
2081 limit /= 1000000;
2082 if (sc->sc_temp_offset) {
2083 limit += sc->sc_temp_offset;
2084 if (limit < 0)
2085 limit = 0;
2086 else if (limit > 255)
2087 limit = 255;
2088 } else {
2089 if (limit < -127)
2090 limit = -127;
2091 else if (limit > 127)
2092 limit = 127;
2093 }
2094 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg,
2095 (uint8_t)limit);
2096 } else if (*props & PROP_DRIVER_LIMITS) {
2097 if (sc->sc_temp_offset)
2098 limit = 0xff;
2099 else
2100 limit = 0x7f;
2101 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg,
2102 (uint8_t)limit);
2103 }
2104 }
2105
2106 static void
dbcool_set_volt_limits(struct dbcool_softc * sc,int idx,sysmon_envsys_lim_t * lims,uint32_t * props)2107 dbcool_set_volt_limits(struct dbcool_softc *sc, int idx,
2108 sysmon_envsys_lim_t *lims, uint32_t *props)
2109 {
2110 struct reg_list *reg = sc->sc_regs[idx];
2111 int64_t limit;
2112 int nom;
2113
2114 nom = nominal_voltages[sc->sc_dc.dc_chip->table[idx].nom_volt_index];
2115 if (nom < 0)
2116 nom = dbcool_supply_voltage(sc);
2117 nom *= 1000000; /* scale for microvolts */
2118
2119 if (*props & PROP_CRITMIN) {
2120 limit = lims->sel_critmin;
2121 limit *= 0xc0;
2122 limit /= nom;
2123 if (limit > 0xff)
2124 limit = 0xff;
2125 else if (limit < 0)
2126 limit = 0;
2127 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, limit);
2128 } else if (*props & PROP_DRIVER_LIMITS)
2129 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 0);
2130
2131 if (*props & PROP_CRITMAX) {
2132 limit = lims->sel_critmax;
2133 limit *= 0xc0;
2134 limit /= nom;
2135 if (limit > 0xff)
2136 limit = 0xff;
2137 else if (limit < 0)
2138 limit = 0;
2139 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, limit);
2140 } else if (*props & PROP_DRIVER_LIMITS)
2141 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->hi_lim_reg, 0xff);
2142 }
2143
2144 static void
dbcool_set_fan_limits(struct dbcool_softc * sc,int idx,sysmon_envsys_lim_t * lims,uint32_t * props)2145 dbcool_set_fan_limits(struct dbcool_softc *sc, int idx,
2146 sysmon_envsys_lim_t *lims, uint32_t *props)
2147 {
2148 struct reg_list *reg = sc->sc_regs[idx];
2149 int32_t limit, dividend;
2150
2151 if (*props & PROP_CRITMIN) {
2152 limit = lims->sel_critmin;
2153 if (limit == 0)
2154 limit = 0xffff;
2155 else {
2156 if (sc->sc_dc.dc_chip->flags & DBCFLAG_ADM1030)
2157 dividend = 11250 * 60;
2158 else
2159 dividend = 90000 * 60;
2160 limit = limit / dividend;
2161 if (limit > 0xffff)
2162 limit = 0xffff;
2163 }
2164 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg,
2165 limit & 0xff);
2166 limit >>= 8;
2167 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg + 1,
2168 limit & 0xff);
2169 } else if (*props & PROP_DRIVER_LIMITS) {
2170 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg, 0xff);
2171 sc->sc_dc.dc_writereg(&sc->sc_dc, reg->lo_lim_reg + 1, 0xff);
2172 }
2173 }
2174
2175 MODULE(MODULE_CLASS_DRIVER, dbcool, "i2cexec,sysmon_envsys");
2176
2177 #ifdef _MODULE
2178 #include "ioconf.c"
2179 #endif
2180
2181 static int
dbcool_modcmd(modcmd_t cmd,void * opaque)2182 dbcool_modcmd(modcmd_t cmd, void *opaque)
2183 {
2184 int error = 0;
2185 #ifdef _MODULE
2186 static struct sysctllog *dbcool_sysctl_clog;
2187 #endif
2188
2189 switch (cmd) {
2190 case MODULE_CMD_INIT:
2191 #ifdef _MODULE
2192 error = config_init_component(cfdriver_ioconf_dbcool,
2193 cfattach_ioconf_dbcool, cfdata_ioconf_dbcool);
2194 sysctl_dbcoolsetup(&dbcool_sysctl_clog);
2195 #endif
2196 return error;
2197 case MODULE_CMD_FINI:
2198 #ifdef _MODULE
2199 error = config_fini_component(cfdriver_ioconf_dbcool,
2200 cfattach_ioconf_dbcool, cfdata_ioconf_dbcool);
2201 sysctl_teardown(&dbcool_sysctl_clog);
2202 #endif
2203 return error;
2204 default:
2205 return ENOTTY;
2206 }
2207 }
2208