1 /**************************************************************************
2
3 Copyright (c) 2007, Chelsio Inc.
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Neither the name of the Chelsio Corporation nor the names of its
13 contributors may be used to endorse or promote products derived from
14 this software without specific prior written permission.
15
16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 POSSIBILITY OF SUCH DAMAGE.
27
28 ***************************************************************************/
29
30 #include <sys/cdefs.h>
31 __KERNEL_RCSID(0, "$NetBSD: cxgb_main.c,v 1.4 2013/01/23 23:31:26 joerg Exp $");
32
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/conf.h>
37 #include <sys/bus.h>
38 #include <sys/ioccom.h>
39 #include <sys/mbuf.h>
40 #include <sys/socket.h>
41 #include <sys/sockio.h>
42 #include <sys/sysctl.h>
43 #include <sys/queue.h>
44
45 #include <net/bpf.h>
46 #include <net/if.h>
47 #include <net/if_arp.h>
48 #include <net/if_dl.h>
49 #include <net/if_media.h>
50 #include <net/if_types.h>
51
52 #include <netinet/in_systm.h>
53 #include <netinet/in.h>
54 #include <netinet/ip.h>
55 #include <netinet/ip.h>
56 #include <netinet/tcp.h>
57 #include <netinet/udp.h>
58 #include <netinet/if_inarp.h>
59
60 #include <dev/pci/pcireg.h>
61 #include <dev/pci/pcivar.h>
62
63 #ifdef CONFIG_DEFINED
64 #include <cxgb_include.h>
65 #else
66 #include <dev/pci/cxgb/cxgb_include.h>
67 #endif
68
69 #ifdef PRIV_SUPPORTED
70 #include <sys/priv.h>
71 #endif
72
73 #include <altq/altq_conf.h>
74
75 static int cxgb_setup_msix(adapter_t *, int);
76 static void cxgb_teardown_msix(adapter_t *);
77 static int cxgb_init(struct ifnet *);
78 static void cxgb_init_locked(struct port_info *);
79 static void cxgb_stop_locked(struct port_info *);
80 static void cxgb_set_rxmode(struct port_info *);
81 static int cxgb_ioctl(struct ifnet *, unsigned long, void *);
82 static void cxgb_start(struct ifnet *);
83 static void cxgb_stop(struct ifnet *, int);
84 static void cxgb_start_proc(struct work *, void *);
85 static int cxgb_media_change(struct ifnet *);
86 static void cxgb_media_status(struct ifnet *, struct ifmediareq *);
87 static int setup_sge_qsets(adapter_t *);
88 static int cxgb_async_intr(void *);
89 static void cxgb_ext_intr_handler(struct work *, void *);
90 static void cxgb_tick_handler(struct work *, void *);
91 static void cxgb_down_locked(struct adapter *sc);
92 static void cxgb_tick(void *);
93 static void setup_rss(adapter_t *sc);
94
95 /* Attachment glue for the PCI controller end of the device. Each port of
96 * the device is attached separately, as defined later.
97 */
98 static int cxgb_controller_match(device_t dev, cfdata_t match, void *context);
99 static void cxgb_controller_attach(device_t parent, device_t dev, void *context);
100 static int cxgb_controller_detach(device_t dev, int flags);
101 static void cxgb_free(struct adapter *);
102 static __inline void reg_block_dump(struct adapter *ap, uint8_t *buf, unsigned int start,
103 unsigned int end);
104 static void touch_bars(device_t dev);
105
106 #ifdef notyet
107 static int offload_close(struct toedev *tdev);
108 #endif
109
110
111 CFATTACH_DECL_NEW(cxgbc, sizeof(struct adapter), cxgb_controller_match, cxgb_controller_attach, cxgb_controller_detach, NULL);
112
113 /*
114 * Attachment glue for the ports. Attachment is done directly to the
115 * controller device.
116 */
117 static int cxgb_port_match(device_t dev, cfdata_t match, void *context);
118 static void cxgb_port_attach(device_t dev, device_t self, void *context);
119 static int cxgb_port_detach(device_t dev, int flags);
120
121 CFATTACH_DECL_NEW(cxgb, sizeof(struct port_device), cxgb_port_match, cxgb_port_attach, cxgb_port_detach, NULL);
122
123 #define SGE_MSIX_COUNT (SGE_QSETS + 1)
124
125 extern int collapse_mbufs;
126 #ifdef MSI_SUPPORTED
127 /*
128 * The driver uses the best interrupt scheme available on a platform in the
129 * order MSI-X, MSI, legacy pin interrupts. This parameter determines which
130 * of these schemes the driver may consider as follows:
131 *
132 * msi = 2: choose from among all three options
133 * msi = 1 : only consider MSI and pin interrupts
134 * msi = 0: force pin interrupts
135 */
136 static int msi_allowed = 2;
137 #endif
138
139 /*
140 * The driver uses an auto-queue algorithm by default.
141 * To disable it and force a single queue-set per port, use singleq = 1.
142 */
143 static int singleq = 1;
144
145 enum {
146 MAX_TXQ_ENTRIES = 16384,
147 MAX_CTRL_TXQ_ENTRIES = 1024,
148 MAX_RSPQ_ENTRIES = 16384,
149 MAX_RX_BUFFERS = 16384,
150 MAX_RX_JUMBO_BUFFERS = 16384,
151 MIN_TXQ_ENTRIES = 4,
152 MIN_CTRL_TXQ_ENTRIES = 4,
153 MIN_RSPQ_ENTRIES = 32,
154 MIN_FL_ENTRIES = 32,
155 MIN_FL_JUMBO_ENTRIES = 32
156 };
157
158 struct filter_info {
159 u32 sip;
160 u32 sip_mask;
161 u32 dip;
162 u16 sport;
163 u16 dport;
164 u32 vlan:12;
165 u32 vlan_prio:3;
166 u32 mac_hit:1;
167 u32 mac_idx:4;
168 u32 mac_vld:1;
169 u32 pkt_type:2;
170 u32 report_filter_id:1;
171 u32 pass:1;
172 u32 rss:1;
173 u32 qset:3;
174 u32 locked:1;
175 u32 valid:1;
176 };
177
178 enum { FILTER_NO_VLAN_PRI = 7 };
179
180 #define PORT_MASK ((1 << MAX_NPORTS) - 1)
181
182 /* Table for probing the cards. The desc field isn't actually used */
183 struct cxgb_ident {
184 uint16_t vendor;
185 uint16_t device;
186 int index;
187 const char *desc;
188 } cxgb_identifiers[] = {
189 {PCI_VENDOR_ID_CHELSIO, 0x0020, 0, "PE9000"},
190 {PCI_VENDOR_ID_CHELSIO, 0x0021, 1, "T302E"},
191 {PCI_VENDOR_ID_CHELSIO, 0x0022, 2, "T310E"},
192 {PCI_VENDOR_ID_CHELSIO, 0x0023, 3, "T320X"},
193 {PCI_VENDOR_ID_CHELSIO, 0x0024, 1, "T302X"},
194 {PCI_VENDOR_ID_CHELSIO, 0x0025, 3, "T320E"},
195 {PCI_VENDOR_ID_CHELSIO, 0x0026, 2, "T310X"},
196 {PCI_VENDOR_ID_CHELSIO, 0x0030, 2, "T3B10"},
197 {PCI_VENDOR_ID_CHELSIO, 0x0031, 3, "T3B20"},
198 {PCI_VENDOR_ID_CHELSIO, 0x0032, 1, "T3B02"},
199 {PCI_VENDOR_ID_CHELSIO, 0x0033, 4, "T3B04"},
200 {0, 0, 0, NULL}
201 };
202
203
204 static inline char
t3rev2char(struct adapter * adapter)205 t3rev2char(struct adapter *adapter)
206 {
207 char rev = 'z';
208
209 switch(adapter->params.rev) {
210 case T3_REV_A:
211 rev = 'a';
212 break;
213 case T3_REV_B:
214 case T3_REV_B2:
215 rev = 'b';
216 break;
217 case T3_REV_C:
218 rev = 'c';
219 break;
220 }
221 return rev;
222 }
223
cxgb_get_ident(struct pci_attach_args * pa)224 static struct cxgb_ident *cxgb_get_ident(struct pci_attach_args *pa)
225 {
226 struct cxgb_ident *id;
227 int vendorid, deviceid;
228
229 vendorid = PCI_VENDOR(pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ID_REG));
230 deviceid = PCI_PRODUCT(pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ID_REG));
231
232 for (id = cxgb_identifiers; id->desc != NULL; id++) {
233 if ((id->vendor == vendorid) &&
234 (id->device == deviceid)) {
235 return (id);
236 }
237 }
238 return (NULL);
239 }
240
cxgb_get_adapter_info(struct pci_attach_args * pa)241 static const struct adapter_info *cxgb_get_adapter_info(struct pci_attach_args *pa)
242 {
243 struct cxgb_ident *id;
244 const struct adapter_info *ai;
245
246 id = cxgb_get_ident(pa);
247 if (id == NULL)
248 return (NULL);
249
250 ai = t3_get_adapter_info(id->index);
251 return (ai);
252 }
253
cxgb_controller_match(device_t dev,cfdata_t match,void * context)254 static int cxgb_controller_match(device_t dev, cfdata_t match, void *context)
255 {
256 struct pci_attach_args *pa = context;
257 const struct adapter_info *ai;
258
259 ai = cxgb_get_adapter_info(pa);
260 if (ai == NULL)
261 return (0);
262
263 return (100); // we ARE the best driver for this card!!
264 }
265
266 #define FW_FNAME "t3fw%d%d%d"
267 #define TPEEPROM_NAME "t3%ctpe%d%d%d"
268 #define TPSRAM_NAME "t3%cps%d%d%d"
269
270 int cxgb_cfprint(void *aux, const char *info);
cxgb_cfprint(void * aux,const char * info)271 int cxgb_cfprint(void *aux, const char *info)
272 {
273 if (info)
274 {
275 printf("cxgb_cfprint(%p, \"%s\")\n", aux, info);
276 INT3;
277 }
278
279 return (QUIET);
280 }
281
cxgb_make_task(void * context)282 void cxgb_make_task(void *context)
283 {
284 struct cxgb_task *w = (struct cxgb_task *)context;
285
286 // we can only use workqueue_create() once the system is up and running
287 workqueue_create(&w->wq, w->name, w->func, w->context, PRIBIO, IPL_NET, 0);
288 // printf("======>> create workqueue for %s %p\n", w->name, w->wq);
289 }
290
291 static void
cxgb_controller_attach(device_t parent,device_t dev,void * context)292 cxgb_controller_attach(device_t parent, device_t dev, void *context)
293 {
294 device_t child;
295 const struct adapter_info *ai;
296 struct adapter *sc;
297 struct pci_attach_args *pa = context;
298 struct cxgb_attach_args cxgb_args;
299 int locs[2];
300 int i, error = 0;
301 uint32_t vers;
302 int port_qsets = 1;
303 int reg;
304 #ifdef MSI_SUPPORTED
305 int msi_needed;
306 #endif
307
308 sc = device_private(dev);
309 sc->dev = dev;
310 memcpy(&sc->pa, pa, sizeof(struct pci_attach_args));
311 sc->msi_count = 0;
312 ai = cxgb_get_adapter_info(pa);
313
314 /*
315 * XXX not really related but a recent addition
316 */
317 #ifdef MSI_SUPPORTED
318 /* find the PCIe link width and set max read request to 4KB*/
319 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) {
320 uint16_t lnk, pectl;
321 lnk = pci_read_config(dev, reg + 0x12, 2);
322 sc->link_width = (lnk >> 4) & 0x3f;
323
324 pectl = pci_read_config(dev, reg + 0x8, 2);
325 pectl = (pectl & ~0x7000) | (5 << 12);
326 pci_write_config(dev, reg + 0x8, pectl, 2);
327 }
328
329 if (sc->link_width != 0 && sc->link_width <= 4 &&
330 (ai->nports0 + ai->nports1) <= 2) {
331 device_printf(sc->dev,
332 "PCIe x%d Link, expect reduced performance\n",
333 sc->link_width);
334 }
335 #endif
336
337 touch_bars(dev);
338
339 pci_enable_busmaster(dev);
340
341 /*
342 * Allocate the registers and make them available to the driver.
343 * The registers that we care about for NIC mode are in BAR 0
344 */
345 sc->regs_rid = PCI_MAPREG_START;
346 t3_os_pci_read_config_4(sc, PCI_MAPREG_START, ®);
347
348 // call bus_space_map
349 sc->bar0 = reg&0xFFFFF000;
350 bus_space_map(sc->pa.pa_memt, sc->bar0, 4096, 0, &sc->bar0_handle);
351
352 MTX_INIT(&sc->sge.reg_lock, sc->reglockbuf, NULL, MTX_DEF);
353 MTX_INIT(&sc->mdio_lock, sc->mdiolockbuf, NULL, MTX_DEF);
354 MTX_INIT(&sc->elmer_lock, sc->elmerlockbuf, NULL, MTX_DEF);
355
356 sc->bt = sc->pa.pa_memt;
357 sc->bh = sc->bar0_handle;
358 sc->mmio_len = 4096;
359
360 if (t3_prep_adapter(sc, ai, 1) < 0) {
361 printf("prep adapter failed\n");
362 error = ENODEV;
363 goto out;
364 }
365 /* Allocate the BAR for doing MSI-X. If it succeeds, try to allocate
366 * enough messages for the queue sets. If that fails, try falling
367 * back to MSI. If that fails, then try falling back to the legacy
368 * interrupt pin model.
369 */
370 #ifdef MSI_SUPPORTED
371
372 sc->msix_regs_rid = 0x20;
373 if ((msi_allowed >= 2) &&
374 (sc->msix_regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
375 &sc->msix_regs_rid, RF_ACTIVE)) != NULL) {
376
377 msi_needed = sc->msi_count = SGE_MSIX_COUNT;
378
379 if (((error = pci_alloc_msix(dev, &sc->msi_count)) != 0) ||
380 (sc->msi_count != msi_needed)) {
381 device_printf(dev, "msix allocation failed - msi_count = %d"
382 " msi_needed=%d will try msi err=%d\n", sc->msi_count,
383 msi_needed, error);
384 sc->msi_count = 0;
385 pci_release_msi(dev);
386 bus_release_resource(dev, SYS_RES_MEMORY,
387 sc->msix_regs_rid, sc->msix_regs_res);
388 sc->msix_regs_res = NULL;
389 } else {
390 sc->flags |= USING_MSIX;
391 sc->cxgb_intr = t3_intr_msix;
392 }
393 }
394
395 if ((msi_allowed >= 1) && (sc->msi_count == 0)) {
396 sc->msi_count = 1;
397 if (pci_alloc_msi(dev, &sc->msi_count)) {
398 device_printf(dev, "alloc msi failed - will try INTx\n");
399 sc->msi_count = 0;
400 pci_release_msi(dev);
401 } else {
402 sc->flags |= USING_MSI;
403 sc->irq_rid = 1;
404 sc->cxgb_intr = t3_intr_msi;
405 }
406 }
407 #endif
408 if (sc->msi_count == 0) {
409 device_printf(dev, "using line interrupts\n");
410 sc->irq_rid = 0;
411 sc->cxgb_intr = t3b_intr;
412 }
413
414 sc->ext_intr_task.name = "cxgb_ext_intr_handler";
415 sc->ext_intr_task.func = cxgb_ext_intr_handler;
416 sc->ext_intr_task.context = sc;
417 kthread_create(PRI_NONE, 0, NULL, cxgb_make_task, &sc->ext_intr_task, NULL, "cxgb_make_task");
418
419 sc->tick_task.name = "cxgb_tick_handler";
420 sc->tick_task.func = cxgb_tick_handler;
421 sc->tick_task.context = sc;
422 kthread_create(PRI_NONE, 0, NULL, cxgb_make_task, &sc->tick_task, NULL, "cxgb_make_task");
423
424 /* Create a periodic callout for checking adapter status */
425 callout_init(&sc->cxgb_tick_ch, 0);
426
427 if (t3_check_fw_version(sc) != 0) {
428 /*
429 * Warn user that a firmware update will be attempted in init.
430 */
431 device_printf(dev, "firmware needs to be updated to version %d.%d.%d\n",
432 FW_VERSION_MAJOR, FW_VERSION_MINOR, FW_VERSION_MICRO);
433 sc->flags &= ~FW_UPTODATE;
434 } else {
435 sc->flags |= FW_UPTODATE;
436 }
437
438 if (t3_check_tpsram_version(sc) != 0) {
439 /*
440 * Warn user that a firmware update will be attempted in init.
441 */
442 device_printf(dev, "SRAM needs to be updated to version %c-%d.%d.%d\n",
443 t3rev2char(sc), TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO);
444 sc->flags &= ~TPS_UPTODATE;
445 } else {
446 sc->flags |= TPS_UPTODATE;
447 }
448
449 if ((sc->flags & USING_MSIX) && !singleq)
450 port_qsets = (SGE_QSETS/(sc)->params.nports);
451
452 /*
453 * Create a child device for each MAC. The ethernet attachment
454 * will be done in these children.
455 */
456 for (i = 0; i < (sc)->params.nports; i++) {
457 struct port_info *pi;
458
459 pi = &sc->port[i];
460 pi->adapter = sc;
461 pi->nqsets = port_qsets;
462 pi->first_qset = i*port_qsets;
463 pi->port_id = i;
464 pi->tx_chan = i >= ai->nports0;
465 pi->txpkt_intf = pi->tx_chan ? 2 * (i - ai->nports0) + 1 : 2 * i;
466 sc->rxpkt_map[pi->txpkt_intf] = i;
467 cxgb_args.port = i;
468 locs[0] = 1;
469 locs[1] = i;
470 printf("\n"); // for cleaner formatting in dmesg
471 child = config_found_sm_loc(dev, "cxgbc", locs, &cxgb_args,
472 cxgb_cfprint, config_stdsubmatch);
473 printf("\n"); // for cleaner formatting in dmesg
474 sc->portdev[i] = child;
475 }
476
477 /*
478 * XXX need to poll for link status
479 */
480 sc->params.stats_update_period = 1;
481
482 /* initialize sge private state */
483 t3_sge_init_adapter(sc);
484
485 t3_led_ready(sc);
486
487 error = t3_get_fw_version(sc, &vers);
488 if (error)
489 goto out;
490
491 snprintf(&sc->fw_version[0], sizeof(sc->fw_version), "%d.%d.%d",
492 G_FW_VERSION_MAJOR(vers), G_FW_VERSION_MINOR(vers),
493 G_FW_VERSION_MICRO(vers));
494 out:
495 if (error)
496 {
497 cxgb_free(sc);
498 }
499 }
500
501 static int
cxgb_controller_detach(device_t dev,int flags)502 cxgb_controller_detach(device_t dev, int flags)
503 {
504 struct adapter *sc;
505
506 sc = device_private(dev);
507
508 cxgb_free(sc);
509
510 return (0);
511 }
512
513 static void
cxgb_free(struct adapter * sc)514 cxgb_free(struct adapter *sc)
515 {
516 int i;
517
518 ADAPTER_LOCK(sc);
519 /*
520 * drops the lock
521 */
522 cxgb_down_locked(sc);
523
524 #ifdef MSI_SUPPORTED
525 if (sc->flags & (USING_MSI | USING_MSIX)) {
526 device_printf(sc->dev, "releasing msi message(s)\n");
527 pci_release_msi(sc->dev);
528 } else {
529 device_printf(sc->dev, "no msi message to release\n");
530 }
531 if (sc->msix_regs_res != NULL) {
532 bus_release_resource(sc->dev, SYS_RES_MEMORY, sc->msix_regs_rid,
533 sc->msix_regs_res);
534 }
535 #endif
536
537 t3_sge_deinit_sw(sc);
538 /*
539 * Wait for last callout
540 */
541
542 tsleep(&sc, 0, "cxgb unload", 3*hz);
543
544 for (i = 0; i < (sc)->params.nports; ++i) {
545 if (sc->portdev[i] != NULL)
546 {
547 INT3;
548 }
549 }
550
551 #ifdef notyet
552 if (is_offload(sc)) {
553 cxgb_adapter_unofld(sc);
554 if (isset(&sc->open_device_map, OFFLOAD_DEVMAP_BIT))
555 offload_close(&sc->tdev);
556 }
557 #endif
558
559 t3_free_sge_resources(sc);
560 free(sc->filters, M_DEVBUF);
561 t3_sge_free(sc);
562
563 MTX_DESTROY(&sc->mdio_lock);
564 MTX_DESTROY(&sc->sge.reg_lock);
565 MTX_DESTROY(&sc->elmer_lock);
566 ADAPTER_LOCK_DEINIT(sc);
567
568 return;
569 }
570
571 /**
572 * setup_sge_qsets - configure SGE Tx/Rx/response queues
573 * @sc: the controller softc
574 *
575 * Determines how many sets of SGE queues to use and initializes them.
576 * We support multiple queue sets per port if we have MSI-X, otherwise
577 * just one queue set per port.
578 */
579 static int
setup_sge_qsets(adapter_t * sc)580 setup_sge_qsets(adapter_t *sc)
581 {
582 int i, j, err, irq_idx = 0, qset_idx = 0;
583 u_int ntxq = SGE_TXQ_PER_SET;
584
585 if ((err = t3_sge_alloc(sc)) != 0) {
586 device_printf(sc->dev, "t3_sge_alloc returned %d\n", err);
587 return (err);
588 }
589
590 if (sc->params.rev > 0 && !(sc->flags & USING_MSI))
591 irq_idx = -1;
592
593 for (i = 0; i < (sc)->params.nports; i++) {
594 struct port_info *pi = &sc->port[i];
595
596 for (j = 0; j < pi->nqsets; j++, qset_idx++) {
597 err = t3_sge_alloc_qset(sc, qset_idx, (sc)->params.nports,
598 (sc->flags & USING_MSIX) ? qset_idx + 1 : irq_idx,
599 &sc->params.sge.qset[qset_idx], ntxq, pi);
600 if (err) {
601 t3_free_sge_resources(sc);
602 device_printf(sc->dev, "t3_sge_alloc_qset failed with %d\n",
603 err);
604 return (err);
605 }
606 }
607 }
608
609 return (0);
610 }
611
612 static void
cxgb_teardown_msix(adapter_t * sc)613 cxgb_teardown_msix(adapter_t *sc)
614 {
615 int i, nqsets;
616
617 for (nqsets = i = 0; i < (sc)->params.nports; i++)
618 nqsets += sc->port[i].nqsets;
619
620 for (i = 0; i < nqsets; i++) {
621 if (sc->msix_intr_tag[i] != NULL) {
622 sc->msix_intr_tag[i] = NULL;
623 }
624 if (sc->msix_irq_res[i] != NULL) {
625 sc->msix_irq_res[i] = NULL;
626 }
627 }
628 }
629
630 static int
cxgb_setup_msix(adapter_t * sc,int msix_count)631 cxgb_setup_msix(adapter_t *sc, int msix_count)
632 {
633 int i, j, k, nqsets, rid;
634
635 /* The first message indicates link changes and error conditions */
636 sc->irq_rid = 1;
637 /* Allocate PCI interrupt resources. */
638 if (pci_intr_map(&sc->pa, &sc->intr_handle))
639 {
640 printf("cxgb_setup_msix(%d): pci_intr_map() failed\n", __LINE__);
641 return (EINVAL);
642 }
643 sc->intr_cookie = pci_intr_establish(sc->pa.pa_pc, sc->intr_handle,
644 IPL_NET, cxgb_async_intr, sc);
645 if (sc->intr_cookie == NULL)
646 {
647 printf("cxgb_setup_msix(%d): pci_intr_establish() failed\n", __LINE__);
648 return (EINVAL);
649 }
650 for (i = k = 0; i < (sc)->params.nports; i++) {
651 nqsets = sc->port[i].nqsets;
652 for (j = 0; j < nqsets; j++, k++) {
653 rid = k + 2;
654 if (cxgb_debug)
655 printf("rid=%d ", rid);
656 INT3;
657 }
658 }
659
660
661 return (0);
662 }
663
cxgb_port_match(device_t dev,cfdata_t match,void * context)664 static int cxgb_port_match(device_t dev, cfdata_t match, void *context)
665 {
666 return (100);
667 }
668
669 #define IFCAP_HWCSUM (IFCAP_CSUM_IPv4_Rx | IFCAP_CSUM_IPv4_Tx)
670 #define IFCAP_RXCSUM IFCAP_CSUM_IPv4_Rx
671 #define IFCAP_TXCSUM IFCAP_CSUM_IPv4_Tx
672
673 #ifdef TSO_SUPPORTED
674 #define CXGB_CAP (IFCAP_HWCSUM | IFCAP_TSO)
675 /* Don't enable TSO6 yet */
676 #define CXGB_CAP_ENABLE (IFCAP_HWCSUM | IFCAP_TSO4)
677 #else
678 #define CXGB_CAP (IFCAP_HWCSUM)
679 /* Don't enable TSO6 yet */
680 #define CXGB_CAP_ENABLE (IFCAP_HWCSUM)
681 #define IFCAP_TSO4 0x0
682 #define IFCAP_TSO6 0x0
683 #define CSUM_TSO 0x0
684 #endif
685
686 static void
cxgb_port_attach(device_t parent,device_t self,void * context)687 cxgb_port_attach(device_t parent, device_t self, void *context)
688 {
689 struct port_info *p;
690 struct port_device *pd;
691 int *port_number = (int *)context;
692 char buf[32];
693 struct ifnet *ifp;
694 int media_flags;
695 pd = device_private(self);
696 pd->dev = self;
697 pd->parent = device_private(parent);
698 pd->port_number = *port_number;
699 p = &pd->parent->port[*port_number];
700 p->pd = pd;
701
702 PORT_LOCK_INIT(p, p->lockbuf);
703
704 /* Allocate an ifnet object and set it up */
705 ifp = p->ifp = (void *)malloc(sizeof (struct ifnet), M_IFADDR, M_WAITOK);
706 if (ifp == NULL) {
707 device_printf(self, "Cannot allocate ifnet\n");
708 return;
709 }
710 memset(ifp, 0, sizeof(struct ifnet));
711
712 /*
713 * Note that there is currently no watchdog timer.
714 */
715 snprintf(buf, sizeof(buf), "cxgb%d", p->port);
716 strcpy(ifp->if_xname, buf);
717 ifp->if_init = cxgb_init;
718 ifp->if_softc = p;
719 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
720 ifp->if_ioctl = cxgb_ioctl;
721 ifp->if_start = cxgb_start;
722 ifp->if_stop = cxgb_stop;
723 ifp->if_timer = 0; /* Disable ifnet watchdog */
724 ifp->if_watchdog = NULL;
725
726 ifp->if_snd.ifq_maxlen = TX_ETH_Q_SIZE;
727 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_maxlen);
728
729 IFQ_SET_READY(&ifp->if_snd);
730
731 ifp->if_capabilities = ifp->if_capenable = 0;
732 ifp->if_baudrate = 10000000000; // 10 Gbps
733 /*
734 * disable TSO on 4-port - it isn't supported by the firmware yet
735 */
736 if (p->adapter->params.nports > 2) {
737 ifp->if_capabilities &= ~(IFCAP_TSO4 | IFCAP_TSO6);
738 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TSO6);
739 }
740
741 if_attach(ifp);
742 ether_ifattach(ifp, p->hw_addr);
743 /*
744 * Only default to jumbo frames on 10GigE
745 */
746 if (p->adapter->params.nports <= 2)
747 ifp->if_mtu = 9000;
748 ifmedia_init(&p->media, IFM_IMASK, cxgb_media_change,
749 cxgb_media_status);
750
751 if (!strcmp(p->port_type->desc, "10GBASE-CX4")) {
752 media_flags = IFM_ETHER | IFM_10G_CX4 | IFM_FDX;
753 } else if (!strcmp(p->port_type->desc, "10GBASE-SR")) {
754 media_flags = IFM_ETHER | IFM_10G_SR | IFM_FDX;
755 } else if (!strcmp(p->port_type->desc, "10GBASE-XR")) {
756 media_flags = IFM_ETHER | IFM_10G_LR | IFM_FDX;
757 } else if (!strcmp(p->port_type->desc, "10/100/1000BASE-T")) {
758 ifmedia_add(&p->media, IFM_ETHER | IFM_10_T, 0, NULL);
759 ifmedia_add(&p->media, IFM_ETHER | IFM_10_T | IFM_FDX,
760 0, NULL);
761 ifmedia_add(&p->media, IFM_ETHER | IFM_100_TX,
762 0, NULL);
763 ifmedia_add(&p->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
764 0, NULL);
765 ifmedia_add(&p->media, IFM_ETHER | IFM_1000_T | IFM_FDX,
766 0, NULL);
767 media_flags = 0;
768 } else {
769 printf("unsupported media type %s\n", p->port_type->desc);
770 return;
771 }
772 if (media_flags) {
773 ifmedia_add(&p->media, media_flags, 0, NULL);
774 ifmedia_set(&p->media, media_flags);
775 } else {
776 ifmedia_add(&p->media, IFM_ETHER | IFM_AUTO, 0, NULL);
777 ifmedia_set(&p->media, IFM_ETHER | IFM_AUTO);
778 }
779
780 snprintf(p->taskqbuf, TASKQ_NAME_LEN, "cxgb_port_taskq%d", p->port_id);
781 p->start_task.name = "cxgb_start_proc";
782 p->start_task.func = cxgb_start_proc;
783 p->start_task.context = ifp;
784 kthread_create(PRI_NONE, 0, NULL, cxgb_make_task, &p->start_task, NULL, "cxgb_make_task");
785
786 t3_sge_init_port(p);
787 }
788
789 static int
cxgb_port_detach(device_t self,int flags)790 cxgb_port_detach(device_t self, int flags)
791 {
792 struct port_info *p;
793
794 p = device_private(self);
795
796 PORT_LOCK(p);
797 if (p->ifp->if_drv_flags & IFF_DRV_RUNNING)
798 cxgb_stop_locked(p);
799 PORT_UNLOCK(p);
800
801 if (p->start_task.wq != NULL) {
802 workqueue_destroy(p->start_task.wq);
803 p->start_task.wq = NULL;
804 }
805
806 ether_ifdetach(p->ifp);
807 /*
808 * the lock may be acquired in ifdetach
809 */
810 PORT_LOCK_DEINIT(p);
811 if_detach(p->ifp);
812
813 return (0);
814 }
815
816 void
t3_fatal_err(struct adapter * sc)817 t3_fatal_err(struct adapter *sc)
818 {
819 u_int fw_status[4];
820
821 if (sc->flags & FULL_INIT_DONE) {
822 t3_sge_stop(sc);
823 t3_write_reg(sc, A_XGM_TX_CTRL, 0);
824 t3_write_reg(sc, A_XGM_RX_CTRL, 0);
825 t3_write_reg(sc, XGM_REG(A_XGM_TX_CTRL, 1), 0);
826 t3_write_reg(sc, XGM_REG(A_XGM_RX_CTRL, 1), 0);
827 t3_intr_disable(sc);
828 }
829 device_printf(sc->dev,"encountered fatal error, operation suspended\n");
830 if (!t3_cim_ctl_blk_read(sc, 0xa0, 4, fw_status))
831 device_printf(sc->dev, "FW_ status: 0x%x, 0x%x, 0x%x, 0x%x\n",
832 fw_status[0], fw_status[1], fw_status[2], fw_status[3]);
833 }
834
835 int
t3_os_find_pci_capability(adapter_t * sc,int cap)836 t3_os_find_pci_capability(adapter_t *sc, int cap)
837 {
838 device_t dev;
839 uint32_t status;
840 uint32_t bhlc;
841 uint32_t temp;
842 uint8_t ptr;
843 dev = sc->dev;
844 status = pci_conf_read(sc->pa.pa_pc, sc->pa.pa_tag, PCI_COMMAND_STATUS_REG);
845 if (!(status&PCI_STATUS_CAPLIST_SUPPORT))
846 return (0);
847 bhlc = pci_conf_read(sc->pa.pa_pc, sc->pa.pa_tag, PCI_BHLC_REG);
848 switch (PCI_HDRTYPE(bhlc))
849 {
850 case 0:
851 case 1:
852 ptr = PCI_CAPLISTPTR_REG;
853 break;
854 case 2:
855 ptr = PCI_CARDBUS_CAPLISTPTR_REG;
856 break;
857 default:
858 return (0);
859 }
860 temp = pci_conf_read(sc->pa.pa_pc, sc->pa.pa_tag, ptr);
861 ptr = PCI_CAPLIST_PTR(temp);
862 while (ptr != 0) {
863 temp = pci_conf_read(sc->pa.pa_pc, sc->pa.pa_tag, ptr);
864 if (PCI_CAPLIST_CAP(temp) == cap)
865 return (ptr);
866 ptr = PCI_CAPLIST_NEXT(temp);
867 }
868
869 return (0);
870 }
871
872 int
t3_os_pci_save_state(struct adapter * sc)873 t3_os_pci_save_state(struct adapter *sc)
874 {
875 INT3;
876 return (0);
877 }
878
879 int
t3_os_pci_restore_state(struct adapter * sc)880 t3_os_pci_restore_state(struct adapter *sc)
881 {
882 INT3;
883 return (0);
884 }
885
886 /**
887 * t3_os_link_changed - handle link status changes
888 * @adapter: the adapter associated with the link change
889 * @port_id: the port index whose limk status has changed
890 * @link_stat: the new status of the link
891 * @speed: the new speed setting
892 * @duplex: the new duplex setting
893 * @fc: the new flow-control setting
894 *
895 * This is the OS-dependent handler for link status changes. The OS
896 * neutral handler takes care of most of the processing for these events,
897 * then calls this handler for any OS-specific processing.
898 */
899 void
t3_os_link_changed(adapter_t * adapter,int port_id,int link_status,int speed,int duplex,int fc)900 t3_os_link_changed(adapter_t *adapter, int port_id, int link_status, int speed,
901 int duplex, int fc)
902 {
903 struct port_info *pi = &adapter->port[port_id];
904 struct cmac *mac = &adapter->port[port_id].mac;
905
906 if ((pi->ifp->if_flags & IFF_UP) == 0)
907 return;
908
909 if (link_status) {
910 t3_mac_enable(mac, MAC_DIRECTION_RX);
911 if_link_state_change(pi->ifp, LINK_STATE_UP);
912 } else {
913 if_link_state_change(pi->ifp, LINK_STATE_DOWN);
914 pi->phy.ops->power_down(&pi->phy, 1);
915 t3_mac_disable(mac, MAC_DIRECTION_RX);
916 t3_link_start(&pi->phy, mac, &pi->link_config);
917 }
918 }
919
920 /*
921 * Interrupt-context handler for external (PHY) interrupts.
922 */
923 void
t3_os_ext_intr_handler(adapter_t * sc)924 t3_os_ext_intr_handler(adapter_t *sc)
925 {
926 if (cxgb_debug)
927 printf("t3_os_ext_intr_handler\n");
928 /*
929 * Schedule a task to handle external interrupts as they may be slow
930 * and we use a mutex to protect MDIO registers. We disable PHY
931 * interrupts in the meantime and let the task reenable them when
932 * it's done.
933 */
934 ADAPTER_LOCK(sc);
935 if (sc->slow_intr_mask) {
936 sc->slow_intr_mask &= ~F_T3DBG;
937 t3_write_reg(sc, A_PL_INT_ENABLE0, sc->slow_intr_mask);
938 workqueue_enqueue(sc->ext_intr_task.wq, &sc->ext_intr_task.w, NULL);
939 }
940 ADAPTER_UNLOCK(sc);
941 }
942
943 void
t3_os_set_hw_addr(adapter_t * adapter,int port_idx,u8 hw_addr[])944 t3_os_set_hw_addr(adapter_t *adapter, int port_idx, u8 hw_addr[])
945 {
946
947 /*
948 * The ifnet might not be allocated before this gets called,
949 * as this is called early on in attach by t3_prep_adapter
950 * save the address off in the port structure
951 */
952 if (cxgb_debug)
953 printf("set_hw_addr on idx %d addr %02x:%02x:%02x:%02x:%02x:%02x\n",
954 port_idx, hw_addr[0], hw_addr[1], hw_addr[2], hw_addr[3], hw_addr[4], hw_addr[5]);
955 memcpy(adapter->port[port_idx].hw_addr, hw_addr, ETHER_ADDR_LEN);
956 }
957
958 /**
959 * link_start - enable a port
960 * @p: the port to enable
961 *
962 * Performs the MAC and PHY actions needed to enable a port.
963 */
964 static void
cxgb_link_start(struct port_info * p)965 cxgb_link_start(struct port_info *p)
966 {
967 struct ifnet *ifp;
968 struct t3_rx_mode rm;
969 struct cmac *mac = &p->mac;
970
971 ifp = p->ifp;
972
973 t3_init_rx_mode(&rm, p);
974 if (!mac->multiport)
975 t3_mac_reset(mac);
976 t3_mac_set_mtu(mac, ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
977 t3_mac_set_address(mac, 0, p->hw_addr);
978 t3_mac_set_rx_mode(mac, &rm);
979 t3_link_start(&p->phy, mac, &p->link_config);
980 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
981 }
982
983 /**
984 * setup_rss - configure Receive Side Steering (per-queue connection demux)
985 * @adap: the adapter
986 *
987 * Sets up RSS to distribute packets to multiple receive queues. We
988 * configure the RSS CPU lookup table to distribute to the number of HW
989 * receive queues, and the response queue lookup table to narrow that
990 * down to the response queues actually configured for each port.
991 * We always configure the RSS mapping for two ports since the mapping
992 * table has plenty of entries.
993 */
994 static void
setup_rss(adapter_t * adap)995 setup_rss(adapter_t *adap)
996 {
997 int i;
998 u_int nq[2];
999 uint8_t cpus[SGE_QSETS + 1];
1000 uint16_t rspq_map[RSS_TABLE_SIZE];
1001
1002 for (i = 0; i < SGE_QSETS; ++i)
1003 cpus[i] = i;
1004 cpus[SGE_QSETS] = 0xff;
1005
1006 nq[0] = nq[1] = 0;
1007 for_each_port(adap, i) {
1008 const struct port_info *pi = adap2pinfo(adap, i);
1009
1010 nq[pi->tx_chan] += pi->nqsets;
1011 }
1012 nq[0] = max(nq[0], 1U);
1013 nq[1] = max(nq[1], 1U);
1014 for (i = 0; i < RSS_TABLE_SIZE / 2; ++i) {
1015 rspq_map[i] = i % nq[0];
1016 rspq_map[i + RSS_TABLE_SIZE / 2] = (i % nq[1]) + nq[0];
1017 }
1018 /* Calculate the reverse RSS map table */
1019 for (i = 0; i < RSS_TABLE_SIZE; ++i)
1020 if (adap->rrss_map[rspq_map[i]] == 0xff)
1021 adap->rrss_map[rspq_map[i]] = i;
1022
1023 t3_config_rss(adap, F_RQFEEDBACKENABLE | F_TNLLKPEN | F_TNLMAPEN |
1024 F_TNLPRTEN | F_TNL2TUPEN | F_TNL4TUPEN | F_OFDMAPEN |
1025 V_RRCPLCPUSIZE(6), cpus, rspq_map);
1026
1027 }
1028
1029 /*
1030 * Sends an mbuf to an offload queue driver
1031 * after dealing with any active network taps.
1032 */
1033 static inline int
offload_tx(struct toedev * tdev,struct mbuf * m)1034 offload_tx(struct toedev *tdev, struct mbuf *m)
1035 {
1036 int ret;
1037
1038 critical_enter();
1039 ret = t3_offload_tx(tdev, m);
1040 critical_exit();
1041 return (ret);
1042 }
1043
1044 static void
send_pktsched_cmd(struct adapter * adap,int sched,int qidx,int lo,int hi,int port)1045 send_pktsched_cmd(struct adapter *adap, int sched, int qidx, int lo,
1046 int hi, int port)
1047 {
1048 struct mbuf *m;
1049 struct mngt_pktsched_wr *req;
1050
1051 m = m_gethdr(M_DONTWAIT, MT_DATA);
1052 if (m) {
1053 req = mtod(m, struct mngt_pktsched_wr *);
1054 req->wr_hi = htonl(V_WR_OP(FW_WROPCODE_MNGT));
1055 req->mngt_opcode = FW_MNGTOPCODE_PKTSCHED_SET;
1056 req->sched = sched;
1057 req->idx = qidx;
1058 req->min = lo;
1059 req->max = hi;
1060 req->binding = port;
1061 m->m_len = m->m_pkthdr.len = sizeof(*req);
1062 t3_mgmt_tx(adap, m);
1063 }
1064 }
1065
1066 static void
bind_qsets(adapter_t * sc)1067 bind_qsets(adapter_t *sc)
1068 {
1069 int i, j;
1070
1071 for (i = 0; i < (sc)->params.nports; ++i) {
1072 const struct port_info *pi = adap2pinfo(sc, i);
1073
1074 for (j = 0; j < pi->nqsets; ++j) {
1075 send_pktsched_cmd(sc, 1, pi->first_qset + j, -1,
1076 -1, pi->tx_chan);
1077
1078 }
1079 }
1080 }
1081
1082 /**
1083 * cxgb_up - enable the adapter
1084 * @adap: adapter being enabled
1085 *
1086 * Called when the first port is enabled, this function performs the
1087 * actions necessary to make an adapter operational, such as completing
1088 * the initialization of HW modules, and enabling interrupts.
1089 *
1090 */
1091 static int
cxgb_up(struct adapter * sc)1092 cxgb_up(struct adapter *sc)
1093 {
1094 int err = 0;
1095
1096 if ((sc->flags & FULL_INIT_DONE) == 0) {
1097
1098 if ((sc->flags & FW_UPTODATE) == 0)
1099 printf("SHOULD UPGRADE FIRMWARE!\n");
1100 if ((sc->flags & TPS_UPTODATE) == 0)
1101 printf("SHOULD UPDATE TPSRAM\n");
1102 err = t3_init_hw(sc, 0);
1103 if (err)
1104 goto out;
1105
1106 t3_write_reg(sc, A_ULPRX_TDDP_PSZ, V_HPZ0(PAGE_SHIFT - 12));
1107
1108 err = setup_sge_qsets(sc);
1109 if (err)
1110 goto out;
1111
1112 setup_rss(sc);
1113 sc->flags |= FULL_INIT_DONE;
1114 }
1115
1116 t3_intr_clear(sc);
1117
1118 /* If it's MSI or INTx, allocate a single interrupt for everything */
1119 if ((sc->flags & USING_MSIX) == 0) {
1120 if (pci_intr_map(&sc->pa, &sc->intr_handle))
1121 {
1122 device_printf(sc->dev, "Cannot allocate interrupt\n");
1123 err = EINVAL;
1124 goto out;
1125 }
1126 device_printf(sc->dev, "allocated intr_handle=%d\n", sc->intr_handle);
1127 sc->intr_cookie = pci_intr_establish(sc->pa.pa_pc,
1128 sc->intr_handle, IPL_NET,
1129 sc->cxgb_intr, sc);
1130 if (sc->intr_cookie == NULL)
1131 {
1132 device_printf(sc->dev, "Cannot establish interrupt\n");
1133 err = EINVAL;
1134 goto irq_err;
1135 }
1136 } else {
1137 printf("Using MSIX?!?!?!\n");
1138 INT3;
1139 cxgb_setup_msix(sc, sc->msi_count);
1140 }
1141
1142 t3_sge_start(sc);
1143 t3_intr_enable(sc);
1144
1145 if (!(sc->flags & QUEUES_BOUND)) {
1146 bind_qsets(sc);
1147 sc->flags |= QUEUES_BOUND;
1148 }
1149 out:
1150 return (err);
1151 irq_err:
1152 CH_ERR(sc, "request_irq failed, err %d\n", err);
1153 goto out;
1154 }
1155
1156
1157 /*
1158 * Release resources when all the ports and offloading have been stopped.
1159 */
1160 static void
cxgb_down_locked(struct adapter * sc)1161 cxgb_down_locked(struct adapter *sc)
1162 {
1163 t3_sge_stop(sc);
1164 t3_intr_disable(sc);
1165
1166 INT3; // XXXXXXXXXXXXXXXXXX
1167
1168 if (sc->flags & USING_MSIX)
1169 cxgb_teardown_msix(sc);
1170 ADAPTER_UNLOCK(sc);
1171
1172 callout_drain(&sc->cxgb_tick_ch);
1173 callout_drain(&sc->sge_timer_ch);
1174
1175 #ifdef notyet
1176
1177 if (sc->port[i].tq != NULL)
1178 #endif
1179
1180 }
1181
1182 static int
cxgb_init(struct ifnet * ifp)1183 cxgb_init(struct ifnet *ifp)
1184 {
1185 struct port_info *p = ifp->if_softc;
1186
1187 PORT_LOCK(p);
1188 cxgb_init_locked(p);
1189 PORT_UNLOCK(p);
1190
1191 return (0); // ????????????
1192 }
1193
1194 static void
cxgb_init_locked(struct port_info * p)1195 cxgb_init_locked(struct port_info *p)
1196 {
1197 struct ifnet *ifp;
1198 adapter_t *sc = p->adapter;
1199 int err;
1200
1201 PORT_LOCK_ASSERT_OWNED(p);
1202 ifp = p->ifp;
1203
1204 ADAPTER_LOCK(p->adapter);
1205 if ((sc->open_device_map == 0) && (err = cxgb_up(sc))) {
1206 ADAPTER_UNLOCK(p->adapter);
1207 cxgb_stop_locked(p);
1208 return;
1209 }
1210 if (p->adapter->open_device_map == 0) {
1211 t3_intr_clear(sc);
1212 t3_sge_init_adapter(sc);
1213 }
1214 setbit(&p->adapter->open_device_map, p->port_id);
1215 ADAPTER_UNLOCK(p->adapter);
1216
1217 cxgb_link_start(p);
1218 t3_link_changed(sc, p->port_id);
1219 ifp->if_baudrate = p->link_config.speed * 1000000;
1220
1221 device_printf(sc->dev, "enabling interrupts on port=%d\n", p->port_id);
1222 t3_port_intr_enable(sc, p->port_id);
1223
1224 callout_reset(&sc->cxgb_tick_ch, sc->params.stats_update_period * hz,
1225 cxgb_tick, sc);
1226
1227 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1228 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1229 }
1230
1231 static void
cxgb_set_rxmode(struct port_info * p)1232 cxgb_set_rxmode(struct port_info *p)
1233 {
1234 struct t3_rx_mode rm;
1235 struct cmac *mac = &p->mac;
1236
1237 PORT_LOCK_ASSERT_OWNED(p);
1238
1239 t3_init_rx_mode(&rm, p);
1240 t3_mac_set_rx_mode(mac, &rm);
1241 }
1242
1243 static void
cxgb_stop_locked(struct port_info * p)1244 cxgb_stop_locked(struct port_info *p)
1245 {
1246 struct ifnet *ifp;
1247
1248 PORT_LOCK_ASSERT_OWNED(p);
1249 ADAPTER_LOCK_ASSERT_NOTOWNED(p->adapter);
1250
1251 ifp = p->ifp;
1252
1253 t3_port_intr_disable(p->adapter, p->port_id);
1254 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1255 p->phy.ops->power_down(&p->phy, 1);
1256 t3_mac_disable(&p->mac, MAC_DIRECTION_TX | MAC_DIRECTION_RX);
1257
1258 ADAPTER_LOCK(p->adapter);
1259 clrbit(&p->adapter->open_device_map, p->port_id);
1260
1261
1262 if (p->adapter->open_device_map == 0) {
1263 cxgb_down_locked(p->adapter);
1264 } else
1265 ADAPTER_UNLOCK(p->adapter);
1266
1267 }
1268
1269 static int
cxgb_set_mtu(struct port_info * p,int mtu)1270 cxgb_set_mtu(struct port_info *p, int mtu)
1271 {
1272 struct ifnet *ifp = p->ifp;
1273 struct ifreq ifr;
1274 int error = 0;
1275
1276 ifr.ifr_mtu = mtu;
1277
1278 if ((mtu < ETHERMIN) || (mtu > ETHER_MAX_LEN_JUMBO))
1279 error = EINVAL;
1280 else if ((error = ifioctl_common(ifp, SIOCSIFMTU, &ifr)) == ENETRESET) {
1281 error = 0;
1282 PORT_LOCK(p);
1283 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1284 callout_stop(&p->adapter->cxgb_tick_ch);
1285 cxgb_stop_locked(p);
1286 cxgb_init_locked(p);
1287 }
1288 PORT_UNLOCK(p);
1289 }
1290 return (error);
1291 }
1292
1293 static int
cxgb_ioctl(struct ifnet * ifp,unsigned long command,void * data)1294 cxgb_ioctl(struct ifnet *ifp, unsigned long command, void *data)
1295 {
1296 struct port_info *p = ifp->if_softc;
1297 struct ifaddr *ifa = (struct ifaddr *)data;
1298 struct ifreq *ifr = (struct ifreq *)data;
1299 int flags, error = 0;
1300
1301 /*
1302 * XXX need to check that we aren't in the middle of an unload
1303 */
1304 printf("cxgb_ioctl(%d): command=%08lx\n", __LINE__, command);
1305 switch (command) {
1306 case SIOCSIFMTU:
1307 error = cxgb_set_mtu(p, ifr->ifr_mtu);
1308 printf("SIOCSIFMTU: error=%d\n", error);
1309 break;
1310 case SIOCINITIFADDR:
1311 printf("SIOCINITIFADDR:\n");
1312 PORT_LOCK(p);
1313 if (ifa->ifa_addr->sa_family == AF_INET) {
1314 ifp->if_flags |= IFF_UP;
1315 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1316 cxgb_init_locked(p);
1317 arp_ifinit(ifp, ifa);
1318 } else
1319 error = ether_ioctl(ifp, command, data);
1320 PORT_UNLOCK(p);
1321 break;
1322 case SIOCSIFFLAGS:
1323 printf("SIOCSIFFLAGS:\n");
1324 #if 0
1325 if ((error = ifioctl_common(ifp, cmd, data)) != 0)
1326 break;
1327 #endif
1328 callout_drain(&p->adapter->cxgb_tick_ch);
1329 PORT_LOCK(p);
1330 if (ifp->if_flags & IFF_UP) {
1331 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1332 flags = p->if_flags;
1333 if (((ifp->if_flags ^ flags) & IFF_PROMISC) ||
1334 ((ifp->if_flags ^ flags) & IFF_ALLMULTI))
1335 cxgb_set_rxmode(p);
1336 } else
1337 cxgb_init_locked(p);
1338 p->if_flags = ifp->if_flags;
1339 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1340 cxgb_stop_locked(p);
1341
1342 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1343 adapter_t *sc = p->adapter;
1344 callout_reset(&sc->cxgb_tick_ch,
1345 sc->params.stats_update_period * hz,
1346 cxgb_tick, sc);
1347 }
1348 PORT_UNLOCK(p);
1349 break;
1350 case SIOCSIFMEDIA:
1351 printf("SIOCSIFMEDIA:\n");
1352 case SIOCGIFMEDIA:
1353 error = ifmedia_ioctl(ifp, ifr, &p->media, command);
1354 printf("SIOCGIFMEDIA: error=%d\n", error);
1355 break;
1356 default:
1357 printf("Dir = %x Len = %x Group = '%c' Num = %x\n",
1358 (unsigned int)(command&0xe0000000)>>28, (unsigned int)(command&0x1fff0000)>>16,
1359 (unsigned int)(command&0xff00)>>8, (unsigned int)command&0xff);
1360 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET)
1361 break;
1362 error = 0;
1363 break;
1364 }
1365 return (error);
1366 }
1367
1368 static int
cxgb_start_tx(struct ifnet * ifp,uint32_t txmax)1369 cxgb_start_tx(struct ifnet *ifp, uint32_t txmax)
1370 {
1371 struct sge_qset *qs;
1372 struct sge_txq *txq;
1373 struct port_info *p = ifp->if_softc;
1374 struct mbuf *m = NULL;
1375 int err, in_use_init, free_it;
1376
1377 if (!p->link_config.link_ok)
1378 {
1379 return (ENXIO);
1380 }
1381
1382 if (IFQ_IS_EMPTY(&ifp->if_snd))
1383 {
1384 return (ENOBUFS);
1385 }
1386
1387 qs = &p->adapter->sge.qs[p->first_qset];
1388 txq = &qs->txq[TXQ_ETH];
1389 err = 0;
1390
1391 if (txq->flags & TXQ_TRANSMITTING)
1392 {
1393 return (EINPROGRESS);
1394 }
1395
1396 mtx_lock(&txq->lock);
1397 txq->flags |= TXQ_TRANSMITTING;
1398 in_use_init = txq->in_use;
1399 while ((txq->in_use - in_use_init < txmax) &&
1400 (txq->size > txq->in_use + TX_MAX_DESC)) {
1401 free_it = 0;
1402 IFQ_DEQUEUE(&ifp->if_snd, m);
1403 if (m == NULL)
1404 break;
1405 /*
1406 * Convert chain to M_IOVEC
1407 */
1408 KASSERT((m->m_flags & M_IOVEC) == 0);
1409 #ifdef notyet
1410 m0 = m;
1411 if (collapse_mbufs && m->m_pkthdr.len > MCLBYTES &&
1412 m_collapse(m, TX_MAX_SEGS, &m0) == EFBIG) {
1413 if ((m0 = m_defrag(m, M_NOWAIT)) != NULL) {
1414 m = m0;
1415 m_collapse(m, TX_MAX_SEGS, &m0);
1416 } else
1417 break;
1418 }
1419 m = m0;
1420 #endif
1421 if ((err = t3_encap(p, &m, &free_it)) != 0)
1422 {
1423 printf("t3_encap() returned %d\n", err);
1424 break;
1425 }
1426 // bpf_mtap(ifp, m);
1427 if (free_it)
1428 {
1429 m_freem(m);
1430 }
1431 }
1432 txq->flags &= ~TXQ_TRANSMITTING;
1433 mtx_unlock(&txq->lock);
1434
1435 if (__predict_false(err)) {
1436 if (err == ENOMEM) {
1437 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1438 // XXXXXXXXXX lock/unlock??
1439 IF_PREPEND(&ifp->if_snd, m);
1440 }
1441 }
1442 if (err == 0 && m == NULL)
1443 err = ENOBUFS;
1444 else if ((err == 0) && (txq->size <= txq->in_use + TX_MAX_DESC) &&
1445 (ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) {
1446 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1447 err = ENOSPC;
1448 }
1449 return (err);
1450 }
1451
1452 static void
cxgb_start_proc(struct work * wk,void * arg)1453 cxgb_start_proc(struct work *wk, void *arg)
1454 {
1455 struct ifnet *ifp = arg;
1456 struct port_info *pi = ifp->if_softc;
1457 struct sge_qset *qs;
1458 struct sge_txq *txq;
1459 int error;
1460
1461 qs = &pi->adapter->sge.qs[pi->first_qset];
1462 txq = &qs->txq[TXQ_ETH];
1463
1464 do {
1465 if (desc_reclaimable(txq) > TX_CLEAN_MAX_DESC >> 2)
1466 workqueue_enqueue(pi->timer_reclaim_task.wq, &pi->timer_reclaim_task.w, NULL);
1467
1468 error = cxgb_start_tx(ifp, TX_START_MAX_DESC);
1469 } while (error == 0);
1470 }
1471
1472 static void
cxgb_start(struct ifnet * ifp)1473 cxgb_start(struct ifnet *ifp)
1474 {
1475 struct port_info *pi = ifp->if_softc;
1476 struct sge_qset *qs;
1477 struct sge_txq *txq;
1478 int err;
1479
1480 qs = &pi->adapter->sge.qs[pi->first_qset];
1481 txq = &qs->txq[TXQ_ETH];
1482
1483 if (desc_reclaimable(txq) > TX_CLEAN_MAX_DESC >> 2)
1484 workqueue_enqueue(pi->timer_reclaim_task.wq, &pi->timer_reclaim_task.w, NULL);
1485
1486 err = cxgb_start_tx(ifp, TX_START_MAX_DESC);
1487
1488 if (err == 0)
1489 workqueue_enqueue(pi->start_task.wq, &pi->start_task.w, NULL);
1490 }
1491
1492 static void
cxgb_stop(struct ifnet * ifp,int reason)1493 cxgb_stop(struct ifnet *ifp, int reason)
1494 {
1495 struct port_info *pi = ifp->if_softc;
1496
1497 printf("cxgb_stop(): pi=%p, reason=%d\n", pi, reason);
1498 INT3;
1499 }
1500
1501 static int
cxgb_media_change(struct ifnet * ifp)1502 cxgb_media_change(struct ifnet *ifp)
1503 {
1504 printf("media change not supported: ifp=%p\n", ifp);
1505 return (ENXIO);
1506 }
1507
1508 static void
cxgb_media_status(struct ifnet * ifp,struct ifmediareq * ifmr)1509 cxgb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1510 {
1511 struct port_info *p;
1512
1513 p = ifp->if_softc;
1514
1515 ifmr->ifm_status = IFM_AVALID;
1516 ifmr->ifm_active = IFM_ETHER;
1517
1518 if (!p->link_config.link_ok)
1519 return;
1520
1521 ifmr->ifm_status |= IFM_ACTIVE;
1522
1523 switch (p->link_config.speed) {
1524 case 10:
1525 ifmr->ifm_active |= IFM_10_T;
1526 break;
1527 case 100:
1528 ifmr->ifm_active |= IFM_100_TX;
1529 break;
1530 case 1000:
1531 ifmr->ifm_active |= IFM_1000_T;
1532 break;
1533 }
1534
1535 if (p->link_config.duplex)
1536 ifmr->ifm_active |= IFM_FDX;
1537 else
1538 ifmr->ifm_active |= IFM_HDX;
1539 }
1540
1541 static int
cxgb_async_intr(void * data)1542 cxgb_async_intr(void *data)
1543 {
1544 adapter_t *sc = data;
1545
1546 if (cxgb_debug)
1547 device_printf(sc->dev, "cxgb_async_intr\n");
1548 /*
1549 * May need to sleep - defer to taskqueue
1550 */
1551 workqueue_enqueue(sc->slow_intr_task.wq, &sc->slow_intr_task.w, NULL);
1552
1553 return (1);
1554 }
1555
1556 static void
cxgb_ext_intr_handler(struct work * wk,void * arg)1557 cxgb_ext_intr_handler(struct work *wk, void *arg)
1558 {
1559 adapter_t *sc = (adapter_t *)arg;
1560
1561 if (cxgb_debug)
1562 printf("cxgb_ext_intr_handler\n");
1563
1564 t3_phy_intr_handler(sc);
1565
1566 /* Now reenable external interrupts */
1567 ADAPTER_LOCK(sc);
1568 if (sc->slow_intr_mask) {
1569 sc->slow_intr_mask |= F_T3DBG;
1570 t3_write_reg(sc, A_PL_INT_CAUSE0, F_T3DBG);
1571 t3_write_reg(sc, A_PL_INT_ENABLE0, sc->slow_intr_mask);
1572 }
1573 ADAPTER_UNLOCK(sc);
1574 }
1575
1576 static void
check_link_status(adapter_t * sc)1577 check_link_status(adapter_t *sc)
1578 {
1579 int i;
1580
1581 for (i = 0; i < (sc)->params.nports; ++i) {
1582 struct port_info *p = &sc->port[i];
1583
1584 if (!(p->port_type->caps & SUPPORTED_IRQ))
1585 t3_link_changed(sc, i);
1586 p->ifp->if_baudrate = p->link_config.speed * 1000000;
1587 }
1588 }
1589
1590 static void
check_t3b2_mac(struct adapter * adapter)1591 check_t3b2_mac(struct adapter *adapter)
1592 {
1593 int i;
1594
1595 for_each_port(adapter, i) {
1596 struct port_info *p = &adapter->port[i];
1597 struct ifnet *ifp = p->ifp;
1598 int status;
1599
1600 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1601 continue;
1602
1603 status = 0;
1604 PORT_LOCK(p);
1605 if ((ifp->if_drv_flags & IFF_DRV_RUNNING))
1606 status = t3b2_mac_watchdog_task(&p->mac);
1607 if (status == 1)
1608 p->mac.stats.num_toggled++;
1609 else if (status == 2) {
1610 struct cmac *mac = &p->mac;
1611
1612 t3_mac_set_mtu(mac, ifp->if_mtu + ETHER_HDR_LEN
1613 + ETHER_VLAN_ENCAP_LEN);
1614 t3_mac_set_address(mac, 0, p->hw_addr);
1615 cxgb_set_rxmode(p);
1616 t3_link_start(&p->phy, mac, &p->link_config);
1617 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
1618 t3_port_intr_enable(adapter, p->port_id);
1619 p->mac.stats.num_resets++;
1620 }
1621 PORT_UNLOCK(p);
1622 }
1623 }
1624
1625 static void
cxgb_tick(void * arg)1626 cxgb_tick(void *arg)
1627 {
1628 adapter_t *sc = (adapter_t *)arg;
1629
1630 workqueue_enqueue(sc->tick_task.wq, &sc->tick_task.w, NULL);
1631
1632 if (sc->open_device_map != 0)
1633 callout_reset(&sc->cxgb_tick_ch, sc->params.stats_update_period * hz,
1634 cxgb_tick, sc);
1635 }
1636
1637 static void
cxgb_tick_handler(struct work * wk,void * arg)1638 cxgb_tick_handler(struct work *wk, void *arg)
1639 {
1640 adapter_t *sc = (adapter_t *)arg;
1641 const struct adapter_params *p = &sc->params;
1642
1643 ADAPTER_LOCK(sc);
1644 if (p->linkpoll_period)
1645 check_link_status(sc);
1646
1647 /*
1648 * adapter lock can currently only be acquire after the
1649 * port lock
1650 */
1651 ADAPTER_UNLOCK(sc);
1652
1653 if (p->rev == T3_REV_B2 && p->nports < 4)
1654 check_t3b2_mac(sc);
1655 }
1656
1657 static void
touch_bars(device_t dev)1658 touch_bars(device_t dev)
1659 {
1660 /*
1661 * Don't enable yet
1662 */
1663 #if !defined(__LP64__) && 0
1664 u32 v;
1665
1666 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_1, &v);
1667 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_1, v);
1668 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_3, &v);
1669 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_3, v);
1670 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &v);
1671 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_5, v);
1672 #endif
1673 }
1674
1675 static __inline void
reg_block_dump(struct adapter * ap,uint8_t * buf,unsigned int start,unsigned int end)1676 reg_block_dump(struct adapter *ap, uint8_t *buf, unsigned int start,
1677 unsigned int end)
1678 {
1679 uint32_t *p = (uint32_t *)buf + start;
1680
1681 for ( ; start <= end; start += sizeof(uint32_t))
1682 *p++ = t3_read_reg(ap, start);
1683 }
1684
1685