1 /* $NetBSD: qe.c,v 1.65 2016/06/10 13:27:15 ozaki-r Exp $ */
2
3 /*-
4 * Copyright (c) 1999 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Paul Kranenburg.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 /*
33 * Copyright (c) 1998 Jason L. Wright.
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 * 1. Redistributions of source code must retain the above copyright
40 * notice, this list of conditions and the following disclaimer.
41 * 2. Redistributions in binary form must reproduce the above copyright
42 * notice, this list of conditions and the following disclaimer in the
43 * documentation and/or other materials provided with the distribution.
44 * 3. The name of the authors may not be used to endorse or promote products
45 * derived from this software without specific prior written permission.
46 *
47 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
50 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
57 */
58
59 /*
60 * Driver for the SBus qec+qe QuadEthernet board.
61 *
62 * This driver was written using the AMD MACE Am79C940 documentation, some
63 * ideas gleaned from the S/Linux driver for this card, Solaris header files,
64 * and a loan of a card from Paul Southworth of the Internet Engineering
65 * Group (www.ieng.com).
66 */
67
68 #include <sys/cdefs.h>
69 __KERNEL_RCSID(0, "$NetBSD: qe.c,v 1.65 2016/06/10 13:27:15 ozaki-r Exp $");
70
71 #define QEDEBUG
72
73 #include "opt_ddb.h"
74 #include "opt_inet.h"
75
76 #include <sys/param.h>
77 #include <sys/systm.h>
78 #include <sys/kernel.h>
79 #include <sys/errno.h>
80 #include <sys/ioctl.h>
81 #include <sys/mbuf.h>
82 #include <sys/socket.h>
83 #include <sys/syslog.h>
84 #include <sys/device.h>
85 #include <sys/malloc.h>
86
87 #include <net/if.h>
88 #include <net/if_dl.h>
89 #include <net/if_types.h>
90 #include <net/netisr.h>
91 #include <net/if_media.h>
92 #include <net/if_ether.h>
93
94 #ifdef INET
95 #include <netinet/in.h>
96 #include <netinet/if_inarp.h>
97 #include <netinet/in_systm.h>
98 #include <netinet/in_var.h>
99 #include <netinet/ip.h>
100 #endif
101
102
103 #include <net/bpf.h>
104 #include <net/bpfdesc.h>
105
106 #include <sys/bus.h>
107 #include <sys/intr.h>
108 #include <machine/autoconf.h>
109
110 #include <dev/sbus/sbusvar.h>
111 #include <dev/sbus/qecreg.h>
112 #include <dev/sbus/qecvar.h>
113 #include <dev/sbus/qereg.h>
114
115 struct qe_softc {
116 device_t sc_dev;
117 bus_space_tag_t sc_bustag; /* bus & DMA tags */
118 bus_dma_tag_t sc_dmatag;
119 bus_dmamap_t sc_dmamap;
120 struct ethercom sc_ethercom;
121 struct ifmedia sc_ifmedia; /* interface media */
122
123 struct qec_softc *sc_qec; /* QEC parent */
124
125 bus_space_handle_t sc_qr; /* QEC registers */
126 bus_space_handle_t sc_mr; /* MACE registers */
127 bus_space_handle_t sc_cr; /* channel registers */
128
129 int sc_channel; /* channel number */
130 u_int sc_rev; /* board revision */
131
132 int sc_burst;
133
134 struct qec_ring sc_rb; /* Packet Ring Buffer */
135
136 /* MAC address */
137 uint8_t sc_enaddr[6];
138
139 #ifdef QEDEBUG
140 int sc_debug;
141 #endif
142 };
143
144 int qematch(device_t, cfdata_t, void *);
145 void qeattach(device_t, device_t, void *);
146
147 void qeinit(struct qe_softc *);
148 void qestart(struct ifnet *);
149 void qestop(struct qe_softc *);
150 void qewatchdog(struct ifnet *);
151 int qeioctl(struct ifnet *, u_long, void *);
152 void qereset(struct qe_softc *);
153
154 int qeintr(void *);
155 int qe_eint(struct qe_softc *, uint32_t);
156 int qe_rint(struct qe_softc *);
157 int qe_tint(struct qe_softc *);
158 void qe_mcreset(struct qe_softc *);
159
160 static int qe_put(struct qe_softc *, int, struct mbuf *);
161 static void qe_read(struct qe_softc *, int, int);
162 static struct mbuf *qe_get(struct qe_softc *, int, int);
163
164 /* ifmedia callbacks */
165 void qe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
166 int qe_ifmedia_upd(struct ifnet *);
167
168 CFATTACH_DECL_NEW(qe, sizeof(struct qe_softc),
169 qematch, qeattach, NULL, NULL);
170
171 int
qematch(device_t parent,cfdata_t cf,void * aux)172 qematch(device_t parent, cfdata_t cf, void *aux)
173 {
174 struct sbus_attach_args *sa = aux;
175
176 return (strcmp(cf->cf_name, sa->sa_name) == 0);
177 }
178
179 void
qeattach(device_t parent,device_t self,void * aux)180 qeattach(device_t parent, device_t self, void *aux)
181 {
182 struct sbus_attach_args *sa = aux;
183 struct qec_softc *qec = device_private(parent);
184 struct qe_softc *sc = device_private(self);
185 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
186 int node = sa->sa_node;
187 bus_dma_tag_t dmatag = sa->sa_dmatag;
188 bus_dma_segment_t seg;
189 bus_size_t size;
190 int rseg, error;
191
192 sc->sc_dev = self;
193
194 if (sa->sa_nreg < 2) {
195 printf("%s: only %d register sets\n",
196 device_xname(self), sa->sa_nreg);
197 return;
198 }
199
200 if (bus_space_map(sa->sa_bustag,
201 (bus_addr_t)BUS_ADDR(
202 sa->sa_reg[0].oa_space,
203 sa->sa_reg[0].oa_base),
204 (bus_size_t)sa->sa_reg[0].oa_size,
205 0, &sc->sc_cr) != 0) {
206 aprint_error_dev(self, "cannot map registers\n");
207 return;
208 }
209
210 if (bus_space_map(sa->sa_bustag,
211 (bus_addr_t)BUS_ADDR(
212 sa->sa_reg[1].oa_space,
213 sa->sa_reg[1].oa_base),
214 (bus_size_t)sa->sa_reg[1].oa_size,
215 0, &sc->sc_mr) != 0) {
216 aprint_error_dev(self, "cannot map registers\n");
217 return;
218 }
219
220 sc->sc_rev = prom_getpropint(node, "mace-version", -1);
221 printf(" rev %x", sc->sc_rev);
222
223 sc->sc_bustag = sa->sa_bustag;
224 sc->sc_dmatag = sa->sa_dmatag;
225 sc->sc_qec = qec;
226 sc->sc_qr = qec->sc_regs;
227
228 sc->sc_channel = prom_getpropint(node, "channel#", -1);
229 sc->sc_burst = qec->sc_burst;
230
231 qestop(sc);
232
233 /* Note: no interrupt level passed */
234 (void)bus_intr_establish(sa->sa_bustag, 0, IPL_NET, qeintr, sc);
235 prom_getether(node, sc->sc_enaddr);
236
237 /*
238 * Allocate descriptor ring and buffers.
239 */
240
241 /* for now, allocate as many bufs as there are ring descriptors */
242 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE;
243 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE;
244
245 size = QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) +
246 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) +
247 sc->sc_rb.rb_ntbuf * QE_PKT_BUF_SZ +
248 sc->sc_rb.rb_nrbuf * QE_PKT_BUF_SZ;
249
250 /* Get a DMA handle */
251 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0,
252 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) {
253 aprint_error_dev(self, "DMA map create error %d\n",
254 error);
255 return;
256 }
257
258 /* Allocate DMA buffer */
259 if ((error = bus_dmamem_alloc(dmatag, size, 0, 0,
260 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
261 aprint_error_dev(self, "DMA buffer alloc error %d\n",
262 error);
263 return;
264 }
265
266 /* Map DMA buffer in CPU addressable space */
267 if ((error = bus_dmamem_map(dmatag, &seg, rseg, size,
268 &sc->sc_rb.rb_membase,
269 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
270 aprint_error_dev(self, "DMA buffer map error %d\n",
271 error);
272 bus_dmamem_free(dmatag, &seg, rseg);
273 return;
274 }
275
276 /* Load the buffer */
277 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap,
278 sc->sc_rb.rb_membase, size, NULL,
279 BUS_DMA_NOWAIT)) != 0) {
280 aprint_error_dev(self, "DMA buffer map load error %d\n",
281 error);
282 bus_dmamem_unmap(dmatag, sc->sc_rb.rb_membase, size);
283 bus_dmamem_free(dmatag, &seg, rseg);
284 return;
285 }
286 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr;
287
288 /* Initialize media properties */
289 ifmedia_init(&sc->sc_ifmedia, 0, qe_ifmedia_upd, qe_ifmedia_sts);
290 ifmedia_add(&sc->sc_ifmedia,
291 IFM_MAKEWORD(IFM_ETHER,IFM_10_T,0,0),
292 0, NULL);
293 ifmedia_add(&sc->sc_ifmedia,
294 IFM_MAKEWORD(IFM_ETHER,IFM_10_5,0,0),
295 0, NULL);
296 ifmedia_add(&sc->sc_ifmedia,
297 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,0),
298 0, NULL);
299 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO);
300
301 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ);
302 ifp->if_softc = sc;
303 ifp->if_start = qestart;
304 ifp->if_ioctl = qeioctl;
305 ifp->if_watchdog = qewatchdog;
306 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS |
307 IFF_MULTICAST;
308 IFQ_SET_READY(&ifp->if_snd);
309
310 /* Attach the interface. */
311 if_attach(ifp);
312 ether_ifattach(ifp, sc->sc_enaddr);
313
314 printf(" address %s\n", ether_sprintf(sc->sc_enaddr));
315 }
316
317 /*
318 * Pull data off an interface.
319 * Len is the length of data, with local net header stripped.
320 * We copy the data into mbufs. When full cluster sized units are present,
321 * we copy into clusters.
322 */
323 static inline struct mbuf *
qe_get(struct qe_softc * sc,int idx,int totlen)324 qe_get(struct qe_softc *sc, int idx, int totlen)
325 {
326 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
327 struct mbuf *m;
328 struct mbuf *top, **mp;
329 int len, pad, boff = 0;
330 uint8_t *bp;
331
332 bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * QE_PKT_BUF_SZ;
333
334 MGETHDR(m, M_DONTWAIT, MT_DATA);
335 if (m == NULL)
336 return (NULL);
337 m_set_rcvif(m, ifp);
338 m->m_pkthdr.len = totlen;
339 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header);
340 m->m_data += pad;
341 len = MHLEN - pad;
342 top = NULL;
343 mp = ⊤
344
345 while (totlen > 0) {
346 if (top) {
347 MGET(m, M_DONTWAIT, MT_DATA);
348 if (m == NULL) {
349 m_freem(top);
350 return (NULL);
351 }
352 len = MLEN;
353 }
354 if (top && totlen >= MINCLSIZE) {
355 MCLGET(m, M_DONTWAIT);
356 if (m->m_flags & M_EXT)
357 len = MCLBYTES;
358 }
359 m->m_len = len = min(totlen, len);
360 memcpy(mtod(m, void *), bp + boff, len);
361 boff += len;
362 totlen -= len;
363 *mp = m;
364 mp = &m->m_next;
365 }
366
367 return (top);
368 }
369
370 /*
371 * Routine to copy from mbuf chain to transmit buffer in
372 * network buffer memory.
373 */
374 inline int
qe_put(struct qe_softc * sc,int idx,struct mbuf * m)375 qe_put(struct qe_softc *sc, int idx, struct mbuf *m)
376 {
377 struct mbuf *n;
378 int len, tlen = 0, boff = 0;
379 uint8_t *bp;
380
381 bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * QE_PKT_BUF_SZ;
382
383 for (; m; m = n) {
384 len = m->m_len;
385 if (len == 0) {
386 MFREE(m, n);
387 continue;
388 }
389 memcpy(bp + boff, mtod(m, void *), len);
390 boff += len;
391 tlen += len;
392 MFREE(m, n);
393 }
394 return (tlen);
395 }
396
397 /*
398 * Pass a packet to the higher levels.
399 */
400 inline void
qe_read(struct qe_softc * sc,int idx,int len)401 qe_read(struct qe_softc *sc, int idx, int len)
402 {
403 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
404 struct mbuf *m;
405
406 if (len <= sizeof(struct ether_header) ||
407 len > ETHERMTU + sizeof(struct ether_header)) {
408
409 printf("%s: invalid packet size %d; dropping\n",
410 ifp->if_xname, len);
411
412 ifp->if_ierrors++;
413 return;
414 }
415
416 /*
417 * Pull packet off interface.
418 */
419 m = qe_get(sc, idx, len);
420 if (m == NULL) {
421 ifp->if_ierrors++;
422 return;
423 }
424 ifp->if_ipackets++;
425
426 /*
427 * Check if there's a BPF listener on this interface.
428 * If so, hand off the raw packet to BPF.
429 */
430 bpf_mtap(ifp, m);
431 /* Pass the packet up. */
432 if_percpuq_enqueue(ifp->if_percpuq, m);
433 }
434
435 /*
436 * Start output on interface.
437 * We make two assumptions here:
438 * 1) that the current priority is set to splnet _before_ this code
439 * is called *and* is returned to the appropriate priority after
440 * return
441 * 2) that the IFF_OACTIVE flag is checked before this code is called
442 * (i.e. that the output part of the interface is idle)
443 */
444 void
qestart(struct ifnet * ifp)445 qestart(struct ifnet *ifp)
446 {
447 struct qe_softc *sc = ifp->if_softc;
448 struct qec_xd *txd = sc->sc_rb.rb_txd;
449 struct mbuf *m;
450 unsigned int bix, len;
451 unsigned int ntbuf = sc->sc_rb.rb_ntbuf;
452
453 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
454 return;
455
456 bix = sc->sc_rb.rb_tdhead;
457
458 for (;;) {
459 IFQ_DEQUEUE(&ifp->if_snd, m);
460 if (m == 0)
461 break;
462
463 /*
464 * If BPF is listening on this interface, let it see the
465 * packet before we commit it to the wire.
466 */
467 bpf_mtap(ifp, m);
468
469 /*
470 * Copy the mbuf chain into the transmit buffer.
471 */
472 len = qe_put(sc, bix, m);
473
474 /*
475 * Initialize transmit registers and start transmission
476 */
477 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP |
478 (len & QEC_XD_LENGTH);
479 bus_space_write_4(sc->sc_bustag, sc->sc_cr, QE_CRI_CTRL,
480 QE_CR_CTRL_TWAKEUP);
481
482 if (++bix == QEC_XD_RING_MAXSIZE)
483 bix = 0;
484
485 if (++sc->sc_rb.rb_td_nbusy == ntbuf) {
486 ifp->if_flags |= IFF_OACTIVE;
487 break;
488 }
489 }
490
491 sc->sc_rb.rb_tdhead = bix;
492 }
493
494 void
qestop(struct qe_softc * sc)495 qestop(struct qe_softc *sc)
496 {
497 bus_space_tag_t t = sc->sc_bustag;
498 bus_space_handle_t mr = sc->sc_mr;
499 bus_space_handle_t cr = sc->sc_cr;
500 int n;
501
502 #if defined(SUN4U) || defined(__GNUC__)
503 (void)&t;
504 #endif
505 /* Stop the schwurst */
506 bus_space_write_1(t, mr, QE_MRI_BIUCC, QE_MR_BIUCC_SWRST);
507 for (n = 200; n > 0; n--) {
508 if ((bus_space_read_1(t, mr, QE_MRI_BIUCC) &
509 QE_MR_BIUCC_SWRST) == 0)
510 break;
511 DELAY(20);
512 }
513
514 /* then reset */
515 bus_space_write_4(t, cr, QE_CRI_CTRL, QE_CR_CTRL_RESET);
516 for (n = 200; n > 0; n--) {
517 if ((bus_space_read_4(t, cr, QE_CRI_CTRL) &
518 QE_CR_CTRL_RESET) == 0)
519 break;
520 DELAY(20);
521 }
522 }
523
524 /*
525 * Reset interface.
526 */
527 void
qereset(struct qe_softc * sc)528 qereset(struct qe_softc *sc)
529 {
530 int s;
531
532 s = splnet();
533 qestop(sc);
534 qeinit(sc);
535 splx(s);
536 }
537
538 void
qewatchdog(struct ifnet * ifp)539 qewatchdog(struct ifnet *ifp)
540 {
541 struct qe_softc *sc = ifp->if_softc;
542
543 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev));
544 ifp->if_oerrors++;
545
546 qereset(sc);
547 }
548
549 /*
550 * Interrupt dispatch.
551 */
552 int
qeintr(void * arg)553 qeintr(void *arg)
554 {
555 struct qe_softc *sc = arg;
556 bus_space_tag_t t = sc->sc_bustag;
557 uint32_t qecstat, qestat;
558 int r = 0;
559
560 #if defined(SUN4U) || defined(__GNUC__)
561 (void)&t;
562 #endif
563 /* Read QEC status and channel status */
564 qecstat = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT);
565 #ifdef QEDEBUG
566 if (sc->sc_debug) {
567 printf("qe%d: intr: qecstat=%x\n", sc->sc_channel, qecstat);
568 }
569 #endif
570
571 /* Filter out status for this channel */
572 qecstat = qecstat >> (4 * sc->sc_channel);
573 if ((qecstat & 0xf) == 0)
574 return (r);
575
576 qestat = bus_space_read_4(t, sc->sc_cr, QE_CRI_STAT);
577
578 #ifdef QEDEBUG
579 if (sc->sc_debug) {
580 char bits[64]; int i;
581 bus_space_tag_t t1 = sc->sc_bustag;
582 bus_space_handle_t mr = sc->sc_mr;
583
584 snprintb(bits, sizeof(bits), QE_CR_STAT_BITS, qestat);
585 printf("qe%d: intr: qestat=%s\n", sc->sc_channel, bits);
586
587 printf("MACE registers:\n");
588 for (i = 0 ; i < 32; i++) {
589 printf(" m[%d]=%x,", i, bus_space_read_1(t1, mr, i));
590 if (((i+1) & 7) == 0)
591 printf("\n");
592 }
593 }
594 #endif
595
596 if (qestat & QE_CR_STAT_ALLERRORS) {
597 #ifdef QEDEBUG
598 if (sc->sc_debug) {
599 char bits[64];
600 snprintb(bits, sizeof(bits), QE_CR_STAT_BITS, qestat);
601 printf("qe%d: eint: qestat=%s\n", sc->sc_channel, bits);
602 }
603 #endif
604 r |= qe_eint(sc, qestat);
605 if (r == -1)
606 return (1);
607 }
608
609 if (qestat & QE_CR_STAT_TXIRQ)
610 r |= qe_tint(sc);
611
612 if (qestat & QE_CR_STAT_RXIRQ)
613 r |= qe_rint(sc);
614
615 return (r);
616 }
617
618 /*
619 * Transmit interrupt.
620 */
621 int
qe_tint(struct qe_softc * sc)622 qe_tint(struct qe_softc *sc)
623 {
624 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
625 unsigned int bix, txflags;
626
627 bix = sc->sc_rb.rb_tdtail;
628
629 for (;;) {
630 if (sc->sc_rb.rb_td_nbusy <= 0)
631 break;
632
633 txflags = sc->sc_rb.rb_txd[bix].xd_flags;
634
635 if (txflags & QEC_XD_OWN)
636 break;
637
638 ifp->if_flags &= ~IFF_OACTIVE;
639 ifp->if_opackets++;
640
641 if (++bix == QEC_XD_RING_MAXSIZE)
642 bix = 0;
643
644 --sc->sc_rb.rb_td_nbusy;
645 }
646
647 sc->sc_rb.rb_tdtail = bix;
648
649 qestart(ifp);
650
651 if (sc->sc_rb.rb_td_nbusy == 0)
652 ifp->if_timer = 0;
653
654 return (1);
655 }
656
657 /*
658 * Receive interrupt.
659 */
660 int
qe_rint(struct qe_softc * sc)661 qe_rint(struct qe_softc *sc)
662 {
663 struct qec_xd *xd = sc->sc_rb.rb_rxd;
664 unsigned int bix, len;
665 unsigned int nrbuf = sc->sc_rb.rb_nrbuf;
666 #ifdef QEDEBUG
667 int npackets = 0;
668 #endif
669
670 bix = sc->sc_rb.rb_rdtail;
671
672 /*
673 * Process all buffers with valid data.
674 */
675 for (;;) {
676 len = xd[bix].xd_flags;
677 if (len & QEC_XD_OWN)
678 break;
679
680 #ifdef QEDEBUG
681 npackets++;
682 #endif
683
684 len &= QEC_XD_LENGTH;
685 len -= 4;
686 qe_read(sc, bix, len);
687
688 /* ... */
689 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags =
690 QEC_XD_OWN | (QE_PKT_BUF_SZ & QEC_XD_LENGTH);
691
692 if (++bix == QEC_XD_RING_MAXSIZE)
693 bix = 0;
694 }
695 #ifdef QEDEBUG
696 if (npackets == 0 && sc->sc_debug)
697 printf("%s: rint: no packets; rb index %d; status 0x%x\n",
698 device_xname(sc->sc_dev), bix, len);
699 #endif
700
701 sc->sc_rb.rb_rdtail = bix;
702
703 return (1);
704 }
705
706 /*
707 * Error interrupt.
708 */
709 int
qe_eint(struct qe_softc * sc,uint32_t why)710 qe_eint(struct qe_softc *sc, uint32_t why)
711 {
712 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
713 device_t self = sc->sc_dev;
714 const char *xname = device_xname(self);
715 int r = 0, rst = 0;
716
717 if (why & QE_CR_STAT_EDEFER) {
718 printf("%s: excessive tx defers.\n", xname);
719 r |= 1;
720 ifp->if_oerrors++;
721 }
722
723 if (why & QE_CR_STAT_CLOSS) {
724 printf("%s: no carrier, link down?\n", xname);
725 ifp->if_oerrors++;
726 r |= 1;
727 }
728
729 if (why & QE_CR_STAT_ERETRIES) {
730 printf("%s: excessive tx retries\n", xname);
731 ifp->if_oerrors++;
732 r |= 1;
733 rst = 1;
734 }
735
736
737 if (why & QE_CR_STAT_LCOLL) {
738 printf("%s: late tx transmission\n", xname);
739 ifp->if_oerrors++;
740 r |= 1;
741 rst = 1;
742 }
743
744 if (why & QE_CR_STAT_FUFLOW) {
745 printf("%s: tx fifo underflow\n", xname);
746 ifp->if_oerrors++;
747 r |= 1;
748 rst = 1;
749 }
750
751 if (why & QE_CR_STAT_JERROR) {
752 printf("%s: jabber seen\n", xname);
753 r |= 1;
754 }
755
756 if (why & QE_CR_STAT_BERROR) {
757 printf("%s: babble seen\n", xname);
758 r |= 1;
759 }
760
761 if (why & QE_CR_STAT_TCCOFLOW) {
762 ifp->if_collisions += 256;
763 ifp->if_oerrors += 256;
764 r |= 1;
765 }
766
767 if (why & QE_CR_STAT_TXDERROR) {
768 printf("%s: tx descriptor is bad\n", xname);
769 rst = 1;
770 r |= 1;
771 }
772
773 if (why & QE_CR_STAT_TXLERR) {
774 printf("%s: tx late error\n", xname);
775 ifp->if_oerrors++;
776 rst = 1;
777 r |= 1;
778 }
779
780 if (why & QE_CR_STAT_TXPERR) {
781 printf("%s: tx DMA parity error\n", xname);
782 ifp->if_oerrors++;
783 rst = 1;
784 r |= 1;
785 }
786
787 if (why & QE_CR_STAT_TXSERR) {
788 printf("%s: tx DMA sbus error ack\n", xname);
789 ifp->if_oerrors++;
790 rst = 1;
791 r |= 1;
792 }
793
794 if (why & QE_CR_STAT_RCCOFLOW) {
795 ifp->if_collisions += 256;
796 ifp->if_ierrors += 256;
797 r |= 1;
798 }
799
800 if (why & QE_CR_STAT_RUOFLOW) {
801 ifp->if_ierrors += 256;
802 r |= 1;
803 }
804
805 if (why & QE_CR_STAT_MCOFLOW) {
806 ifp->if_ierrors += 256;
807 r |= 1;
808 }
809
810 if (why & QE_CR_STAT_RXFOFLOW) {
811 printf("%s: rx fifo overflow\n", xname);
812 ifp->if_ierrors++;
813 r |= 1;
814 }
815
816 if (why & QE_CR_STAT_RLCOLL) {
817 printf("%s: rx late collision\n", xname);
818 ifp->if_ierrors++;
819 ifp->if_collisions++;
820 r |= 1;
821 }
822
823 if (why & QE_CR_STAT_FCOFLOW) {
824 ifp->if_ierrors += 256;
825 r |= 1;
826 }
827
828 if (why & QE_CR_STAT_CECOFLOW) {
829 ifp->if_ierrors += 256;
830 r |= 1;
831 }
832
833 if (why & QE_CR_STAT_RXDROP) {
834 printf("%s: rx packet dropped\n", xname);
835 ifp->if_ierrors++;
836 r |= 1;
837 }
838
839 if (why & QE_CR_STAT_RXSMALL) {
840 printf("%s: rx buffer too small\n", xname);
841 ifp->if_ierrors++;
842 r |= 1;
843 rst = 1;
844 }
845
846 if (why & QE_CR_STAT_RXLERR) {
847 printf("%s: rx late error\n", xname);
848 ifp->if_ierrors++;
849 r |= 1;
850 rst = 1;
851 }
852
853 if (why & QE_CR_STAT_RXPERR) {
854 printf("%s: rx DMA parity error\n", xname);
855 ifp->if_ierrors++;
856 r |= 1;
857 rst = 1;
858 }
859
860 if (why & QE_CR_STAT_RXSERR) {
861 printf("%s: rx DMA sbus error ack\n", xname);
862 ifp->if_ierrors++;
863 r |= 1;
864 rst = 1;
865 }
866
867 if (r == 0)
868 aprint_error_dev(self, "unexpected interrupt error: %08x\n",
869 why);
870
871 if (rst) {
872 printf("%s: resetting...\n", xname);
873 qereset(sc);
874 return (-1);
875 }
876
877 return (r);
878 }
879
880 int
qeioctl(struct ifnet * ifp,u_long cmd,void * data)881 qeioctl(struct ifnet *ifp, u_long cmd, void *data)
882 {
883 struct qe_softc *sc = ifp->if_softc;
884 struct ifaddr *ifa = data;
885 struct ifreq *ifr = data;
886 int s, error = 0;
887
888 s = splnet();
889
890 switch (cmd) {
891 case SIOCINITIFADDR:
892 ifp->if_flags |= IFF_UP;
893 qeinit(sc);
894 switch (ifa->ifa_addr->sa_family) {
895 #ifdef INET
896 case AF_INET:
897 arp_ifinit(ifp, ifa);
898 break;
899 #endif /* INET */
900 default:
901 break;
902 }
903 break;
904
905 case SIOCSIFFLAGS:
906 if ((error = ifioctl_common(ifp, cmd, data)) != 0)
907 break;
908 /* XXX re-use ether_ioctl() */
909 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) {
910 case IFF_RUNNING:
911 /*
912 * If interface is marked down and it is running, then
913 * stop it.
914 */
915 qestop(sc);
916 ifp->if_flags &= ~IFF_RUNNING;
917 break;
918 case IFF_UP:
919 /*
920 * If interface is marked up and it is stopped, then
921 * start it.
922 */
923 qeinit(sc);
924 break;
925 default:
926 /*
927 * Reset the interface to pick up changes in any other
928 * flags that affect hardware registers.
929 */
930 qestop(sc);
931 qeinit(sc);
932 break;
933 }
934 #ifdef QEDEBUG
935 sc->sc_debug = (ifp->if_flags & IFF_DEBUG) != 0 ? 1 : 0;
936 #endif
937 break;
938
939 case SIOCADDMULTI:
940 case SIOCDELMULTI:
941 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) {
942 /*
943 * Multicast list has changed; set the hardware filter
944 * accordingly.
945 */
946 if (ifp->if_flags & IFF_RUNNING)
947 qe_mcreset(sc);
948 error = 0;
949 }
950 break;
951
952 case SIOCGIFMEDIA:
953 case SIOCSIFMEDIA:
954 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, cmd);
955 break;
956
957 default:
958 error = ether_ioctl(ifp, cmd, data);
959 break;
960 }
961
962 splx(s);
963 return (error);
964 }
965
966
967 void
qeinit(struct qe_softc * sc)968 qeinit(struct qe_softc *sc)
969 {
970 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
971 bus_space_tag_t t = sc->sc_bustag;
972 bus_space_handle_t cr = sc->sc_cr;
973 bus_space_handle_t mr = sc->sc_mr;
974 struct qec_softc *qec = sc->sc_qec;
975 uint32_t qecaddr;
976 uint8_t *ea;
977 int s;
978
979 #if defined(SUN4U) || defined(__GNUC__)
980 (void)&t;
981 #endif
982 s = splnet();
983
984 qestop(sc);
985
986 /*
987 * Allocate descriptor ring and buffers
988 */
989 qec_meminit(&sc->sc_rb, QE_PKT_BUF_SZ);
990
991 /* Channel registers: */
992 bus_space_write_4(t, cr, QE_CRI_RXDS, (uint32_t)sc->sc_rb.rb_rxddma);
993 bus_space_write_4(t, cr, QE_CRI_TXDS, (uint32_t)sc->sc_rb.rb_txddma);
994
995 bus_space_write_4(t, cr, QE_CRI_RIMASK, 0);
996 bus_space_write_4(t, cr, QE_CRI_TIMASK, 0);
997 bus_space_write_4(t, cr, QE_CRI_QMASK, 0);
998 bus_space_write_4(t, cr, QE_CRI_MMASK, QE_CR_MMASK_RXCOLL);
999 bus_space_write_4(t, cr, QE_CRI_CCNT, 0);
1000 bus_space_write_4(t, cr, QE_CRI_PIPG, 0);
1001
1002 qecaddr = sc->sc_channel * qec->sc_msize;
1003 bus_space_write_4(t, cr, QE_CRI_RXWBUF, qecaddr);
1004 bus_space_write_4(t, cr, QE_CRI_RXRBUF, qecaddr);
1005 bus_space_write_4(t, cr, QE_CRI_TXWBUF, qecaddr + qec->sc_rsize);
1006 bus_space_write_4(t, cr, QE_CRI_TXRBUF, qecaddr + qec->sc_rsize);
1007
1008 /* MACE registers: */
1009 bus_space_write_1(t, mr, QE_MRI_PHYCC, QE_MR_PHYCC_ASEL);
1010 bus_space_write_1(t, mr, QE_MRI_XMTFC, QE_MR_XMTFC_APADXMT);
1011 bus_space_write_1(t, mr, QE_MRI_RCVFC, 0);
1012
1013 /*
1014 * Mask MACE's receive interrupt, since we're being notified
1015 * by the QEC after DMA completes.
1016 */
1017 bus_space_write_1(t, mr, QE_MRI_IMR,
1018 QE_MR_IMR_CERRM | QE_MR_IMR_RCVINTM);
1019
1020 bus_space_write_1(t, mr, QE_MRI_BIUCC,
1021 QE_MR_BIUCC_BSWAP | QE_MR_BIUCC_64TS);
1022
1023 bus_space_write_1(t, mr, QE_MRI_FIFOFC,
1024 QE_MR_FIFOCC_TXF16 | QE_MR_FIFOCC_RXF32 |
1025 QE_MR_FIFOCC_RFWU | QE_MR_FIFOCC_TFWU);
1026
1027 bus_space_write_1(t, mr, QE_MRI_PLSCC, QE_MR_PLSCC_TP);
1028
1029 /*
1030 * Station address
1031 */
1032 ea = sc->sc_enaddr;
1033 bus_space_write_1(t, mr, QE_MRI_IAC,
1034 QE_MR_IAC_ADDRCHG | QE_MR_IAC_PHYADDR);
1035 bus_space_write_multi_1(t, mr, QE_MRI_PADR, ea, 6);
1036
1037 /* Apply media settings */
1038 qe_ifmedia_upd(ifp);
1039
1040 /*
1041 * Clear Logical address filter
1042 */
1043 bus_space_write_1(t, mr, QE_MRI_IAC,
1044 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR);
1045 bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0, 8);
1046 bus_space_write_1(t, mr, QE_MRI_IAC, 0);
1047
1048 /* Clear missed packet count (register cleared on read) */
1049 (void)bus_space_read_1(t, mr, QE_MRI_MPC);
1050
1051 #if 0
1052 /* test register: */
1053 bus_space_write_1(t, mr, QE_MRI_UTR, 0);
1054 #endif
1055
1056 /* Reset multicast filter */
1057 qe_mcreset(sc);
1058
1059 ifp->if_flags |= IFF_RUNNING;
1060 ifp->if_flags &= ~IFF_OACTIVE;
1061 splx(s);
1062 }
1063
1064 /*
1065 * Reset multicast filter.
1066 */
1067 void
qe_mcreset(struct qe_softc * sc)1068 qe_mcreset(struct qe_softc *sc)
1069 {
1070 struct ethercom *ec = &sc->sc_ethercom;
1071 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1072 bus_space_tag_t t = sc->sc_bustag;
1073 bus_space_handle_t mr = sc->sc_mr;
1074 struct ether_multi *enm;
1075 struct ether_multistep step;
1076 uint32_t crc;
1077 uint16_t hash[4];
1078 uint8_t octet, maccc, *ladrp = (uint8_t *)&hash[0];
1079 int i;
1080
1081 #if defined(SUN4U) || defined(__GNUC__)
1082 (void)&t;
1083 #endif
1084
1085 /* We also enable transmitter & receiver here */
1086 maccc = QE_MR_MACCC_ENXMT | QE_MR_MACCC_ENRCV;
1087
1088 if (ifp->if_flags & IFF_PROMISC) {
1089 maccc |= QE_MR_MACCC_PROM;
1090 bus_space_write_1(t, mr, QE_MRI_MACCC, maccc);
1091 return;
1092 }
1093
1094 if (ifp->if_flags & IFF_ALLMULTI) {
1095 bus_space_write_1(t, mr, QE_MRI_IAC,
1096 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR);
1097 bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0xff, 8);
1098 bus_space_write_1(t, mr, QE_MRI_IAC, 0);
1099 bus_space_write_1(t, mr, QE_MRI_MACCC, maccc);
1100 return;
1101 }
1102
1103 hash[3] = hash[2] = hash[1] = hash[0] = 0;
1104
1105 ETHER_FIRST_MULTI(step, ec, enm);
1106 while (enm != NULL) {
1107 if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
1108 ETHER_ADDR_LEN) != 0) {
1109 /*
1110 * We must listen to a range of multicast
1111 * addresses. For now, just accept all
1112 * multicasts, rather than trying to set only
1113 * those filter bits needed to match the range.
1114 * (At this time, the only use of address
1115 * ranges is for IP multicast routing, for
1116 * which the range is big enough to require
1117 * all bits set.)
1118 */
1119 bus_space_write_1(t, mr, QE_MRI_IAC,
1120 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR);
1121 bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0xff, 8);
1122 bus_space_write_1(t, mr, QE_MRI_IAC, 0);
1123 ifp->if_flags |= IFF_ALLMULTI;
1124 break;
1125 }
1126
1127 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN);
1128 crc >>= 26;
1129 hash[crc >> 4] |= 1 << (crc & 0xf);
1130 ETHER_NEXT_MULTI(step, enm);
1131 }
1132
1133 /* We need to byte-swap the hash before writing to the chip. */
1134 for (i = 0; i < 7; i += 2) {
1135 octet = ladrp[i];
1136 ladrp[i] = ladrp[i + 1];
1137 ladrp[i + 1] = octet;
1138 }
1139 bus_space_write_1(t, mr, QE_MRI_IAC,
1140 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR);
1141 bus_space_write_multi_1(t, mr, QE_MRI_LADRF, ladrp, 8);
1142 bus_space_write_1(t, mr, QE_MRI_IAC, 0);
1143 bus_space_write_1(t, mr, QE_MRI_MACCC, maccc);
1144 }
1145
1146 /*
1147 * Get current media settings.
1148 */
1149 void
qe_ifmedia_sts(struct ifnet * ifp,struct ifmediareq * ifmr)1150 qe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1151 {
1152 struct qe_softc *sc = ifp->if_softc;
1153 bus_space_tag_t t = sc->sc_bustag;
1154 bus_space_handle_t mr = sc->sc_mr;
1155 uint8_t v;
1156
1157 #if defined(SUN4U) || defined(__GNUC__)
1158 (void)&t;
1159 #endif
1160 v = bus_space_read_1(t, mr, QE_MRI_PLSCC);
1161
1162 switch (bus_space_read_1(t, mr, QE_MRI_PLSCC) & QE_MR_PLSCC_PORTMASK) {
1163 case QE_MR_PLSCC_TP:
1164 ifmr->ifm_active = IFM_ETHER | IFM_10_T;
1165 break;
1166 case QE_MR_PLSCC_AUI:
1167 ifmr->ifm_active = IFM_ETHER | IFM_10_5;
1168 break;
1169 case QE_MR_PLSCC_GPSI:
1170 case QE_MR_PLSCC_DAI:
1171 /* ... */
1172 break;
1173 }
1174
1175 v = bus_space_read_1(t, mr, QE_MRI_PHYCC);
1176 ifmr->ifm_status |= IFM_AVALID;
1177 if ((v & QE_MR_PHYCC_LNKFL) != 0)
1178 ifmr->ifm_status &= ~IFM_ACTIVE;
1179 else
1180 ifmr->ifm_status |= IFM_ACTIVE;
1181
1182 }
1183
1184 /*
1185 * Set media options.
1186 */
1187 int
qe_ifmedia_upd(struct ifnet * ifp)1188 qe_ifmedia_upd(struct ifnet *ifp)
1189 {
1190 struct qe_softc *sc = ifp->if_softc;
1191 struct ifmedia *ifm = &sc->sc_ifmedia;
1192 bus_space_tag_t t = sc->sc_bustag;
1193 bus_space_handle_t mr = sc->sc_mr;
1194 int newmedia = ifm->ifm_media;
1195 uint8_t plscc, phycc;
1196
1197 #if defined(SUN4U) || defined(__GNUC__)
1198 (void)&t;
1199 #endif
1200 if (IFM_TYPE(newmedia) != IFM_ETHER)
1201 return (EINVAL);
1202
1203 plscc = bus_space_read_1(t, mr, QE_MRI_PLSCC) & ~QE_MR_PLSCC_PORTMASK;
1204 phycc = bus_space_read_1(t, mr, QE_MRI_PHYCC) & ~QE_MR_PHYCC_ASEL;
1205
1206 if (IFM_SUBTYPE(newmedia) == IFM_AUTO)
1207 phycc |= QE_MR_PHYCC_ASEL;
1208 else if (IFM_SUBTYPE(newmedia) == IFM_10_T)
1209 plscc |= QE_MR_PLSCC_TP;
1210 else if (IFM_SUBTYPE(newmedia) == IFM_10_5)
1211 plscc |= QE_MR_PLSCC_AUI;
1212
1213 bus_space_write_1(t, mr, QE_MRI_PLSCC, plscc);
1214 bus_space_write_1(t, mr, QE_MRI_PHYCC, phycc);
1215
1216 return (0);
1217 }
1218