1 /*
2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 * $Id: ar5416_attach.c,v 1.4 2011/03/07 11:25:44 cegger Exp $
18 */
19 #include "opt_ah.h"
20
21 #include "ah.h"
22 #include "ah_internal.h"
23 #include "ah_devid.h"
24
25 #include "ah_eeprom_v14.h"
26
27 #include "ar5416/ar5416.h"
28 #include "ar5416/ar5416reg.h"
29 #include "ar5416/ar5416phy.h"
30
31 #include "ar5416/ar5416.ini"
32
33 static void ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore);
34 static void ar5416WriteIni(struct ath_hal *ah,
35 HAL_CHANNEL_INTERNAL *chan);
36 static void ar5416SpurMitigate(struct ath_hal *ah,
37 HAL_CHANNEL_INTERNAL *chan);
38
39 static void
ar5416AniSetup(struct ath_hal * ah)40 ar5416AniSetup(struct ath_hal *ah)
41 {
42 static const struct ar5212AniParams aniparams = {
43 .maxNoiseImmunityLevel = 4, /* levels 0..4 */
44 .totalSizeDesired = { -55, -55, -55, -55, -62 },
45 .coarseHigh = { -14, -14, -14, -14, -12 },
46 .coarseLow = { -64, -64, -64, -64, -70 },
47 .firpwr = { -78, -78, -78, -78, -80 },
48 .maxSpurImmunityLevel = 2,
49 .cycPwrThr1 = { 2, 4, 6 },
50 .maxFirstepLevel = 2, /* levels 0..2 */
51 .firstep = { 0, 4, 8 },
52 .ofdmTrigHigh = 500,
53 .ofdmTrigLow = 200,
54 .cckTrigHigh = 200,
55 .cckTrigLow = 100,
56 .rssiThrHigh = 40,
57 .rssiThrLow = 7,
58 .period = 100,
59 };
60 /* NB: ANI is not enabled yet */
61 ar5212AniAttach(ah, &aniparams, &aniparams, AH_FALSE);
62 }
63
64 /*
65 * Attach for an AR5416 part.
66 */
67 void
ar5416InitState(struct ath_hal_5416 * ahp5416,uint16_t devid,HAL_SOFTC sc,HAL_BUS_TAG st,HAL_BUS_HANDLE sh,HAL_STATUS * status)68 ar5416InitState(struct ath_hal_5416 *ahp5416, uint16_t devid, HAL_SOFTC sc,
69 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status)
70 {
71 struct ath_hal_5212 *ahp;
72 struct ath_hal *ah;
73
74 ahp = &ahp5416->ah_5212;
75 ar5212InitState(ahp, devid, sc, st, sh, status);
76 ah = &ahp->ah_priv.h;
77
78 /* override 5212 methods for our needs */
79 ah->ah_magic = AR5416_MAGIC;
80 ah->ah_getRateTable = ar5416GetRateTable;
81 ah->ah_detach = ar5416Detach;
82
83 /* Reset functions */
84 ah->ah_reset = ar5416Reset;
85 ah->ah_phyDisable = ar5416PhyDisable;
86 ah->ah_disable = ar5416Disable;
87 ah->ah_configPCIE = ar5416ConfigPCIE;
88 ah->ah_perCalibration = ar5416PerCalibration;
89 ah->ah_perCalibrationN = ar5416PerCalibrationN,
90 ah->ah_resetCalValid = ar5416ResetCalValid,
91 ah->ah_setTxPowerLimit = ar5416SetTxPowerLimit;
92 ah->ah_setTxPower = ar5416SetTransmitPower;
93 ah->ah_setBoardValues = ar5416SetBoardValues;
94
95 /* Transmit functions */
96 ah->ah_stopTxDma = ar5416StopTxDma;
97 ah->ah_setupTxDesc = ar5416SetupTxDesc;
98 ah->ah_setupXTxDesc = ar5416SetupXTxDesc;
99 ah->ah_fillTxDesc = ar5416FillTxDesc;
100 ah->ah_procTxDesc = ar5416ProcTxDesc;
101
102 /* Receive Functions */
103 ah->ah_startPcuReceive = ar5416StartPcuReceive;
104 ah->ah_stopPcuReceive = ar5416StopPcuReceive;
105 ah->ah_setupRxDesc = ar5416SetupRxDesc;
106 ah->ah_procRxDesc = ar5416ProcRxDesc;
107 ah->ah_rxMonitor = ar5416AniPoll,
108 ah->ah_procMibEvent = ar5416ProcessMibIntr,
109
110 /* Misc Functions */
111 ah->ah_getDiagState = ar5416GetDiagState;
112 ah->ah_setLedState = ar5416SetLedState;
113 ah->ah_gpioCfgOutput = ar5416GpioCfgOutput;
114 ah->ah_gpioCfgInput = ar5416GpioCfgInput;
115 ah->ah_gpioGet = ar5416GpioGet;
116 ah->ah_gpioSet = ar5416GpioSet;
117 ah->ah_gpioSetIntr = ar5416GpioSetIntr;
118 ah->ah_resetTsf = ar5416ResetTsf;
119 ah->ah_getRfGain = ar5416GetRfgain;
120 ah->ah_setAntennaSwitch = ar5416SetAntennaSwitch;
121 ah->ah_setDecompMask = ar5416SetDecompMask;
122 ah->ah_setCoverageClass = ar5416SetCoverageClass;
123
124 ah->ah_resetKeyCacheEntry = ar5416ResetKeyCacheEntry;
125 ah->ah_setKeyCacheEntry = ar5416SetKeyCacheEntry;
126
127 /* Power Management Functions */
128 ah->ah_setPowerMode = ar5416SetPowerMode;
129
130 /* Beacon Management Functions */
131 ah->ah_setBeaconTimers = ar5416SetBeaconTimers;
132 ah->ah_beaconInit = ar5416BeaconInit;
133 ah->ah_setStationBeaconTimers = ar5416SetStaBeaconTimers;
134 ah->ah_resetStationBeaconTimers = ar5416ResetStaBeaconTimers;
135
136 /* XXX 802.11n Functions */
137 #if 0
138 ah->ah_chainTxDesc = ar5416ChainTxDesc;
139 ah->ah_setupFirstTxDesc = ar5416SetupFirstTxDesc;
140 ah->ah_setupLastTxDesc = ar5416SetupLastTxDesc;
141 ah->ah_set11nRateScenario = ar5416Set11nRateScenario;
142 ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle;
143 ah->ah_clr11nAggr = ar5416Clr11nAggr;
144 ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration;
145 ah->ah_get11nExtBusy = ar5416Get11nExtBusy;
146 ah->ah_set11nMac2040 = ar5416Set11nMac2040;
147 ah->ah_get11nRxClear = ar5416Get11nRxClear;
148 ah->ah_set11nRxClear = ar5416Set11nRxClear;
149 #endif
150
151 /* Interrupt functions */
152 ah->ah_isInterruptPending = ar5416IsInterruptPending;
153 ah->ah_getPendingInterrupts = ar5416GetPendingInterrupts;
154 ah->ah_setInterrupts = ar5416SetInterrupts;
155
156 ahp->ah_priv.ah_getWirelessModes= ar5416GetWirelessModes;
157 ahp->ah_priv.ah_eepromRead = ar5416EepromRead;
158 #ifdef AH_SUPPORT_WRITE_EEPROM
159 ahp->ah_priv.ah_eepromWrite = ar5416EepromWrite;
160 #endif
161 ahp->ah_priv.ah_gpioCfgOutput = ar5416GpioCfgOutput;
162 ahp->ah_priv.ah_gpioCfgInput = ar5416GpioCfgInput;
163 ahp->ah_priv.ah_gpioGet = ar5416GpioGet;
164 ahp->ah_priv.ah_gpioSet = ar5416GpioSet;
165 ahp->ah_priv.ah_gpioSetIntr = ar5416GpioSetIntr;
166 ahp->ah_priv.ah_getChipPowerLimits = ar5416GetChipPowerLimits;
167
168 AH5416(ah)->ah_writeIni = ar5416WriteIni;
169 AH5416(ah)->ah_spurMitigate = ar5416SpurMitigate;
170 /*
171 * Start by setting all Owl devices to 2x2
172 */
173 AH5416(ah)->ah_rx_chainmask = AR5416_DEFAULT_RXCHAINMASK;
174 AH5416(ah)->ah_tx_chainmask = AR5416_DEFAULT_TXCHAINMASK;
175 }
176
177 uint32_t
ar5416GetRadioRev(struct ath_hal * ah)178 ar5416GetRadioRev(struct ath_hal *ah)
179 {
180 uint32_t val;
181 int i;
182
183 /* Read Radio Chip Rev Extract */
184 OS_REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
185 for (i = 0; i < 8; i++)
186 OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
187 val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
188 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
189 return ath_hal_reverseBits(val, 8);
190 }
191
192 /*
193 * Attach for an AR5416 part.
194 */
195 struct ath_hal *
ar5416Attach(uint16_t devid,HAL_SOFTC sc,HAL_BUS_TAG st,HAL_BUS_HANDLE sh,HAL_STATUS * status)196 ar5416Attach(uint16_t devid, HAL_SOFTC sc,
197 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status)
198 {
199 struct ath_hal_5416 *ahp5416;
200 struct ath_hal_5212 *ahp;
201 struct ath_hal *ah;
202 uint32_t val;
203 HAL_STATUS ecode;
204 HAL_BOOL rfStatus;
205
206 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
207 __func__, sc, (void*) st, (void*) sh);
208
209 /* NB: memory is returned zero'd */
210 ahp5416 = ath_hal_malloc(sizeof (struct ath_hal_5416) +
211 /* extra space for Owl 2.1/2.2 WAR */
212 sizeof(ar5416Addac)
213 );
214 if (ahp5416 == AH_NULL) {
215 HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
216 "%s: cannot allocate memory for state block\n", __func__);
217 *status = HAL_ENOMEM;
218 return AH_NULL;
219 }
220 ar5416InitState(ahp5416, devid, sc, st, sh, status);
221 ahp = &ahp5416->ah_5212;
222 ah = &ahp->ah_priv.h;
223
224 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {
225 /* reset chip */
226 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", __func__);
227 ecode = HAL_EIO;
228 goto bad;
229 }
230
231 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
232 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", __func__);
233 ecode = HAL_EIO;
234 goto bad;
235 }
236 /* Read Revisions from Chips before taking out of reset */
237 val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID;
238 AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S;
239 AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION;
240 AH_PRIVATE(ah)->ah_ispcie = (devid == AR5416_DEVID_PCIE);
241
242 /* setup common ini data; rf backends handle remainder */
243 HAL_INI_INIT(&ahp->ah_ini_modes, ar5416Modes, 6);
244 HAL_INI_INIT(&ahp->ah_ini_common, ar5416Common, 2);
245
246 HAL_INI_INIT(&AH5416(ah)->ah_ini_bb_rfgain, ar5416BB_RfGain, 3);
247 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank0, ar5416Bank0, 2);
248 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank1, ar5416Bank1, 2);
249 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank2, ar5416Bank2, 2);
250 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank3, ar5416Bank3, 3);
251 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank6, ar5416Bank6, 3);
252 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank7, ar5416Bank7, 2);
253 HAL_INI_INIT(&AH5416(ah)->ah_ini_addac, ar5416Addac, 2);
254
255 if (!IS_5416V2_2(ah)) { /* Owl 2.1/2.0 */
256 struct ini {
257 uint32_t *data; /* NB: !const */
258 int rows, cols;
259 };
260 /* override CLKDRV value */
261 OS_MEMCPY(&AH5416(ah)[1], ar5416Addac, sizeof(ar5416Addac));
262 AH5416(ah)->ah_ini_addac.data = (uint32_t *) &AH5416(ah)[1];
263 HAL_INI_VAL((struct ini *)&AH5416(ah)->ah_ini_addac, 31, 1) = 0;
264 }
265
266 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, ar5416PciePhy, 2);
267 ar5416AttachPCIE(ah);
268
269 ecode = ath_hal_v14EepromAttach(ah);
270 if (ecode != HAL_OK)
271 goto bad;
272
273 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */
274 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n",
275 __func__);
276 ecode = HAL_EIO;
277 goto bad;
278 }
279
280 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
281
282 if (!ar5212ChipTest(ah)) {
283 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
284 __func__);
285 ecode = HAL_ESELFTEST;
286 goto bad;
287 }
288
289 /*
290 * Set correct Baseband to analog shift
291 * setting to access analog chips.
292 */
293 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
294
295 /* Read Radio Chip Rev Extract */
296 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah);
297 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
298 case AR_RAD5122_SREV_MAJOR: /* Fowl: 5G/2x2 */
299 case AR_RAD2122_SREV_MAJOR: /* Fowl: 2+5G/2x2 */
300 case AR_RAD2133_SREV_MAJOR: /* Fowl: 2G/3x3 */
301 case AR_RAD5133_SREV_MAJOR: /* Fowl: 2+5G/3x3 */
302 break;
303 default:
304 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
305 /*
306 * When RF_Silen is used the analog chip is reset.
307 * So when the system boots with radio switch off
308 * the RF chip rev reads back as zero and we need
309 * to use the mac+phy revs to set the radio rev.
310 */
311 AH_PRIVATE(ah)->ah_analog5GhzRev =
312 AR_RAD5133_SREV_MAJOR;
313 break;
314 }
315 /* NB: silently accept anything in release code per Atheros */
316 #ifdef AH_DEBUG
317 HALDEBUG(ah, HAL_DEBUG_ANY,
318 "%s: 5G Radio Chip Rev 0x%02X is not supported by "
319 "this driver\n", __func__,
320 AH_PRIVATE(ah)->ah_analog5GhzRev);
321 ecode = HAL_ENOTSUPP;
322 goto bad;
323 #endif
324 }
325
326 /*
327 * Got everything we need now to setup the capabilities.
328 */
329 if (!ar5416FillCapabilityInfo(ah)) {
330 ecode = HAL_EEREAD;
331 goto bad;
332 }
333
334 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
335 if (ecode != HAL_OK) {
336 HALDEBUG(ah, HAL_DEBUG_ANY,
337 "%s: error getting mac address from EEPROM\n", __func__);
338 goto bad;
339 }
340 /* XXX How about the serial number ? */
341 /* Read Reg Domain */
342 AH_PRIVATE(ah)->ah_currentRD =
343 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL);
344
345 /*
346 * ah_miscMode is populated by ar5416FillCapabilityInfo()
347 * starting from griffin. Set here to make sure that
348 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is
349 * placed into hardware.
350 */
351 if (ahp->ah_miscMode != 0)
352 OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode);
353
354 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: Attaching AR2133 radio\n",
355 __func__);
356 rfStatus = ar2133RfAttach(ah, &ecode);
357 if (!rfStatus) {
358 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
359 __func__, ecode);
360 goto bad;
361 }
362
363 ar5416AniSetup(ah); /* Anti Noise Immunity */
364 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);
365
366 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
367
368 return ah;
369 bad:
370 if (ahp)
371 ar5416Detach((struct ath_hal *) ahp);
372 if (status)
373 *status = ecode;
374 return AH_NULL;
375 }
376
377 void
ar5416Detach(struct ath_hal * ah)378 ar5416Detach(struct ath_hal *ah)
379 {
380 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__);
381
382 HALASSERT(ah != AH_NULL);
383 HALASSERT(ah->ah_magic == AR5416_MAGIC);
384
385 ar5416AniDetach(ah);
386 ar5212RfDetach(ah);
387 ah->ah_disable(ah);
388 ar5416SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE);
389 ath_hal_eepromDetach(ah);
390 ath_hal_free(ah);
391 }
392
393 void
ar5416AttachPCIE(struct ath_hal * ah)394 ar5416AttachPCIE(struct ath_hal *ah)
395 {
396 if (AH_PRIVATE(ah)->ah_ispcie)
397 ath_hal_configPCIE(ah, AH_FALSE);
398 else
399 ath_hal_disablePCIE(ah);
400 }
401
402 static void
ar5416ConfigPCIE(struct ath_hal * ah,HAL_BOOL restore)403 ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore)
404 {
405 if (AH_PRIVATE(ah)->ah_ispcie && !restore) {
406 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0);
407 OS_DELAY(1000);
408 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
409 OS_REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
410 }
411 }
412
413 static void
ar5416WriteIni(struct ath_hal * ah,HAL_CHANNEL_INTERNAL * chan)414 ar5416WriteIni(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
415 {
416 u_int modesIndex, freqIndex;
417 int regWrites = 0;
418
419 /* Setup the indices for the next set of register array writes */
420 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */
421 if (IS_CHAN_2GHZ(chan)) {
422 freqIndex = 2;
423 if (IS_CHAN_HT40(chan))
424 modesIndex = 3;
425 else if (IS_CHAN_108G(chan))
426 modesIndex = 5;
427 else
428 modesIndex = 4;
429 } else {
430 freqIndex = 1;
431 if (IS_CHAN_HT40(chan) ||
432 IS_CHAN_TURBO(chan))
433 modesIndex = 2;
434 else
435 modesIndex = 1;
436 }
437
438 /* Set correct Baseband to analog shift setting to access analog chips. */
439 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
440
441 /*
442 * Write addac shifts
443 */
444 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
445 #if 0
446 /* NB: only required for Sowl */
447 ar5416EepromSetAddac(ah, chan);
448 #endif
449 regWrites = ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_addac, 1,
450 regWrites);
451 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
452
453 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes,
454 modesIndex, regWrites);
455 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common,
456 1, regWrites);
457
458 /* XXX updated regWrites? */
459 AH5212(ah)->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites);
460 }
461
462 /*
463 * Convert to baseband spur frequency given input channel frequency
464 * and compute register settings below.
465 */
466
467 static void
ar5416SpurMitigate(struct ath_hal * ah,HAL_CHANNEL_INTERNAL * chan)468 ar5416SpurMitigate(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
469 {
470 uint16_t freq = ath_hal_gethwchannel(ah, chan);
471 static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
472 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 };
473 static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
474 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 };
475 static const int inc[4] = { 0, 100, 0, 0 };
476
477 int bb_spur = AR_NO_SPUR;
478 int bin, cur_bin;
479 int spur_freq_sd;
480 int spur_delta_phase;
481 int denominator;
482 int upper, lower, cur_vit_mask;
483 int tmp, new;
484 int i;
485
486 int8_t mask_m[123];
487 int8_t mask_p[123];
488 int8_t mask_amt;
489 int tmp_mask;
490 int cur_bb_spur;
491 HAL_BOOL is2GHz = IS_CHAN_2GHZ(chan);
492
493 OS_MEMZERO(mask_m, sizeof(mask_m));
494 OS_MEMZERO(mask_p, sizeof(mask_p));
495
496 /*
497 * Need to verify range +/- 9.5 for static ht20, otherwise spur
498 * is out-of-band and can be ignored.
499 */
500 /* XXX ath9k changes */
501 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
502 cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz);
503 if (AR_NO_SPUR == cur_bb_spur)
504 break;
505 cur_bb_spur = cur_bb_spur - (freq * 10);
506 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
507 bb_spur = cur_bb_spur;
508 break;
509 }
510 }
511 if (AR_NO_SPUR == bb_spur)
512 return;
513
514 bin = bb_spur * 32;
515
516 tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0));
517 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
518 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
519 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
520 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
521
522 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), new);
523
524 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
525 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
526 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
527 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
528 SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
529 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, new);
530 /*
531 * Should offset bb_spur by +/- 10 MHz for dynamic 2040 MHz
532 * config, no offset for HT20.
533 * spur_delta_phase = bb_spur/40 * 2**21 for static ht20,
534 * /80 for dyn2040.
535 */
536 spur_delta_phase = ((bb_spur * 524288) / 100) &
537 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
538 /*
539 * in 11A mode the denominator of spur_freq_sd should be 40 and
540 * it should be 44 in 11G
541 */
542 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
543 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
544
545 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
546 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
547 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
548 OS_REG_WRITE(ah, AR_PHY_TIMING11, new);
549
550
551 /*
552 * ============================================
553 * pilot mask 1 [31:0] = +6..-26, no 0 bin
554 * pilot mask 2 [19:0] = +26..+7
555 *
556 * channel mask 1 [31:0] = +6..-26, no 0 bin
557 * channel mask 2 [19:0] = +26..+7
558 */
559 //cur_bin = -26;
560 cur_bin = -6000;
561 upper = bin + 100;
562 lower = bin - 100;
563
564 for (i = 0; i < 4; i++) {
565 int pilot_mask = 0;
566 int chan_mask = 0;
567 int bp = 0;
568 for (bp = 0; bp < 30; bp++) {
569 if ((cur_bin > lower) && (cur_bin < upper)) {
570 pilot_mask = pilot_mask | 0x1 << bp;
571 chan_mask = chan_mask | 0x1 << bp;
572 }
573 cur_bin += 100;
574 }
575 cur_bin += inc[i];
576 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
577 OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask);
578 }
579
580 /* =================================================
581 * viterbi mask 1 based on channel magnitude
582 * four levels 0-3
583 * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c)
584 * [1 2 2 1] for -9.6 or [1 2 1] for +16
585 * - enable_mask_ppm, all bins move with freq
586 *
587 * - mask_select, 8 bits for rates (reg 67,0x990c)
588 * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c)
589 * choose which mask to use mask or mask2
590 */
591
592 /*
593 * viterbi mask 2 2nd set for per data rate puncturing
594 * four levels 0-3
595 * - mask_select, 8 bits for rates (reg 67)
596 * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994)
597 * [1 2 2 1] for -9.6 or [1 2 1] for +16
598 */
599 cur_vit_mask = 6100;
600 upper = bin + 120;
601 lower = bin - 120;
602
603 for (i = 0; i < 123; i++) {
604 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
605 if ((abs(cur_vit_mask - bin)) < 75) {
606 mask_amt = 1;
607 } else {
608 mask_amt = 0;
609 }
610 if (cur_vit_mask < 0) {
611 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
612 } else {
613 mask_p[cur_vit_mask / 100] = mask_amt;
614 }
615 }
616 cur_vit_mask -= 100;
617 }
618
619 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
620 | (mask_m[48] << 26) | (mask_m[49] << 24)
621 | (mask_m[50] << 22) | (mask_m[51] << 20)
622 | (mask_m[52] << 18) | (mask_m[53] << 16)
623 | (mask_m[54] << 14) | (mask_m[55] << 12)
624 | (mask_m[56] << 10) | (mask_m[57] << 8)
625 | (mask_m[58] << 6) | (mask_m[59] << 4)
626 | (mask_m[60] << 2) | (mask_m[61] << 0);
627 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
628 OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
629
630 tmp_mask = (mask_m[31] << 28)
631 | (mask_m[32] << 26) | (mask_m[33] << 24)
632 | (mask_m[34] << 22) | (mask_m[35] << 20)
633 | (mask_m[36] << 18) | (mask_m[37] << 16)
634 | (mask_m[48] << 14) | (mask_m[39] << 12)
635 | (mask_m[40] << 10) | (mask_m[41] << 8)
636 | (mask_m[42] << 6) | (mask_m[43] << 4)
637 | (mask_m[44] << 2) | (mask_m[45] << 0);
638 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
639 OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
640
641 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
642 | (mask_m[18] << 26) | (mask_m[18] << 24)
643 | (mask_m[20] << 22) | (mask_m[20] << 20)
644 | (mask_m[22] << 18) | (mask_m[22] << 16)
645 | (mask_m[24] << 14) | (mask_m[24] << 12)
646 | (mask_m[25] << 10) | (mask_m[26] << 8)
647 | (mask_m[27] << 6) | (mask_m[28] << 4)
648 | (mask_m[29] << 2) | (mask_m[30] << 0);
649 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
650 OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
651
652 tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28)
653 | (mask_m[ 2] << 26) | (mask_m[ 3] << 24)
654 | (mask_m[ 4] << 22) | (mask_m[ 5] << 20)
655 | (mask_m[ 6] << 18) | (mask_m[ 7] << 16)
656 | (mask_m[ 8] << 14) | (mask_m[ 9] << 12)
657 | (mask_m[10] << 10) | (mask_m[11] << 8)
658 | (mask_m[12] << 6) | (mask_m[13] << 4)
659 | (mask_m[14] << 2) | (mask_m[15] << 0);
660 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
661 OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
662
663 tmp_mask = (mask_p[15] << 28)
664 | (mask_p[14] << 26) | (mask_p[13] << 24)
665 | (mask_p[12] << 22) | (mask_p[11] << 20)
666 | (mask_p[10] << 18) | (mask_p[ 9] << 16)
667 | (mask_p[ 8] << 14) | (mask_p[ 7] << 12)
668 | (mask_p[ 6] << 10) | (mask_p[ 5] << 8)
669 | (mask_p[ 4] << 6) | (mask_p[ 3] << 4)
670 | (mask_p[ 2] << 2) | (mask_p[ 1] << 0);
671 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
672 OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
673
674 tmp_mask = (mask_p[30] << 28)
675 | (mask_p[29] << 26) | (mask_p[28] << 24)
676 | (mask_p[27] << 22) | (mask_p[26] << 20)
677 | (mask_p[25] << 18) | (mask_p[24] << 16)
678 | (mask_p[23] << 14) | (mask_p[22] << 12)
679 | (mask_p[21] << 10) | (mask_p[20] << 8)
680 | (mask_p[19] << 6) | (mask_p[18] << 4)
681 | (mask_p[17] << 2) | (mask_p[16] << 0);
682 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
683 OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
684
685 tmp_mask = (mask_p[45] << 28)
686 | (mask_p[44] << 26) | (mask_p[43] << 24)
687 | (mask_p[42] << 22) | (mask_p[41] << 20)
688 | (mask_p[40] << 18) | (mask_p[39] << 16)
689 | (mask_p[38] << 14) | (mask_p[37] << 12)
690 | (mask_p[36] << 10) | (mask_p[35] << 8)
691 | (mask_p[34] << 6) | (mask_p[33] << 4)
692 | (mask_p[32] << 2) | (mask_p[31] << 0);
693 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
694 OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
695
696 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
697 | (mask_p[59] << 26) | (mask_p[58] << 24)
698 | (mask_p[57] << 22) | (mask_p[56] << 20)
699 | (mask_p[55] << 18) | (mask_p[54] << 16)
700 | (mask_p[53] << 14) | (mask_p[52] << 12)
701 | (mask_p[51] << 10) | (mask_p[50] << 8)
702 | (mask_p[49] << 6) | (mask_p[48] << 4)
703 | (mask_p[47] << 2) | (mask_p[46] << 0);
704 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
705 OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
706 }
707
708 /*
709 * Fill all software cached or static hardware state information.
710 * Return failure if capabilities are to come from EEPROM and
711 * cannot be read.
712 */
713 HAL_BOOL
ar5416FillCapabilityInfo(struct ath_hal * ah)714 ar5416FillCapabilityInfo(struct ath_hal *ah)
715 {
716 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
717 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps;
718 uint16_t val;
719
720 /* Construct wireless mode from EEPROM */
721 pCap->halWirelessModes = 0;
722 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) {
723 pCap->halWirelessModes |= HAL_MODE_11A
724 | HAL_MODE_11NA_HT20
725 | HAL_MODE_11NA_HT40PLUS
726 | HAL_MODE_11NA_HT40MINUS
727 ;
728 }
729 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE)) {
730 pCap->halWirelessModes |= HAL_MODE_11G
731 | HAL_MODE_11NG_HT20
732 | HAL_MODE_11NG_HT40PLUS
733 | HAL_MODE_11NG_HT40MINUS
734 ;
735 pCap->halWirelessModes |= HAL_MODE_11A
736 | HAL_MODE_11NA_HT20
737 | HAL_MODE_11NA_HT40PLUS
738 | HAL_MODE_11NA_HT40MINUS
739 ;
740 }
741
742 pCap->halLow2GhzChan = 2312;
743 pCap->halHigh2GhzChan = 2732;
744
745 pCap->halLow5GhzChan = 4915;
746 pCap->halHigh5GhzChan = 6100;
747
748 pCap->halCipherCkipSupport = AH_FALSE;
749 pCap->halCipherTkipSupport = AH_TRUE;
750 pCap->halCipherAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES);
751
752 pCap->halMicCkipSupport = AH_FALSE;
753 pCap->halMicTkipSupport = AH_TRUE;
754 pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES);
755 /*
756 * Starting with Griffin TX+RX mic keys can be combined
757 * in one key cache slot.
758 */
759 pCap->halTkipMicTxRxKeySupport = AH_TRUE;
760 pCap->halChanSpreadSupport = AH_TRUE;
761 pCap->halSleepAfterBeaconBroken = AH_TRUE;
762
763 pCap->halCompressSupport = AH_FALSE;
764 pCap->halBurstSupport = AH_TRUE;
765 pCap->halFastFramesSupport = AH_FALSE; /* XXX? */
766 pCap->halChapTuningSupport = AH_TRUE;
767 pCap->halTurboPrimeSupport = AH_TRUE;
768
769 pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G;
770
771 pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */
772 pCap->halVEOLSupport = AH_TRUE;
773 pCap->halBssIdMaskSupport = AH_TRUE;
774 pCap->halMcastKeySrchSupport = AH_FALSE;
775 pCap->halTsfAddSupport = AH_TRUE;
776
777 if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK)
778 pCap->halTotalQueues = val;
779 else
780 pCap->halTotalQueues = HAL_NUM_TX_QUEUES;
781
782 if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK)
783 pCap->halKeyCacheSize = val;
784 else
785 pCap->halKeyCacheSize = AR5416_KEYTABLE_SIZE;
786
787 /* XXX not needed */
788 pCap->halChanHalfRate = AH_FALSE; /* XXX ? */
789 pCap->halChanQuarterRate = AH_FALSE; /* XXX ? */
790
791 pCap->halTstampPrecision = 32;
792 pCap->halHwPhyCounterSupport = AH_TRUE;
793 pCap->halIntrMask = HAL_INT_COMMON
794 | HAL_INT_RX
795 | HAL_INT_TX
796 | HAL_INT_FATAL
797 | HAL_INT_BNR
798 | HAL_INT_BMISC
799 | HAL_INT_DTIMSYNC
800 | HAL_INT_TSFOOR
801 | HAL_INT_CST
802 | HAL_INT_GTT
803 ;
804
805 pCap->halFastCCSupport = AH_TRUE;
806 pCap->halNumGpioPins = 6;
807 pCap->halWowSupport = AH_FALSE;
808 pCap->halWowMatchPatternExact = AH_FALSE;
809 pCap->halBtCoexSupport = AH_FALSE; /* XXX need support */
810 pCap->halAutoSleepSupport = AH_FALSE;
811 #if 0 /* XXX not yet */
812 pCap->halNumAntCfg2GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_2GHZ);
813 pCap->halNumAntCfg5GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_5GHZ);
814 #endif
815 pCap->halHTSupport = AH_TRUE;
816 pCap->halTxChainMask = ath_hal_eepromGet(ah, AR_EEP_TXMASK, AH_NULL);
817 /* XXX CB71 uses GPIO 0 to indicate 3 rx chains */
818 pCap->halRxChainMask = ath_hal_eepromGet(ah, AR_EEP_RXMASK, AH_NULL);
819 pCap->halRtsAggrLimit = 8*1024; /* Owl 2.0 limit */
820 pCap->halMbssidAggrSupport = AH_TRUE;
821 pCap->halForcePpmSupport = AH_TRUE;
822 pCap->halEnhancedPmSupport = AH_TRUE;
823 pCap->halBssidMatchSupport = AH_TRUE;
824
825 if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) &&
826 ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) {
827 /* NB: enabled by default */
828 ahpriv->ah_rfkillEnabled = AH_TRUE;
829 pCap->halRfSilentSupport = AH_TRUE;
830 }
831
832 ahpriv->ah_rxornIsFatal = AH_FALSE;
833
834 return AH_TRUE;
835 }
836
837 static const char*
ar5416Probe(uint16_t vendorid,uint16_t devid)838 ar5416Probe(uint16_t vendorid, uint16_t devid)
839 {
840 if (vendorid == ATHEROS_VENDOR_ID &&
841 (devid == AR5416_DEVID_PCI || devid == AR5416_DEVID_PCIE))
842 return "Atheros 5416";
843 return AH_NULL;
844 }
845 AH_CHIP(AR5416, ar5416Probe, ar5416Attach);
846