1 /* 2 * Copyright (c) 2017, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_vdbox_vdenc_hwcmd_g10_X.h 24 //! \brief Auto-generated constructors for MHW and states. 25 //! \details This file may not be included outside of g10_X as other components 26 //! should use MHW interface to interact with MHW commands and states. 27 //! 28 #ifndef __MHW_VDBOX_VDENC_HWCMD_G10_X_H__ 29 #define __MHW_VDBOX_VDENC_HWCMD_G10_X_H__ 30 31 #pragma once 32 #pragma pack(1) 33 34 #include <cstdint> 35 #include <cstddef> 36 37 class mhw_vdbox_vdenc_g10_X 38 { 39 public: 40 // Internal Macros 41 #define __CODEGEN_MAX(_a, _b) (((_a) > (_b)) ? (_a) : (_b)) 42 #define __CODEGEN_BITFIELD(l, h) (h) - (l) + 1 43 #define __CODEGEN_OP_LENGTH_BIAS 2 44 #define __CODEGEN_OP_LENGTH(x) (uint32_t)((__CODEGEN_MAX(x, __CODEGEN_OP_LENGTH_BIAS)) - __CODEGEN_OP_LENGTH_BIAS) 45 GetOpLength(uint32_t uiLength)46 static uint32_t GetOpLength(uint32_t uiLength) { return __CODEGEN_OP_LENGTH(uiLength); } 47 48 //! 49 //! \brief VDENC_64B_Aligned_Lower_Address 50 //! \details 51 //! 52 //! 53 struct VDENC_64B_Aligned_Lower_Address_CMD 54 { 55 union 56 { 57 //!< DWORD 0 58 struct 59 { 60 uint32_t Reserved0 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 61 uint32_t Address : __CODEGEN_BITFIELD( 6, 31) ; //!< Address 62 }; 63 uint32_t Value; 64 } DW0; 65 66 //! \name Local enumerations 67 68 //! \name Initializations 69 70 //! \brief Explicit member initialization function 71 VDENC_64B_Aligned_Lower_Address_CMD(); 72 73 static const size_t dwSize = 1; 74 static const size_t byteSize = 4; 75 }; 76 77 //! 78 //! \brief VDENC_64B_Aligned_Upper_Address 79 //! \details 80 //! 81 //! 82 struct VDENC_64B_Aligned_Upper_Address_CMD 83 { 84 union 85 { 86 //!< DWORD 0 87 struct 88 { 89 uint32_t AddressUpperDword : __CODEGEN_BITFIELD( 0, 15) ; //!< Address Upper DWord 90 uint32_t Reserved16 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 91 }; 92 uint32_t Value; 93 } DW0; 94 95 //! \name Local enumerations 96 97 //! \name Initializations 98 99 //! \brief Explicit member initialization function 100 VDENC_64B_Aligned_Upper_Address_CMD(); 101 102 static const size_t dwSize = 1; 103 static const size_t byteSize = 4; 104 }; 105 106 //! 107 //! \brief VDENC_Surface_Control_Bits 108 //! \details 109 //! 110 //! 111 struct VDENC_Surface_Control_Bits_CMD 112 { 113 union 114 { 115 //!< DWORD 0 116 struct 117 { 118 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Index to Memory Object Control State (MOCS) Tables: 119 uint32_t ArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< ARBITRATION_PRIORITY_CONTROL 120 uint32_t MemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< MEMORY_COMPRESSION_ENABLE 121 uint32_t MemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< MEMORY_COMPRESSION_MODE 122 uint32_t Reserved11 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 123 uint32_t CacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< CACHE_SELECT 124 uint32_t TiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< TILED_RESOURCE_MODE 125 uint32_t Reserved15 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 126 }; 127 uint32_t Value; 128 } DW0; 129 130 //! \name Local enumerations 131 132 //! \brief ARBITRATION_PRIORITY_CONTROL 133 //! \details 134 //! This field controls the priority of arbitration used in the GAC/GAM 135 //! pipeline for this surface. 136 enum ARBITRATION_PRIORITY_CONTROL 137 { 138 ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 139 ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 140 ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 141 ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 142 }; 143 144 //! \brief MEMORY_COMPRESSION_ENABLE 145 //! \details 146 //! Memory compression will be attempted for this surface. 147 enum MEMORY_COMPRESSION_ENABLE 148 { 149 MEMORY_COMPRESSION_ENABLE_DISABLE = 0, //!< No additional details 150 MEMORY_COMPRESSION_ENABLE_ENABLE = 1, //!< No additional details 151 }; 152 153 //! \brief MEMORY_COMPRESSION_MODE 154 //! \details 155 //! Distinguishes Vertical from Horizontal compression. Please refer to 156 //! vol1a <b>Memory Data</b>. 157 enum MEMORY_COMPRESSION_MODE 158 { 159 MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 160 MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 161 }; 162 163 //! \brief CACHE_SELECT 164 //! \details 165 //! This field controls if the Row Store is going to store inside Media 166 //! Cache (rowstore cache) or to LLC. 167 enum CACHE_SELECT 168 { 169 CACHE_SELECT_UNNAMED0 = 0, //!< Buffer going to LLC. 170 CACHE_SELECT_UNNAMED1 = 1, //!< Buffer going to Internal Media Storage. 171 }; 172 173 //! \brief TILED_RESOURCE_MODE 174 //! \details 175 //! <b>For Media Surfaces</b>: This field specifies the tiled resource mode. 176 enum TILED_RESOURCE_MODE 177 { 178 TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource. 179 TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 180 TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 181 }; 182 183 //! \name Initializations 184 185 //! \brief Explicit member initialization function 186 VDENC_Surface_Control_Bits_CMD(); 187 188 static const size_t dwSize = 1; 189 static const size_t byteSize = 4; 190 }; 191 192 //! 193 //! \brief VDENC_Sub_Mb_Pred_Mode 194 //! \details 195 //! 196 //! 197 struct VDENC_Sub_Mb_Pred_Mode_CMD 198 { 199 union 200 { 201 //!< WORD 0 202 struct 203 { 204 uint8_t Submbpredmode0 : __CODEGEN_BITFIELD( 0, 1) ; //!< SubMbPredMode[0] 205 uint8_t Submbpredmode1 : __CODEGEN_BITFIELD( 2, 3) ; //!< SubMbPredMode[1] 206 uint8_t Submbpredmode2 : __CODEGEN_BITFIELD( 4, 5) ; //!< SubMbPredMode[2] 207 uint8_t Submbpredmode3 : __CODEGEN_BITFIELD( 6, 7) ; //!< SubMbPredMode[3] 208 }; 209 uint8_t Value; 210 } DW0; 211 212 //! \name Local enumerations 213 214 //! \name Initializations 215 216 //! \brief Explicit member initialization function 217 VDENC_Sub_Mb_Pred_Mode_CMD(); 218 219 static const size_t dwSize = 0; 220 static const size_t byteSize = 1; 221 }; 222 223 //! 224 //! \brief VDENC_Block_8x8_4 225 //! \details 226 //! 227 //! 228 struct VDENC_Block_8x8_4_CMD 229 { 230 union 231 { 232 //!< WORD 0 233 struct 234 { 235 uint16_t Block8X80 : __CODEGEN_BITFIELD( 0, 3) ; //!< Block8x8[0] 236 uint16_t Block8X81 : __CODEGEN_BITFIELD( 4, 7) ; //!< Block8x8[1] 237 uint16_t Block8X82 : __CODEGEN_BITFIELD( 8, 11) ; //!< Block8x8[2] 238 uint16_t Block8X83 : __CODEGEN_BITFIELD(12, 15) ; //!< Block8x8[3] 239 }; 240 uint16_t Value; 241 } DW0; 242 243 //! \name Local enumerations 244 245 //! \name Initializations 246 247 //! \brief Explicit member initialization function 248 VDENC_Block_8x8_4_CMD(); 249 250 static const size_t dwSize = 0; 251 static const size_t byteSize = 2; 252 }; 253 254 //! 255 //! \brief VDENC_Delta_MV_XY 256 //! \details 257 //! 258 //! 259 //! Calculates the difference between the actual MV for the Sub Macroblock 260 //! and the predicted MV based on the availability of the neighbors. 261 //! 262 //! This is calculated and populated for Inter frames only. In case of an 263 //! Intra MB in Inter frames, this value should be 0. 264 //! 265 struct VDENC_Delta_MV_XY_CMD 266 { 267 union 268 { 269 //!< DWORD 0 270 struct 271 { 272 uint32_t X0 : __CODEGEN_BITFIELD( 0, 15) ; //!< X0 273 uint32_t Y0 : __CODEGEN_BITFIELD(16, 31) ; //!< Y0 274 }; 275 uint32_t Value; 276 } DW0; 277 union 278 { 279 //!< DWORD 1 280 struct 281 { 282 uint32_t X1 : __CODEGEN_BITFIELD( 0, 15) ; //!< X1 283 uint32_t Y1 : __CODEGEN_BITFIELD(16, 31) ; //!< Y1 284 }; 285 uint32_t Value; 286 } DW1; 287 union 288 { 289 //!< DWORD 2 290 struct 291 { 292 uint32_t X2 : __CODEGEN_BITFIELD( 0, 15) ; //!< X2 293 uint32_t Y2 : __CODEGEN_BITFIELD(16, 31) ; //!< Y2 294 }; 295 uint32_t Value; 296 } DW2; 297 union 298 { 299 //!< DWORD 3 300 struct 301 { 302 uint32_t X3 : __CODEGEN_BITFIELD( 0, 15) ; //!< X3 303 uint32_t Y3 : __CODEGEN_BITFIELD(16, 31) ; //!< Y3 304 }; 305 uint32_t Value; 306 } DW3; 307 308 //! \name Local enumerations 309 310 //! \brief X0 311 //! \details 312 enum X0 313 { 314 X0_UNNAMED0 = 0, //!< No additional details 315 }; 316 317 //! \brief Y0 318 //! \details 319 enum Y0 320 { 321 Y0_UNNAMED0 = 0, //!< No additional details 322 }; 323 324 //! \brief X1 325 //! \details 326 enum X1 327 { 328 X1_UNNAMED0 = 0, //!< No additional details 329 }; 330 331 //! \brief Y1 332 //! \details 333 enum Y1 334 { 335 Y1_UNNAMED0 = 0, //!< No additional details 336 }; 337 338 //! \brief X2 339 //! \details 340 enum X2 341 { 342 X2_UNNAMED0 = 0, //!< No additional details 343 }; 344 345 //! \brief Y2 346 //! \details 347 enum Y2 348 { 349 Y2_UNNAMED0 = 0, //!< No additional details 350 }; 351 352 //! \brief X3 353 //! \details 354 enum X3 355 { 356 X3_UNNAMED0 = 0, //!< No additional details 357 }; 358 359 //! \brief Y3 360 //! \details 361 enum Y3 362 { 363 Y3_UNNAMED0 = 0, //!< No additional details 364 }; 365 366 //! \name Initializations 367 368 //! \brief Explicit member initialization function 369 VDENC_Delta_MV_XY_CMD(); 370 371 static const size_t dwSize = 4; 372 static const size_t byteSize = 16; 373 }; 374 375 //! 376 //! \brief VDENC_Colocated_MV_Picture 377 //! \details 378 //! 379 //! 380 struct VDENC_Colocated_MV_Picture_CMD 381 { 382 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress ; //!< Lower Address 383 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress ; //!< Upper Address 384 VDENC_Surface_Control_Bits_CMD PictureFields ; //!< Picture Fields 385 386 //! \name Local enumerations 387 388 //! \name Initializations 389 390 //! \brief Explicit member initialization function 391 VDENC_Colocated_MV_Picture_CMD(); 392 393 static const size_t dwSize = 3; 394 static const size_t byteSize = 12; 395 }; 396 397 //! 398 //! \brief VDENC_Down_Scaled_Reference_Picture 399 //! \details 400 //! 401 //! 402 struct VDENC_Down_Scaled_Reference_Picture_CMD 403 { 404 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress ; //!< Lower Address 405 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress ; //!< Upper Address 406 VDENC_Surface_Control_Bits_CMD PictureFields ; //!< Picture Fields 407 408 //! \name Local enumerations 409 410 //! \name Initializations 411 412 //! \brief Explicit member initialization function 413 VDENC_Down_Scaled_Reference_Picture_CMD(); 414 415 static const size_t dwSize = 3; 416 static const size_t byteSize = 12; 417 }; 418 419 //! 420 //! \brief VDENC_FRAME_BASED_STATISTICS_STREAMOUT 421 //! \details 422 //! 423 //! 424 struct VDENC_FRAME_BASED_STATISTICS_STREAMOUT_CMD 425 { 426 union 427 { 428 //!< DWORD 0 429 struct 430 { 431 uint32_t SumSadHaarForBestMbChoice ; //!< Sum sad\haar for best MB choice 432 }; 433 uint32_t Value; 434 } DW0; 435 union 436 { 437 //!< DWORD 1 438 struct 439 { 440 uint32_t IntraIso16X16MbCount : __CODEGEN_BITFIELD( 0, 15) ; //!< Intra iso 16x16 MB count 441 uint32_t IntraMbCount : __CODEGEN_BITFIELD(16, 31) ; //!< Intra MB count 442 }; 443 uint32_t Value; 444 } DW1; 445 union 446 { 447 //!< DWORD 2 448 struct 449 { 450 uint32_t IntraIso4X4MbCount : __CODEGEN_BITFIELD( 0, 15) ; //!< Intra iso 4x4 MB count 451 uint32_t IntraIso8X8MbCount : __CODEGEN_BITFIELD(16, 31) ; //!< Intra iso 8x8 MB count 452 }; 453 uint32_t Value; 454 } DW2; 455 union 456 { 457 //!< DWORD 3 458 struct 459 { 460 uint32_t SegmentMapCount0 : __CODEGEN_BITFIELD( 0, 15) ; //!< segment map count 0 461 uint32_t SegmentMapCount1 : __CODEGEN_BITFIELD(16, 31) ; //!< segment map count 1 462 }; 463 uint32_t Value; 464 } DW3; 465 union 466 { 467 //!< DWORD 4 468 struct 469 { 470 uint32_t SegmentMapCount2 : __CODEGEN_BITFIELD( 0, 15) ; //!< segment map count 2 471 uint32_t SegmentMapCount3 : __CODEGEN_BITFIELD(16, 31) ; //!< segment map count 3 472 }; 473 uint32_t Value; 474 } DW4; 475 476 uint32_t Reserved160[12]; //!< Reserved 477 478 union 479 { 480 //!< DWORD 17 481 struct 482 { 483 uint32_t SumSadHaarForBestMbChoiceBottomHalfPopulation ; //!< Sum sad\haar for best MB choice bottom half population 484 }; 485 uint32_t Value; 486 } DW17; 487 union 488 { 489 //!< DWORD 18 490 struct 491 { 492 uint32_t SumSadHaarForBestMbChoiceTopHalfPopulation ; //!< Sum sad\haar for best MB choice top half population 493 }; 494 uint32_t Value; 495 } DW18; 496 union 497 { 498 //!< DWORD 19 499 struct 500 { 501 uint32_t SumTopHalfPopulationOccurrences : __CODEGEN_BITFIELD( 0, 15) ; //!< Sum top half population occurrences 502 uint32_t SumBottomHalfPopulationOccurrences : __CODEGEN_BITFIELD(16, 31) ; //!< Sum bottom half population occurrences 503 }; 504 uint32_t Value; 505 } DW19; 506 507 //! \name Local enumerations 508 509 //! \name Initializations 510 511 //! \brief Explicit member initialization function 512 VDENC_FRAME_BASED_STATISTICS_STREAMOUT_CMD(); 513 514 static const size_t dwSize = 20; 515 static const size_t byteSize = 80; 516 }; 517 518 //! 519 //! \brief VDENC_Mode_StreamOut_Data 520 //! \details 521 //! 522 //! 523 struct VDENC_Mode_StreamOut_Data_CMD 524 { 525 union 526 { 527 //!< DWORD 0 528 struct 529 { 530 uint32_t MbX : __CODEGEN_BITFIELD( 0, 7) ; //!< MB.X 531 uint32_t MbY : __CODEGEN_BITFIELD( 8, 15) ; //!< MB.Y 532 uint32_t MinimalDistortion : __CODEGEN_BITFIELD(16, 31) ; //!< Minimal Distortion 533 }; 534 uint32_t Value; 535 } DW0; 536 union 537 { 538 //!< DWORD 1 539 struct 540 { 541 uint32_t Skiprawdistortion : __CODEGEN_BITFIELD( 0, 15) ; //!< SkipRawDistortion 542 uint32_t Interrawdistortion : __CODEGEN_BITFIELD(16, 31) ; //!< InterRawDistortion 543 }; 544 uint32_t Value; 545 } DW1; 546 union 547 { 548 //!< DWORD 2 549 struct 550 { 551 uint32_t Bestintrarawdistortion : __CODEGEN_BITFIELD( 0, 15) ; //!< BestIntraRawDistortion 552 uint32_t IntermbmodeChromaPredictionMode : __CODEGEN_BITFIELD(16, 17) ; //!< INTERMBMODECHROMA_PREDICTION_MODE 553 uint32_t Intrambmode : __CODEGEN_BITFIELD(18, 19) ; //!< INTRAMBMODE 554 uint32_t Intrambflag : __CODEGEN_BITFIELD(20, 20) ; //!< INTRAMBFLAG 555 uint32_t Lastmbflag : __CODEGEN_BITFIELD(21, 21) ; //!< LASTMBFLAG 556 uint32_t CoefficientClampOccurred : __CODEGEN_BITFIELD(22, 22) ; //!< Coefficient Clamp Occurred 557 uint32_t ConformanceViolation : __CODEGEN_BITFIELD(23, 23) ; //!< Conformance Violation 558 uint32_t Submbpredmode : __CODEGEN_BITFIELD(24, 31) ; //!< SubMbPredMode 559 }; 560 uint32_t Value; 561 } DW2; 562 union 563 { 564 //!< DWORD 3 565 struct 566 { 567 uint32_t Lumaintramode0 : __CODEGEN_BITFIELD( 0, 15) ; //!< LumaIntraMode[0] 568 uint32_t Lumaintramode1 : __CODEGEN_BITFIELD(16, 31) ; //!< LumaIntraMode[1] 569 }; 570 uint32_t Value; 571 } DW3; 572 union 573 { 574 //!< DWORD 4 575 struct 576 { 577 uint32_t Lumaintramode2 : __CODEGEN_BITFIELD( 0, 15) ; //!< LumaIntraMode[2] 578 uint32_t Lumaintramode3 : __CODEGEN_BITFIELD(16, 31) ; //!< LumaIntraMode[3] 579 }; 580 uint32_t Value; 581 } DW4; 582 VDENC_Delta_MV_XY_CMD DeltaMv0 ; //!< Delta MV0 583 VDENC_Delta_MV_XY_CMD DeltaMv1 ; //!< Delta MV1 584 union 585 { 586 //!< DWORD 13 587 struct 588 { 589 uint32_t FwdRefids : __CODEGEN_BITFIELD( 0, 15) ; //!< FWD REFIDs 590 uint32_t BwdRefids : __CODEGEN_BITFIELD(16, 31) ; //!< BWD REFIDs 591 }; 592 uint32_t Value; 593 } DW13; 594 union 595 { 596 //!< DWORD 14 597 struct 598 { 599 uint32_t QpY : __CODEGEN_BITFIELD( 0, 5) ; //!< QP_y 600 uint32_t MbBitCount : __CODEGEN_BITFIELD( 6, 18) ; //!< MB_Bit_Count 601 uint32_t MbHeaderCount : __CODEGEN_BITFIELD(19, 31) ; //!< MB_Header_Count 602 }; 603 uint32_t Value; 604 } DW14; 605 union 606 { 607 //!< DWORD 15 608 struct 609 { 610 uint32_t MbType : __CODEGEN_BITFIELD( 0, 4) ; //!< MB Type 611 uint32_t BlockCbp : __CODEGEN_BITFIELD( 5, 30) ; //!< Block CBP 612 uint32_t Skipmbflag : __CODEGEN_BITFIELD(31, 31) ; //!< SkipMbFlag 613 }; 614 uint32_t Value; 615 } DW15; 616 617 //! \name Local enumerations 618 619 //! \brief INTERMBMODECHROMA_PREDICTION_MODE 620 //! \details 621 //! This field indicates the InterMB Parition type for Inter MB. 622 //! <br>OR</br> 623 //! This field indicates Chroma Prediction Mode for Intra MB. 624 enum INTERMBMODECHROMA_PREDICTION_MODE 625 { 626 INTERMBMODECHROMA_PREDICTION_MODE_UNNAMED0 = 0, //!< 16x16 627 INTERMBMODECHROMA_PREDICTION_MODE_UNNAMED1 = 1, //!< 16x8 628 INTERMBMODECHROMA_PREDICTION_MODE_UNNAMED2 = 2, //!< 8x16 629 INTERMBMODECHROMA_PREDICTION_MODE_UNNAMED3 = 3, //!< 8x8 630 }; 631 632 //! \brief INTRAMBMODE 633 //! \details 634 //! This field indicates the Best Intra Partition. 635 enum INTRAMBMODE 636 { 637 INTRAMBMODE_UNNAMED0 = 0, //!< 16x16 638 INTRAMBMODE_UNNAMED1 = 1, //!< 8x8 639 INTRAMBMODE_UNNAMED2 = 2, //!< 4x4 640 }; 641 642 //! \brief INTRAMBFLAG 643 //! \details 644 //! This field specifies whether the current macroblock is an Intra (I) 645 //! macroblock. 646 enum INTRAMBFLAG 647 { 648 INTRAMBFLAG_INTER = 0, //!< inter macroblock 649 INTRAMBFLAG_INTRA = 1, //!< intra macroblock 650 }; 651 652 enum LASTMBFLAG 653 { 654 LASTMBFLAG_NOTLAST = 0, //!< The current MB is not the last MB in the current Slice. 655 LASTMBFLAG_LAST = 1, //!< The current MB is the last MB in the current Slice. 656 }; 657 658 //! \name Initializations 659 660 //! \brief Explicit member initialization function 661 VDENC_Mode_StreamOut_Data_CMD(); 662 663 static const size_t dwSize = 16; 664 static const size_t byteSize = 64; 665 }; 666 667 //! 668 //! \brief VDENC_Original_Uncompressed_Picture 669 //! \details 670 //! 671 //! 672 struct VDENC_Original_Uncompressed_Picture_CMD 673 { 674 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress ; //!< Lower Address 675 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress ; //!< Upper Address 676 VDENC_Surface_Control_Bits_CMD PictureFields ; //!< Picture Fields 677 678 //! \name Local enumerations 679 680 //! \name Initializations 681 682 //! \brief Explicit member initialization function 683 VDENC_Original_Uncompressed_Picture_CMD(); 684 685 static const size_t dwSize = 3; 686 static const size_t byteSize = 12; 687 }; 688 689 //! 690 //! \brief VDENC_Reference_Picture 691 //! \details 692 //! 693 //! 694 struct VDENC_Reference_Picture_CMD 695 { 696 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress ; //!< Lower Address 697 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress ; //!< Upper Address 698 VDENC_Surface_Control_Bits_CMD PictureFields ; //!< Picture Fields 699 700 //! \name Local enumerations 701 702 //! \name Initializations 703 704 //! \brief Explicit member initialization function 705 VDENC_Reference_Picture_CMD(); 706 707 static const size_t dwSize = 3; 708 static const size_t byteSize = 12; 709 }; 710 711 //! 712 //! \brief VDENC_Row_Store_Scratch_Buffer_Picture 713 //! \details 714 //! 715 //! 716 struct VDENC_Row_Store_Scratch_Buffer_Picture_CMD 717 { 718 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress ; //!< Lower Address 719 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress ; //!< Upper Address 720 VDENC_Surface_Control_Bits_CMD BufferPictureFields ; //!< Buffer Picture Fields 721 722 //! \name Local enumerations 723 724 //! \name Initializations 725 726 //! \brief Explicit member initialization function 727 VDENC_Row_Store_Scratch_Buffer_Picture_CMD(); 728 729 static const size_t dwSize = 3; 730 static const size_t byteSize = 12; 731 }; 732 733 //! 734 //! \brief VDENC_Statistics_Streamout 735 //! \details 736 //! 737 //! 738 struct VDENC_Statistics_Streamout_CMD 739 { 740 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress ; //!< Lower Address 741 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress ; //!< Upper Address 742 VDENC_Surface_Control_Bits_CMD PictureFields ; //!< Picture Fields 743 744 //! \name Local enumerations 745 746 //! \name Initializations 747 748 //! \brief Explicit member initialization function 749 VDENC_Statistics_Streamout_CMD(); 750 751 static const size_t dwSize = 3; 752 static const size_t byteSize = 12; 753 }; 754 755 //! 756 //! \brief VDENC_Streamin_Data_Picture 757 //! \details 758 //! 759 //! 760 struct VDENC_Streamin_Data_Picture_CMD 761 { 762 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress ; //!< Lower Address 763 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress ; //!< Upper Address 764 VDENC_Surface_Control_Bits_CMD PictureFields ; //!< Picture Fields 765 766 //! \name Local enumerations 767 768 //! \name Initializations 769 770 //! \brief Explicit member initialization function 771 VDENC_Streamin_Data_Picture_CMD(); 772 773 static const size_t dwSize = 3; 774 static const size_t byteSize = 12; 775 }; 776 777 //! 778 //! \brief VDENC_STREAMIN_STATE 779 //! \details 780 //! 781 //! 782 struct VDENC_STREAMIN_STATE_CMD 783 { 784 union 785 { 786 //!< DWORD 0 787 struct 788 { 789 uint32_t RegionOfInterestRoiSelection : __CODEGEN_BITFIELD( 0, 7) ; //!< Region of Interest (ROI) Selection 790 uint32_t Forceintra : __CODEGEN_BITFIELD( 8, 8) ; //!< FORCEINTRA 791 uint32_t Forceskip : __CODEGEN_BITFIELD( 9, 9) ; //!< FORCESKIP 792 uint32_t Reserved10 : __CODEGEN_BITFIELD(10, 31) ; //!< Reserved 793 }; 794 uint32_t Value; 795 } DW0; 796 union 797 { 798 //!< DWORD 1 799 struct 800 { 801 uint32_t Qpprimey : __CODEGEN_BITFIELD( 0, 7) ; //!< QPPRIMEY 802 uint32_t Targetsizeinword : __CODEGEN_BITFIELD( 8, 15) ; //!< TargetSizeInWord 803 uint32_t Maxsizeinword : __CODEGEN_BITFIELD(16, 23) ; //!< MaxSizeInWord 804 uint32_t Reserved56 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 805 }; 806 uint32_t Value; 807 } DW1; 808 union 809 { 810 //!< DWORD 2 811 struct 812 { 813 uint32_t FwdPredictorX : __CODEGEN_BITFIELD( 0, 15) ; //!< Fwd Predictor.X 814 uint32_t FwdPredictorY : __CODEGEN_BITFIELD(16, 31) ; //!< Fwd Predictor.Y 815 }; 816 uint32_t Value; 817 } DW2; 818 union 819 { 820 //!< DWORD 3 821 struct 822 { 823 uint32_t BwdPredictorX : __CODEGEN_BITFIELD( 0, 15) ; //!< Bwd Predictor.X 824 uint32_t BwdPredictorY : __CODEGEN_BITFIELD(16, 31) ; //!< Bwd Predictor.Y 825 }; 826 uint32_t Value; 827 } DW3; 828 union 829 { 830 //!< DWORD 4 831 struct 832 { 833 uint32_t FwdRefid0 : __CODEGEN_BITFIELD( 0, 3) ; //!< Fwd RefID0 834 uint32_t BwdRefid0 : __CODEGEN_BITFIELD( 4, 7) ; //!< Bwd RefID0 835 uint32_t Reserved136 : __CODEGEN_BITFIELD( 8, 31) ; //!< Reserved 836 }; 837 uint32_t Value; 838 } DW4; 839 840 uint32_t Reserved160[11]; //!< Reserved 841 842 //! \name Local enumerations 843 844 //! \brief FORCEINTRA 845 //! \details 846 //! This field specifies whether current macroblock should be coded as an 847 //! intra macroblock. 848 //! It is illegal to enable both ForceSkip and ForceIntra for 849 //! the same macroblock. 850 //! This should be disabled if Rolling-I is enabled in the 851 //! VDEnc Image State. 852 enum FORCEINTRA 853 { 854 FORCEINTRA_DISABLE = 0, //!< VDEnc determined macroblock type 855 FORCEINTRA_ENABLE = 1, //!< Force to be coded as an intra macroblock 856 }; 857 858 //! \brief FORCESKIP 859 //! \details 860 //! This field specifies whether current macroblock should be coded as a 861 //! skipped macroblock. 862 //! It is illegal to enable both ForceSkip and ForceIntra for 863 //! the same macroblock. 864 //! This should be disabled if Rolling-I is enabled in the 865 //! VDEnc Image State. 866 //! It is illegal to enable ForceSkip for I-Frames. 867 enum FORCESKIP 868 { 869 FORCESKIP_DISABLE = 0, //!< VDEnc determined macroblock type 870 FORCESKIP_ENABLE = 1, //!< Force to be coded as a skipped macroblock 871 }; 872 873 //! \brief QPPRIMEY 874 //! \details 875 //! Quantization parameter for Y. 876 enum QPPRIMEY 877 { 878 QPPRIMEY_UNNAMED0 = 0, //!< No additional details 879 QPPRIMEY_UNNAMED51 = 51, //!< No additional details 880 }; 881 882 //! \name Initializations 883 884 //! \brief Explicit member initialization function 885 VDENC_STREAMIN_STATE_CMD(); 886 887 static const size_t dwSize = 16; 888 static const size_t byteSize = 64; 889 }; 890 891 //! 892 //! \brief VDENC_HEVC_VP9_FRAME_BASED_STATISTICS_STREAMOUT 893 //! \details 894 //! 895 //! 896 struct VDENC_HEVC_VP9_FRAME_BASED_STATISTICS_STREAMOUT_CMD 897 { 898 union 899 { 900 //!< DWORD 0 901 struct 902 { 903 uint32_t SumSadHaarForBestModeDecision ; //!< Sum sad\haar for best mode decision 904 }; 905 uint32_t Value; 906 } DW0; 907 union 908 { 909 //!< DWORD 1 910 struct 911 { 912 uint32_t IntraCuCountNormalized : __CODEGEN_BITFIELD( 0, 19) ; //!< Intra CU count normalized 913 uint32_t Reserved52 : __CODEGEN_BITFIELD(20, 31) ; //!< Reserved 914 }; 915 uint32_t Value; 916 } DW1; 917 union 918 { 919 //!< DWORD 2 920 struct 921 { 922 uint32_t NonSkipInterCuCountNormalized : __CODEGEN_BITFIELD( 0, 19) ; //!< Non-skip Inter CU count normalized 923 uint32_t Reserved84 : __CODEGEN_BITFIELD(20, 31) ; //!< Reserved 924 }; 925 uint32_t Value; 926 } DW2; 927 union 928 { 929 //!< DWORD 3 930 struct 931 { 932 uint32_t SegmentMapCount0 : __CODEGEN_BITFIELD( 0, 19) ; //!< segment map count 0 933 uint32_t Reserved116 : __CODEGEN_BITFIELD(20, 31) ; //!< Reserved 934 }; 935 uint32_t Value; 936 } DW3; 937 union 938 { 939 //!< DWORD 4 940 struct 941 { 942 uint32_t SegmentMapCount1 : __CODEGEN_BITFIELD( 0, 19) ; //!< segment map count 1 943 uint32_t Reserved148 : __CODEGEN_BITFIELD(20, 31) ; //!< Reserved 944 }; 945 uint32_t Value; 946 } DW4; 947 union 948 { 949 //!< DWORD 5 950 struct 951 { 952 uint32_t SegmentMapCount2 : __CODEGEN_BITFIELD( 0, 19) ; //!< segment map count 2 953 uint32_t Reserved180 : __CODEGEN_BITFIELD(20, 31) ; //!< Reserved 954 }; 955 uint32_t Value; 956 } DW5; 957 union 958 { 959 //!< DWORD 6 960 struct 961 { 962 uint32_t SegmentMapCount3 : __CODEGEN_BITFIELD( 0, 19) ; //!< segment map count 3 963 uint32_t Reserved212 : __CODEGEN_BITFIELD(20, 31) ; //!< Reserved 964 }; 965 uint32_t Value; 966 } DW6; 967 union 968 { 969 //!< DWORD 7 970 struct 971 { 972 uint32_t MvXGlobalMeSample025X25X : __CODEGEN_BITFIELD( 0, 15) ; //!< MV.x Global ME sample 0 (.25x,.25x) 973 uint32_t MvYGlobalMeSample025X25X : __CODEGEN_BITFIELD(16, 31) ; //!< MV.y Global ME sample 0 (.25x,.25x) 974 }; 975 uint32_t Value; 976 } DW7; 977 union 978 { 979 //!< DWORD 8 980 struct 981 { 982 uint32_t MvXGlobalMeSample125X25X : __CODEGEN_BITFIELD( 0, 15) ; //!< MV.x Global ME sample 1 (.25x,.25x) 983 uint32_t MvYGlobalMeSample125X25X : __CODEGEN_BITFIELD(16, 31) ; //!< MV.y Global ME sample 1 (.25x,.25x) 984 }; 985 uint32_t Value; 986 } DW8; 987 union 988 { 989 //!< DWORD 9 990 struct 991 { 992 uint32_t MvXGlobalMeSample225X25X : __CODEGEN_BITFIELD( 0, 15) ; //!< MV.x Global ME sample 2 (.25x,.25x) 993 uint32_t MvYGlobalMeSample225X25X : __CODEGEN_BITFIELD(16, 31) ; //!< MV.y Global ME sample 2 (.25x,.25x) 994 }; 995 uint32_t Value; 996 } DW9; 997 union 998 { 999 //!< DWORD 10 1000 struct 1001 { 1002 uint32_t MvXGlobalMeSample325X25X : __CODEGEN_BITFIELD( 0, 15) ; //!< MV.x Global ME sample 3 (.25x,.25x) 1003 uint32_t MvYGlobalMeSample325X25X : __CODEGEN_BITFIELD(16, 31) ; //!< MV.y Global ME sample 3 (.25x,.25x) 1004 }; 1005 uint32_t Value; 1006 } DW10; 1007 union 1008 { 1009 //!< DWORD 11 1010 struct 1011 { 1012 uint32_t MvXGlobalMeSample425X25X : __CODEGEN_BITFIELD( 0, 15) ; //!< MV.x Global ME sample 4 (.25x,.25x) 1013 uint32_t MvYGlobalMeSample425X25X : __CODEGEN_BITFIELD(16, 31) ; //!< MV.y Global ME sample 4 (.25x,.25x) 1014 }; 1015 uint32_t Value; 1016 } DW11; 1017 union 1018 { 1019 //!< DWORD 12 1020 struct 1021 { 1022 uint32_t MvXGlobalMeSample525X25X : __CODEGEN_BITFIELD( 0, 15) ; //!< MV.x Global ME sample 5 (.25x,.25x) 1023 uint32_t MvYGlobalMeSample525X25X : __CODEGEN_BITFIELD(16, 31) ; //!< MV.y Global ME sample 5 (.25x,.25x) 1024 }; 1025 uint32_t Value; 1026 } DW12; 1027 union 1028 { 1029 //!< DWORD 13 1030 struct 1031 { 1032 uint32_t MvXGlobalMeSample625X25X : __CODEGEN_BITFIELD( 0, 15) ; //!< MV.x Global ME sample 6 (.25x,.25x) 1033 uint32_t MvYGlobalMeSample625X25X : __CODEGEN_BITFIELD(16, 31) ; //!< MV.y Global ME sample 6 (.25x,.25x) 1034 }; 1035 uint32_t Value; 1036 } DW13; 1037 union 1038 { 1039 //!< DWORD 14 1040 struct 1041 { 1042 uint32_t MvXGlobalMeSample725X25X : __CODEGEN_BITFIELD( 0, 15) ; //!< MV.x Global ME sample 7 (.25x,.25x) 1043 uint32_t MvYGlobalMeSample725X25X : __CODEGEN_BITFIELD(16, 31) ; //!< MV.y Global ME sample 7 (.25x,.25x) 1044 }; 1045 uint32_t Value; 1046 } DW14; 1047 union 1048 { 1049 //!< DWORD 15 1050 struct 1051 { 1052 uint32_t MvXGlobalMeSample825X25X : __CODEGEN_BITFIELD( 0, 15) ; //!< MV.x Global ME sample 8 (.25x,.25x) 1053 uint32_t MvYGlobalMeSample825X25X : __CODEGEN_BITFIELD(16, 31) ; //!< MV.y Global ME sample 8 (.25x,.25x) 1054 }; 1055 uint32_t Value; 1056 } DW15; 1057 union 1058 { 1059 //!< DWORD 16 1060 struct 1061 { 1062 uint32_t RefidForGlobalmeSample0 : __CODEGEN_BITFIELD( 0, 1) ; //!< RefID for GlobalME sample 0 1063 uint32_t RefidForGlobalmeSample18 : __CODEGEN_BITFIELD( 2, 17) ; //!< RefID for GlobalME sample 1-8 1064 uint32_t Reserved530 : __CODEGEN_BITFIELD(18, 31) ; //!< Reserved 1065 }; 1066 uint32_t Value; 1067 } DW16; 1068 union 1069 { 1070 //!< DWORD 17 1071 struct 1072 { 1073 uint32_t PaletteCuCountNormalized : __CODEGEN_BITFIELD( 0, 19) ; //!< Palette CU Count Normalized 1074 uint32_t Reserved564 : __CODEGEN_BITFIELD(20, 31) ; //!< Reserved 1075 }; 1076 uint32_t Value; 1077 } DW17; 1078 union 1079 { 1080 //!< DWORD 18 1081 struct 1082 { 1083 uint32_t IbcCuCountNormalized : __CODEGEN_BITFIELD( 0, 19) ; //!< IBC CU Count Normalized 1084 uint32_t Reserved596 : __CODEGEN_BITFIELD(20, 31) ; //!< Reserved 1085 }; 1086 uint32_t Value; 1087 } DW18; 1088 union 1089 { 1090 //!< DWORD 19 1091 struct 1092 { 1093 uint32_t NumberOfSecondaryColorsChannel1 : __CODEGEN_BITFIELD( 0, 15) ; //!< Number of secondary colors (Channel1) 1094 uint32_t NumberOfPrimaryColorsChannel0 : __CODEGEN_BITFIELD(16, 31) ; //!< Number of primary colors (Channel0) 1095 }; 1096 uint32_t Value; 1097 } DW19; 1098 union 1099 { 1100 //!< DWORD 20 1101 struct 1102 { 1103 uint32_t NumberOfSecondaryColorsChannel2 : __CODEGEN_BITFIELD( 0, 15) ; //!< Number of secondary colors (Channel2) 1104 uint32_t Reserved656 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1105 }; 1106 uint32_t Value; 1107 } DW20; 1108 union 1109 { 1110 //!< DWORD 21 1111 struct 1112 { 1113 uint32_t Reserved672 ; //!< Reserved 1114 }; 1115 uint32_t Value; 1116 } DW21; 1117 union 1118 { 1119 //!< DWORD 22 1120 struct 1121 { 1122 uint32_t PositionOfTimerExpiration : __CODEGEN_BITFIELD( 0, 15) ; //!< Position of Timer expiration 1123 uint32_t TimerExpireStatus : __CODEGEN_BITFIELD(16, 16) ; //!< Timer Expire status 1124 uint32_t Reserved721 : __CODEGEN_BITFIELD(17, 31) ; //!< Reserved 1125 }; 1126 uint32_t Value; 1127 } DW22; 1128 union 1129 { 1130 //!< DWORD 23 1131 struct 1132 { 1133 uint32_t LocationOfPanic : __CODEGEN_BITFIELD( 0, 15) ; //!< Location of panic 1134 uint32_t PanicDetected : __CODEGEN_BITFIELD(16, 16) ; //!< Panic detected 1135 uint32_t Reserved753 : __CODEGEN_BITFIELD(17, 31) ; //!< Reserved 1136 }; 1137 uint32_t Value; 1138 } DW23; 1139 1140 uint32_t Reserved768[5]; //!< Reserved 1141 1142 union 1143 { 1144 //!< DWORD 29 1145 struct 1146 { 1147 uint32_t SumSadHaarForBestModeDecisionBottomHalfPopulation ; //!< Sum sad\haar for best mode decision bottom half population 1148 }; 1149 uint32_t Value; 1150 } DW29; 1151 union 1152 { 1153 //!< DWORD 30 1154 struct 1155 { 1156 uint32_t SumSadHaarForBestModeDecisionTopHalfPopulation ; //!< Sum sad\haar for best mode decision top half population 1157 }; 1158 uint32_t Value; 1159 } DW30; 1160 union 1161 { 1162 //!< DWORD 31 1163 struct 1164 { 1165 uint32_t SumTopHalfPopulationOccurrences : __CODEGEN_BITFIELD( 0, 15) ; //!< Sum top half population occurrences 1166 uint32_t SumBottomHalfPopulationOccurrences : __CODEGEN_BITFIELD(16, 31) ; //!< Sum bottom half population occurrences 1167 }; 1168 uint32_t Value; 1169 } DW31; 1170 1171 //! \name Local enumerations 1172 1173 //! \name Initializations 1174 1175 //! \brief Explicit member initialization function 1176 VDENC_HEVC_VP9_FRAME_BASED_STATISTICS_STREAMOUT_CMD(); 1177 1178 static const size_t dwSize = 32; 1179 static const size_t byteSize = 128; 1180 }; 1181 1182 //! 1183 //! \brief VDENC_HEVC_VP9_STREAMIN_STATE 1184 //! \details 1185 //! For the NumMergeCandidate paramaters [64x64/32x32/16x16/8x8], only the 1186 //! following configurations are valid. 1187 //! Normal Mode without force mv or force intra: 4321 [64x64 --> 16x16]. 1188 //! Speed Mode without force mv or force intra: 2220, 2110, 1210, 2200, 1110 1189 //! [64x64 --> 16x16]. 1190 //! 1191 struct VDENC_HEVC_VP9_STREAMIN_STATE_CMD 1192 { 1193 union 1194 { 1195 //!< DWORD 0 1196 struct 1197 { 1198 uint32_t Roi32X32016X1603 : __CODEGEN_BITFIELD( 0, 7) ; //!< ROI 32x32_0 16x16_03 1199 uint32_t Maxtusize : __CODEGEN_BITFIELD( 8, 9) ; //!< MaxTUSize 1200 uint32_t Maxcusize : __CODEGEN_BITFIELD(10, 11) ; //!< MaxCUSize 1201 uint32_t Numimepredictors : __CODEGEN_BITFIELD(12, 15) ; //!< NUMIMEPREDICTORS 1202 uint32_t PuType32X32016X1603 : __CODEGEN_BITFIELD(24, 31) ; //!< PU Type 32x32_0 16x16_03 1203 }; 1204 uint32_t Value; 1205 } DW0; 1206 union 1207 { 1208 //!< DWORD 1 1209 struct 1210 { 1211 uint32_t ForceMvX32X32016X160 : __CODEGEN_BITFIELD( 0, 15) ; //!< force_mv.x 32x32_0 16x16_0 1212 uint32_t ForceMvY32X32016X160 : __CODEGEN_BITFIELD(16, 31) ; //!< force_mv.y 32x32_0 16x16_0 1213 }; 1214 uint32_t Value; 1215 } DW1; 1216 union 1217 { 1218 //!< DWORD 2 1219 struct 1220 { 1221 uint32_t ForceMvX32X32016X161 : __CODEGEN_BITFIELD( 0, 15) ; //!< force_mv.x 32x32_0 16x16_1 1222 uint32_t ForceMvY32X32016X161 : __CODEGEN_BITFIELD(16, 31) ; //!< force_mv.y 32x32_0 16x16_1 1223 }; 1224 uint32_t Value; 1225 } DW2; 1226 union 1227 { 1228 //!< DWORD 3 1229 struct 1230 { 1231 uint32_t ForceMvX32X32016X162 : __CODEGEN_BITFIELD( 0, 15) ; //!< force_mv.x 32x32_0 16x16_2 1232 uint32_t ForceMvY32X32016X162 : __CODEGEN_BITFIELD(16, 31) ; //!< force_mv.y 32x32_0 16x16_2 1233 }; 1234 uint32_t Value; 1235 } DW3; 1236 union 1237 { 1238 //!< DWORD 4 1239 struct 1240 { 1241 uint32_t ForceMvX32X32016X163 : __CODEGEN_BITFIELD( 0, 15) ; //!< force_mv.x 32x32_0 16x16_3 1242 uint32_t ForceMvY32X32016X163 : __CODEGEN_BITFIELD(16, 31) ; //!< force_mv.y 32x32_0 16x16_3 1243 }; 1244 uint32_t Value; 1245 } DW4; 1246 union 1247 { 1248 //!< DWORD 5 1249 struct 1250 { 1251 uint32_t Reserved160 ; //!< Reserved 1252 }; 1253 uint32_t Value; 1254 } DW5; 1255 union 1256 { 1257 //!< DWORD 6 1258 struct 1259 { 1260 uint32_t ForceMvRefidx32X32016X160 : __CODEGEN_BITFIELD( 0, 3) ; //!< force_mv refidx 32x32_0 16x16_0 1261 uint32_t ForceMvRefidx32X32016X1613 : __CODEGEN_BITFIELD( 4, 15) ; //!< force_mv refidx 32x32_0 16x16_1-3 1262 uint32_t Nummergecandidatecu8X8 : __CODEGEN_BITFIELD(16, 19) ; //!< NumMergeCandidateCU8x8 1263 uint32_t Nummergecandidatecu16X16 : __CODEGEN_BITFIELD(20, 23) ; //!< NumMergeCandidateCU16x16 1264 uint32_t Nummergecandidatecu32X32 : __CODEGEN_BITFIELD(24, 27) ; //!< NumMergeCandidateCU32x32 1265 uint32_t Nummergecandidatecu64X64 : __CODEGEN_BITFIELD(28, 31) ; //!< NumMergeCandidateCU64x64 1266 }; 1267 uint32_t Value; 1268 } DW6; 1269 union 1270 { 1271 //!< DWORD 7 1272 struct 1273 { 1274 uint32_t Segid32X32016X1603Vp9Only : __CODEGEN_BITFIELD( 0, 15) ; //!< SegID 32x32_0 16x16_03 (VP9 only) 1275 uint32_t QpEn32X32016X1603 : __CODEGEN_BITFIELD(16, 19) ; //!< QP_En 32x32_0 16x16_03 1276 uint32_t SegidEnable : __CODEGEN_BITFIELD(20, 20) ; //!< SegID Enable 1277 uint32_t Reserved245 : __CODEGEN_BITFIELD(21, 22) ; //!< Reserved 1278 uint32_t ForceRefidEnable32X320 : __CODEGEN_BITFIELD(23, 23) ; //!< Force Refid Enable (32x32_0) 1279 uint32_t ImePredictorRefidSelect0332X320 : __CODEGEN_BITFIELD(24, 31) ; //!< IME predictor/refid Select0-3 32x32_0 1280 }; 1281 uint32_t Value; 1282 } DW7; 1283 union 1284 { 1285 //!< DWORD 8 1286 struct 1287 { 1288 uint32_t ImePredictor0X32X320 : __CODEGEN_BITFIELD( 0, 15) ; //!< ime_predictor0.x 32x32_0 1289 uint32_t ImePredictor0Y32X320 : __CODEGEN_BITFIELD(16, 31) ; //!< ime_predictor0.y 32x32_0 1290 }; 1291 uint32_t Value; 1292 } DW8; 1293 union 1294 { 1295 //!< DWORD 9 1296 struct 1297 { 1298 uint32_t ImePredictor0X32X321 : __CODEGEN_BITFIELD( 0, 15) ; //!< ime_predictor0.x 32x32_1 1299 uint32_t ImePredictor0Y32X321 : __CODEGEN_BITFIELD(16, 31) ; //!< ime_predictor0.y 32x32_1 1300 }; 1301 uint32_t Value; 1302 } DW9; 1303 union 1304 { 1305 //!< DWORD 10 1306 struct 1307 { 1308 uint32_t ImePredictor0X32X322 : __CODEGEN_BITFIELD( 0, 15) ; //!< ime_predictor0.x 32x32_2 1309 uint32_t ImePredictor0Y32X322 : __CODEGEN_BITFIELD(16, 31) ; //!< ime_predictor0.y 32x32_2 1310 }; 1311 uint32_t Value; 1312 } DW10; 1313 union 1314 { 1315 //!< DWORD 11 1316 struct 1317 { 1318 uint32_t ImePredictor0X32X323 : __CODEGEN_BITFIELD( 0, 15) ; //!< ime_predictor0.x 32x32_3 1319 uint32_t ImePredictor0Y32X323 : __CODEGEN_BITFIELD(16, 31) ; //!< ime_predictor0.y 32x32_3 1320 }; 1321 uint32_t Value; 1322 } DW11; 1323 union 1324 { 1325 //!< DWORD 12 1326 struct 1327 { 1328 uint32_t ImePredictor0Refidx32X320 : __CODEGEN_BITFIELD( 0, 3) ; //!< ime_predictor0 refidx 32x32_0 1329 uint32_t ImePredictor13Refidx32X3213 : __CODEGEN_BITFIELD( 4, 15) ; //!< ime_predictor1-3 refidx 32x32_1-3 1330 uint32_t Reserved400 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1331 }; 1332 uint32_t Value; 1333 } DW12; 1334 union 1335 { 1336 //!< DWORD 13 1337 struct 1338 { 1339 uint32_t Panicmodelcuthreshold : __CODEGEN_BITFIELD( 0, 15) ; //!< PanicModeLCUThreshold 1340 uint32_t Reserved432 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1341 }; 1342 uint32_t Value; 1343 } DW13; 1344 union 1345 { 1346 //!< DWORD 14 1347 struct 1348 { 1349 uint32_t ForceQpValue16X160 : __CODEGEN_BITFIELD( 0, 7) ; //!< Force QP Value 16x16_0 1350 uint32_t ForceQpValue16X161 : __CODEGEN_BITFIELD( 8, 15) ; //!< Force QP Value 16x16_1 1351 uint32_t ForceQpValue16X162 : __CODEGEN_BITFIELD(16, 23) ; //!< Force QP Value 16x16_2 1352 uint32_t ForceQpValue16X163 : __CODEGEN_BITFIELD(24, 31) ; //!< Force QP Value 16x16_3 1353 }; 1354 uint32_t Value; 1355 } DW14; 1356 union 1357 { 1358 //!< DWORD 15 1359 struct 1360 { 1361 uint32_t Reserved480 ; //!< Reserved 1362 }; 1363 uint32_t Value; 1364 } DW15; 1365 1366 //! \name Local enumerations 1367 1368 //! \brief NUMIMEPREDICTORS 1369 //! \details 1370 //! <p>This parameter specifes the number of IME predictors to be processed 1371 //! in stage3 IME.</p> 1372 //! <p></p> 1373 enum NUMIMEPREDICTORS 1374 { 1375 NUMIMEPREDICTORS_UNNAMED0 = 0, //!< No additional details 1376 NUMIMEPREDICTORS_UNNAMED4 = 4, //!< No additional details 1377 NUMIMEPREDICTORS_UNNAMED8 = 8, //!< No additional details 1378 NUMIMEPREDICTORS_UNNAMED12 = 12, //!< No additional details 1379 }; 1380 1381 //! \name Initializations 1382 1383 //! \brief Explicit member initialization function 1384 VDENC_HEVC_VP9_STREAMIN_STATE_CMD(); 1385 1386 static const size_t dwSize = 16; 1387 static const size_t byteSize = 64; 1388 }; 1389 1390 //! 1391 //! \brief VDENC_Surface_State_Fields 1392 //! \details 1393 //! 1394 //! 1395 struct VDENC_Surface_State_Fields_CMD 1396 { 1397 union 1398 { 1399 //!< DWORD 0 1400 struct 1401 { 1402 uint32_t CrVCbUPixelOffsetVDirection : __CODEGEN_BITFIELD( 0, 1) ; //!< Cr(V)/Cb(U) Pixel Offset V Direction 1403 uint32_t SurfaceFormatByteSwizzle : __CODEGEN_BITFIELD( 2, 2) ; //!< Surface Format Byte Swizzle 1404 uint32_t ColorSpaceSelection : __CODEGEN_BITFIELD( 3, 3) ; //!< Color space selection 1405 uint32_t Width : __CODEGEN_BITFIELD( 4, 17) ; //!< Width 1406 uint32_t Height : __CODEGEN_BITFIELD(18, 31) ; //!< Height 1407 }; 1408 uint32_t Value; 1409 } DW0; 1410 union 1411 { 1412 //!< DWORD 1 1413 struct 1414 { 1415 uint32_t TileWalk : __CODEGEN_BITFIELD( 0, 0) ; //!< TILE_WALK 1416 uint32_t TiledSurface : __CODEGEN_BITFIELD( 1, 1) ; //!< TILED_SURFACE 1417 uint32_t HalfPitchForChroma : __CODEGEN_BITFIELD( 2, 2) ; //!< HALF_PITCH_FOR_CHROMA 1418 uint32_t SurfacePitch : __CODEGEN_BITFIELD( 3, 19) ; //!< Surface Pitch 1419 uint32_t ChromaDownsampleFilterControl : __CODEGEN_BITFIELD(20, 22) ; //!< Chroma Downsample Filter Control 1420 uint32_t Reserved55 : __CODEGEN_BITFIELD(23, 26) ; //!< Reserved 1421 uint32_t InterleaveChroma : __CODEGEN_BITFIELD(27, 27) ; //!< INTERLEAVE_CHROMA_ 1422 uint32_t SurfaceFormat : __CODEGEN_BITFIELD(28, 31) ; //!< SURFACE_FORMAT 1423 }; 1424 uint32_t Value; 1425 } DW1; 1426 union 1427 { 1428 //!< DWORD 2 1429 struct 1430 { 1431 uint32_t YOffsetForUCb : __CODEGEN_BITFIELD( 0, 14) ; //!< Y Offset for U(Cb) 1432 uint32_t Reserved79 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 1433 uint32_t XOffsetForUCb : __CODEGEN_BITFIELD(16, 30) ; //!< X Offset for U(Cb) 1434 uint32_t Reserved95 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 1435 }; 1436 uint32_t Value; 1437 } DW2; 1438 union 1439 { 1440 //!< DWORD 3 1441 struct 1442 { 1443 uint32_t YOffsetForVCr : __CODEGEN_BITFIELD( 0, 15) ; //!< Y Offset for V(Cr) 1444 uint32_t XOffsetForVCr : __CODEGEN_BITFIELD(16, 28) ; //!< X Offset for V(Cr) 1445 uint32_t Reserved125 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 1446 }; 1447 uint32_t Value; 1448 } DW3; 1449 1450 //! \name Local enumerations 1451 1452 //! \brief TILE_WALK 1453 //! \details 1454 //! (This field must be set to 1: TILEWALK_YMAJOR.) This field specifies the 1455 //! type of memory tiling 1456 //! (XMajor or YMajor) employed to tile this surface. See Memory 1457 //! Interface Functions for details 1458 //! on memory tiling and restrictions.This field is ignored when the 1459 //! surface is linear. Internally 1460 //! H/W always treats this as set to 1 for all VDEnc usage. 1461 enum TILE_WALK 1462 { 1463 TILE_WALK_XMAJOR = 0, //!< TILEWALK_XMAJOR 1464 TILE_WALK_YMAJOR = 1, //!< TILEWALK_YMAJOR 1465 }; 1466 1467 //! \brief TILED_SURFACE 1468 //! \details 1469 //! (This field must be set to TRUE: Tiled.) This field specifies whether 1470 //! the surface is tiled. 1471 //! This field is ignored by VDEnc usage. 1472 enum TILED_SURFACE 1473 { 1474 TILED_SURFACE_FALSE = 0, //!< Linear 1475 TILED_SURFACE_TRUE = 1, //!< Tiled 1476 }; 1477 1478 //! \brief HALF_PITCH_FOR_CHROMA 1479 //! \details 1480 //! (This field must be set to Disable.) This field indicates that the 1481 //! chroma plane(s) will use a pitch equal 1482 //! to half the value specified in the Surface Pitch field. This field 1483 //! is only used for PLANAR surface formats. 1484 //! This field is igored by VDEnc (unless we support YV12). 1485 enum HALF_PITCH_FOR_CHROMA 1486 { 1487 HALF_PITCH_FOR_CHROMA_DISABLE = 0, //!< No additional details 1488 HALF_PITCH_FOR_CHROMA_ENABLE = 1, //!< No additional details 1489 }; 1490 1491 //! \brief INTERLEAVE_CHROMA_ 1492 //! \details 1493 //! This field indicates that the chroma fields are interleaved in a single 1494 //! plane rather than stored as 1495 //! two separate planes. This field is only used for PLANAR surface 1496 //! formats. 1497 enum INTERLEAVE_CHROMA_ 1498 { 1499 INTERLEAVE_CHROMA_DISABLE = 0, //!< No additional details 1500 INTERLEAVE_CHROMA_ENABLE = 1, //!< No additional details 1501 }; 1502 1503 //! \brief SURFACE_FORMAT 1504 //! \details 1505 //! Specifies the format of the surface. 1506 enum SURFACE_FORMAT 1507 { 1508 SURFACE_FORMAT_YUV422 = 0, //!< YUYV/YUY2 (8:8:8:8 MSB V0 Y1 U0 Y0) 1509 SURFACE_FORMAT_RGBA4444 = 1, //!< RGBA 32-bit 4:4:4:4 packed (8:8:8:8 MSB-X:B:G:R) 1510 SURFACE_FORMAT_YUV444 = 2, //!< YUV 32-bit 4:4:4 packed (8:8:8:8 MSB-A:Y:U:V) 1511 SURFACE_FORMAT_Y8UNORM = 3, //!< No additional details 1512 SURFACE_FORMAT_PLANAR_420_8 = 4, //!< (NV12, IMC1,2,3,4, YV12) 1513 SURFACE_FORMAT_YCRCB_SWAPY_422 = 5, //!< UYVY (8:8:8:8 MSB Y1 V0 Y0 U0) 1514 SURFACE_FORMAT_YCRCB_SWAPUV_422 = 6, //!< YVYU (8:8:8:8 MSB U0 Y1 V0 Y0) 1515 SURFACE_FORMAT_YCRCB_SWAPUVY_422 = 7, //!< VYUY (8:8:8:8 MSB Y1 U0 Y0 V0) 1516 SURFACE_FORMAT_P010 = 8, //!< 10 - bit planar 420 (Tile - Y / Linear / Tile - X) 1517 SURFACE_FORMAT_RGBA_10_10_10_2 = 9, //!< Need to convert to YUV. 2 bits Alpha, 10 bits R 10 bits G 10 bits B 1518 SURFACE_FORMAT_Y410 = 10, //!< 10 bit 4:4:4 packed 1519 SURFACE_FORMAT_NV21 = 11, //!< 8-bit, same as NV12 but UV interleave is reversed 1520 SURFACE_FORMAT_P010_VARIANT = 12, //!< >8 bit planar 420 with MSB together and LSB at an offset in x direction 1521 }; 1522 1523 //! \name Initializations 1524 1525 //! \brief Explicit member initialization function 1526 VDENC_Surface_State_Fields_CMD(); 1527 1528 static const size_t dwSize = 4; 1529 static const size_t byteSize = 16; 1530 }; 1531 1532 //! 1533 //! \brief VD_PIPELINE_FLUSH 1534 //! \details 1535 //! 1536 //! 1537 struct VD_PIPELINE_FLUSH_CMD 1538 { 1539 union 1540 { 1541 //!< DWORD 0 1542 struct 1543 { 1544 uint32_t DwordCountN : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_COUNT_N 1545 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1546 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 1547 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPCODEA 1548 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_COMMAND_OPCODE 1549 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1550 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1551 }; 1552 uint32_t Value; 1553 } DW0; 1554 union 1555 { 1556 //!< DWORD 1 1557 struct 1558 { 1559 uint32_t HevcPipelineDone : __CODEGEN_BITFIELD( 0, 0) ; //!< HEVC pipeline Done 1560 uint32_t VdencPipelineDone : __CODEGEN_BITFIELD( 1, 1) ; //!< VD-ENC pipeline Done 1561 uint32_t MflPipelineDone : __CODEGEN_BITFIELD( 2, 2) ; //!< MFL pipeline Done 1562 uint32_t MfxPipelineDone : __CODEGEN_BITFIELD( 3, 3) ; //!< MFX pipeline Done 1563 uint32_t VdCommandMessageParserDone : __CODEGEN_BITFIELD( 4, 4) ; //!< VD command/message parser Done 1564 uint32_t Reserved37 : __CODEGEN_BITFIELD( 5, 15) ; //!< Reserved 1565 uint32_t HevcPipelineCommandFlush : __CODEGEN_BITFIELD(16, 16) ; //!< HEVC pipeline command flush 1566 uint32_t VdencPipelineCommandFlush : __CODEGEN_BITFIELD(17, 17) ; //!< VD-ENC pipeline command flush 1567 uint32_t MflPipelineCommandFlush : __CODEGEN_BITFIELD(18, 18) ; //!< MFL pipeline command flush 1568 uint32_t MfxPipelineCommandFlush : __CODEGEN_BITFIELD(19, 19) ; //!< MFX pipeline command flush 1569 uint32_t Reserved52 : __CODEGEN_BITFIELD(20, 31) ; //!< Reserved 1570 }; 1571 uint32_t Value; 1572 } DW1; 1573 1574 //! \name Local enumerations 1575 1576 //! \brief DWORD_COUNT_N 1577 //! \details 1578 //! Total Length - 2 1579 enum DWORD_COUNT_N 1580 { 1581 DWORD_COUNT_N_EXCLUDESDWORD_0 = 0, //!< No additional details 1582 }; 1583 1584 enum SUBOPCODEB 1585 { 1586 SUBOPCODEB_UNNAMED0 = 0, //!< No additional details 1587 }; 1588 1589 enum SUBOPCODEA 1590 { 1591 SUBOPCODEA_UNNAMED0 = 0, //!< No additional details 1592 }; 1593 1594 enum MEDIA_COMMAND_OPCODE 1595 { 1596 MEDIA_COMMAND_OPCODE_EXTENDEDCOMMAND = 15, //!< No additional details 1597 }; 1598 1599 enum PIPELINE 1600 { 1601 PIPELINE_MEDIA = 2, //!< No additional details 1602 }; 1603 1604 enum COMMAND_TYPE 1605 { 1606 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1607 }; 1608 1609 //! \name Initializations 1610 1611 //! \brief Explicit member initialization function 1612 VD_PIPELINE_FLUSH_CMD(); 1613 1614 static const size_t dwSize = 2; 1615 static const size_t byteSize = 8; 1616 }; 1617 1618 //! 1619 //! \brief VDENC_WEIGHTSOFFSETS_STATE 1620 //! \details 1621 //! 1622 //! 1623 struct VDENC_WEIGHTSOFFSETS_STATE_CMD 1624 { 1625 union 1626 { 1627 //!< DWORD 0 1628 struct 1629 { 1630 uint32_t DwLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DW_LENGTH 1631 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1632 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 1633 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 1634 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 1635 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1636 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1637 }; 1638 uint32_t Value; 1639 } DW0; 1640 union 1641 { 1642 //!< DWORD 1 1643 struct 1644 { 1645 uint32_t WeightsForwardReference0 : __CODEGEN_BITFIELD( 0, 7) ; //!< Weights Forward Reference0 1646 uint32_t OffsetForwardReference0 : __CODEGEN_BITFIELD( 8, 15) ; //!< Offset Forward Reference0 1647 uint32_t WeightsForwardReference1 : __CODEGEN_BITFIELD(16, 23) ; //!< Weights Forward Reference1 1648 uint32_t OffsetForwardReference1 : __CODEGEN_BITFIELD(24, 31) ; //!< Offset Forward Reference1 1649 }; 1650 uint32_t Value; 1651 } DW1; 1652 union 1653 { 1654 //!< DWORD 2 1655 struct 1656 { 1657 uint32_t WeightsForwardReference2 : __CODEGEN_BITFIELD( 0, 7) ; //!< Weights Forward Reference2 1658 uint32_t OffsetForwardReference2 : __CODEGEN_BITFIELD( 8, 15) ; //!< Offset Forward Reference2 1659 uint32_t HevcVp9WeightsBackwardReference0 : __CODEGEN_BITFIELD(16, 23) ; //!< HEVC/VP9 Weights Backward Reference0 1660 uint32_t HevcVp9OffsetBackwardReference0 : __CODEGEN_BITFIELD(24, 31) ; //!< HEVC/VP9 Offset Backward Reference0 1661 }; 1662 uint32_t Value; 1663 } DW2; 1664 union 1665 { 1666 //!< DWORD 3 1667 struct 1668 { 1669 uint32_t HevcVp9WeightsForwardReference0 : __CODEGEN_BITFIELD( 0, 7) ; //!< HEVC/VP9 Weights Forward Reference0 1670 uint32_t HevcVp9OffsetForwardReference0 : __CODEGEN_BITFIELD( 8, 15) ; //!< HEVC/VP9 Offset Forward Reference0 1671 uint32_t HevcVp9WeightsForwardReference1 : __CODEGEN_BITFIELD(16, 23) ; //!< HEVC/VP9 Weights Forward Reference1 1672 uint32_t HevcVp9OffsetForwardReference1 : __CODEGEN_BITFIELD(24, 31) ; //!< HEVC/VP9 Offset Forward Reference1 1673 }; 1674 uint32_t Value; 1675 } DW3; 1676 union 1677 { 1678 //!< DWORD 4 1679 struct 1680 { 1681 uint32_t HevcVp9WeightsForwardReference2 : __CODEGEN_BITFIELD( 0, 7) ; //!< HEVC/VP9 Weights Forward Reference2 1682 uint32_t HevcVp9OffsetForwardReference2 : __CODEGEN_BITFIELD( 8, 15) ; //!< HEVC/VP9 Offset Forward Reference2 1683 uint32_t HevcVp9WeightsBackwardReference0 : __CODEGEN_BITFIELD(16, 23) ; //!< HEVC/VP9 Weights Backward Reference0 1684 uint32_t HevcVp9OffsetBackwardReference0 : __CODEGEN_BITFIELD(24, 31) ; //!< HEVC/VP9 Offset Backward Reference0 1685 }; 1686 uint32_t Value; 1687 } DW4; 1688 1689 //! \name Local enumerations 1690 1691 //! \brief DW_LENGTH 1692 //! \details 1693 //! Total Length - 2 1694 enum DW_LENGTH 1695 { 1696 DW_LENGTH_DWORDCOUNTN = 1, //!< Excludes DWord (0,1) 1697 }; 1698 1699 enum SUBOPB 1700 { 1701 SUBOPB_VDENCAVCWEIGHTSOFFSETSTATE = 8, //!< No additional details 1702 }; 1703 1704 enum SUBOPA 1705 { 1706 SUBOPA_UNNAMED0 = 0, //!< No additional details 1707 }; 1708 1709 enum OPCODE 1710 { 1711 OPCODE_VDENCPIPE = 1, //!< No additional details 1712 }; 1713 1714 enum PIPELINE 1715 { 1716 PIPELINE_MFXCOMMON = 2, //!< No additional details 1717 }; 1718 1719 enum COMMAND_TYPE 1720 { 1721 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1722 }; 1723 1724 //! \name Initializations 1725 1726 //! \brief Explicit member initialization function 1727 VDENC_WEIGHTSOFFSETS_STATE_CMD(); 1728 1729 static const size_t dwSize = 5; 1730 static const size_t byteSize = 20; 1731 }; 1732 1733 //! 1734 //! \brief VDENC_CONST_QPT_STATE 1735 //! \details 1736 //! This commands provides the tables for frame constants to the VDEnc HW. 1737 //! The specific parameter value is picked by the VDEnc HW based on the 1738 //! frame level QP. The QP Lambda array for costing (motion-vectors and mode 1739 //! costs) has 42 entires. Skip Threshold tables has 27 entries. 7 FTQ 1740 //! thresholds [0-6] are programmed using 4 sets of tables with 27 entires 1741 //! each. 1742 //! 1743 struct VDENC_CONST_QPT_STATE_CMD 1744 { 1745 union 1746 { 1747 //!< DWORD 0 1748 struct 1749 { 1750 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1751 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1752 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 1753 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 1754 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 1755 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1756 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1757 }; 1758 uint32_t Value; 1759 } DW0; 1760 union { 1761 //!< DWORD 1..10 1762 struct { 1763 uint8_t QpLambdaArrayIndex[40]; //!< QP Lambda Array Index[n] 1764 }; 1765 uint32_t Value[10]; 1766 } DW1_10; 1767 union { 1768 //!< DWORD 11 1769 struct { 1770 uint32_t QpLambdaArrayIndex40 : __CODEGEN_BITFIELD(0, 7); 1771 uint32_t QpLambdaArrayIndex41 : __CODEGEN_BITFIELD(8, 15); 1772 uint32_t Reserved : __CODEGEN_BITFIELD(16, 31); 1773 }; 1774 uint32_t Value; 1775 } DW11; 1776 union { 1777 //!< DWORD 12..24 1778 struct { 1779 uint16_t SkipThresholdArrayIndex[26]; //!< Skip Threshold Array Index[n] 1780 }; 1781 uint32_t Value[13]; 1782 } DW12_24; 1783 union { 1784 //!< DWORD 25 1785 struct { 1786 uint32_t SkipThresholdArrayIndex26 : __CODEGEN_BITFIELD(0, 15); 1787 uint32_t Reserved : __CODEGEN_BITFIELD(16, 31); 1788 }; 1789 uint32_t Value; 1790 } DW25; 1791 union { 1792 //!< DWORD 26..38 1793 struct { 1794 uint16_t SicForwardTransformCoeffThresholdMatrix0ArrayIndex[26]; //!< SIC Forward Transform Coeff Threshold Matrix0 Array Index[n] 1795 }; 1796 uint32_t Value[13]; 1797 } DW26_38; 1798 union { 1799 //!< DWORD 39 1800 struct { 1801 uint32_t SicForwardTransformCoeffThresholdMatrix0ArrayIndex26 : __CODEGEN_BITFIELD(0, 15); 1802 uint32_t Reserved : __CODEGEN_BITFIELD(16, 31); 1803 }; 1804 uint32_t Value; 1805 } DW39; 1806 union { 1807 //!< DWORD 40..45 1808 struct { 1809 uint8_t SicForwardTransformCoeffThresholdMatrix135ArrayIndexN[24]; //!< SIC Forward Transform Coeff Threshold Matrix1/3/5 Array Index[n] 1810 }; 1811 uint32_t Value[6]; 1812 } DW40_45; 1813 union { 1814 //!< DWORD 46 1815 struct { 1816 uint32_t SicForwardTransformCoeffThresholdMatrix135ArrayIndex24 : __CODEGEN_BITFIELD(0, 7); 1817 uint32_t SicForwardTransformCoeffThresholdMatrix135ArrayIndex25 : __CODEGEN_BITFIELD(8, 15); 1818 uint32_t SicForwardTransformCoeffThresholdMatrix135ArrayIndex26 : __CODEGEN_BITFIELD(16, 23); 1819 uint32_t Reserved : __CODEGEN_BITFIELD(24, 31); 1820 }; 1821 uint32_t Value; 1822 } DW46; 1823 union { 1824 //!< DWORD 47..52 1825 struct { 1826 uint8_t SicForwardTransformCoeffThresholdMatrix2ArrayIndex[24]; //!< SIC Forward Transform Coeff Threshold Matrix2 Array Index[n] 1827 }; 1828 uint32_t Value[6]; 1829 } DW47_52; 1830 union { 1831 //!< DWORD 53 1832 struct { 1833 uint32_t SicForwardTransformCoeffThresholdMatrix2ArrayIndex24 : __CODEGEN_BITFIELD(0, 7); 1834 uint32_t SicForwardTransformCoeffThresholdMatrix2ArrayIndex25 : __CODEGEN_BITFIELD(8, 15); 1835 uint32_t SicForwardTransformCoeffThresholdMatrix2ArrayIndex26 : __CODEGEN_BITFIELD(16, 23); 1836 uint32_t Reserved : __CODEGEN_BITFIELD(24, 31); 1837 }; 1838 uint32_t Value; 1839 } DW53; 1840 union { 1841 //!< DWORD 54..59 1842 struct { 1843 uint8_t SicForwardTransformCoeffThresholdMatrix46ArrayIndexN[24]; //!< SIC Forward Transform Coeff Threshold Matrix4/6 Array Index[n] 1844 }; 1845 uint32_t Value[6]; 1846 } DW54_59; 1847 union { 1848 //!< DWORD 60 1849 struct { 1850 uint32_t SicForwardTransformCoeffThresholdMatrix46ArrayIndex24 : __CODEGEN_BITFIELD(0, 7); 1851 uint32_t SicForwardTransformCoeffThresholdMatrix46ArrayIndex25 : __CODEGEN_BITFIELD(8, 15); 1852 uint32_t SicForwardTransformCoeffThresholdMatrix46ArrayIndex26 : __CODEGEN_BITFIELD(16, 23); 1853 uint32_t Reserved : __CODEGEN_BITFIELD(24, 31); 1854 }; 1855 uint32_t Value; 1856 } DW60; 1857 1858 //! \name Local enumerations 1859 1860 enum SUBOPB 1861 { 1862 SUBOPB_VDENCCONSTQPTSTATE = 6, //!< No additional details 1863 }; 1864 1865 enum SUBOPA 1866 { 1867 SUBOPA_UNNAMED0 = 0, //!< No additional details 1868 }; 1869 1870 enum OPCODE 1871 { 1872 OPCODE_VDENCPIPE = 1, //!< No additional details 1873 }; 1874 1875 enum PIPELINE 1876 { 1877 PIPELINE_MFXCOMMON = 2, //!< No additional details 1878 }; 1879 1880 enum COMMAND_TYPE 1881 { 1882 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1883 }; 1884 1885 //! \name Initializations 1886 1887 //! \brief Explicit member initialization function 1888 VDENC_CONST_QPT_STATE_CMD(); 1889 1890 static const size_t dwSize = 61; 1891 static const size_t byteSize = 244; 1892 }; 1893 1894 //! 1895 //! \brief VDENC_DS_REF_SURFACE_STATE 1896 //! \details 1897 //! This command specifies the surface state parameters for the downscaled 1898 //! reference surfaces. 1899 //! 1900 struct VDENC_DS_REF_SURFACE_STATE_CMD 1901 { 1902 union 1903 { 1904 //!< DWORD 0 1905 struct 1906 { 1907 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1908 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1909 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 1910 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 1911 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 1912 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1913 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1914 }; 1915 uint32_t Value; 1916 } DW0; 1917 union 1918 { 1919 //!< DWORD 1 1920 struct 1921 { 1922 uint32_t Reserved32 ; //!< Reserved 1923 }; 1924 uint32_t Value; 1925 } DW1; 1926 VDENC_Surface_State_Fields_CMD Dwords25 ; //!< Dwords 2..5 1927 VDENC_Surface_State_Fields_CMD Dwords69 ; //!< Dwords 6..9 1928 1929 //! \name Local enumerations 1930 1931 enum SUBOPB 1932 { 1933 SUBOPB_VDENCDSREFSURFACESTATE = 3, //!< No additional details 1934 }; 1935 1936 enum SUBOPA 1937 { 1938 SUBOPA_UNNAMED0 = 0, //!< No additional details 1939 }; 1940 1941 enum OPCODE 1942 { 1943 OPCODE_VDENCPIPE = 1, //!< No additional details 1944 }; 1945 1946 enum PIPELINE 1947 { 1948 PIPELINE_MFXCOMMON = 2, //!< No additional details 1949 }; 1950 1951 enum COMMAND_TYPE 1952 { 1953 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1954 }; 1955 1956 //! \name Initializations 1957 1958 //! \brief Explicit member initialization function 1959 VDENC_DS_REF_SURFACE_STATE_CMD(); 1960 1961 static const size_t dwSize = 10; 1962 static const size_t byteSize = 40; 1963 }; 1964 1965 //! 1966 //! \brief VDENC_IMG_STATE 1967 //! \details 1968 //! This command programs the frame level parameters required by the VDEnc 1969 //! pipeline. 1970 //! 1971 struct VDENC_IMG_STATE_CMD 1972 { 1973 union 1974 { 1975 //!< DWORD 0 1976 struct 1977 { 1978 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1979 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1980 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 1981 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 1982 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 1983 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1984 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1985 }; 1986 uint32_t Value; 1987 } DW0; 1988 union 1989 { 1990 //!< DWORD 1 1991 struct 1992 { 1993 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 1994 uint32_t BidirectionalMixDisable : __CODEGEN_BITFIELD( 2, 2) ; //!< BIDIRECTIONAL_MIX_DISABLE 1995 uint32_t VdencPerfmode : __CODEGEN_BITFIELD( 3, 3) ; //!< VDENC_PERFMODE 1996 uint32_t TimeBudgetOverflowCheck : __CODEGEN_BITFIELD( 4, 4) ; //!< TIME_BUDGET_OVERFLOW_CHECK 1997 uint32_t Reserved37 : __CODEGEN_BITFIELD( 5, 5) ; //!< Reserved 1998 uint32_t VdencExtendedPakObjCmdEnable : __CODEGEN_BITFIELD( 6, 6) ; //!< VDENC_EXTENDED_PAK_OBJ_CMD_ENABLE 1999 uint32_t Transform8X8Flag : __CODEGEN_BITFIELD( 7, 7) ; //!< TRANSFORM_8X8_FLAG 2000 uint32_t VdencL1CachePriority : __CODEGEN_BITFIELD( 8, 9) ; //!< VDENC_L1_CACHE_PRIORITY 2001 uint32_t Reserved42 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 2002 uint32_t LambdaValueForTrellis : __CODEGEN_BITFIELD(16, 31) ; //!< Lambda value for Trellis 2003 }; 2004 uint32_t Value; 2005 } DW1; 2006 union 2007 { 2008 //!< DWORD 2 2009 struct 2010 { 2011 uint32_t Reserved64 : __CODEGEN_BITFIELD( 0, 15) ; //!< Reserved 2012 uint32_t BidirectionalWeight : __CODEGEN_BITFIELD(16, 21) ; //!< BIDIRECTIONAL_WEIGHT 2013 uint32_t Reserved86 : __CODEGEN_BITFIELD(22, 27) ; //!< Reserved 2014 uint32_t UnidirectionalMixDisable : __CODEGEN_BITFIELD(28, 28) ; //!< Unidirectional Mix Disable 2015 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 2016 }; 2017 uint32_t Value; 2018 } DW2; 2019 union 2020 { 2021 //!< DWORD 3 2022 struct 2023 { 2024 uint32_t Reserved96 : __CODEGEN_BITFIELD( 0, 15) ; //!< Reserved 2025 uint32_t PictureWidth : __CODEGEN_BITFIELD(16, 31) ; //!< Picture Width 2026 }; 2027 uint32_t Value; 2028 } DW3; 2029 union 2030 { 2031 //!< DWORD 4 2032 struct 2033 { 2034 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 2035 uint32_t SubPelMode : __CODEGEN_BITFIELD(12, 13) ; //!< SUB_PEL_MODE 2036 uint32_t Reserved142 : __CODEGEN_BITFIELD(14, 16) ; //!< Reserved 2037 uint32_t ForwardTransformSkipCheckEnable : __CODEGEN_BITFIELD(17, 17) ; //!< FORWARD_TRANSFORM_SKIP_CHECK_ENABLE 2038 uint32_t BmeDisableForFbrMessage : __CODEGEN_BITFIELD(18, 18) ; //!< BME_DISABLE_FOR_FBR_MESSAGE 2039 uint32_t BlockBasedSkipEnabled : __CODEGEN_BITFIELD(19, 19) ; //!< BLOCK_BASED_SKIP_ENABLED 2040 uint32_t InterSadMeasureAdjustment : __CODEGEN_BITFIELD(20, 21) ; //!< INTER_SAD_MEASURE_ADJUSTMENT 2041 uint32_t IntraSadMeasureAdjustment : __CODEGEN_BITFIELD(22, 23) ; //!< INTRA_SAD_MEASURE_ADJUSTMENT 2042 uint32_t SubMacroblockSubPartitionMask : __CODEGEN_BITFIELD(24, 30) ; //!< SUB_MACROBLOCK_SUB_PARTITION_MASK 2043 uint32_t BlockBasedSkipType : __CODEGEN_BITFIELD(31, 31) ; //!< BLOCK_BASED_SKIP_TYPE 2044 }; 2045 uint32_t Value; 2046 } DW4; 2047 union 2048 { 2049 //!< DWORD 5 2050 struct 2051 { 2052 uint32_t PictureHeightMinusOne : __CODEGEN_BITFIELD( 0, 15) ; //!< Picture Height Minus One 2053 uint32_t CrePrefetchEnable : __CODEGEN_BITFIELD(16, 16) ; //!< CRE_PREFETCH_ENABLE 2054 uint32_t HmeRef1Disable : __CODEGEN_BITFIELD(17, 17) ; //!< HME_REF1_DISABLE 2055 uint32_t MbSliceThresholdValue : __CODEGEN_BITFIELD(18, 21) ; //!< MB Slice Threshold Value 2056 uint32_t Reserved182 : __CODEGEN_BITFIELD(22, 25) ; //!< Reserved 2057 uint32_t ConstrainedIntraPredictionFlag : __CODEGEN_BITFIELD(26, 26) ; //!< CONSTRAINED_INTRA_PREDICTION_FLAG 2058 uint32_t Reserved187 : __CODEGEN_BITFIELD(27, 28) ; //!< Reserved 2059 uint32_t PictureType : __CODEGEN_BITFIELD(29, 30) ; //!< PICTURE_TYPE 2060 uint32_t Reserved191 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 2061 }; 2062 uint32_t Value; 2063 } DW5; 2064 union 2065 { 2066 //!< DWORD 6 2067 struct 2068 { 2069 uint32_t SliceMacroblockHeightMinusOne : __CODEGEN_BITFIELD( 0, 15) ; //!< Slice Macroblock Height Minus One 2070 uint32_t Reserved208 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 2071 }; 2072 uint32_t Value; 2073 } DW6; 2074 union 2075 { 2076 //!< DWORD 7 2077 struct 2078 { 2079 uint32_t Hme0XOffset : __CODEGEN_BITFIELD( 0, 7) ; //!< HME0 X Offset 2080 uint32_t Hme0YOffset : __CODEGEN_BITFIELD( 8, 15) ; //!< HME0 Y Offset 2081 uint32_t Hme1XOffset : __CODEGEN_BITFIELD(16, 23) ; //!< HME1 X Offset 2082 uint32_t Hme1YOffset : __CODEGEN_BITFIELD(24, 31) ; //!< HME1 Y Offset 2083 }; 2084 uint32_t Value; 2085 } DW7; 2086 union 2087 { 2088 //!< DWORD 8 2089 struct 2090 { 2091 uint32_t LumaIntraPartitionMask : __CODEGEN_BITFIELD( 0, 4) ; //!< LUMA_INTRA_PARTITION_MASK 2092 uint32_t NonSkipZeroMvCostAdded : __CODEGEN_BITFIELD( 5, 5) ; //!< Non Skip Zero MV Cost Added 2093 uint32_t NonSkipMbModeCostAdded : __CODEGEN_BITFIELD( 6, 6) ; //!< Non Skip MB Mode Cost Added 2094 uint32_t Reserved263 : __CODEGEN_BITFIELD( 7, 15) ; //!< Reserved 2095 uint32_t MvCostScalingFactor : __CODEGEN_BITFIELD(16, 17) ; //!< MV_COST_SCALING_FACTOR 2096 uint32_t BilinearFilterEnable : __CODEGEN_BITFIELD(18, 18) ; //!< BiLinear Filter Enable 2097 uint32_t Reserved275 : __CODEGEN_BITFIELD(19, 21) ; //!< Reserved 2098 uint32_t RefidCostModeSelect : __CODEGEN_BITFIELD(22, 22) ; //!< REFID_COST_MODE_SELECT 2099 uint32_t Reserved279 : __CODEGEN_BITFIELD(23, 31) ; //!< Reserved 2100 }; 2101 uint32_t Value; 2102 } DW8; 2103 union 2104 { 2105 //!< DWORD 9 2106 struct 2107 { 2108 uint32_t Mode0Cost : __CODEGEN_BITFIELD( 0, 7) ; //!< Mode 0 Cost 2109 uint32_t Mode1Cost : __CODEGEN_BITFIELD( 8, 15) ; //!< Mode 1 Cost 2110 uint32_t Mode2Cost : __CODEGEN_BITFIELD(16, 23) ; //!< Mode 2 Cost 2111 uint32_t Mode3Cost : __CODEGEN_BITFIELD(24, 31) ; //!< Mode 3 Cost 2112 }; 2113 uint32_t Value; 2114 } DW9; 2115 union 2116 { 2117 //!< DWORD 10 2118 struct 2119 { 2120 uint32_t Mode4Cost : __CODEGEN_BITFIELD( 0, 7) ; //!< Mode 4 Cost 2121 uint32_t Mode5Cost : __CODEGEN_BITFIELD( 8, 15) ; //!< Mode 5 Cost 2122 uint32_t Mode6Cost : __CODEGEN_BITFIELD(16, 23) ; //!< Mode 6 Cost 2123 uint32_t Mode7Cost : __CODEGEN_BITFIELD(24, 31) ; //!< Mode 7 Cost 2124 }; 2125 uint32_t Value; 2126 } DW10; 2127 union 2128 { 2129 //!< DWORD 11 2130 struct 2131 { 2132 uint32_t Mode8Cost : __CODEGEN_BITFIELD( 0, 7) ; //!< Mode 8 Cost 2133 uint32_t Mode9Cost : __CODEGEN_BITFIELD( 8, 15) ; //!< Mode 9 Cost 2134 uint32_t RefIdCost : __CODEGEN_BITFIELD(16, 23) ; //!< RefID Cost 2135 uint32_t ChromaIntraModeCost : __CODEGEN_BITFIELD(24, 31) ; //!< Chroma Intra Mode Cost 2136 }; 2137 uint32_t Value; 2138 } DW11; 2139 union 2140 { 2141 //!< DWORD 12 2142 struct 2143 { 2144 uint32_t MvCost0 : __CODEGEN_BITFIELD( 0, 7) ; //!< MvCost 0 2145 uint32_t MvCost1 : __CODEGEN_BITFIELD( 8, 15) ; //!< MvCost 1 2146 uint32_t MvCost2 : __CODEGEN_BITFIELD(16, 23) ; //!< MvCost 2 2147 uint32_t MvCost3 : __CODEGEN_BITFIELD(24, 31) ; //!< MvCost 3 2148 }; 2149 uint32_t Value; 2150 } DW12; 2151 union 2152 { 2153 //!< DWORD 13 2154 struct 2155 { 2156 uint32_t MvCost4 : __CODEGEN_BITFIELD( 0, 7) ; //!< MvCost 4 2157 uint32_t MvCost5 : __CODEGEN_BITFIELD( 8, 15) ; //!< MvCost 5 2158 uint32_t MvCost6 : __CODEGEN_BITFIELD(16, 23) ; //!< MvCost 6 2159 uint32_t MvCost7 : __CODEGEN_BITFIELD(24, 31) ; //!< MvCost 7 2160 }; 2161 uint32_t Value; 2162 } DW13; 2163 union 2164 { 2165 //!< DWORD 14 2166 struct 2167 { 2168 uint32_t QpPrimeY : __CODEGEN_BITFIELD( 0, 7) ; //!< QpPrimeY 2169 uint32_t Reserved456 : __CODEGEN_BITFIELD( 8, 23) ; //!< Reserved 2170 uint32_t TargetSizeInWord : __CODEGEN_BITFIELD(24, 31) ; //!< TargetSizeInWord 2171 }; 2172 uint32_t Value; 2173 } DW14; 2174 union 2175 { 2176 //!< DWORD 15 2177 struct 2178 { 2179 uint32_t Reserved480 ; //!< Reserved 2180 }; 2181 uint32_t Value; 2182 } DW15; 2183 union 2184 { 2185 //!< DWORD 16 2186 struct 2187 { 2188 uint32_t Reserved512 ; //!< Reserved 2189 }; 2190 uint32_t Value; 2191 } DW16; 2192 union 2193 { 2194 //!< DWORD 17 2195 struct 2196 { 2197 uint32_t AvcIntra4X4ModeMask : __CODEGEN_BITFIELD( 0, 8) ; //!< AVC Intra 4x4 Mode Mask 2198 uint32_t Reserved553 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved 2199 uint32_t AvcIntra8X8ModeMask : __CODEGEN_BITFIELD(16, 24) ; //!< AVC Intra 8x8 Mode Mask 2200 uint32_t Reserved569 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 2201 }; 2202 uint32_t Value; 2203 } DW17; 2204 union 2205 { 2206 //!< DWORD 18 2207 struct 2208 { 2209 uint32_t AvcIntra16X16ModeMask : __CODEGEN_BITFIELD( 0, 3) ; //!< AVC_INTRA_16X16_MODE_MASK 2210 uint32_t AvcIntraChromaModeMask : __CODEGEN_BITFIELD( 4, 7) ; //!< AVC_INTRA_CHROMA_MODE_MASK 2211 uint32_t IntraComputeTypeIntracomputetype : __CODEGEN_BITFIELD( 8, 9) ; //!< INTRA_COMPUTE_TYPE_INTRACOMPUTETYPE 2212 uint32_t Reserved586 : __CODEGEN_BITFIELD(10, 31) ; //!< Reserved 2213 }; 2214 uint32_t Value; 2215 } DW18; 2216 union 2217 { 2218 //!< DWORD 19 2219 struct 2220 { 2221 uint32_t Reserved608 ; //!< Reserved 2222 }; 2223 uint32_t Value; 2224 } DW19; 2225 union 2226 { 2227 //!< DWORD 20 2228 struct 2229 { 2230 uint32_t PenaltyForIntra16X16NondcPrediction : __CODEGEN_BITFIELD( 0, 7) ; //!< Penalty for Intra16x16 NonDC Prediction. 2231 uint32_t PenaltyForIntra8X8NondcPrediction : __CODEGEN_BITFIELD( 8, 15) ; //!< Penalty for Intra8x8 NonDC Prediction. 2232 uint32_t PenaltyForIntra4X4NondcPrediction : __CODEGEN_BITFIELD(16, 23) ; //!< Penalty for Intra4x4 NonDC Prediction. 2233 uint32_t Reserved664 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 2234 }; 2235 uint32_t Value; 2236 } DW20; 2237 union 2238 { 2239 //!< DWORD 21 2240 struct 2241 { 2242 uint32_t IntraRefreshMBPos : __CODEGEN_BITFIELD( 0, 7) ; //!< IntraRefreshMBPos 2243 uint32_t IntraRefreshMBSizeMinusOne : __CODEGEN_BITFIELD( 8, 15) ; //!< IntraRefreshMBSizeMinusOne 2244 uint32_t IntraRefreshEnableRollingIEnable : __CODEGEN_BITFIELD(16, 16) ; //!< INTRAREFRESHENABLE_ROLLING_I_ENABLE 2245 uint32_t IntraRefreshMode : __CODEGEN_BITFIELD(17, 17) ; //!< INTRAREFRESHMODE 2246 uint32_t Reserved690 : __CODEGEN_BITFIELD(18, 23) ; //!< Reserved 2247 uint32_t QpAdjustmentForRollingI : __CODEGEN_BITFIELD(24, 31) ; //!< QP adjustment for Rolling-I 2248 }; 2249 uint32_t Value; 2250 } DW21; 2251 union 2252 { 2253 //!< DWORD 22 2254 struct 2255 { 2256 uint32_t Panicmodembthreshold : __CODEGEN_BITFIELD( 0, 15) ; //!< PanicModeMBThreshold 2257 uint32_t Smallmbsizeinword : __CODEGEN_BITFIELD(16, 23) ; //!< SmallMbSizeInWord 2258 uint32_t Largembsizeinword : __CODEGEN_BITFIELD(24, 31) ; //!< LargeMbSizeInWord 2259 }; 2260 uint32_t Value; 2261 } DW22; 2262 union 2263 { 2264 //!< DWORD 23 2265 struct 2266 { 2267 uint32_t L0NumberOfReferencesMinusOne : __CODEGEN_BITFIELD( 0, 7) ; //!< L0 number of references Minus one 2268 uint32_t Reserved744 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 2269 uint32_t L1NumberOfReferencesMinusOne : __CODEGEN_BITFIELD(16, 23) ; //!< L1 number of references Minus One 2270 uint32_t Reserved760 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 2271 }; 2272 uint32_t Value; 2273 } DW23; 2274 union 2275 { 2276 //!< DWORD 24 2277 struct 2278 { 2279 uint32_t MacroblockBudget : __CODEGEN_BITFIELD( 0, 15) ; //!< Macroblock Budget 2280 uint32_t InitialTime : __CODEGEN_BITFIELD(16, 31) ; //!< Initial Time 2281 }; 2282 uint32_t Value; 2283 } DW24; 2284 union 2285 { 2286 //!< DWORD 25 2287 struct 2288 { 2289 uint32_t Reserved800 ; //!< Reserved 2290 }; 2291 uint32_t Value; 2292 } DW25; 2293 union 2294 { 2295 //!< DWORD 26 2296 struct 2297 { 2298 uint32_t Reserved832 : __CODEGEN_BITFIELD( 0, 7) ; //!< Reserved 2299 uint32_t HmeRefWindowsCombiningThreshold : __CODEGEN_BITFIELD( 8, 15) ; //!< HME_REF_WINDOWS_COMBINING_THRESHOLD 2300 uint32_t Reserved848 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 2301 }; 2302 uint32_t Value; 2303 } DW26; 2304 union 2305 { 2306 //!< DWORD 27 2307 struct 2308 { 2309 uint32_t MaxHmvR : __CODEGEN_BITFIELD( 0, 15) ; //!< MAXHMVR 2310 uint32_t MaxVmvR : __CODEGEN_BITFIELD(16, 31) ; //!< MAXVMVR 2311 }; 2312 uint32_t Value; 2313 } DW27; 2314 union 2315 { 2316 //!< DWORD 28 2317 struct 2318 { 2319 uint32_t HmeMvCost0 : __CODEGEN_BITFIELD( 0, 7) ; //!< HmeMvCost 0 2320 uint32_t HmeMvCost1 : __CODEGEN_BITFIELD( 8, 15) ; //!< HmeMvCost 1 2321 uint32_t HmeMvCost2 : __CODEGEN_BITFIELD(16, 23) ; //!< HmeMvCost 2 2322 uint32_t HmeMvCost3 : __CODEGEN_BITFIELD(24, 31) ; //!< HmeMvCost 3 2323 }; 2324 uint32_t Value; 2325 } DW28; 2326 union 2327 { 2328 //!< DWORD 29 2329 struct 2330 { 2331 uint32_t HmeMvCost4 : __CODEGEN_BITFIELD( 0, 7) ; //!< HmeMvCost 4 2332 uint32_t HmeMvCost5 : __CODEGEN_BITFIELD( 8, 15) ; //!< HmeMvCost 5 2333 uint32_t HmeMvCost6 : __CODEGEN_BITFIELD(16, 23) ; //!< HmeMvCost 6 2334 uint32_t HmeMvCost7 : __CODEGEN_BITFIELD(24, 31) ; //!< HmeMvCost 7 2335 }; 2336 uint32_t Value; 2337 } DW29; 2338 union 2339 { 2340 //!< DWORD 30 2341 struct 2342 { 2343 uint32_t RoiQpAdjustmentForZone0 : __CODEGEN_BITFIELD( 0, 3) ; //!< ROI QP adjustment for Zone0 2344 uint32_t RoiQpAdjustmentForZone1 : __CODEGEN_BITFIELD( 4, 7) ; //!< ROI QP adjustment for Zone1 2345 uint32_t RoiQpAdjustmentForZone2 : __CODEGEN_BITFIELD( 8, 11) ; //!< ROI QP adjustment for Zone2 2346 uint32_t RoiQpAdjustmentForZone3 : __CODEGEN_BITFIELD(12, 15) ; //!< ROI QP adjustment for Zone3 2347 uint32_t QpAdjustmentForShapeBestIntra4X4Winner : __CODEGEN_BITFIELD(16, 19) ; //!< QP adjustment for shape best intra 4x4 winner 2348 uint32_t QpAdjustmentForShapeBestIntra8X8Winner : __CODEGEN_BITFIELD(20, 23) ; //!< QP adjustment for shape best intra 8x8 winner 2349 uint32_t QpAdjustmentForShapeBestIntra16X16Winner : __CODEGEN_BITFIELD(24, 27) ; //!< QP adjustment for shape best intra 16x16 winner 2350 uint32_t Reserved988 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 2351 }; 2352 uint32_t Value; 2353 } DW30; 2354 union 2355 { 2356 //!< DWORD 31 2357 struct 2358 { 2359 uint32_t BestdistortionQpAdjustmentForZone0 : __CODEGEN_BITFIELD( 0, 3) ; //!< BestDistortion QP adjustment for Zone0 2360 uint32_t BestdistortionQpAdjustmentForZone1 : __CODEGEN_BITFIELD( 4, 7) ; //!< BestDistortion QP adjustment for Zone1 2361 uint32_t BestdistortionQpAdjustmentForZone2 : __CODEGEN_BITFIELD( 8, 11) ; //!< BestDistortion QP adjustment for Zone2 2362 uint32_t BestdistortionQpAdjustmentForZone3 : __CODEGEN_BITFIELD(12, 15) ; //!< BestDistortion QP adjustment for Zone3 2363 uint32_t SadHaarThreshold0 : __CODEGEN_BITFIELD(16, 31) ; //!< Sad/Haar_Threshold_0 2364 }; 2365 uint32_t Value; 2366 } DW31; 2367 union 2368 { 2369 //!< DWORD 32 2370 struct 2371 { 2372 uint32_t SadHaarThreshold1 : __CODEGEN_BITFIELD( 0, 15) ; //!< Sad/Haar_Threshold_1 2373 uint32_t SadHaarThreshold2 : __CODEGEN_BITFIELD(16, 31) ; //!< Sad/Haar_Threshold_2 2374 }; 2375 uint32_t Value; 2376 } DW32; 2377 union 2378 { 2379 //!< DWORD 33 2380 struct 2381 { 2382 uint32_t MaxQp : __CODEGEN_BITFIELD( 0, 7) ; //!< MaxQP 2383 uint32_t MinQp : __CODEGEN_BITFIELD( 8, 15) ; //!< MinQP 2384 uint32_t Reserved1072 : __CODEGEN_BITFIELD(16, 23) ; //!< Reserved 2385 uint32_t Maxdeltaqp : __CODEGEN_BITFIELD(24, 27) ; //!< MaxDeltaQP 2386 uint32_t Reserved1084 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 2387 }; 2388 uint32_t Value; 2389 } DW33; 2390 union 2391 { 2392 //!< DWORD 34 2393 struct 2394 { 2395 uint32_t RoiEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< ROI_Enable 2396 uint32_t FwdPredictor0MvEnable : __CODEGEN_BITFIELD( 1, 1) ; //!< Fwd/Predictor0 MV Enable 2397 uint32_t BwdPredictor1MvEnable : __CODEGEN_BITFIELD( 2, 2) ; //!< Bwd/Predictor1 MV Enable 2398 uint32_t MbLevelQpEnable : __CODEGEN_BITFIELD( 3, 3) ; //!< MB Level QP Enable 2399 uint32_t TargetsizeinwordsmbMaxsizeinwordsmbEnable : __CODEGEN_BITFIELD( 4, 4) ; //!< TargetSizeinWordsMB/MaxSizeinWordsMB Enable 2400 uint32_t Reserverd : __CODEGEN_BITFIELD( 5, 7) ; //!< Reserverd 2401 uint32_t PpmvDisable : __CODEGEN_BITFIELD( 8, 8) ; //!< PPMV_DISABLE 2402 uint32_t CoefficientClampEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< Coefficient Clamp Enable 2403 uint32_t LongtermReferenceFrameBwdRef0Indicator : __CODEGEN_BITFIELD(10, 10) ; //!< LONGTERM_REFERENCE_FRAME_BWD_REF0_INDICATOR 2404 uint32_t LongtermReferenceFrameFwdRef2Indicator : __CODEGEN_BITFIELD(11, 11) ; //!< LONGTERM_REFERENCE_FRAME_FWD_REF2_INDICATOR 2405 uint32_t LongtermReferenceFrameFwdRef1Indicator : __CODEGEN_BITFIELD(12, 12) ; //!< LONGTERM_REFERENCE_FRAME_FWD_REF1_INDICATOR 2406 uint32_t LongtermReferenceFrameFwdRef0Indicator : __CODEGEN_BITFIELD(13, 13) ; //!< LONGTERM_REFERENCE_FRAME_FWD_REF0_INDICATOR 2407 uint32_t Reserved1102 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 2408 uint32_t MidpointSadHaar : __CODEGEN_BITFIELD(16, 31) ; //!< Midpoint sad/haar 2409 }; 2410 uint32_t Value; 2411 } DW34; 2412 2413 //! \name Local enumerations 2414 2415 enum SUBOPB 2416 { 2417 SUBOPB_VDENCIMGSTATE = 5, //!< No additional details 2418 }; 2419 2420 enum SUBOPA 2421 { 2422 SUBOPA_UNNAMED0 = 0, //!< No additional details 2423 }; 2424 2425 enum OPCODE 2426 { 2427 OPCODE_VDENCPIPE = 1, //!< No additional details 2428 }; 2429 2430 enum PIPELINE 2431 { 2432 PIPELINE_MFXCOMMON = 2, //!< No additional details 2433 }; 2434 2435 enum COMMAND_TYPE 2436 { 2437 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2438 }; 2439 2440 enum BIDIRECTIONAL_MIX_DISABLE 2441 { 2442 BIDIRECTIONAL_MIX_DISABLE_SUBBLOCKENABLED = 0, //!< Bidirectional decision on subblock level that bidirectional mode is enabled. 2443 BIDIRECTIONAL_MIX_DISABLE_WHOLEMACROBLOCKENABLED = 1, //!< Bidirectional decision on whole macroblock. 2444 }; 2445 2446 //! \brief VDENC_PERFMODE 2447 //! \details 2448 //! This bit indicates if VDEnc is configured for normal or speed mode of 2449 //! operation. 2450 enum VDENC_PERFMODE 2451 { 2452 VDENC_PERFMODE_NORMAL = 0, //!< VDEnc is running in normal mode. IME Search: 3x3 SU per each reference. HME Search: 88x92 search window per HME instance (0 & 1). 2453 VDENC_PERFMODE_SPEED = 1, //!< VDEnc is configured for speed mode. IME Search: 2x2 SU per each reference. HME Search: 48x92 search window per HME instance (0 & 1). 2454 }; 2455 2456 //! \brief TIME_BUDGET_OVERFLOW_CHECK 2457 //! \details 2458 //! <p>This bit enables the frame time budget detection in VDEnc.</p> 2459 //! <p>To detect if a Time Budget Overflow happened in a frame, SW 2460 //! can read "PAK_Stream-Out Report (Errors)" register in MFX. When Time 2461 //! budget overflow condition happens in the frame, this register bits 15:8 2462 //! indicate MB y position and bits 7:0 indicate MB x position where Time 2463 //! budget overflow occured. When there is no time budget overflow in a 2464 //! frame, "<span style="line-height: 20.7999992370605px;">PAK_Stream-Out 2465 //! Report (Errors)" register reads zero.</span></p> 2466 enum TIME_BUDGET_OVERFLOW_CHECK 2467 { 2468 TIME_BUDGET_OVERFLOW_CHECK_DISABLED = 0, //!< No additional details 2469 TIME_BUDGET_OVERFLOW_CHECK_ENABLED = 1, //!< No additional details 2470 }; 2471 2472 //! \brief VDENC_EXTENDED_PAK_OBJ_CMD_ENABLE 2473 //! \details 2474 //! This bit enables the distortion data to be populated in the VDenc PAK 2475 //! Obj inline data. 2476 enum VDENC_EXTENDED_PAK_OBJ_CMD_ENABLE 2477 { 2478 VDENC_EXTENDED_PAK_OBJ_CMD_ENABLE_DISABLE = 0, //!< The extra two DWS from VDEnc (MDC) to PAK will be Zero. 2479 VDENC_EXTENDED_PAK_OBJ_CMD_ENABLE_ENABLE = 1, //!< The last two DWs from VDEnc (MDC) to PAK will be populated with distortion data. (Defined in the PAK Object command DW 22,23.) 2480 }; 2481 2482 //! \brief TRANSFORM_8X8_FLAG 2483 //! \details 2484 //! 8x8 IDCT Transform Mode Flag, trans8x8_mode_flag specifies 8x8 IDCT 2485 //! transform may be used in this 2486 //! picture. It is set to the value of the syntax element in the 2487 //! current active PPS. 2488 enum TRANSFORM_8X8_FLAG 2489 { 2490 TRANSFORM_8X8_FLAG_DISABLED = 0, //!< No 8x8 IDCT Transform, only 4x4 IDCT transform blocks are present. 2491 TRANSFORM_8X8_FLAG_ENABLED = 1, //!< 8x8 Transform is allowed. 2492 }; 2493 2494 //! \brief VDENC_L1_CACHE_PRIORITY 2495 //! \details 2496 //! L1 Cache inside VDEnc has 3 clients - IME, CRE and VMC. These bits 2497 //! indicate the priority order for 2498 //! L1 cache to service the client requests. 2499 enum VDENC_L1_CACHE_PRIORITY 2500 { 2501 VDENC_L1_CACHE_PRIORITY_UNNAMED0 = 0, //!< CRE High Priority, VMC and IME round robin. 2502 VDENC_L1_CACHE_PRIORITY_UNNAMED1 = 1, //!< CRE and VMC round robin, IME low priority. 2503 VDENC_L1_CACHE_PRIORITY_UNNAMED2 = 2, //!< CRE High Priority, IME Medium, VMC Low. 2504 VDENC_L1_CACHE_PRIORITY_UNNAMED3 = 3, //!< VMC High Priority, CRE Medium, IME low. 2505 }; 2506 2507 //! \brief BIDIRECTIONAL_WEIGHT 2508 //! \details 2509 //! Default value: Depends on the distance between the B and reference 2510 //! pictures. 2511 enum BIDIRECTIONAL_WEIGHT 2512 { 2513 BIDIRECTIONAL_WEIGHT_UNNAMED16 = 16, //!< No additional details 2514 BIDIRECTIONAL_WEIGHT_UNNAMED21 = 21, //!< No additional details 2515 BIDIRECTIONAL_WEIGHT_UNNAMED32 = 32, //!< No additional details 2516 BIDIRECTIONAL_WEIGHT_UNNAMED43 = 43, //!< No additional details 2517 BIDIRECTIONAL_WEIGHT_UNNAMED48 = 48, //!< No additional details 2518 }; 2519 2520 //! \brief SUB_PEL_MODE 2521 //! \details 2522 //! This field defines the half/quarter pel modes. The mode is inclusive, 2523 //! i.e., higher precision mode samples lower precision locations. 2524 enum SUB_PEL_MODE 2525 { 2526 SUB_PEL_MODE_UNNAMED0 = 0, //!< Integer mode searching. 2527 SUB_PEL_MODE_UNNAMED1 = 1, //!< Half-pel mode searching. 2528 SUB_PEL_MODE_UNNAMED3 = 3, //!< Quarter-pel mode searching. 2529 }; 2530 2531 //! \brief FORWARD_TRANSFORM_SKIP_CHECK_ENABLE 2532 //! \details 2533 //! This field enables the forward transform calculation for skip check. It 2534 //! does not override the other 2535 //! skip calculations but it does decrease the performance marginally 2536 //! so don't enable it unless the transform is necessary. 2537 enum FORWARD_TRANSFORM_SKIP_CHECK_ENABLE 2538 { 2539 FORWARD_TRANSFORM_SKIP_CHECK_ENABLE_FTDISABLED = 0, //!< No additional details 2540 FORWARD_TRANSFORM_SKIP_CHECK_ENABLE_FTENABLED = 1, //!< No additional details 2541 }; 2542 2543 //! \brief BME_DISABLE_FOR_FBR_MESSAGE 2544 //! \details 2545 //! FBR messages that do not want bidirectional motion estimation performed 2546 //! will set this bit and VME will 2547 //! only perform fractional refinement on the shapes identified by 2548 //! subpredmode. Note: only the LSB of the 2549 //! subpredmode for each shape will be considered in FBR (a shape is 2550 //! either FWD or BWD as input of FBR, 2551 //! output however could change to BI if BME is enabled). 2552 enum BME_DISABLE_FOR_FBR_MESSAGE 2553 { 2554 BME_DISABLE_FOR_FBR_MESSAGE_BMEENABLED = 0, //!< No additional details 2555 BME_DISABLE_FOR_FBR_MESSAGE_BMEDISABLED = 1, //!< No additional details 2556 }; 2557 2558 //! \brief BLOCK_BASED_SKIP_ENABLED 2559 //! \details 2560 //! When this field is set on the skip thresholding passing criterion will 2561 //! be based on the maximal distortion 2562 //! of individual blocks (8x8's or 4x4's) instead of their sum (i.e. 2563 //! the distortion of 16x16). 2564 enum BLOCK_BASED_SKIP_ENABLED 2565 { 2566 BLOCK_BASED_SKIP_ENABLED_UNNAMED0 = 0, //!< 16x16 Block Based Skip threshold check. 2567 BLOCK_BASED_SKIP_ENABLED_BLOCK_BASEDSKIPTYPE = 1, //!< Parameter indicates 8x8 vs. 4x4 based check. 2568 }; 2569 2570 //! \brief INTER_SAD_MEASURE_ADJUSTMENT 2571 //! \details 2572 //! This field specifies distortion measure adjustments used for the motion 2573 //! search SAD comparison. 2574 //! This field applies to both luma and chroma inter measurement. 2575 enum INTER_SAD_MEASURE_ADJUSTMENT 2576 { 2577 INTER_SAD_MEASURE_ADJUSTMENT_NONE = 0, //!< No additional details 2578 INTER_SAD_MEASURE_ADJUSTMENT_HAARTRANSFORMADJUSTED = 2, //!< No additional details 2579 }; 2580 2581 //! \brief INTRA_SAD_MEASURE_ADJUSTMENT 2582 //! \details 2583 //! This field specifies distortion measure adjustments used for the motion 2584 //! search SAD comparison. 2585 //! This field applies to both luma and chroma intra measurement. 2586 enum INTRA_SAD_MEASURE_ADJUSTMENT 2587 { 2588 INTRA_SAD_MEASURE_ADJUSTMENT_NONE = 0, //!< No additional details 2589 INTRA_SAD_MEASURE_ADJUSTMENT_HAARTRANSFORMADJUSTED = 2, //!< No additional details 2590 }; 2591 2592 //! \brief SUB_MACROBLOCK_SUB_PARTITION_MASK 2593 //! \details 2594 //! This field defines the bit-mask for disabling 2595 //! <ul> 2596 //! <li>sub-partition (minor partition [30:28]) modes</li> 2597 //! <li>sub-macroblock (major partition [27:24]) modes</li> 2598 //! </ul> 2599 enum SUB_MACROBLOCK_SUB_PARTITION_MASK 2600 { 2601 SUB_MACROBLOCK_SUB_PARTITION_MASK_UNNAMED113 = 113, //!< 16x16 sub-macroblock disabled 2602 SUB_MACROBLOCK_SUB_PARTITION_MASK_UNNAMED114 = 114, //!< 2x(16x8) sub-macroblock within 16x16 disabled 2603 SUB_MACROBLOCK_SUB_PARTITION_MASK_UNNAMED116 = 116, //!< 2x(8x16) sub-macroblock within 16x16 disabled 2604 SUB_MACROBLOCK_SUB_PARTITION_MASK_UNNAMED120 = 120, //!< 1x(8x8) sub-partition for 4x(8x8) within 16x16 disabled 2605 }; 2606 2607 //! \brief BLOCK_BASED_SKIP_TYPE 2608 //! \details 2609 //! The skip thresholding passing criterion will be based on the maximal 2610 //! distortion of individual blocks 2611 //! (8x8's or 4x4's) instead of their sum (i.e. the distortion of 2612 //! 16x16). This field is only valid when 2613 //! <b>Block-Based Skip Enabled</b> = 1. 2614 enum BLOCK_BASED_SKIP_TYPE 2615 { 2616 BLOCK_BASED_SKIP_TYPE_UNNAMED0 = 0, //!< 4x4 block-based skip threshold check. 2617 BLOCK_BASED_SKIP_TYPE_UNNAMED1 = 1, //!< 8x8 block-based skip threshold check. 2618 }; 2619 2620 //! \brief CRE_PREFETCH_ENABLE 2621 //! \details 2622 //! This field determines if IME will prefetch the fractional CLs that are 2623 //! required by CRE ahead of time 2624 //! while fetching the reference windows around the IME predictors. The 2625 //! recommendation for driver is to 2626 //! always program this bit to 1 unless some usages restrict SubPelMode 2627 //! to be "<i>Integer mode searching</i>". 2628 enum CRE_PREFETCH_ENABLE 2629 { 2630 CRE_PREFETCH_ENABLE_UNNAMED0 = 0, //!< Disable 2631 CRE_PREFETCH_ENABLE_UNNAMED1 = 1, //!< Enable 2632 }; 2633 2634 //! \brief HME_REF1_DISABLE 2635 //! \details 2636 //! This field indicates if HME is disabled for reference 1 (second forward 2637 //! reference). 2638 enum HME_REF1_DISABLE 2639 { 2640 HME_REF1_DISABLE_UNNAMED0 = 0, //!< HME search is performed on forward reference 1. 2641 HME_REF1_DISABLE_UNNAMED1 = 1, //!< HME search is disabled on forward reference 1. 2642 }; 2643 2644 enum CONSTRAINED_INTRA_PREDICTION_FLAG 2645 { 2646 CONSTRAINED_INTRA_PREDICTION_FLAG_UNNAMED0 = 0, //!< Allows both intra and inter neighboring MB to be used in the intra-prediction decoding of the current MB. 2647 CONSTRAINED_INTRA_PREDICTION_FLAG_UNNAMED1 = 1, //!< Allows only to use neighboring Intra MBs in the intra-prediction decoding of the current MB.If the neighbor is an inter MB, it is considered as not available. 2648 }; 2649 2650 //! \brief PICTURE_TYPE 2651 //! \details 2652 //! This field specifies how the current picture is predicted. (It might be 2653 //! redundant from the kernel type.) 2654 enum PICTURE_TYPE 2655 { 2656 PICTURE_TYPE_I = 0, //!< No additional details 2657 PICTURE_TYPE_P = 1, //!< No additional details 2658 }; 2659 2660 //! \brief LUMA_INTRA_PARTITION_MASK 2661 //! \details 2662 //! This field specifies which Luma Intra partition is enabled/disabled for 2663 //! intra mode decision. 2664 enum LUMA_INTRA_PARTITION_MASK 2665 { 2666 LUMA_INTRA_PARTITION_MASK_UNNAMED1 = 1, //!< luma_intra_16x16 disabled 2667 LUMA_INTRA_PARTITION_MASK_UNNAMED2 = 2, //!< luma_intra_8x8 disabled 2668 LUMA_INTRA_PARTITION_MASK_UNNAMED4 = 4, //!< luma_intra_4x4 disabled 2669 }; 2670 2671 enum MV_COST_SCALING_FACTOR 2672 { 2673 MV_COST_SCALING_FACTOR_QPEL = 0, //!< Qpel difference between MV and cost center: eff cost range 0-15pel 2674 MV_COST_SCALING_FACTOR_HPEL = 1, //!< Hpel difference between MV and cost center: eff cost range 0-31pel 2675 MV_COST_SCALING_FACTOR_PEL = 2, //!< Pel difference between MV and cost center: eff cost range 0-63pel 2676 MV_COST_SCALING_FACTOR_2PEL = 3, //!< 2Pel difference between MV and cost center: eff cost range 0-127pel 2677 }; 2678 2679 enum REFID_COST_MODE_SELECT 2680 { 2681 REFID_COST_MODE_SELECT_MODE0 = 0, //!< AVC 2682 REFID_COST_MODE_SELECT_MODE1 = 1, //!< Linear 2683 }; 2684 2685 enum AVC_INTRA_16X16_MODE_MASK 2686 { 2687 AVC_INTRA_16X16_MODE_MASK_VERT = 1, //!< No additional details 2688 AVC_INTRA_16X16_MODE_MASK_HORZ = 2, //!< No additional details 2689 AVC_INTRA_16X16_MODE_MASK_DC = 4, //!< No additional details 2690 AVC_INTRA_16X16_MODE_MASK_PLANAR = 8, //!< No additional details 2691 }; 2692 2693 enum AVC_INTRA_CHROMA_MODE_MASK 2694 { 2695 AVC_INTRA_CHROMA_MODE_MASK_VERT = 1, //!< No additional details 2696 AVC_INTRA_CHROMA_MODE_MASK_HORZ = 2, //!< No additional details 2697 AVC_INTRA_CHROMA_MODE_MASK_DC = 4, //!< No additional details 2698 AVC_INTRA_CHROMA_MODE_MASK_PLANAR = 8, //!< No additional details 2699 }; 2700 2701 //! \brief INTRA_COMPUTE_TYPE_INTRACOMPUTETYPE 2702 //! \details 2703 //! This field specifies the pixel components measured for Intra prediction. 2704 enum INTRA_COMPUTE_TYPE_INTRACOMPUTETYPE 2705 { 2706 INTRA_COMPUTE_TYPE_INTRACOMPUTETYPE_UNNAMED0 = 0, //!< Luma+Chroma enabled. 2707 INTRA_COMPUTE_TYPE_INTRACOMPUTETYPE_UNNAMED1 = 1, //!< Luma Only. 2708 INTRA_COMPUTE_TYPE_INTRACOMPUTETYPE_UNNAMED2 = 2, //!< Intra Disabled. 2709 }; 2710 2711 //! \brief INTRAREFRESHENABLE_ROLLING_I_ENABLE 2712 //! \details 2713 //! <p>This parameter indicates if the IntraRefresh is enabled or 2714 //! disabled.</p> 2715 //! 2716 //! <p>This must be disabled on I-Frames.</p> 2717 enum INTRAREFRESHENABLE_ROLLING_I_ENABLE 2718 { 2719 INTRAREFRESHENABLE_ROLLING_I_ENABLE_DISABLE = 0, //!< No additional details 2720 INTRAREFRESHENABLE_ROLLING_I_ENABLE_ENABLE = 1, //!< No additional details 2721 }; 2722 2723 //! \brief INTRAREFRESHMODE 2724 //! \details 2725 //! This parameter indicates if the IntraRefresh is row based or column 2726 //! based. 2727 enum INTRAREFRESHMODE 2728 { 2729 INTRAREFRESHMODE_ROWBASED = 0, //!< No additional details 2730 INTRAREFRESHMODE_COLUMNBASED = 1, //!< No additional details 2731 }; 2732 2733 //! \brief HME_REF_WINDOWS_COMBINING_THRESHOLD 2734 //! \details 2735 //! When the reference windows of the HME refinement VME call and the 2736 //! regular VME call are overlapped 2737 //! and the difference of the locations is within this threshold in 2738 //! quarter pixel unit, the two calls 2739 //! are merged to a single call. 2740 enum HME_REF_WINDOWS_COMBINING_THRESHOLD 2741 { 2742 HME_REF_WINDOWS_COMBINING_THRESHOLD_UNNAMED0 = 0, //!< No additional details 2743 HME_REF_WINDOWS_COMBINING_THRESHOLD_UNNAMED255 = 255, //!< No additional details 2744 }; 2745 2746 //! \brief MAXHMVR 2747 //! \details 2748 //! Horizontal MV component range. The MV range is restricted to 2749 //! [-MaxHmvR+1, MaxHmvR-1] in luma quarter pel unit, 2750 //! which corresponds to [-MaxHmvR/4 + 0.25, MaxHmvR/4-0.25] in luma 2751 //! integer pel unit. 2752 enum MAXHMVR 2753 { 2754 MAXHMVR_UNNAMED256 = 256, //!< No additional details 2755 MAXHMVR_UNNAMED512 = 512, //!< No additional details 2756 MAXHMVR_UNNAMED1024 = 1024, //!< No additional details 2757 MAXHMVR_UNNAMED2048 = 2048, //!< No additional details 2758 MAXHMVR_UNNAMED4096 = 4096, //!< No additional details 2759 MAXHMVR_UNNAMED8192 = 8192, //!< No additional details 2760 }; 2761 2762 //! \brief MAXVMVR 2763 //! \details 2764 //! Vertical MV component range defined in the AVC Spec Annex A. The MV 2765 //! range is restricted to [-MaxVmvR+1, MaxVmvR-1] 2766 //! in luma quarter pel unit, which corresponds to [-MaxVmvR/4 + 0.25, 2767 //! MaxVmvR/4-0.25] in luma integer pel unit. 2768 enum MAXVMVR 2769 { 2770 MAXVMVR_UNNAMED256 = 256, //!< No additional details 2771 MAXVMVR_UNNAMED512 = 512, //!< No additional details 2772 MAXVMVR_UNNAMED1024 = 1024, //!< No additional details 2773 MAXVMVR_UNNAMED2048 = 2048, //!< No additional details 2774 }; 2775 2776 //! \brief PPMV_DISABLE 2777 //! \details 2778 //! This bit forces the IME to use the actual PMV predictor for the IME 2779 //! search. 2780 enum PPMV_DISABLE 2781 { 2782 PPMV_DISABLE_UNNAMED0 = 0, //!< Use PPMV based IME search. 2783 PPMV_DISABLE_UNNAMED1 = 1, //!< Use PMV based IME search. 2784 }; 2785 2786 //! \brief LONGTERM_REFERENCE_FRAME_BWD_REF0_INDICATOR 2787 //! \details 2788 //! Indicates whether the reference frame is a long or short term reference. 2789 enum LONGTERM_REFERENCE_FRAME_BWD_REF0_INDICATOR 2790 { 2791 LONGTERM_REFERENCE_FRAME_BWD_REF0_INDICATOR_SHORT_TERMREFERENCE = 0, //!< No additional details 2792 LONGTERM_REFERENCE_FRAME_BWD_REF0_INDICATOR_LONG_TERMREFERENCE = 1, //!< No additional details 2793 }; 2794 2795 //! \brief LONGTERM_REFERENCE_FRAME_FWD_REF2_INDICATOR 2796 //! \details 2797 //! Indicates whether the reference frame is a long or short term reference. 2798 enum LONGTERM_REFERENCE_FRAME_FWD_REF2_INDICATOR 2799 { 2800 LONGTERM_REFERENCE_FRAME_FWD_REF2_INDICATOR_SHORT_TERMREFERENCE = 0, //!< No additional details 2801 LONGTERM_REFERENCE_FRAME_FWD_REF2_INDICATOR_LONG_TERMREFERENCE = 1, //!< No additional details 2802 }; 2803 2804 //! \brief LONGTERM_REFERENCE_FRAME_FWD_REF1_INDICATOR 2805 //! \details 2806 //! Indicates whether the reference frame is a long or short term reference. 2807 enum LONGTERM_REFERENCE_FRAME_FWD_REF1_INDICATOR 2808 { 2809 LONGTERM_REFERENCE_FRAME_FWD_REF1_INDICATOR_SHORT_TERMREFERENCE = 0, //!< No additional details 2810 LONGTERM_REFERENCE_FRAME_FWD_REF1_INDICATOR_LONG_TERMREFERENCE = 1, //!< No additional details 2811 }; 2812 2813 //! \brief LONGTERM_REFERENCE_FRAME_FWD_REF0_INDICATOR 2814 //! \details 2815 //! Indicates whether the reference frame is a long or short term reference. 2816 enum LONGTERM_REFERENCE_FRAME_FWD_REF0_INDICATOR 2817 { 2818 LONGTERM_REFERENCE_FRAME_FWD_REF0_INDICATOR_SHORT_TERMREFERENCE = 0, //!< No additional details 2819 LONGTERM_REFERENCE_FRAME_FWD_REF0_INDICATOR_LONG_TERMREFERENCE = 1, //!< No additional details 2820 }; 2821 2822 //! \name Initializations 2823 2824 //! \brief Explicit member initialization function 2825 VDENC_IMG_STATE_CMD(); 2826 2827 static const size_t dwSize = 35; 2828 static const size_t byteSize = 140; 2829 }; 2830 2831 //! 2832 //! \brief VDENC_PIPE_BUF_ADDR_STATE 2833 //! \details 2834 //! This state command provides the memory base addresses for all row 2835 //! stores, Streamin/StreamOut, DMV buffer along with the uncompressed 2836 //! source, reference pictures and downscaled reference pictures required by 2837 //! the VDENC pipeline. All reference pixel surfaces in the Encoder are 2838 //! programmed with the same surface state (NV12 and TileY format), except 2839 //! each has its own frame buffer base address. Same holds true for the 2840 //! down-scaled reference pictures too. In the tile format, there is no need 2841 //! to provide buffer offset for each slice; since from each MB address, the 2842 //! hardware can calculated the corresponding memory location within the 2843 //! frame buffer directly. VDEnc supports 3 Downscaled reference frames ( 2 2844 //! fwd, 1 bwd) and 4 normal reference frames ( 3 fwd, 1 bwd). The driver 2845 //! will sort out the base address from the DPB table and populate the base 2846 //! addresses that map to the corresponding reference index for both DS 2847 //! references and normal reference frames. Each of the individual DS ref/ 2848 //! Normal ref frames have their own MOCS DW that corresponds to the 2849 //! respective base address. The only thing that is different in the MOCS DW 2850 //! amongst the DS reference frames is the MMCD controls (specified in bits 2851 //! [10:9] of the MOCS DW). Driver needs to ensure that the other bits need 2852 //! to be the same across the different DS ref frames. The same is 2853 //! applicable for the normal reference frames. 2854 //! 2855 struct VDENC_PIPE_BUF_ADDR_STATE_CMD 2856 { 2857 union 2858 { 2859 //!< DWORD 0 2860 struct 2861 { 2862 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2863 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2864 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 2865 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 2866 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 2867 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 2868 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2869 }; 2870 uint32_t Value; 2871 } DW0; 2872 VDENC_Down_Scaled_Reference_Picture_CMD DsFwdRef0 ; //!< DS FWD REF0 2873 VDENC_Down_Scaled_Reference_Picture_CMD DsFwdRef1 ; //!< DS FWD REF1 2874 VDENC_Down_Scaled_Reference_Picture_CMD DsBwdRef0 ; //!< DS BWD REF0 2875 VDENC_Original_Uncompressed_Picture_CMD OriginalUncompressedPicture ; //!< Original Uncompressed Picture 2876 VDENC_Streamin_Data_Picture_CMD StreaminDataPicture ; //!< Streamin Data Picture 2877 VDENC_Row_Store_Scratch_Buffer_Picture_CMD RowStoreScratchBuffer ; //!< Row Store Scratch Buffer 2878 VDENC_Colocated_MV_Picture_CMD ColocatedMv ; //!< Colocated MV 2879 VDENC_Reference_Picture_CMD FwdRef0 ; //!< FWD REF0 2880 VDENC_Reference_Picture_CMD FwdRef1 ; //!< FWD REF1 2881 VDENC_Reference_Picture_CMD FwdRef2 ; //!< FWD REF2 2882 VDENC_Reference_Picture_CMD BwdRef0 ; //!< BWD REF0 2883 VDENC_Statistics_Streamout_CMD VdencStatisticsStreamout ; //!< VDEnc Statistics Streamout 2884 VDENC_Down_Scaled_Reference_Picture_CMD DsFwdRef04X ; //!< DS FWD REF0 4X 2885 VDENC_Down_Scaled_Reference_Picture_CMD DsFwdRef14X ; //!< DS FWD REF1 4X 2886 VDENC_Colocated_MV_Picture_CMD VdencCuRecordStreamOutBuffer ; //!< VDEnc CuRecord stream-out buffer 2887 VDENC_Colocated_MV_Picture_CMD VdencLcuPakObjCmdBuffer ; //!< VDEnc LCU PAK OBJ CMD Buffer 2888 VDENC_Down_Scaled_Reference_Picture_CMD ScaledReferenceSurface8X ; //!< Scaled Reference Surface 8X 2889 VDENC_Down_Scaled_Reference_Picture_CMD ScaledReferenceSurface4X ; //!< Scaled Reference Surface 4X 2890 VDENC_Colocated_MV_Picture_CMD Vp9SegmentationMapStreaminBuffer ; //!< VP9 Segmentation Map Streamin Buffer 2891 VDENC_Colocated_MV_Picture_CMD Vp9SegmentationMapStreamoutBuffer ; //!< VP9 Segmentation Map Streamout Buffer 2892 union 2893 { 2894 //!< DWORD 61 2895 struct 2896 { 2897 uint32_t WeightsHistogramStreamoutOffset ; //!< Weights Histogram Streamout offset 2898 }; 2899 uint32_t Value; 2900 } DW61; 2901 2902 //! \name Local enumerations 2903 2904 enum SUBOPB 2905 { 2906 SUBOPB_VDENCPIPEBUFADDRSTATE = 4, //!< No additional details 2907 }; 2908 2909 enum SUBOPA 2910 { 2911 SUBOPA_UNNAMED0 = 0, //!< No additional details 2912 }; 2913 2914 enum OPCODE 2915 { 2916 OPCODE_VDENCPIPE = 1, //!< No additional details 2917 }; 2918 2919 enum PIPELINE 2920 { 2921 PIPELINE_MFXCOMMON = 2, //!< No additional details 2922 }; 2923 2924 enum COMMAND_TYPE 2925 { 2926 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2927 }; 2928 2929 //! \name Initializations 2930 2931 //! \brief Explicit member initialization function 2932 VDENC_PIPE_BUF_ADDR_STATE_CMD(); 2933 2934 static const size_t dwSize = 62; 2935 static const size_t byteSize = 248; 2936 }; 2937 2938 //! 2939 //! \brief VDENC_PIPE_MODE_SELECT 2940 //! \details 2941 //! Specifies which codec and hardware module is being used to encode/decode 2942 //! the video data, on a per-frame basis. The VDENC_PIPE_MODE_SELECT command 2943 //! specifies which codec and hardware module is being used to encode/decode 2944 //! the video data, on a per-frame basis. It also configures the hardware 2945 //! pipeline according to the active encoder/decoder operating mode for 2946 //! encoding/decoding the current picture. 2947 //! 2948 struct VDENC_PIPE_MODE_SELECT_CMD 2949 { 2950 union 2951 { 2952 //!< DWORD 0 2953 struct 2954 { 2955 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2956 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2957 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 2958 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 2959 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 2960 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 2961 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2962 }; 2963 uint32_t Value; 2964 } DW0; 2965 union 2966 { 2967 //!< DWORD 1 2968 struct 2969 { 2970 uint32_t StandardSelect : __CODEGEN_BITFIELD( 0, 3) ; //!< STANDARD_SELECT 2971 uint32_t Reserved36 : __CODEGEN_BITFIELD( 4, 4) ; //!< Reserved 2972 uint32_t FrameStatisticsStreamOutEnable : __CODEGEN_BITFIELD( 5, 5) ; //!< FRAME_STATISTICS_STREAM_OUT_ENABLE 2973 uint32_t VdencPakObjCmdStreamOutEnable : __CODEGEN_BITFIELD( 6, 6) ; //!< VDEnc PAK_OBJ_CMD Stream-Out Enable 2974 uint32_t TlbPrefetchEnable : __CODEGEN_BITFIELD( 7, 7) ; //!< TLB_PREFETCH_ENABLE 2975 uint32_t PakThresholdCheckEnable : __CODEGEN_BITFIELD( 8, 8) ; //!< PAK_THRESHOLD_CHECK_ENABLE 2976 uint32_t VdencStreamInEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< VDENC_STREAM_IN_ENABLE 2977 uint32_t Downscaled8XWriteDisable : __CODEGEN_BITFIELD(10, 10) ; //!< DownScaled 8x write Disable 2978 uint32_t Downscaled4XWriteDisable : __CODEGEN_BITFIELD(11, 11) ; //!< DownScaled 4x write Disable 2979 uint32_t BitDepth : __CODEGEN_BITFIELD(12, 14) ; //!< BIT_DEPTH 2980 uint32_t PakChromaSubSamplingType : __CODEGEN_BITFIELD(15, 16) ; //!< PAK_CHROMA_SUB_SAMPLING_TYPE 2981 uint32_t OutputRangeControlAfterColorSpaceConversion : __CODEGEN_BITFIELD(17, 17) ; //!< output range control after color space conversion 2982 uint32_t Reserved50 : __CODEGEN_BITFIELD(18, 30) ; //!< Reserved 2983 uint32_t DisableSpeedModeFetchOptimization : __CODEGEN_BITFIELD(31, 31) ; //!< Disable Speed Mode fetch optimization 2984 }; 2985 uint32_t Value; 2986 } DW1; 2987 2988 //! \name Local enumerations 2989 2990 enum SUBOPB 2991 { 2992 SUBOPB_VDENCPIPEMODESELECT = 0, //!< No additional details 2993 }; 2994 2995 enum SUBOPA 2996 { 2997 SUBOPA_UNNAMED0 = 0, //!< No additional details 2998 }; 2999 3000 enum OPCODE 3001 { 3002 OPCODE_VDENCPIPE = 1, //!< No additional details 3003 }; 3004 3005 enum PIPELINE 3006 { 3007 PIPELINE_MFXCOMMON = 2, //!< No additional details 3008 }; 3009 3010 enum COMMAND_TYPE 3011 { 3012 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3013 }; 3014 3015 enum STANDARD_SELECT 3016 { 3017 STANDARD_SELECT_AVC = 2, //!< No additional details 3018 }; 3019 3020 //! \brief FRAME_STATISTICS_STREAM_OUT_ENABLE 3021 //! \details 3022 //! This field controls whether the frame statistics stream-out is enabled. 3023 enum FRAME_STATISTICS_STREAM_OUT_ENABLE 3024 { 3025 FRAME_STATISTICS_STREAM_OUT_ENABLE_DISABLE = 0, //!< No additional details 3026 FRAME_STATISTICS_STREAM_OUT_ENABLE_ENABLE = 1, //!< No additional details 3027 }; 3028 3029 //! \brief TLB_PREFETCH_ENABLE 3030 //! \details 3031 //! This field controls whether TLB prefetching is enabled. 3032 enum TLB_PREFETCH_ENABLE 3033 { 3034 TLB_PREFETCH_ENABLE_DISABLE = 0, //!< No additional details 3035 TLB_PREFETCH_ENABLE_ENABLE = 1, //!< No additional details 3036 }; 3037 3038 //! \brief PAK_THRESHOLD_CHECK_ENABLE 3039 //! \details 3040 //! <p>For AVC standard: This field controls whether VDEnc will check the 3041 //! PAK indicator for bits overflow and terminates the slice. This mode is 3042 //! called Dynamic Slice Mode. When this field is disabled, VDEnc is in 3043 //! Static Slice Mode. It uses the driver programmed Slice Macroblock Height 3044 //! Minus One to terminate the slice. This feature is also referred to as 3045 //! slice size conformance.</p> 3046 //! <p>For HEVC standard: This bit is used to enable dynamic slice size 3047 //! control.</p> 3048 enum PAK_THRESHOLD_CHECK_ENABLE 3049 { 3050 PAK_THRESHOLD_CHECK_ENABLE_DISABLESTATICSLICEMODE = 0, //!< No additional details 3051 PAK_THRESHOLD_CHECK_ENABLE_ENABLEDYNAMICSLICEMODE = 1, //!< No additional details 3052 }; 3053 3054 //! \brief VDENC_STREAM_IN_ENABLE 3055 //! \details 3056 //! <p>This field controls whether VDEnc will read the stream-in surface 3057 //! that is programmed. Currently the stream-in surface has MB level QP, 3058 //! ROI, predictors and MaxSize/TargetSizeinWordsMB parameters. The 3059 //! individual enables for each of the fields is programmed in the 3060 //! VDENC_IMG_STATE.</p> 3061 //! <p>(ROI_Enable, Fwd/Predictor0 MV Enable, Bwd/Predictor1 MV Enable, MB 3062 //! Level QP Enable, TargetSizeinWordsMB/MaxSizeinWordsMB Enable).</p> 3063 //! <p>This bit is valid only in AVC mode. In HEVC / VP9 mode this bit is 3064 //! reserved and should be set to zero.</p> 3065 enum VDENC_STREAM_IN_ENABLE 3066 { 3067 VDENC_STREAM_IN_ENABLE_DISABLE = 0, //!< No additional details 3068 VDENC_STREAM_IN_ENABLE_ENABLE = 1, //!< No additional details 3069 }; 3070 3071 //! \brief BIT_DEPTH 3072 //! \details 3073 //! <p>This parameter indicates the PAK bit depth. The valid values for this 3074 //! are 0 / 2 in HEVC / VP9 standard. In AVC standard this field should be 3075 //! set to 0.</p> 3076 //! <p></p> 3077 enum BIT_DEPTH 3078 { 3079 BIT_DEPTH_8BIT = 0, //!< No additional details 3080 BIT_DEPTH_10BIT = 2, //!< No additional details 3081 BIT_DEPTH_12BIT = 3, //!< No additional details 3082 }; 3083 3084 //! \brief PAK_CHROMA_SUB_SAMPLING_TYPE 3085 //! \details 3086 //! <p>This field is applicable only in HEVC and VP9. In AVC, this field is 3087 //! ignored.</p> 3088 //! <p></p> 3089 enum PAK_CHROMA_SUB_SAMPLING_TYPE 3090 { 3091 PAK_CHROMA_SUB_SAMPLING_TYPE_420 = 1, //!< Used for Main8 and Main10 HEVC, VP9 profile0, AVC. 3092 PAK_CHROMA_SUB_SAMPLING_TYPE_444 = 3, //!< HEVC RExt 444, VP9 444 profiles. 3093 }; 3094 3095 //! \name Initializations 3096 3097 //! \brief Explicit member initialization function 3098 VDENC_PIPE_MODE_SELECT_CMD(); 3099 3100 static const size_t dwSize = 2; 3101 static const size_t byteSize = 8; 3102 }; 3103 3104 //! 3105 //! \brief VDENC_REF_SURFACE_STATE 3106 //! \details 3107 //! This command specifies the surface state parameters for the normal 3108 //! reference surfaces. 3109 //! 3110 struct VDENC_REF_SURFACE_STATE_CMD 3111 { 3112 union 3113 { 3114 //!< DWORD 0 3115 struct 3116 { 3117 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3118 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3119 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 3120 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 3121 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 3122 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 3123 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3124 }; 3125 uint32_t Value; 3126 } DW0; 3127 union 3128 { 3129 //!< DWORD 1 3130 struct 3131 { 3132 uint32_t Reserved32 ; //!< Reserved 3133 }; 3134 uint32_t Value; 3135 } DW1; 3136 VDENC_Surface_State_Fields_CMD Dwords25 ; //!< Dwords 2..5 3137 3138 //! \name Local enumerations 3139 3140 enum SUBOPB 3141 { 3142 SUBOPB_VDENCREFSURFACESTATE = 2, //!< No additional details 3143 }; 3144 3145 enum SUBOPA 3146 { 3147 SUBOPA_UNNAMED0 = 0, //!< No additional details 3148 }; 3149 3150 enum OPCODE 3151 { 3152 OPCODE_VDENCPIPE = 1, //!< No additional details 3153 }; 3154 3155 enum PIPELINE 3156 { 3157 PIPELINE_MFXCOMMON = 2, //!< No additional details 3158 }; 3159 3160 enum COMMAND_TYPE 3161 { 3162 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3163 }; 3164 3165 //! \name Initializations 3166 3167 //! \brief Explicit member initialization function 3168 VDENC_REF_SURFACE_STATE_CMD(); 3169 3170 static const size_t dwSize = 6; 3171 static const size_t byteSize = 24; 3172 }; 3173 3174 //! 3175 //! \brief VDENC_SRC_SURFACE_STATE 3176 //! \details 3177 //! This command specifies the uncompressed original input picture to be 3178 //! encoded. The actual base address is defined in the 3179 //! VDENC_PIPE_BUF_ADDR_STATE. Pitch can be wider than the Picture Width in 3180 //! pixels and garbage will be there at the end of each line. The following 3181 //! describes all the different formats that are supported in WLV+ VDEnc: 3182 //! NV12 - 4:2:0 only; UV interleaved; Full Pitch, U and V offset is set to 3183 //! 0 (the only format supported for video codec); vertical UV offset is MB 3184 //! aligned; UV xoffsets = 0. 3185 //! This surface state here is identical to the Surface State for 3186 //! deinterlace and sample_8x8 messages described in the Shared Function 3187 //! Volume and Sampler Chapter. For non pixel data, such as row stores, DMV 3188 //! and streamin/out, a linear buffer is employed. For row stores, the H/W 3189 //! is designed to guarantee legal memory accesses (read and write). For the 3190 //! remaining cases, indirect object base address, indirect object address 3191 //! upper bound, object data start address (offset) and object data length 3192 //! are used to fully specified their corresponding buffer. This mechanism 3193 //! is chosen over the pixel surface type because of their variable record 3194 //! sizes. All row store surfaces are linear surface. Their addresses are 3195 //! programmed in VDEnc_Pipe_Buf_Base_State. 3196 //! 3197 struct VDENC_SRC_SURFACE_STATE_CMD 3198 { 3199 union 3200 { 3201 //!< DWORD 0 3202 struct 3203 { 3204 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3205 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3206 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 3207 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 3208 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 3209 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 3210 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3211 }; 3212 uint32_t Value; 3213 } DW0; 3214 union 3215 { 3216 //!< DWORD 1 3217 struct 3218 { 3219 uint32_t Reserved32 ; //!< Reserved 3220 }; 3221 uint32_t Value; 3222 } DW1; 3223 VDENC_Surface_State_Fields_CMD Dwords25 ; //!< Dwords 2..5 3224 3225 //! \name Local enumerations 3226 3227 enum SUBOPB 3228 { 3229 SUBOPB_VDENCSRCSURFACESTATE = 1, //!< No additional details 3230 }; 3231 3232 enum SUBOPA 3233 { 3234 SUBOPA_UNNAMED0 = 0, //!< No additional details 3235 }; 3236 3237 enum OPCODE 3238 { 3239 OPCODE_VDENCPIPE = 1, //!< No additional details 3240 }; 3241 3242 enum PIPELINE 3243 { 3244 PIPELINE_MFXCOMMON = 2, //!< No additional details 3245 }; 3246 3247 enum COMMAND_TYPE 3248 { 3249 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3250 }; 3251 3252 //! \name Initializations 3253 3254 //! \brief Explicit member initialization function 3255 VDENC_SRC_SURFACE_STATE_CMD(); 3256 3257 static const size_t dwSize = 6; 3258 static const size_t byteSize = 24; 3259 }; 3260 3261 //! 3262 //! \brief VDENC_WALKER_STATE 3263 //! \details 3264 //! This command provides the macroblock start location for the VDEnc 3265 //! walker. Current programming to always have this command at the frame 3266 //! level, hence the macroblock X,Y location need to be programmed to 0,0 to 3267 //! always start at frame origin. Once the hardware receives this command 3268 //! packet, it internally starts the VDEnc pipeline. This should be the last 3269 //! command that is programmed for the VDEnc pipeline. 3270 //! 3271 //! This command is programmed per super-slice. The X location always needs 3272 //! to be programmed to 0. The Y location needs to be programmed to the 3273 //! starting point of the current super-slice. The programming needs to 3274 //! ensure that all super-slices are contiguous. It is illegal to have gaps 3275 //! between the super-slices. 3276 //! 3277 struct VDENC_WALKER_STATE_CMD 3278 { 3279 union 3280 { 3281 //!< DWORD 0 3282 struct 3283 { 3284 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3285 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3286 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 3287 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 3288 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 3289 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 3290 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3291 }; 3292 uint32_t Value; 3293 } DW0; 3294 union 3295 { 3296 //!< DWORD 1 3297 struct 3298 { 3299 uint32_t MbLcuStartYPosition : __CODEGEN_BITFIELD( 0, 8) ; //!< MB/LCU Start Y Position 3300 uint32_t Reserved41 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved 3301 uint32_t MbLcuStartXPosition : __CODEGEN_BITFIELD(16, 24) ; //!< MB/LCU Start X Position 3302 uint32_t Reserved57 : __CODEGEN_BITFIELD(25, 27) ; //!< Reserved 3303 uint32_t FirstSuperSlice : __CODEGEN_BITFIELD(28, 28) ; //!< First Super Slice 3304 uint32_t Reserved61 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 3305 }; 3306 uint32_t Value; 3307 } DW1; 3308 union 3309 { 3310 //!< DWORD 2 3311 struct 3312 { 3313 uint32_t NextsliceMbStartYPosition : __CODEGEN_BITFIELD( 0, 9) ; //!< NextSlice MB Start Y Position 3314 uint32_t Reserved74 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 3315 uint32_t NextsliceMbLcuStartXPosition : __CODEGEN_BITFIELD(16, 25) ; //!< NextSlice MB/LCU Start X Position 3316 uint32_t Reserved90 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 3317 }; 3318 uint32_t Value; 3319 } DW2; 3320 union 3321 { 3322 //!< DWORD 3 3323 struct 3324 { 3325 uint32_t Log2WeightDenomLuma : __CODEGEN_BITFIELD( 0, 2) ; //!< Log 2 Weight Denom Luma 3326 uint32_t Reserved99 : __CODEGEN_BITFIELD( 3, 3) ; //!< Reserved 3327 uint32_t HevcLog2WeightDemonLuma : __CODEGEN_BITFIELD( 4, 6) ; //!< HevcLog2WeightDemonLuma 3328 uint32_t Reserved107 : __CODEGEN_BITFIELD( 7, 31) ; //!< Reserved 3329 }; 3330 uint32_t Value; 3331 } DW3; 3332 union 3333 { 3334 //!< DWORD 4 3335 struct 3336 { 3337 uint32_t TileStartCtbY : __CODEGEN_BITFIELD( 0, 15) ; //!< Tile Start CTB-Y 3338 uint32_t TileStartCtbX : __CODEGEN_BITFIELD(16, 31) ; //!< Tile Start CTB-X 3339 }; 3340 uint32_t Value; 3341 } DW4; 3342 union 3343 { 3344 //!< DWORD 5 3345 struct 3346 { 3347 uint32_t TileWidth : __CODEGEN_BITFIELD( 0, 15) ; //!< Tile Width 3348 uint32_t TileHeight : __CODEGEN_BITFIELD(16, 31) ; //!< Tile Height 3349 }; 3350 uint32_t Value; 3351 } DW5; 3352 3353 //! \name Local enumerations 3354 3355 enum SUBOPB 3356 { 3357 SUBOPB_VDENCWALKERSTATE = 7, //!< No additional details 3358 }; 3359 3360 enum SUBOPA 3361 { 3362 SUBOPA_UNNAMED0 = 0, //!< No additional details 3363 }; 3364 3365 enum OPCODE 3366 { 3367 OPCODE_VDENCPIPE = 1, //!< No additional details 3368 }; 3369 3370 enum PIPELINE 3371 { 3372 PIPELINE_MFXCOMMON = 2, //!< No additional details 3373 }; 3374 3375 enum COMMAND_TYPE 3376 { 3377 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3378 }; 3379 3380 //! \name Initializations 3381 3382 //! \brief Explicit member initialization function 3383 VDENC_WALKER_STATE_CMD(); 3384 3385 static const size_t dwSize = 6; 3386 static const size_t byteSize = 24; 3387 }; 3388 3389 }; 3390 3391 #pragma pack() 3392 3393 #endif // __MHW_VDBOX_VDENC_HWCMD_G10_X_H__ 3394