1 /* 2 * Copyright (c) 2017-2019, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file codechal_encode_csc_ds_g12.h 24 //! \brief Gen12 class for CSC and Downscaling. 25 //! 26 27 #ifndef __CodechalEncodeCscDsG12__ 28 #define __CodechalEncodeCscDsG12__ 29 30 #include "codechal_encode_csc_ds.h" 31 32 class CodechalEncodeCscDsG12 : public CodechalEncodeCscDs 33 { 34 public: 35 //! 36 //! \brief Extension params used only by HEVC 37 //! 38 struct HevcExtKernelParams 39 { 40 bool bHevcEncHistorySum = false; 41 bool bUseLCU32 = false; 42 PMOS_RESOURCE presHistoryBuffer = nullptr; 43 uint32_t dwSizeHistoryBuffer = 0; 44 uint32_t dwOffsetHistoryBuffer = 0; 45 PMOS_RESOURCE presHistorySumBuffer = nullptr; 46 uint32_t dwSizeHistorySumBuffer = 0; 47 uint32_t dwOffsetHistorySumBuffer = 0; 48 PMOS_RESOURCE presMultiThreadTaskBuffer = nullptr; 49 uint32_t dwSizeMultiThreadTaskBuffer = 0; 50 uint32_t dwOffsetMultiThreadTaskBuffer = 0; 51 }; 52 53 //! 54 //! \brief 4xDS kernel Curbe data 55 //! 56 struct Ds4xKernelCurbeData 57 { Ds4xKernelCurbeDataDs4xKernelCurbeData58 Ds4xKernelCurbeData() 59 { 60 DW0 = 0; 61 DW1 = ds4xSrcYPlane; 62 DW2 = ds4xDstYPlane; 63 DW3_InputYBTIBottomField = 64 DW4_OutputYBTIBottomField = 65 DW5_FlatnessThreshold = 66 DW6 = 67 DW7_Reserved = 0; 68 DW8 = ds4xDstMbVProc; 69 DW9_MBVProcStatsBTIBottomField = 0; 70 DW10_Reserved = 71 DW11_Reserved = 72 DW12_Reserved = 73 DW13_Reserved = 74 DW14_Reserved = 75 DW15_Reserved = 0; 76 } 77 78 // DW0 79 union 80 { 81 struct 82 { 83 uint32_t DW0_InputPictureWidth : MOS_BITFIELD_RANGE(0, 15); 84 uint32_t DW0_InputPictureHeight : MOS_BITFIELD_RANGE(16, 31); 85 }; 86 uint32_t DW0; 87 }; 88 89 // DW1 90 union 91 { 92 struct 93 { 94 uint32_t DW1_InputYBTIFrame; 95 }; 96 struct 97 { 98 uint32_t DW1_InputYBTITopField; 99 }; 100 uint32_t DW1; 101 }; 102 103 // DW2 104 union 105 { 106 struct 107 { 108 uint32_t DW2_OutputYBTIFrame; 109 }; 110 struct 111 { 112 uint32_t DW2_OutputYBTITopField; 113 }; 114 uint32_t DW2; 115 }; 116 117 // DW3 118 uint32_t DW3_InputYBTIBottomField; 119 120 // DW4 121 uint32_t DW4_OutputYBTIBottomField; 122 123 // DW5 124 uint32_t DW5_FlatnessThreshold; 125 126 // DW6 127 union 128 { 129 struct 130 { 131 uint32_t DW6_EnableMBFlatnessCheck : MOS_BITFIELD_BIT(0); 132 uint32_t DW6_EnableMBVarianceOutput : MOS_BITFIELD_BIT(1); 133 uint32_t DW6_EnableMBPixelAverageOutput : MOS_BITFIELD_BIT(2); 134 uint32_t DW6_EnableBlock8x8StatisticsOutput : MOS_BITFIELD_BIT(3); 135 uint32_t: MOS_BITFIELD_RANGE(4, 31); 136 }; 137 uint32_t DW6; 138 }; 139 140 // DW7 141 uint32_t DW7_Reserved; 142 143 // DW8 144 union 145 { 146 struct 147 { 148 uint32_t DW8_MBVProcStatsBTIFrame; 149 }; 150 struct 151 { 152 uint32_t DW8_MBVProcStatsBTITopField; 153 }; 154 uint32_t DW8; 155 }; 156 157 // DW9 158 uint32_t DW9_MBVProcStatsBTIBottomField; 159 160 // DW10 161 uint32_t DW10_Reserved; 162 163 // DW11 164 uint32_t DW11_Reserved; 165 166 //DW12 167 uint32_t DW12_Reserved; 168 169 //DW13 170 uint32_t DW13_Reserved; 171 172 //DW14 173 uint32_t DW14_Reserved; 174 175 //DW15 176 uint32_t DW15_Reserved; 177 178 }; 179 C_ASSERT(MOS_BYTES_TO_DWORDS(sizeof(Ds4xKernelCurbeData)) == 16); 180 181 //! 182 //! \brief Constructor 183 //! 184 CodechalEncodeCscDsG12(CodechalEncoderState* encoder); 185 186 //! 187 //! \brief Destructor 188 //! 189 ~CodechalEncodeCscDsG12(); 190 191 virtual uint8_t GetBTCount() const override; 192 193 protected: 194 virtual MOS_STATUS AllocateSurfaceCsc() override; 195 virtual MOS_STATUS InitKernelStateDS() override; 196 virtual MOS_STATUS SetCurbeDS4x() override; 197 virtual MOS_STATUS SetKernelParamsCsc(KernelParams* params) override; 198 virtual MOS_STATUS InitKernelStateCsc() override; 199 200 private: 201 //! 202 //! \brief CSC kernel binding table 203 //! 204 enum CscKernelBTI 205 { 206 cscSrcYPlane = 0, 207 cscSrcUVPlane = 1, 208 cscDstConvYPlane = 2, 209 cscDstConvUVlane = 3, 210 cscDst4xDs = 4, 211 cscDstMbStats = 5, 212 cscDst2xDs = 6, 213 cscDstHistBuffer = 7, 214 cscDstHistSum = 8, 215 cscDstMultiTask = 9, 216 cscNumSurfaces = 10, 217 }; 218 219 //! 220 //! \brief Csc kernel Curbe data 221 //! 222 struct CscKernelCurbeData 223 { CscKernelCurbeDataCscKernelCurbeData224 CscKernelCurbeData() 225 { 226 DW0 = 227 DW1 = 228 DW2 = 229 DW3_MBFlatnessThreshold = 230 DW4_CSC_Coefficient_C0 = 231 DW4_CSC_Coefficient_C1 = 232 DW5_CSC_Coefficient_C2 = 233 DW5_CSC_Coefficient_C3 = 234 DW6_CSC_Coefficient_C4 = 235 DW6_CSC_Coefficient_C5 = 236 DW7_CSC_Coefficient_C6 = 237 DW7_CSC_Coefficient_C7 = 238 DW8_CSC_Coefficient_C8 = 239 DW8_CSC_Coefficient_C9 = 240 DW9_CSC_Coefficient_C10 = 241 DW9_CSC_Coefficient_C11 = 0; 242 DW10_BTI_InputSurface = cscSrcYPlane; 243 DW11_BTI_Enc8BitSurface = cscDstConvYPlane; 244 DW12_BTI_4xDsSurface = cscDst4xDs; 245 DW13_BTI_MbStatsSurface = cscDstMbStats; 246 DW14_BTI_2xDsSurface = cscDst2xDs; 247 DW15_BTI_HistoryBuffer = cscDstHistBuffer; 248 DW16_BTI_HistorySumBuffer = cscDstHistSum; 249 DW17_BTI_MultiTaskBuffer = cscDstMultiTask; 250 } 251 252 union 253 { 254 struct 255 { 256 // DWORD 0 257 uint32_t DW0_Reserved_0 : MOS_BITFIELD_RANGE(0, 7); 258 uint32_t DW0_Reserved_1 : MOS_BITFIELD_RANGE(8, 15); 259 uint32_t DW0_OutputBitDepthForChroma : MOS_BITFIELD_RANGE(16, 23); 260 uint32_t DW0_OutputBitDepthForLuma : MOS_BITFIELD_RANGE(24, 30); 261 uint32_t DW0_RoundingEnable : MOS_BITFIELD_BIT(31); 262 }; 263 uint32_t DW0; 264 }; 265 266 union 267 { 268 struct 269 { 270 // DWORD 1 271 uint32_t DW1_PictureFormat : MOS_BITFIELD_RANGE(0, 7); 272 uint32_t DW1_ConvertFlag : MOS_BITFIELD_BIT(8); 273 uint32_t DW1_DownscaleStage : MOS_BITFIELD_RANGE(9, 11); 274 uint32_t DW1_MbStatisticsDumpFlag : MOS_BITFIELD_BIT(12); 275 uint32_t DW1_YUY2ConversionFlag : MOS_BITFIELD_BIT(13); 276 uint32_t DW1_HevcEncHistorySum : MOS_BITFIELD_BIT(14); 277 uint32_t DW1_LCUSize : MOS_BITFIELD_BIT(15); 278 uint32_t DW1_ChromaSitingLocation : MOS_BITFIELD_RANGE(16, 23); 279 uint32_t DW1_Reserved_0 : MOS_BITFIELD_RANGE(24, 31); 280 }; 281 uint32_t DW1; 282 }; 283 284 union 285 { 286 struct 287 { 288 // DWORD 2 289 uint32_t DW2_OriginalPicWidthInSamples : MOS_BITFIELD_RANGE(0, 15); 290 uint32_t DW2_OriginalPicHeightInSamples : MOS_BITFIELD_RANGE(16, 31); 291 }; 292 uint32_t DW2; 293 }; 294 295 // DWORD 3 296 uint32_t DW3_MBFlatnessThreshold; 297 298 // DWORD 4 299 uint32_t DW4_CSC_Coefficient_C0 : MOS_BITFIELD_RANGE(0, 15); 300 uint32_t DW4_CSC_Coefficient_C1 : MOS_BITFIELD_RANGE(16, 31); 301 302 // DWORD 5 303 uint32_t DW5_CSC_Coefficient_C2 : MOS_BITFIELD_RANGE(0, 15); 304 uint32_t DW5_CSC_Coefficient_C3 : MOS_BITFIELD_RANGE(16, 31); 305 306 // DWORD 6 307 uint32_t DW6_CSC_Coefficient_C4 : MOS_BITFIELD_RANGE(0, 15); 308 uint32_t DW6_CSC_Coefficient_C5 : MOS_BITFIELD_RANGE(16, 31); 309 310 // DWORD 7 311 uint32_t DW7_CSC_Coefficient_C6 : MOS_BITFIELD_RANGE(0, 15); 312 uint32_t DW7_CSC_Coefficient_C7 : MOS_BITFIELD_RANGE(16, 31); 313 314 // DWORD 8 315 uint32_t DW8_CSC_Coefficient_C8 : MOS_BITFIELD_RANGE(0, 15); 316 uint32_t DW8_CSC_Coefficient_C9 : MOS_BITFIELD_RANGE(16, 31); 317 318 // DWORD 9 319 uint32_t DW9_CSC_Coefficient_C10 : MOS_BITFIELD_RANGE(0, 15); 320 uint32_t DW9_CSC_Coefficient_C11 : MOS_BITFIELD_RANGE(16, 31); 321 322 // DWORD 10 323 uint32_t DW10_BTI_InputSurface; 324 325 // DWORD 11 326 uint32_t DW11_BTI_Enc8BitSurface; 327 328 // DWORD 12 329 uint32_t DW12_BTI_4xDsSurface; 330 331 // DWORD 13 332 uint32_t DW13_BTI_MbStatsSurface; 333 334 // DWORD 14 335 uint32_t DW14_BTI_2xDsSurface; 336 337 // DWORD 15 338 uint32_t DW15_BTI_HistoryBuffer; 339 340 // DWORD 16 341 uint32_t DW16_BTI_HistorySumBuffer; 342 343 // DWORD 17 344 uint32_t DW17_BTI_MultiTaskBuffer; 345 }; 346 C_ASSERT(MOS_BYTES_TO_DWORDS(sizeof(CscKernelCurbeData)) == 18); 347 348 //! 349 //! \brief 4xDS kernel binding table 350 //! 351 enum Ds4xKernelBTI 352 { 353 ds4xSrcYPlane = 0, 354 ds4xDstYPlane = 1, 355 ds4xSrcYPlaneTopField = 0, 356 ds4xDstYPlaneTopField = 1, 357 ds4xSrcYPlaneBtmField = 2, 358 ds4xDstYPlaneBtmField = 3, 359 ds4xDstMbVProc = 4, 360 ds4xDstMbVProcTopField = 4, 361 ds4xDstMbVProcBtmField = 5, 362 ds4xNumSurfaces = 6 363 }; 364 365 virtual MOS_STATUS CheckRawColorFormat(MOS_FORMAT format, MOS_TILE_TYPE tileType) override; 366 virtual MOS_STATUS SetCurbeCsc() override; 367 virtual MOS_STATUS SendSurfaceCsc(PMOS_COMMAND_BUFFER cmdBuffer) override; 368 virtual MOS_STATUS InitSfcState() override; 369 }; 370 371 #endif // __CodechalEncodeCscDsG12__ 372