1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __ALPHA_IRONGATE__H__
3 #define __ALPHA_IRONGATE__H__
4 
5 #include <linux/types.h>
6 #include <asm/compiler.h>
7 
8 /*
9  * IRONGATE is the internal name for the AMD-751 K7 core logic chipset
10  * which provides memory controller and PCI access for NAUTILUS-based
11  * EV6 (21264) systems.
12  *
13  * This file is based on:
14  *
15  * IronGate management library, (c) 1999 Alpha Processor, Inc.
16  * Copyright (C) 1999 Alpha Processor, Inc.,
17  *	(David Daniel, Stig Telfer, Soohoon Lee)
18  */
19 
20 /*
21  * The 21264 supports, and internally recognizes, a 44-bit physical
22  * address space that is divided equally between memory address space
23  * and I/O address space. Memory address space resides in the lower
24  * half of the physical address space (PA[43]=0) and I/O address space
25  * resides in the upper half of the physical address space (PA[43]=1).
26  */
27 
28 /*
29  * Irongate CSR map.  Some of the CSRs are 8 or 16 bits, but all access
30  * through the routines given is 32-bit.
31  *
32  * The first 0x40 bytes are standard as per the PCI spec.
33  */
34 
35 typedef volatile __u32	igcsr32;
36 
37 typedef struct {
38 	igcsr32 dev_vendor;		/* 0x00 - device ID, vendor ID */
39 	igcsr32 stat_cmd;		/* 0x04 - status, command */
40 	igcsr32 class;			/* 0x08 - class code, rev ID */
41 	igcsr32 latency;		/* 0x0C - header type, PCI latency */
42 	igcsr32 bar0;			/* 0x10 - BAR0 - AGP */
43 	igcsr32 bar1;			/* 0x14 - BAR1 - GART */
44 	igcsr32 bar2;			/* 0x18 - Power Management reg block */
45 
46 	igcsr32 rsrvd0[6];		/* 0x1C-0x33 reserved */
47 
48 	igcsr32 capptr;			/* 0x34 - Capabilities pointer */
49 
50 	igcsr32 rsrvd1[2];		/* 0x38-0x3F reserved */
51 
52 	igcsr32 bacsr10;		/* 0x40 - base address chip selects */
53 	igcsr32 bacsr32;		/* 0x44 - base address chip selects */
54 	igcsr32 bacsr54_eccms761;	/* 0x48 - 751: base addr. chip selects
55 						  761: ECC, mode/status */
56 
57 	igcsr32 rsrvd2[1];		/* 0x4C-0x4F reserved */
58 
59 	igcsr32 drammap;		/* 0x50 - address mapping control */
60 	igcsr32 dramtm;			/* 0x54 - timing, driver strength */
61 	igcsr32 dramms;			/* 0x58 - DRAM mode/status */
62 
63 	igcsr32 rsrvd3[1];		/* 0x5C-0x5F reserved */
64 
65 	igcsr32 biu0;			/* 0x60 - bus interface unit */
66 	igcsr32 biusip;			/* 0x64 - Serial initialisation pkt */
67 
68 	igcsr32 rsrvd4[2];		/* 0x68-0x6F reserved */
69 
70 	igcsr32 mro;			/* 0x70 - memory request optimiser */
71 
72 	igcsr32 rsrvd5[3];		/* 0x74-0x7F reserved */
73 
74 	igcsr32 whami;			/* 0x80 - who am I */
75 	igcsr32 pciarb;			/* 0x84 - PCI arbitration control */
76 	igcsr32 pcicfg;			/* 0x88 - PCI config status */
77 
78 	igcsr32 rsrvd6[4];		/* 0x8C-0x9B reserved */
79 
80 	igcsr32 pci_mem;		/* 0x9C - PCI top of memory,
81 						  761 only */
82 
83 	/* AGP (bus 1) control registers */
84 	igcsr32 agpcap;			/* 0xA0 - AGP Capability Identifier */
85 	igcsr32 agpstat;		/* 0xA4 - AGP status register */
86 	igcsr32 agpcmd;			/* 0xA8 - AGP control register */
87 	igcsr32 agpva;			/* 0xAC - AGP Virtual Address Space */
88 	igcsr32 agpmode;		/* 0xB0 - AGP/GART mode control */
89 } Irongate0;
90 
91 
92 typedef struct {
93 
94 	igcsr32 dev_vendor;		/* 0x00 - Device and Vendor IDs */
95 	igcsr32 stat_cmd;		/* 0x04 - Status and Command regs */
96 	igcsr32 class;			/* 0x08 - subclass, baseclass etc */
97 	igcsr32 htype;			/* 0x0C - header type (at 0x0E) */
98 	igcsr32 rsrvd0[2];		/* 0x10-0x17 reserved */
99 	igcsr32 busnos;			/* 0x18 - Primary, secondary bus nos */
100 	igcsr32 io_baselim_regs;	/* 0x1C - IO base, IO lim, AGP status */
101 	igcsr32	mem_baselim;		/* 0x20 - memory base, memory lim */
102 	igcsr32 pfmem_baselim;		/* 0x24 - prefetchable base, lim */
103 	igcsr32 rsrvd1[2];		/* 0x28-0x2F reserved */
104 	igcsr32 io_baselim;		/* 0x30 - IO base, IO limit */
105 	igcsr32 rsrvd2[2];		/* 0x34-0x3B - reserved */
106 	igcsr32 interrupt;		/* 0x3C - interrupt, PCI bridge ctrl */
107 
108 } Irongate1;
109 
110 extern igcsr32 *IronECC;
111 
112 /*
113  * Memory spaces:
114  */
115 
116 /* Irongate is consistent with a subset of the Tsunami memory map */
117 #ifdef USE_48_BIT_KSEG
118 #define IRONGATE_BIAS 0x80000000000UL
119 #else
120 #define IRONGATE_BIAS 0x10000000000UL
121 #endif
122 
123 
124 #define IRONGATE_MEM		(IDENT_ADDR | IRONGATE_BIAS | 0x000000000UL)
125 #define IRONGATE_IACK_SC	(IDENT_ADDR | IRONGATE_BIAS | 0x1F8000000UL)
126 #define IRONGATE_IO		(IDENT_ADDR | IRONGATE_BIAS | 0x1FC000000UL)
127 #define IRONGATE_CONF		(IDENT_ADDR | IRONGATE_BIAS | 0x1FE000000UL)
128 
129 /*
130  * PCI Configuration space accesses are formed like so:
131  *
132  * 0x1FE << 24 |  : 2 2 2 2 1 1 1 1 : 1 1 1 1 1 1 0 0 : 0 0 0 0 0 0 0 0 :
133  *                : 3 2 1 0 9 8 7 6 : 5 4 3 2 1 0 9 8 : 7 6 5 4 3 2 1 0 :
134  *                  ---bus numer---   -device-- -fun-   ---register----
135  */
136 
137 #define IGCSR(dev,fun,reg)	( IRONGATE_CONF | \
138 				((dev)<<11) | \
139 				((fun)<<8) | \
140 				(reg) )
141 
142 #define IRONGATE0		((Irongate0 *) IGCSR(0, 0, 0))
143 #define IRONGATE1		((Irongate1 *) IGCSR(1, 0, 0))
144 
145 /*
146  * Data structure for handling IRONGATE machine checks:
147  * This is the standard OSF logout frame
148  */
149 
150 #define SCB_Q_SYSERR	0x620			/* OSF definitions */
151 #define SCB_Q_PROCERR	0x630
152 #define SCB_Q_SYSMCHK	0x660
153 #define SCB_Q_PROCMCHK	0x670
154 
155 struct el_IRONGATE_sysdata_mcheck {
156 	__u32 FrameSize;                 /* Bytes, including this field */
157 	__u32 FrameFlags;                /* <31> = Retry, <30> = Second Error */
158 	__u32 CpuOffset;                 /* Offset to CPU-specific into */
159 	__u32 SystemOffset;              /* Offset to system-specific info */
160 	__u32 MCHK_Code;
161 	__u32 MCHK_Frame_Rev;
162 	__u64 I_STAT;
163 	__u64 DC_STAT;
164 	__u64 C_ADDR;
165 	__u64 DC1_SYNDROME;
166 	__u64 DC0_SYNDROME;
167 	__u64 C_STAT;
168 	__u64 C_STS;
169 	__u64 RESERVED0;
170 	__u64 EXC_ADDR;
171 	__u64 IER_CM;
172 	__u64 ISUM;
173 	__u64 MM_STAT;
174 	__u64 PAL_BASE;
175 	__u64 I_CTL;
176 	__u64 PCTX;
177 };
178 
179 
180 #ifdef __KERNEL__
181 
182 #ifndef __EXTERN_INLINE
183 #define __EXTERN_INLINE extern inline
184 #define __IO_EXTERN_INLINE
185 #endif
186 
187 /*
188  * I/O functions:
189  *
190  * IRONGATE (AMD-751) PCI/memory support chip for the EV6 (21264) and
191  * K7 can only use linear accesses to get at PCI memory and I/O spaces.
192  */
193 
194 /*
195  * Memory functions.  All accesses are done through linear space.
196  */
197 
irongate_ioportmap(unsigned long addr)198 __EXTERN_INLINE void __iomem *irongate_ioportmap(unsigned long addr)
199 {
200 	return (void __iomem *)(addr + IRONGATE_IO);
201 }
202 
203 extern void __iomem *irongate_ioremap(unsigned long addr, unsigned long size);
204 extern void irongate_iounmap(volatile void __iomem *addr);
205 
irongate_is_ioaddr(unsigned long addr)206 __EXTERN_INLINE int irongate_is_ioaddr(unsigned long addr)
207 {
208 	return addr >= IRONGATE_MEM;
209 }
210 
irongate_is_mmio(const volatile void __iomem * xaddr)211 __EXTERN_INLINE int irongate_is_mmio(const volatile void __iomem *xaddr)
212 {
213 	unsigned long addr = (unsigned long)xaddr;
214 	return addr < IRONGATE_IO || addr >= IRONGATE_CONF;
215 }
216 
217 #undef __IO_PREFIX
218 #define __IO_PREFIX			irongate
219 #define irongate_trivial_rw_bw		1
220 #define irongate_trivial_rw_lq		1
221 #define irongate_trivial_io_bw		1
222 #define irongate_trivial_io_lq		1
223 #define irongate_trivial_iounmap	0
224 #include <asm/io_trivial.h>
225 
226 #ifdef __IO_EXTERN_INLINE
227 #undef __EXTERN_INLINE
228 #undef __IO_EXTERN_INLINE
229 #endif
230 
231 #endif /* __KERNEL__ */
232 
233 #endif /* __ALPHA_IRONGATE__H__ */
234