1 // SPDX-License-Identifier: GPL-2.0
2 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
3
4 #include <linux/errno.h>
5 #include <linux/kernel.h>
6 #include <linux/mm.h>
7 #include <linux/smp.h>
8 #include <linux/prctl.h>
9 #include <linux/slab.h>
10 #include <linux/sched.h>
11 #include <linux/sched/idle.h>
12 #include <linux/sched/debug.h>
13 #include <linux/sched/task.h>
14 #include <linux/sched/task_stack.h>
15 #include <linux/init.h>
16 #include <linux/export.h>
17 #include <linux/pm.h>
18 #include <linux/tick.h>
19 #include <linux/random.h>
20 #include <linux/user-return-notifier.h>
21 #include <linux/dmi.h>
22 #include <linux/utsname.h>
23 #include <linux/stackprotector.h>
24 #include <linux/cpuidle.h>
25 #include <linux/acpi.h>
26 #include <linux/elf-randomize.h>
27 #include <trace/events/power.h>
28 #include <linux/hw_breakpoint.h>
29 #include <asm/cpu.h>
30 #include <asm/apic.h>
31 #include <linux/uaccess.h>
32 #include <asm/mwait.h>
33 #include <asm/fpu/internal.h>
34 #include <asm/debugreg.h>
35 #include <asm/nmi.h>
36 #include <asm/tlbflush.h>
37 #include <asm/mce.h>
38 #include <asm/vm86.h>
39 #include <asm/switch_to.h>
40 #include <asm/desc.h>
41 #include <asm/prctl.h>
42 #include <asm/spec-ctrl.h>
43 #include <asm/io_bitmap.h>
44 #include <asm/proto.h>
45 #include <asm/frame.h>
46
47 #include "process.h"
48
49 /*
50 * per-CPU TSS segments. Threads are completely 'soft' on Linux,
51 * no more per-task TSS's. The TSS size is kept cacheline-aligned
52 * so they are allowed to end up in the .data..cacheline_aligned
53 * section. Since TSS's are completely CPU-local, we want them
54 * on exact cacheline boundaries, to eliminate cacheline ping-pong.
55 */
56 __visible DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw) = {
57 .x86_tss = {
58 /*
59 * .sp0 is only used when entering ring 0 from a lower
60 * privilege level. Since the init task never runs anything
61 * but ring 0 code, there is no need for a valid value here.
62 * Poison it.
63 */
64 .sp0 = (1UL << (BITS_PER_LONG-1)) + 1,
65
66 #ifdef CONFIG_X86_32
67 .sp1 = TOP_OF_INIT_STACK,
68
69 .ss0 = __KERNEL_DS,
70 .ss1 = __KERNEL_CS,
71 #endif
72 .io_bitmap_base = IO_BITMAP_OFFSET_INVALID,
73 },
74 };
75 EXPORT_PER_CPU_SYMBOL(cpu_tss_rw);
76
77 DEFINE_PER_CPU(bool, __tss_limit_invalid);
78 EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid);
79
80 /*
81 * this gets called so that we can store lazy state into memory and copy the
82 * current task into the new thread.
83 */
arch_dup_task_struct(struct task_struct * dst,struct task_struct * src)84 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
85 {
86 memcpy(dst, src, arch_task_struct_size);
87 #ifdef CONFIG_VM86
88 dst->thread.vm86 = NULL;
89 #endif
90
91 return fpu__copy(dst, src);
92 }
93
94 /*
95 * Free thread data structures etc..
96 */
exit_thread(struct task_struct * tsk)97 void exit_thread(struct task_struct *tsk)
98 {
99 struct thread_struct *t = &tsk->thread;
100 struct fpu *fpu = &t->fpu;
101
102 if (test_thread_flag(TIF_IO_BITMAP))
103 io_bitmap_exit(tsk);
104
105 free_vm86(t);
106
107 fpu__drop(fpu);
108 }
109
set_new_tls(struct task_struct * p,unsigned long tls)110 static int set_new_tls(struct task_struct *p, unsigned long tls)
111 {
112 struct user_desc __user *utls = (struct user_desc __user *)tls;
113
114 if (in_ia32_syscall())
115 return do_set_thread_area(p, -1, utls, 0);
116 else
117 return do_set_thread_area_64(p, ARCH_SET_FS, tls);
118 }
119
copy_thread(unsigned long clone_flags,unsigned long sp,unsigned long arg,struct task_struct * p,unsigned long tls)120 int copy_thread(unsigned long clone_flags, unsigned long sp, unsigned long arg,
121 struct task_struct *p, unsigned long tls)
122 {
123 struct inactive_task_frame *frame;
124 struct fork_frame *fork_frame;
125 struct pt_regs *childregs;
126 int ret = 0;
127
128 childregs = task_pt_regs(p);
129 fork_frame = container_of(childregs, struct fork_frame, regs);
130 frame = &fork_frame->frame;
131
132 frame->bp = encode_frame_pointer(childregs);
133 frame->ret_addr = (unsigned long) ret_from_fork;
134 p->thread.sp = (unsigned long) fork_frame;
135 p->thread.io_bitmap = NULL;
136 memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps));
137
138 #ifdef CONFIG_X86_64
139 current_save_fsgs();
140 p->thread.fsindex = current->thread.fsindex;
141 p->thread.fsbase = current->thread.fsbase;
142 p->thread.gsindex = current->thread.gsindex;
143 p->thread.gsbase = current->thread.gsbase;
144
145 savesegment(es, p->thread.es);
146 savesegment(ds, p->thread.ds);
147 #else
148 p->thread.sp0 = (unsigned long) (childregs + 1);
149 /*
150 * Clear all status flags including IF and set fixed bit. 64bit
151 * does not have this initialization as the frame does not contain
152 * flags. The flags consistency (especially vs. AC) is there
153 * ensured via objtool, which lacks 32bit support.
154 */
155 frame->flags = X86_EFLAGS_FIXED;
156 #endif
157
158 /* Kernel thread ? */
159 if (unlikely(p->flags & PF_KTHREAD)) {
160 memset(childregs, 0, sizeof(struct pt_regs));
161 kthread_frame_init(frame, sp, arg);
162 return 0;
163 }
164
165 frame->bx = 0;
166 *childregs = *current_pt_regs();
167 childregs->ax = 0;
168 if (sp)
169 childregs->sp = sp;
170
171 #ifdef CONFIG_X86_32
172 task_user_gs(p) = get_user_gs(current_pt_regs());
173 #endif
174
175 if (unlikely(p->flags & PF_IO_WORKER)) {
176 /*
177 * An IO thread is a user space thread, but it doesn't
178 * return to ret_after_fork().
179 *
180 * In order to indicate that to tools like gdb,
181 * we reset the stack and instruction pointers.
182 *
183 * It does the same kernel frame setup to return to a kernel
184 * function that a kernel thread does.
185 */
186 childregs->sp = 0;
187 childregs->ip = 0;
188 kthread_frame_init(frame, sp, arg);
189 return 0;
190 }
191
192 /* Set a new TLS for the child thread? */
193 if (clone_flags & CLONE_SETTLS)
194 ret = set_new_tls(p, tls);
195
196 if (!ret && unlikely(test_tsk_thread_flag(current, TIF_IO_BITMAP)))
197 io_bitmap_share(p);
198
199 return ret;
200 }
201
flush_thread(void)202 void flush_thread(void)
203 {
204 struct task_struct *tsk = current;
205
206 flush_ptrace_hw_breakpoint(tsk);
207 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
208
209 fpu__clear_all(&tsk->thread.fpu);
210 }
211
disable_TSC(void)212 void disable_TSC(void)
213 {
214 preempt_disable();
215 if (!test_and_set_thread_flag(TIF_NOTSC))
216 /*
217 * Must flip the CPU state synchronously with
218 * TIF_NOTSC in the current running context.
219 */
220 cr4_set_bits(X86_CR4_TSD);
221 preempt_enable();
222 }
223
enable_TSC(void)224 static void enable_TSC(void)
225 {
226 preempt_disable();
227 if (test_and_clear_thread_flag(TIF_NOTSC))
228 /*
229 * Must flip the CPU state synchronously with
230 * TIF_NOTSC in the current running context.
231 */
232 cr4_clear_bits(X86_CR4_TSD);
233 preempt_enable();
234 }
235
get_tsc_mode(unsigned long adr)236 int get_tsc_mode(unsigned long adr)
237 {
238 unsigned int val;
239
240 if (test_thread_flag(TIF_NOTSC))
241 val = PR_TSC_SIGSEGV;
242 else
243 val = PR_TSC_ENABLE;
244
245 return put_user(val, (unsigned int __user *)adr);
246 }
247
set_tsc_mode(unsigned int val)248 int set_tsc_mode(unsigned int val)
249 {
250 if (val == PR_TSC_SIGSEGV)
251 disable_TSC();
252 else if (val == PR_TSC_ENABLE)
253 enable_TSC();
254 else
255 return -EINVAL;
256
257 return 0;
258 }
259
260 DEFINE_PER_CPU(u64, msr_misc_features_shadow);
261
set_cpuid_faulting(bool on)262 static void set_cpuid_faulting(bool on)
263 {
264 u64 msrval;
265
266 msrval = this_cpu_read(msr_misc_features_shadow);
267 msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT;
268 msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT);
269 this_cpu_write(msr_misc_features_shadow, msrval);
270 wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval);
271 }
272
disable_cpuid(void)273 static void disable_cpuid(void)
274 {
275 preempt_disable();
276 if (!test_and_set_thread_flag(TIF_NOCPUID)) {
277 /*
278 * Must flip the CPU state synchronously with
279 * TIF_NOCPUID in the current running context.
280 */
281 set_cpuid_faulting(true);
282 }
283 preempt_enable();
284 }
285
enable_cpuid(void)286 static void enable_cpuid(void)
287 {
288 preempt_disable();
289 if (test_and_clear_thread_flag(TIF_NOCPUID)) {
290 /*
291 * Must flip the CPU state synchronously with
292 * TIF_NOCPUID in the current running context.
293 */
294 set_cpuid_faulting(false);
295 }
296 preempt_enable();
297 }
298
get_cpuid_mode(void)299 static int get_cpuid_mode(void)
300 {
301 return !test_thread_flag(TIF_NOCPUID);
302 }
303
set_cpuid_mode(struct task_struct * task,unsigned long cpuid_enabled)304 static int set_cpuid_mode(struct task_struct *task, unsigned long cpuid_enabled)
305 {
306 if (!boot_cpu_has(X86_FEATURE_CPUID_FAULT))
307 return -ENODEV;
308
309 if (cpuid_enabled)
310 enable_cpuid();
311 else
312 disable_cpuid();
313
314 return 0;
315 }
316
317 /*
318 * Called immediately after a successful exec.
319 */
arch_setup_new_exec(void)320 void arch_setup_new_exec(void)
321 {
322 /* If cpuid was previously disabled for this task, re-enable it. */
323 if (test_thread_flag(TIF_NOCPUID))
324 enable_cpuid();
325
326 /*
327 * Don't inherit TIF_SSBD across exec boundary when
328 * PR_SPEC_DISABLE_NOEXEC is used.
329 */
330 if (test_thread_flag(TIF_SSBD) &&
331 task_spec_ssb_noexec(current)) {
332 clear_thread_flag(TIF_SSBD);
333 task_clear_spec_ssb_disable(current);
334 task_clear_spec_ssb_noexec(current);
335 speculation_ctrl_update(task_thread_info(current)->flags);
336 }
337 }
338
339 #ifdef CONFIG_X86_IOPL_IOPERM
switch_to_bitmap(unsigned long tifp)340 static inline void switch_to_bitmap(unsigned long tifp)
341 {
342 /*
343 * Invalidate I/O bitmap if the previous task used it. This prevents
344 * any possible leakage of an active I/O bitmap.
345 *
346 * If the next task has an I/O bitmap it will handle it on exit to
347 * user mode.
348 */
349 if (tifp & _TIF_IO_BITMAP)
350 tss_invalidate_io_bitmap();
351 }
352
tss_copy_io_bitmap(struct tss_struct * tss,struct io_bitmap * iobm)353 static void tss_copy_io_bitmap(struct tss_struct *tss, struct io_bitmap *iobm)
354 {
355 /*
356 * Copy at least the byte range of the incoming tasks bitmap which
357 * covers the permitted I/O ports.
358 *
359 * If the previous task which used an I/O bitmap had more bits
360 * permitted, then the copy needs to cover those as well so they
361 * get turned off.
362 */
363 memcpy(tss->io_bitmap.bitmap, iobm->bitmap,
364 max(tss->io_bitmap.prev_max, iobm->max));
365
366 /*
367 * Store the new max and the sequence number of this bitmap
368 * and a pointer to the bitmap itself.
369 */
370 tss->io_bitmap.prev_max = iobm->max;
371 tss->io_bitmap.prev_sequence = iobm->sequence;
372 }
373
374 /**
375 * tss_update_io_bitmap - Update I/O bitmap before exiting to usermode
376 */
native_tss_update_io_bitmap(void)377 void native_tss_update_io_bitmap(void)
378 {
379 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
380 struct thread_struct *t = ¤t->thread;
381 u16 *base = &tss->x86_tss.io_bitmap_base;
382
383 if (!test_thread_flag(TIF_IO_BITMAP)) {
384 native_tss_invalidate_io_bitmap();
385 return;
386 }
387
388 if (IS_ENABLED(CONFIG_X86_IOPL_IOPERM) && t->iopl_emul == 3) {
389 *base = IO_BITMAP_OFFSET_VALID_ALL;
390 } else {
391 struct io_bitmap *iobm = t->io_bitmap;
392
393 /*
394 * Only copy bitmap data when the sequence number differs. The
395 * update time is accounted to the incoming task.
396 */
397 if (tss->io_bitmap.prev_sequence != iobm->sequence)
398 tss_copy_io_bitmap(tss, iobm);
399
400 /* Enable the bitmap */
401 *base = IO_BITMAP_OFFSET_VALID_MAP;
402 }
403
404 /*
405 * Make sure that the TSS limit is covering the IO bitmap. It might have
406 * been cut down by a VMEXIT to 0x67 which would cause a subsequent I/O
407 * access from user space to trigger a #GP because tbe bitmap is outside
408 * the TSS limit.
409 */
410 refresh_tss_limit();
411 }
412 #else /* CONFIG_X86_IOPL_IOPERM */
switch_to_bitmap(unsigned long tifp)413 static inline void switch_to_bitmap(unsigned long tifp) { }
414 #endif
415
416 #ifdef CONFIG_SMP
417
418 struct ssb_state {
419 struct ssb_state *shared_state;
420 raw_spinlock_t lock;
421 unsigned int disable_state;
422 unsigned long local_state;
423 };
424
425 #define LSTATE_SSB 0
426
427 static DEFINE_PER_CPU(struct ssb_state, ssb_state);
428
speculative_store_bypass_ht_init(void)429 void speculative_store_bypass_ht_init(void)
430 {
431 struct ssb_state *st = this_cpu_ptr(&ssb_state);
432 unsigned int this_cpu = smp_processor_id();
433 unsigned int cpu;
434
435 st->local_state = 0;
436
437 /*
438 * Shared state setup happens once on the first bringup
439 * of the CPU. It's not destroyed on CPU hotunplug.
440 */
441 if (st->shared_state)
442 return;
443
444 raw_spin_lock_init(&st->lock);
445
446 /*
447 * Go over HT siblings and check whether one of them has set up the
448 * shared state pointer already.
449 */
450 for_each_cpu(cpu, topology_sibling_cpumask(this_cpu)) {
451 if (cpu == this_cpu)
452 continue;
453
454 if (!per_cpu(ssb_state, cpu).shared_state)
455 continue;
456
457 /* Link it to the state of the sibling: */
458 st->shared_state = per_cpu(ssb_state, cpu).shared_state;
459 return;
460 }
461
462 /*
463 * First HT sibling to come up on the core. Link shared state of
464 * the first HT sibling to itself. The siblings on the same core
465 * which come up later will see the shared state pointer and link
466 * themselves to the state of this CPU.
467 */
468 st->shared_state = st;
469 }
470
471 /*
472 * Logic is: First HT sibling enables SSBD for both siblings in the core
473 * and last sibling to disable it, disables it for the whole core. This how
474 * MSR_SPEC_CTRL works in "hardware":
475 *
476 * CORE_SPEC_CTRL = THREAD0_SPEC_CTRL | THREAD1_SPEC_CTRL
477 */
amd_set_core_ssb_state(unsigned long tifn)478 static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
479 {
480 struct ssb_state *st = this_cpu_ptr(&ssb_state);
481 u64 msr = x86_amd_ls_cfg_base;
482
483 if (!static_cpu_has(X86_FEATURE_ZEN)) {
484 msr |= ssbd_tif_to_amd_ls_cfg(tifn);
485 wrmsrl(MSR_AMD64_LS_CFG, msr);
486 return;
487 }
488
489 if (tifn & _TIF_SSBD) {
490 /*
491 * Since this can race with prctl(), block reentry on the
492 * same CPU.
493 */
494 if (__test_and_set_bit(LSTATE_SSB, &st->local_state))
495 return;
496
497 msr |= x86_amd_ls_cfg_ssbd_mask;
498
499 raw_spin_lock(&st->shared_state->lock);
500 /* First sibling enables SSBD: */
501 if (!st->shared_state->disable_state)
502 wrmsrl(MSR_AMD64_LS_CFG, msr);
503 st->shared_state->disable_state++;
504 raw_spin_unlock(&st->shared_state->lock);
505 } else {
506 if (!__test_and_clear_bit(LSTATE_SSB, &st->local_state))
507 return;
508
509 raw_spin_lock(&st->shared_state->lock);
510 st->shared_state->disable_state--;
511 if (!st->shared_state->disable_state)
512 wrmsrl(MSR_AMD64_LS_CFG, msr);
513 raw_spin_unlock(&st->shared_state->lock);
514 }
515 }
516 #else
amd_set_core_ssb_state(unsigned long tifn)517 static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
518 {
519 u64 msr = x86_amd_ls_cfg_base | ssbd_tif_to_amd_ls_cfg(tifn);
520
521 wrmsrl(MSR_AMD64_LS_CFG, msr);
522 }
523 #endif
524
amd_set_ssb_virt_state(unsigned long tifn)525 static __always_inline void amd_set_ssb_virt_state(unsigned long tifn)
526 {
527 /*
528 * SSBD has the same definition in SPEC_CTRL and VIRT_SPEC_CTRL,
529 * so ssbd_tif_to_spec_ctrl() just works.
530 */
531 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn));
532 }
533
534 /*
535 * Update the MSRs managing speculation control, during context switch.
536 *
537 * tifp: Previous task's thread flags
538 * tifn: Next task's thread flags
539 */
__speculation_ctrl_update(unsigned long tifp,unsigned long tifn)540 static __always_inline void __speculation_ctrl_update(unsigned long tifp,
541 unsigned long tifn)
542 {
543 unsigned long tif_diff = tifp ^ tifn;
544 u64 msr = x86_spec_ctrl_base;
545 bool updmsr = false;
546
547 lockdep_assert_irqs_disabled();
548
549 /* Handle change of TIF_SSBD depending on the mitigation method. */
550 if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) {
551 if (tif_diff & _TIF_SSBD)
552 amd_set_ssb_virt_state(tifn);
553 } else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) {
554 if (tif_diff & _TIF_SSBD)
555 amd_set_core_ssb_state(tifn);
556 } else if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
557 static_cpu_has(X86_FEATURE_AMD_SSBD)) {
558 updmsr |= !!(tif_diff & _TIF_SSBD);
559 msr |= ssbd_tif_to_spec_ctrl(tifn);
560 }
561
562 /* Only evaluate TIF_SPEC_IB if conditional STIBP is enabled. */
563 if (IS_ENABLED(CONFIG_SMP) &&
564 static_branch_unlikely(&switch_to_cond_stibp)) {
565 updmsr |= !!(tif_diff & _TIF_SPEC_IB);
566 msr |= stibp_tif_to_spec_ctrl(tifn);
567 }
568
569 if (updmsr)
570 wrmsrl(MSR_IA32_SPEC_CTRL, msr);
571 }
572
speculation_ctrl_update_tif(struct task_struct * tsk)573 static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk)
574 {
575 if (test_and_clear_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE)) {
576 if (task_spec_ssb_disable(tsk))
577 set_tsk_thread_flag(tsk, TIF_SSBD);
578 else
579 clear_tsk_thread_flag(tsk, TIF_SSBD);
580
581 if (task_spec_ib_disable(tsk))
582 set_tsk_thread_flag(tsk, TIF_SPEC_IB);
583 else
584 clear_tsk_thread_flag(tsk, TIF_SPEC_IB);
585 }
586 /* Return the updated threadinfo flags*/
587 return task_thread_info(tsk)->flags;
588 }
589
speculation_ctrl_update(unsigned long tif)590 void speculation_ctrl_update(unsigned long tif)
591 {
592 unsigned long flags;
593
594 /* Forced update. Make sure all relevant TIF flags are different */
595 local_irq_save(flags);
596 __speculation_ctrl_update(~tif, tif);
597 local_irq_restore(flags);
598 }
599
600 /* Called from seccomp/prctl update */
speculation_ctrl_update_current(void)601 void speculation_ctrl_update_current(void)
602 {
603 preempt_disable();
604 speculation_ctrl_update(speculation_ctrl_update_tif(current));
605 preempt_enable();
606 }
607
cr4_toggle_bits_irqsoff(unsigned long mask)608 static inline void cr4_toggle_bits_irqsoff(unsigned long mask)
609 {
610 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4);
611
612 newval = cr4 ^ mask;
613 if (newval != cr4) {
614 this_cpu_write(cpu_tlbstate.cr4, newval);
615 __write_cr4(newval);
616 }
617 }
618
__switch_to_xtra(struct task_struct * prev_p,struct task_struct * next_p)619 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p)
620 {
621 unsigned long tifp, tifn;
622
623 tifn = READ_ONCE(task_thread_info(next_p)->flags);
624 tifp = READ_ONCE(task_thread_info(prev_p)->flags);
625
626 switch_to_bitmap(tifp);
627
628 propagate_user_return_notify(prev_p, next_p);
629
630 if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) &&
631 arch_has_block_step()) {
632 unsigned long debugctl, msk;
633
634 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
635 debugctl &= ~DEBUGCTLMSR_BTF;
636 msk = tifn & _TIF_BLOCKSTEP;
637 debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT;
638 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
639 }
640
641 if ((tifp ^ tifn) & _TIF_NOTSC)
642 cr4_toggle_bits_irqsoff(X86_CR4_TSD);
643
644 if ((tifp ^ tifn) & _TIF_NOCPUID)
645 set_cpuid_faulting(!!(tifn & _TIF_NOCPUID));
646
647 if (likely(!((tifp | tifn) & _TIF_SPEC_FORCE_UPDATE))) {
648 __speculation_ctrl_update(tifp, tifn);
649 } else {
650 speculation_ctrl_update_tif(prev_p);
651 tifn = speculation_ctrl_update_tif(next_p);
652
653 /* Enforce MSR update to ensure consistent state */
654 __speculation_ctrl_update(~tifn, tifn);
655 }
656
657 if ((tifp ^ tifn) & _TIF_SLD)
658 switch_to_sld(tifn);
659 }
660
661 /*
662 * Idle related variables and functions
663 */
664 unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
665 EXPORT_SYMBOL(boot_option_idle_override);
666
667 static void (*x86_idle)(void);
668
669 #ifndef CONFIG_SMP
play_dead(void)670 static inline void play_dead(void)
671 {
672 BUG();
673 }
674 #endif
675
arch_cpu_idle_enter(void)676 void arch_cpu_idle_enter(void)
677 {
678 tsc_verify_tsc_adjust(false);
679 local_touch_nmi();
680 }
681
arch_cpu_idle_dead(void)682 void arch_cpu_idle_dead(void)
683 {
684 play_dead();
685 }
686
687 /*
688 * Called from the generic idle code.
689 */
arch_cpu_idle(void)690 void arch_cpu_idle(void)
691 {
692 x86_idle();
693 }
694
695 /*
696 * We use this if we don't have any better idle routine..
697 */
default_idle(void)698 void __cpuidle default_idle(void)
699 {
700 raw_safe_halt();
701 }
702 #if defined(CONFIG_APM_MODULE) || defined(CONFIG_HALTPOLL_CPUIDLE_MODULE)
703 EXPORT_SYMBOL(default_idle);
704 #endif
705
706 #ifdef CONFIG_XEN
xen_set_default_idle(void)707 bool xen_set_default_idle(void)
708 {
709 bool ret = !!x86_idle;
710
711 x86_idle = default_idle;
712
713 return ret;
714 }
715 #endif
716
stop_this_cpu(void * dummy)717 void stop_this_cpu(void *dummy)
718 {
719 local_irq_disable();
720 /*
721 * Remove this CPU:
722 */
723 set_cpu_online(smp_processor_id(), false);
724 disable_local_APIC();
725 mcheck_cpu_clear(this_cpu_ptr(&cpu_info));
726
727 /*
728 * Use wbinvd on processors that support SME. This provides support
729 * for performing a successful kexec when going from SME inactive
730 * to SME active (or vice-versa). The cache must be cleared so that
731 * if there are entries with the same physical address, both with and
732 * without the encryption bit, they don't race each other when flushed
733 * and potentially end up with the wrong entry being committed to
734 * memory.
735 */
736 if (boot_cpu_has(X86_FEATURE_SME))
737 native_wbinvd();
738 for (;;) {
739 /*
740 * Use native_halt() so that memory contents don't change
741 * (stack usage and variables) after possibly issuing the
742 * native_wbinvd() above.
743 */
744 native_halt();
745 }
746 }
747
748 /*
749 * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power
750 * states (local apic timer and TSC stop).
751 *
752 * XXX this function is completely buggered vs RCU and tracing.
753 */
amd_e400_idle(void)754 static void amd_e400_idle(void)
755 {
756 /*
757 * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E
758 * gets set after static_cpu_has() places have been converted via
759 * alternatives.
760 */
761 if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
762 default_idle();
763 return;
764 }
765
766 tick_broadcast_enter();
767
768 default_idle();
769
770 /*
771 * The switch back from broadcast mode needs to be called with
772 * interrupts disabled.
773 */
774 raw_local_irq_disable();
775 tick_broadcast_exit();
776 raw_local_irq_enable();
777 }
778
779 /*
780 * Intel Core2 and older machines prefer MWAIT over HALT for C1.
781 * We can't rely on cpuidle installing MWAIT, because it will not load
782 * on systems that support only C1 -- so the boot default must be MWAIT.
783 *
784 * Some AMD machines are the opposite, they depend on using HALT.
785 *
786 * So for default C1, which is used during boot until cpuidle loads,
787 * use MWAIT-C1 on Intel HW that has it, else use HALT.
788 */
prefer_mwait_c1_over_halt(const struct cpuinfo_x86 * c)789 static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c)
790 {
791 if (c->x86_vendor != X86_VENDOR_INTEL)
792 return 0;
793
794 if (!cpu_has(c, X86_FEATURE_MWAIT) || boot_cpu_has_bug(X86_BUG_MONITOR))
795 return 0;
796
797 return 1;
798 }
799
800 /*
801 * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT
802 * with interrupts enabled and no flags, which is backwards compatible with the
803 * original MWAIT implementation.
804 */
mwait_idle(void)805 static __cpuidle void mwait_idle(void)
806 {
807 if (!current_set_polling_and_test()) {
808 if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) {
809 mb(); /* quirk */
810 clflush((void *)¤t_thread_info()->flags);
811 mb(); /* quirk */
812 }
813
814 __monitor((void *)¤t_thread_info()->flags, 0, 0);
815 if (!need_resched())
816 __sti_mwait(0, 0);
817 else
818 raw_local_irq_enable();
819 } else {
820 raw_local_irq_enable();
821 }
822 __current_clr_polling();
823 }
824
select_idle_routine(const struct cpuinfo_x86 * c)825 void select_idle_routine(const struct cpuinfo_x86 *c)
826 {
827 #ifdef CONFIG_SMP
828 if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
829 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
830 #endif
831 if (x86_idle || boot_option_idle_override == IDLE_POLL)
832 return;
833
834 if (boot_cpu_has_bug(X86_BUG_AMD_E400)) {
835 pr_info("using AMD E400 aware idle routine\n");
836 x86_idle = amd_e400_idle;
837 } else if (prefer_mwait_c1_over_halt(c)) {
838 pr_info("using mwait in idle threads\n");
839 x86_idle = mwait_idle;
840 } else
841 x86_idle = default_idle;
842 }
843
amd_e400_c1e_apic_setup(void)844 void amd_e400_c1e_apic_setup(void)
845 {
846 if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
847 pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id());
848 local_irq_disable();
849 tick_broadcast_force();
850 local_irq_enable();
851 }
852 }
853
arch_post_acpi_subsys_init(void)854 void __init arch_post_acpi_subsys_init(void)
855 {
856 u32 lo, hi;
857
858 if (!boot_cpu_has_bug(X86_BUG_AMD_E400))
859 return;
860
861 /*
862 * AMD E400 detection needs to happen after ACPI has been enabled. If
863 * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in
864 * MSR_K8_INT_PENDING_MSG.
865 */
866 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
867 if (!(lo & K8_INTP_C1E_ACTIVE_MASK))
868 return;
869
870 boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E);
871
872 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
873 mark_tsc_unstable("TSC halt in AMD C1E");
874 pr_info("System has AMD C1E enabled\n");
875 }
876
idle_setup(char * str)877 static int __init idle_setup(char *str)
878 {
879 if (!str)
880 return -EINVAL;
881
882 if (!strcmp(str, "poll")) {
883 pr_info("using polling idle threads\n");
884 boot_option_idle_override = IDLE_POLL;
885 cpu_idle_poll_ctrl(true);
886 } else if (!strcmp(str, "halt")) {
887 /*
888 * When the boot option of idle=halt is added, halt is
889 * forced to be used for CPU idle. In such case CPU C2/C3
890 * won't be used again.
891 * To continue to load the CPU idle driver, don't touch
892 * the boot_option_idle_override.
893 */
894 x86_idle = default_idle;
895 boot_option_idle_override = IDLE_HALT;
896 } else if (!strcmp(str, "nomwait")) {
897 /*
898 * If the boot option of "idle=nomwait" is added,
899 * it means that mwait will be disabled for CPU C2/C3
900 * states. In such case it won't touch the variable
901 * of boot_option_idle_override.
902 */
903 boot_option_idle_override = IDLE_NOMWAIT;
904 } else
905 return -1;
906
907 return 0;
908 }
909 early_param("idle", idle_setup);
910
arch_align_stack(unsigned long sp)911 unsigned long arch_align_stack(unsigned long sp)
912 {
913 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
914 sp -= get_random_int() % 8192;
915 return sp & ~0xf;
916 }
917
arch_randomize_brk(struct mm_struct * mm)918 unsigned long arch_randomize_brk(struct mm_struct *mm)
919 {
920 return randomize_page(mm->brk, 0x02000000);
921 }
922
923 /*
924 * Called from fs/proc with a reference on @p to find the function
925 * which called into schedule(). This needs to be done carefully
926 * because the task might wake up and we might look at a stack
927 * changing under us.
928 */
get_wchan(struct task_struct * p)929 unsigned long get_wchan(struct task_struct *p)
930 {
931 unsigned long start, bottom, top, sp, fp, ip, ret = 0;
932 int count = 0;
933
934 if (p == current || p->state == TASK_RUNNING)
935 return 0;
936
937 if (!try_get_task_stack(p))
938 return 0;
939
940 start = (unsigned long)task_stack_page(p);
941 if (!start)
942 goto out;
943
944 /*
945 * Layout of the stack page:
946 *
947 * ----------- topmax = start + THREAD_SIZE - sizeof(unsigned long)
948 * PADDING
949 * ----------- top = topmax - TOP_OF_KERNEL_STACK_PADDING
950 * stack
951 * ----------- bottom = start
952 *
953 * The tasks stack pointer points at the location where the
954 * framepointer is stored. The data on the stack is:
955 * ... IP FP ... IP FP
956 *
957 * We need to read FP and IP, so we need to adjust the upper
958 * bound by another unsigned long.
959 */
960 top = start + THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING;
961 top -= 2 * sizeof(unsigned long);
962 bottom = start;
963
964 sp = READ_ONCE(p->thread.sp);
965 if (sp < bottom || sp > top)
966 goto out;
967
968 fp = READ_ONCE_NOCHECK(((struct inactive_task_frame *)sp)->bp);
969 do {
970 if (fp < bottom || fp > top)
971 goto out;
972 ip = READ_ONCE_NOCHECK(*(unsigned long *)(fp + sizeof(unsigned long)));
973 if (!in_sched_functions(ip)) {
974 ret = ip;
975 goto out;
976 }
977 fp = READ_ONCE_NOCHECK(*(unsigned long *)fp);
978 } while (count++ < 16 && p->state != TASK_RUNNING);
979
980 out:
981 put_task_stack(p);
982 return ret;
983 }
984
do_arch_prctl_common(struct task_struct * task,int option,unsigned long cpuid_enabled)985 long do_arch_prctl_common(struct task_struct *task, int option,
986 unsigned long cpuid_enabled)
987 {
988 switch (option) {
989 case ARCH_GET_CPUID:
990 return get_cpuid_mode();
991 case ARCH_SET_CPUID:
992 return set_cpuid_mode(task, cpuid_enabled);
993 }
994
995 return -EINVAL;
996 }
997