1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/ktime.h>
29 #include <linux/module.h>
30 #include <linux/pagemap.h>
31 #include <linux/pci.h>
32 #include <linux/dma-buf.h>
33
34 #include <drm/amdgpu_drm.h>
35 #include <drm/drm_gem_ttm_helper.h>
36
37 #include "amdgpu.h"
38 #include "amdgpu_display.h"
39 #include "amdgpu_dma_buf.h"
40 #include "amdgpu_xgmi.h"
41
42 static const struct drm_gem_object_funcs amdgpu_gem_object_funcs;
43
amdgpu_gem_object_free(struct drm_gem_object * gobj)44 static void amdgpu_gem_object_free(struct drm_gem_object *gobj)
45 {
46 struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj);
47
48 if (robj) {
49 amdgpu_mn_unregister(robj);
50 amdgpu_bo_unref(&robj);
51 }
52 }
53
amdgpu_gem_object_create(struct amdgpu_device * adev,unsigned long size,int alignment,u32 initial_domain,u64 flags,enum ttm_bo_type type,struct dma_resv * resv,struct drm_gem_object ** obj)54 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
55 int alignment, u32 initial_domain,
56 u64 flags, enum ttm_bo_type type,
57 struct dma_resv *resv,
58 struct drm_gem_object **obj)
59 {
60 struct amdgpu_bo *bo;
61 struct amdgpu_bo_user *ubo;
62 struct amdgpu_bo_param bp;
63 int r;
64
65 memset(&bp, 0, sizeof(bp));
66 *obj = NULL;
67
68 bp.size = size;
69 bp.byte_align = alignment;
70 bp.type = type;
71 bp.resv = resv;
72 bp.preferred_domain = initial_domain;
73 bp.flags = flags;
74 bp.domain = initial_domain;
75 bp.bo_ptr_size = sizeof(struct amdgpu_bo);
76
77 r = amdgpu_bo_create_user(adev, &bp, &ubo);
78 if (r)
79 return r;
80
81 bo = &ubo->bo;
82 *obj = &bo->tbo.base;
83 (*obj)->funcs = &amdgpu_gem_object_funcs;
84
85 return 0;
86 }
87
amdgpu_gem_force_release(struct amdgpu_device * adev)88 void amdgpu_gem_force_release(struct amdgpu_device *adev)
89 {
90 struct drm_device *ddev = adev_to_drm(adev);
91 struct drm_file *file;
92
93 mutex_lock(&ddev->filelist_mutex);
94
95 list_for_each_entry(file, &ddev->filelist, lhead) {
96 struct drm_gem_object *gobj;
97 int handle;
98
99 WARN_ONCE(1, "Still active user space clients!\n");
100 spin_lock(&file->table_lock);
101 idr_for_each_entry(&file->object_idr, gobj, handle) {
102 WARN_ONCE(1, "And also active allocations!\n");
103 drm_gem_object_put(gobj);
104 }
105 idr_destroy(&file->object_idr);
106 spin_unlock(&file->table_lock);
107 }
108
109 mutex_unlock(&ddev->filelist_mutex);
110 }
111
112 /*
113 * Call from drm_gem_handle_create which appear in both new and open ioctl
114 * case.
115 */
amdgpu_gem_object_open(struct drm_gem_object * obj,struct drm_file * file_priv)116 static int amdgpu_gem_object_open(struct drm_gem_object *obj,
117 struct drm_file *file_priv)
118 {
119 struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj);
120 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
121 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
122 struct amdgpu_vm *vm = &fpriv->vm;
123 struct amdgpu_bo_va *bo_va;
124 struct mm_struct *mm;
125 int r;
126
127 mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm);
128 if (mm && mm != current->mm)
129 return -EPERM;
130
131 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID &&
132 abo->tbo.base.resv != vm->root.base.bo->tbo.base.resv)
133 return -EPERM;
134
135 r = amdgpu_bo_reserve(abo, false);
136 if (r)
137 return r;
138
139 bo_va = amdgpu_vm_bo_find(vm, abo);
140 if (!bo_va) {
141 bo_va = amdgpu_vm_bo_add(adev, vm, abo);
142 } else {
143 ++bo_va->ref_count;
144 }
145 amdgpu_bo_unreserve(abo);
146 return 0;
147 }
148
amdgpu_gem_object_close(struct drm_gem_object * obj,struct drm_file * file_priv)149 static void amdgpu_gem_object_close(struct drm_gem_object *obj,
150 struct drm_file *file_priv)
151 {
152 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
153 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
154 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
155 struct amdgpu_vm *vm = &fpriv->vm;
156
157 struct amdgpu_bo_list_entry vm_pd;
158 struct list_head list, duplicates;
159 struct dma_fence *fence = NULL;
160 struct ttm_validate_buffer tv;
161 struct ww_acquire_ctx ticket;
162 struct amdgpu_bo_va *bo_va;
163 long r;
164
165 INIT_LIST_HEAD(&list);
166 INIT_LIST_HEAD(&duplicates);
167
168 tv.bo = &bo->tbo;
169 tv.num_shared = 2;
170 list_add(&tv.head, &list);
171
172 amdgpu_vm_get_pd_bo(vm, &list, &vm_pd);
173
174 r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates);
175 if (r) {
176 dev_err(adev->dev, "leaking bo va because "
177 "we fail to reserve bo (%ld)\n", r);
178 return;
179 }
180 bo_va = amdgpu_vm_bo_find(vm, bo);
181 if (!bo_va || --bo_va->ref_count)
182 goto out_unlock;
183
184 amdgpu_vm_bo_rmv(adev, bo_va);
185 if (!amdgpu_vm_ready(vm))
186 goto out_unlock;
187
188 fence = dma_resv_get_excl(bo->tbo.base.resv);
189 if (fence) {
190 amdgpu_bo_fence(bo, fence, true);
191 fence = NULL;
192 }
193
194 r = amdgpu_vm_clear_freed(adev, vm, &fence);
195 if (r || !fence)
196 goto out_unlock;
197
198 amdgpu_bo_fence(bo, fence, true);
199 dma_fence_put(fence);
200
201 out_unlock:
202 if (unlikely(r < 0))
203 dev_err(adev->dev, "failed to clear page "
204 "tables on GEM object close (%ld)\n", r);
205 ttm_eu_backoff_reservation(&ticket, &list);
206 }
207
208 static const struct drm_gem_object_funcs amdgpu_gem_object_funcs = {
209 .free = amdgpu_gem_object_free,
210 .open = amdgpu_gem_object_open,
211 .close = amdgpu_gem_object_close,
212 .export = amdgpu_gem_prime_export,
213 .vmap = drm_gem_ttm_vmap,
214 .vunmap = drm_gem_ttm_vunmap,
215 };
216
217 /*
218 * GEM ioctls.
219 */
amdgpu_gem_create_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)220 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
221 struct drm_file *filp)
222 {
223 struct amdgpu_device *adev = drm_to_adev(dev);
224 struct amdgpu_fpriv *fpriv = filp->driver_priv;
225 struct amdgpu_vm *vm = &fpriv->vm;
226 union drm_amdgpu_gem_create *args = data;
227 uint64_t flags = args->in.domain_flags;
228 uint64_t size = args->in.bo_size;
229 struct dma_resv *resv = NULL;
230 struct drm_gem_object *gobj;
231 uint32_t handle, initial_domain;
232 int r;
233
234 /* reject invalid gem flags */
235 if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
236 AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
237 AMDGPU_GEM_CREATE_CPU_GTT_USWC |
238 AMDGPU_GEM_CREATE_VRAM_CLEARED |
239 AMDGPU_GEM_CREATE_VM_ALWAYS_VALID |
240 AMDGPU_GEM_CREATE_EXPLICIT_SYNC |
241 AMDGPU_GEM_CREATE_ENCRYPTED))
242
243 return -EINVAL;
244
245 /* reject invalid gem domains */
246 if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK)
247 return -EINVAL;
248
249 if (!amdgpu_is_tmz(adev) && (flags & AMDGPU_GEM_CREATE_ENCRYPTED)) {
250 DRM_NOTE_ONCE("Cannot allocate secure buffer since TMZ is disabled\n");
251 return -EINVAL;
252 }
253
254 /* create a gem object to contain this object in */
255 if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
256 AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
257 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
258 /* if gds bo is created from user space, it must be
259 * passed to bo list
260 */
261 DRM_ERROR("GDS bo cannot be per-vm-bo\n");
262 return -EINVAL;
263 }
264 flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
265 }
266
267 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
268 r = amdgpu_bo_reserve(vm->root.base.bo, false);
269 if (r)
270 return r;
271
272 resv = vm->root.base.bo->tbo.base.resv;
273 }
274
275 initial_domain = (u32)(0xffffffff & args->in.domains);
276 retry:
277 r = amdgpu_gem_object_create(adev, size, args->in.alignment,
278 initial_domain,
279 flags, ttm_bo_type_device, resv, &gobj);
280 if (r) {
281 if (r != -ERESTARTSYS) {
282 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
283 flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
284 goto retry;
285 }
286
287 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
288 initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
289 goto retry;
290 }
291 DRM_DEBUG("Failed to allocate GEM object (%llu, %d, %llu, %d)\n",
292 size, initial_domain, args->in.alignment, r);
293 }
294 return r;
295 }
296
297 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
298 if (!r) {
299 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
300
301 abo->parent = amdgpu_bo_ref(vm->root.base.bo);
302 }
303 amdgpu_bo_unreserve(vm->root.base.bo);
304 }
305 if (r)
306 return r;
307
308 r = drm_gem_handle_create(filp, gobj, &handle);
309 /* drop reference from allocate - handle holds it now */
310 drm_gem_object_put(gobj);
311 if (r)
312 return r;
313
314 memset(args, 0, sizeof(*args));
315 args->out.handle = handle;
316 return 0;
317 }
318
amdgpu_gem_userptr_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)319 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
320 struct drm_file *filp)
321 {
322 struct ttm_operation_ctx ctx = { true, false };
323 struct amdgpu_device *adev = drm_to_adev(dev);
324 struct drm_amdgpu_gem_userptr *args = data;
325 struct drm_gem_object *gobj;
326 struct amdgpu_bo *bo;
327 uint32_t handle;
328 int r;
329
330 args->addr = untagged_addr(args->addr);
331
332 if (offset_in_page(args->addr | args->size))
333 return -EINVAL;
334
335 /* reject unknown flag values */
336 if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY |
337 AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE |
338 AMDGPU_GEM_USERPTR_REGISTER))
339 return -EINVAL;
340
341 if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) &&
342 !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) {
343
344 /* if we want to write to it we must install a MMU notifier */
345 return -EACCES;
346 }
347
348 /* create a gem object to contain this object in */
349 r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU,
350 0, ttm_bo_type_device, NULL, &gobj);
351 if (r)
352 return r;
353
354 bo = gem_to_amdgpu_bo(gobj);
355 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
356 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
357 r = amdgpu_ttm_tt_set_userptr(&bo->tbo, args->addr, args->flags);
358 if (r)
359 goto release_object;
360
361 if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) {
362 r = amdgpu_mn_register(bo, args->addr);
363 if (r)
364 goto release_object;
365 }
366
367 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
368 r = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages);
369 if (r)
370 goto release_object;
371
372 r = amdgpu_bo_reserve(bo, true);
373 if (r)
374 goto user_pages_done;
375
376 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
377 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
378 amdgpu_bo_unreserve(bo);
379 if (r)
380 goto user_pages_done;
381 }
382
383 r = drm_gem_handle_create(filp, gobj, &handle);
384 if (r)
385 goto user_pages_done;
386
387 args->handle = handle;
388
389 user_pages_done:
390 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE)
391 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
392
393 release_object:
394 drm_gem_object_put(gobj);
395
396 return r;
397 }
398
amdgpu_mode_dumb_mmap(struct drm_file * filp,struct drm_device * dev,uint32_t handle,uint64_t * offset_p)399 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
400 struct drm_device *dev,
401 uint32_t handle, uint64_t *offset_p)
402 {
403 struct drm_gem_object *gobj;
404 struct amdgpu_bo *robj;
405
406 gobj = drm_gem_object_lookup(filp, handle);
407 if (gobj == NULL) {
408 return -ENOENT;
409 }
410 robj = gem_to_amdgpu_bo(gobj);
411 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) ||
412 (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
413 drm_gem_object_put(gobj);
414 return -EPERM;
415 }
416 *offset_p = amdgpu_bo_mmap_offset(robj);
417 drm_gem_object_put(gobj);
418 return 0;
419 }
420
amdgpu_gem_mmap_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)421 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
422 struct drm_file *filp)
423 {
424 union drm_amdgpu_gem_mmap *args = data;
425 uint32_t handle = args->in.handle;
426 memset(args, 0, sizeof(*args));
427 return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr);
428 }
429
430 /**
431 * amdgpu_gem_timeout - calculate jiffies timeout from absolute value
432 *
433 * @timeout_ns: timeout in ns
434 *
435 * Calculate the timeout in jiffies from an absolute timeout in ns.
436 */
amdgpu_gem_timeout(uint64_t timeout_ns)437 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns)
438 {
439 unsigned long timeout_jiffies;
440 ktime_t timeout;
441
442 /* clamp timeout if it's to large */
443 if (((int64_t)timeout_ns) < 0)
444 return MAX_SCHEDULE_TIMEOUT;
445
446 timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get());
447 if (ktime_to_ns(timeout) < 0)
448 return 0;
449
450 timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout));
451 /* clamp timeout to avoid unsigned-> signed overflow */
452 if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT )
453 return MAX_SCHEDULE_TIMEOUT - 1;
454
455 return timeout_jiffies;
456 }
457
amdgpu_gem_wait_idle_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)458 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
459 struct drm_file *filp)
460 {
461 union drm_amdgpu_gem_wait_idle *args = data;
462 struct drm_gem_object *gobj;
463 struct amdgpu_bo *robj;
464 uint32_t handle = args->in.handle;
465 unsigned long timeout = amdgpu_gem_timeout(args->in.timeout);
466 int r = 0;
467 long ret;
468
469 gobj = drm_gem_object_lookup(filp, handle);
470 if (gobj == NULL) {
471 return -ENOENT;
472 }
473 robj = gem_to_amdgpu_bo(gobj);
474 ret = dma_resv_wait_timeout_rcu(robj->tbo.base.resv, true, true,
475 timeout);
476
477 /* ret == 0 means not signaled,
478 * ret > 0 means signaled
479 * ret < 0 means interrupted before timeout
480 */
481 if (ret >= 0) {
482 memset(args, 0, sizeof(*args));
483 args->out.status = (ret == 0);
484 } else
485 r = ret;
486
487 drm_gem_object_put(gobj);
488 return r;
489 }
490
amdgpu_gem_metadata_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)491 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
492 struct drm_file *filp)
493 {
494 struct drm_amdgpu_gem_metadata *args = data;
495 struct drm_gem_object *gobj;
496 struct amdgpu_bo *robj;
497 int r = -1;
498
499 DRM_DEBUG("%d \n", args->handle);
500 gobj = drm_gem_object_lookup(filp, args->handle);
501 if (gobj == NULL)
502 return -ENOENT;
503 robj = gem_to_amdgpu_bo(gobj);
504
505 r = amdgpu_bo_reserve(robj, false);
506 if (unlikely(r != 0))
507 goto out;
508
509 if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) {
510 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info);
511 r = amdgpu_bo_get_metadata(robj, args->data.data,
512 sizeof(args->data.data),
513 &args->data.data_size_bytes,
514 &args->data.flags);
515 } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) {
516 if (args->data.data_size_bytes > sizeof(args->data.data)) {
517 r = -EINVAL;
518 goto unreserve;
519 }
520 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info);
521 if (!r)
522 r = amdgpu_bo_set_metadata(robj, args->data.data,
523 args->data.data_size_bytes,
524 args->data.flags);
525 }
526
527 unreserve:
528 amdgpu_bo_unreserve(robj);
529 out:
530 drm_gem_object_put(gobj);
531 return r;
532 }
533
534 /**
535 * amdgpu_gem_va_update_vm -update the bo_va in its VM
536 *
537 * @adev: amdgpu_device pointer
538 * @vm: vm to update
539 * @bo_va: bo_va to update
540 * @operation: map, unmap or clear
541 *
542 * Update the bo_va directly after setting its address. Errors are not
543 * vital here, so they are not reported back to userspace.
544 */
amdgpu_gem_va_update_vm(struct amdgpu_device * adev,struct amdgpu_vm * vm,struct amdgpu_bo_va * bo_va,uint32_t operation)545 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
546 struct amdgpu_vm *vm,
547 struct amdgpu_bo_va *bo_va,
548 uint32_t operation)
549 {
550 int r;
551
552 if (!amdgpu_vm_ready(vm))
553 return;
554
555 r = amdgpu_vm_clear_freed(adev, vm, NULL);
556 if (r)
557 goto error;
558
559 if (operation == AMDGPU_VA_OP_MAP ||
560 operation == AMDGPU_VA_OP_REPLACE) {
561 r = amdgpu_vm_bo_update(adev, bo_va, false);
562 if (r)
563 goto error;
564 }
565
566 r = amdgpu_vm_update_pdes(adev, vm, false);
567
568 error:
569 if (r && r != -ERESTARTSYS)
570 DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
571 }
572
573 /**
574 * amdgpu_gem_va_map_flags - map GEM UAPI flags into hardware flags
575 *
576 * @adev: amdgpu_device pointer
577 * @flags: GEM UAPI flags
578 *
579 * Returns the GEM UAPI flags mapped into hardware for the ASIC.
580 */
amdgpu_gem_va_map_flags(struct amdgpu_device * adev,uint32_t flags)581 uint64_t amdgpu_gem_va_map_flags(struct amdgpu_device *adev, uint32_t flags)
582 {
583 uint64_t pte_flag = 0;
584
585 if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
586 pte_flag |= AMDGPU_PTE_EXECUTABLE;
587 if (flags & AMDGPU_VM_PAGE_READABLE)
588 pte_flag |= AMDGPU_PTE_READABLE;
589 if (flags & AMDGPU_VM_PAGE_WRITEABLE)
590 pte_flag |= AMDGPU_PTE_WRITEABLE;
591 if (flags & AMDGPU_VM_PAGE_PRT)
592 pte_flag |= AMDGPU_PTE_PRT;
593
594 if (adev->gmc.gmc_funcs->map_mtype)
595 pte_flag |= amdgpu_gmc_map_mtype(adev,
596 flags & AMDGPU_VM_MTYPE_MASK);
597
598 return pte_flag;
599 }
600
amdgpu_gem_va_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)601 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
602 struct drm_file *filp)
603 {
604 const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE |
605 AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
606 AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK;
607 const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE |
608 AMDGPU_VM_PAGE_PRT;
609
610 struct drm_amdgpu_gem_va *args = data;
611 struct drm_gem_object *gobj;
612 struct amdgpu_device *adev = drm_to_adev(dev);
613 struct amdgpu_fpriv *fpriv = filp->driver_priv;
614 struct amdgpu_bo *abo;
615 struct amdgpu_bo_va *bo_va;
616 struct amdgpu_bo_list_entry vm_pd;
617 struct ttm_validate_buffer tv;
618 struct ww_acquire_ctx ticket;
619 struct list_head list, duplicates;
620 uint64_t va_flags;
621 uint64_t vm_size;
622 int r = 0;
623
624 if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
625 dev_dbg(dev->dev,
626 "va_address 0x%LX is in reserved area 0x%LX\n",
627 args->va_address, AMDGPU_VA_RESERVED_SIZE);
628 return -EINVAL;
629 }
630
631 if (args->va_address >= AMDGPU_GMC_HOLE_START &&
632 args->va_address < AMDGPU_GMC_HOLE_END) {
633 dev_dbg(dev->dev,
634 "va_address 0x%LX is in VA hole 0x%LX-0x%LX\n",
635 args->va_address, AMDGPU_GMC_HOLE_START,
636 AMDGPU_GMC_HOLE_END);
637 return -EINVAL;
638 }
639
640 args->va_address &= AMDGPU_GMC_HOLE_MASK;
641
642 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
643 vm_size -= AMDGPU_VA_RESERVED_SIZE;
644 if (args->va_address + args->map_size > vm_size) {
645 dev_dbg(dev->dev,
646 "va_address 0x%llx is in top reserved area 0x%llx\n",
647 args->va_address + args->map_size, vm_size);
648 return -EINVAL;
649 }
650
651 if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
652 dev_dbg(dev->dev, "invalid flags combination 0x%08X\n",
653 args->flags);
654 return -EINVAL;
655 }
656
657 switch (args->operation) {
658 case AMDGPU_VA_OP_MAP:
659 case AMDGPU_VA_OP_UNMAP:
660 case AMDGPU_VA_OP_CLEAR:
661 case AMDGPU_VA_OP_REPLACE:
662 break;
663 default:
664 dev_dbg(dev->dev, "unsupported operation %d\n",
665 args->operation);
666 return -EINVAL;
667 }
668
669 INIT_LIST_HEAD(&list);
670 INIT_LIST_HEAD(&duplicates);
671 if ((args->operation != AMDGPU_VA_OP_CLEAR) &&
672 !(args->flags & AMDGPU_VM_PAGE_PRT)) {
673 gobj = drm_gem_object_lookup(filp, args->handle);
674 if (gobj == NULL)
675 return -ENOENT;
676 abo = gem_to_amdgpu_bo(gobj);
677 tv.bo = &abo->tbo;
678 if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
679 tv.num_shared = 1;
680 else
681 tv.num_shared = 0;
682 list_add(&tv.head, &list);
683 } else {
684 gobj = NULL;
685 abo = NULL;
686 }
687
688 amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd);
689
690 r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates);
691 if (r)
692 goto error_unref;
693
694 if (abo) {
695 bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo);
696 if (!bo_va) {
697 r = -ENOENT;
698 goto error_backoff;
699 }
700 } else if (args->operation != AMDGPU_VA_OP_CLEAR) {
701 bo_va = fpriv->prt_va;
702 } else {
703 bo_va = NULL;
704 }
705
706 switch (args->operation) {
707 case AMDGPU_VA_OP_MAP:
708 va_flags = amdgpu_gem_va_map_flags(adev, args->flags);
709 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
710 args->offset_in_bo, args->map_size,
711 va_flags);
712 break;
713 case AMDGPU_VA_OP_UNMAP:
714 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address);
715 break;
716
717 case AMDGPU_VA_OP_CLEAR:
718 r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm,
719 args->va_address,
720 args->map_size);
721 break;
722 case AMDGPU_VA_OP_REPLACE:
723 va_flags = amdgpu_gem_va_map_flags(adev, args->flags);
724 r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address,
725 args->offset_in_bo, args->map_size,
726 va_flags);
727 break;
728 default:
729 break;
730 }
731 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug)
732 amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va,
733 args->operation);
734
735 error_backoff:
736 ttm_eu_backoff_reservation(&ticket, &list);
737
738 error_unref:
739 drm_gem_object_put(gobj);
740 return r;
741 }
742
amdgpu_gem_op_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)743 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
744 struct drm_file *filp)
745 {
746 struct amdgpu_device *adev = drm_to_adev(dev);
747 struct drm_amdgpu_gem_op *args = data;
748 struct drm_gem_object *gobj;
749 struct amdgpu_vm_bo_base *base;
750 struct amdgpu_bo *robj;
751 int r;
752
753 gobj = drm_gem_object_lookup(filp, args->handle);
754 if (gobj == NULL) {
755 return -ENOENT;
756 }
757 robj = gem_to_amdgpu_bo(gobj);
758
759 r = amdgpu_bo_reserve(robj, false);
760 if (unlikely(r))
761 goto out;
762
763 switch (args->op) {
764 case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: {
765 struct drm_amdgpu_gem_create_in info;
766 void __user *out = u64_to_user_ptr(args->value);
767
768 info.bo_size = robj->tbo.base.size;
769 info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT;
770 info.domains = robj->preferred_domains;
771 info.domain_flags = robj->flags;
772 amdgpu_bo_unreserve(robj);
773 if (copy_to_user(out, &info, sizeof(info)))
774 r = -EFAULT;
775 break;
776 }
777 case AMDGPU_GEM_OP_SET_PLACEMENT:
778 if (robj->prime_shared_count && (args->value & AMDGPU_GEM_DOMAIN_VRAM)) {
779 r = -EINVAL;
780 amdgpu_bo_unreserve(robj);
781 break;
782 }
783 if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) {
784 r = -EPERM;
785 amdgpu_bo_unreserve(robj);
786 break;
787 }
788 for (base = robj->vm_bo; base; base = base->next)
789 if (amdgpu_xgmi_same_hive(amdgpu_ttm_adev(robj->tbo.bdev),
790 amdgpu_ttm_adev(base->vm->root.base.bo->tbo.bdev))) {
791 r = -EINVAL;
792 amdgpu_bo_unreserve(robj);
793 goto out;
794 }
795
796
797 robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM |
798 AMDGPU_GEM_DOMAIN_GTT |
799 AMDGPU_GEM_DOMAIN_CPU);
800 robj->allowed_domains = robj->preferred_domains;
801 if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
802 robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
803
804 if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
805 amdgpu_vm_bo_invalidate(adev, robj, true);
806
807 amdgpu_bo_unreserve(robj);
808 break;
809 default:
810 amdgpu_bo_unreserve(robj);
811 r = -EINVAL;
812 }
813
814 out:
815 drm_gem_object_put(gobj);
816 return r;
817 }
818
amdgpu_mode_dumb_create(struct drm_file * file_priv,struct drm_device * dev,struct drm_mode_create_dumb * args)819 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
820 struct drm_device *dev,
821 struct drm_mode_create_dumb *args)
822 {
823 struct amdgpu_device *adev = drm_to_adev(dev);
824 struct drm_gem_object *gobj;
825 uint32_t handle;
826 u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
827 AMDGPU_GEM_CREATE_CPU_GTT_USWC;
828 u32 domain;
829 int r;
830
831 /*
832 * The buffer returned from this function should be cleared, but
833 * it can only be done if the ring is enabled or we'll fail to
834 * create the buffer.
835 */
836 if (adev->mman.buffer_funcs_enabled)
837 flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED;
838
839 args->pitch = amdgpu_align_pitch(adev, args->width,
840 DIV_ROUND_UP(args->bpp, 8), 0);
841 args->size = (u64)args->pitch * args->height;
842 args->size = ALIGN(args->size, PAGE_SIZE);
843 domain = amdgpu_bo_get_preferred_pin_domain(adev,
844 amdgpu_display_supported_domains(adev, flags));
845 r = amdgpu_gem_object_create(adev, args->size, 0, domain, flags,
846 ttm_bo_type_device, NULL, &gobj);
847 if (r)
848 return -ENOMEM;
849
850 r = drm_gem_handle_create(file_priv, gobj, &handle);
851 /* drop reference from allocate - handle holds it now */
852 drm_gem_object_put(gobj);
853 if (r) {
854 return r;
855 }
856 args->handle = handle;
857 return 0;
858 }
859
860 #if defined(CONFIG_DEBUG_FS)
amdgpu_debugfs_gem_info_show(struct seq_file * m,void * unused)861 static int amdgpu_debugfs_gem_info_show(struct seq_file *m, void *unused)
862 {
863 struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
864 struct drm_device *dev = adev_to_drm(adev);
865 struct drm_file *file;
866 int r;
867
868 r = mutex_lock_interruptible(&dev->filelist_mutex);
869 if (r)
870 return r;
871
872 list_for_each_entry(file, &dev->filelist, lhead) {
873 struct task_struct *task;
874 struct drm_gem_object *gobj;
875 int id;
876
877 /*
878 * Although we have a valid reference on file->pid, that does
879 * not guarantee that the task_struct who called get_pid() is
880 * still alive (e.g. get_pid(current) => fork() => exit()).
881 * Therefore, we need to protect this ->comm access using RCU.
882 */
883 rcu_read_lock();
884 task = pid_task(file->pid, PIDTYPE_PID);
885 seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid),
886 task ? task->comm : "<unknown>");
887 rcu_read_unlock();
888
889 spin_lock(&file->table_lock);
890 idr_for_each_entry(&file->object_idr, gobj, id) {
891 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
892
893 amdgpu_bo_print_info(id, bo, m);
894 }
895 spin_unlock(&file->table_lock);
896 }
897
898 mutex_unlock(&dev->filelist_mutex);
899 return 0;
900 }
901
902 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_gem_info);
903
904 #endif
905
amdgpu_debugfs_gem_init(struct amdgpu_device * adev)906 void amdgpu_debugfs_gem_init(struct amdgpu_device *adev)
907 {
908 #if defined(CONFIG_DEBUG_FS)
909 struct drm_minor *minor = adev_to_drm(adev)->primary;
910 struct dentry *root = minor->debugfs_root;
911
912 debugfs_create_file("amdgpu_gem_info", 0444, root, adev,
913 &amdgpu_debugfs_gem_info_fops);
914 #endif
915 }
916