1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30
31 #include <drm/drm_atomic_helper.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_edid.h>
34 #include <drm/drm_probe_helper.h>
35
36 #include "i915_drv.h"
37 #include "intel_connector.h"
38 #include "intel_crt.h"
39 #include "intel_ddi.h"
40 #include "intel_display_types.h"
41 #include "intel_fdi.h"
42 #include "intel_fifo_underrun.h"
43 #include "intel_gmbus.h"
44 #include "intel_hotplug.h"
45
46 /* Here's the desired hotplug mode */
47 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \
48 ADPA_CRT_HOTPLUG_WARMUP_10MS | \
49 ADPA_CRT_HOTPLUG_SAMPLE_4S | \
50 ADPA_CRT_HOTPLUG_VOLTAGE_50 | \
51 ADPA_CRT_HOTPLUG_VOLREF_325MV | \
52 ADPA_CRT_HOTPLUG_ENABLE)
53
54 struct intel_crt {
55 struct intel_encoder base;
56 /* DPMS state is stored in the connector, which we need in the
57 * encoder's enable/disable callbacks */
58 struct intel_connector *connector;
59 bool force_hotplug_required;
60 i915_reg_t adpa_reg;
61 };
62
intel_encoder_to_crt(struct intel_encoder * encoder)63 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
64 {
65 return container_of(encoder, struct intel_crt, base);
66 }
67
intel_attached_crt(struct intel_connector * connector)68 static struct intel_crt *intel_attached_crt(struct intel_connector *connector)
69 {
70 return intel_encoder_to_crt(intel_attached_encoder(connector));
71 }
72
intel_crt_port_enabled(struct drm_i915_private * dev_priv,i915_reg_t adpa_reg,enum pipe * pipe)73 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
74 i915_reg_t adpa_reg, enum pipe *pipe)
75 {
76 u32 val;
77
78 val = intel_de_read(dev_priv, adpa_reg);
79
80 /* asserts want to know the pipe even if the port is disabled */
81 if (HAS_PCH_CPT(dev_priv))
82 *pipe = (val & ADPA_PIPE_SEL_MASK_CPT) >> ADPA_PIPE_SEL_SHIFT_CPT;
83 else
84 *pipe = (val & ADPA_PIPE_SEL_MASK) >> ADPA_PIPE_SEL_SHIFT;
85
86 return val & ADPA_DAC_ENABLE;
87 }
88
intel_crt_get_hw_state(struct intel_encoder * encoder,enum pipe * pipe)89 static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
90 enum pipe *pipe)
91 {
92 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
93 struct intel_crt *crt = intel_encoder_to_crt(encoder);
94 intel_wakeref_t wakeref;
95 bool ret;
96
97 wakeref = intel_display_power_get_if_enabled(dev_priv,
98 encoder->power_domain);
99 if (!wakeref)
100 return false;
101
102 ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe);
103
104 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
105
106 return ret;
107 }
108
intel_crt_get_flags(struct intel_encoder * encoder)109 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
110 {
111 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
112 struct intel_crt *crt = intel_encoder_to_crt(encoder);
113 u32 tmp, flags = 0;
114
115 tmp = intel_de_read(dev_priv, crt->adpa_reg);
116
117 if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
118 flags |= DRM_MODE_FLAG_PHSYNC;
119 else
120 flags |= DRM_MODE_FLAG_NHSYNC;
121
122 if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
123 flags |= DRM_MODE_FLAG_PVSYNC;
124 else
125 flags |= DRM_MODE_FLAG_NVSYNC;
126
127 return flags;
128 }
129
intel_crt_get_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)130 static void intel_crt_get_config(struct intel_encoder *encoder,
131 struct intel_crtc_state *pipe_config)
132 {
133 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
134
135 pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
136
137 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock;
138 }
139
hsw_crt_get_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)140 static void hsw_crt_get_config(struct intel_encoder *encoder,
141 struct intel_crtc_state *pipe_config)
142 {
143 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
144
145 hsw_ddi_get_config(encoder, pipe_config);
146
147 pipe_config->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
148 DRM_MODE_FLAG_NHSYNC |
149 DRM_MODE_FLAG_PVSYNC |
150 DRM_MODE_FLAG_NVSYNC);
151 pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
152
153 pipe_config->hw.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv);
154 }
155
156 /* Note: The caller is required to filter out dpms modes not supported by the
157 * platform. */
intel_crt_set_dpms(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int mode)158 static void intel_crt_set_dpms(struct intel_encoder *encoder,
159 const struct intel_crtc_state *crtc_state,
160 int mode)
161 {
162 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
163 struct intel_crt *crt = intel_encoder_to_crt(encoder);
164 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
165 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
166 u32 adpa;
167
168 if (DISPLAY_VER(dev_priv) >= 5)
169 adpa = ADPA_HOTPLUG_BITS;
170 else
171 adpa = 0;
172
173 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
174 adpa |= ADPA_HSYNC_ACTIVE_HIGH;
175 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
176 adpa |= ADPA_VSYNC_ACTIVE_HIGH;
177
178 /* For CPT allow 3 pipe config, for others just use A or B */
179 if (HAS_PCH_LPT(dev_priv))
180 ; /* Those bits don't exist here */
181 else if (HAS_PCH_CPT(dev_priv))
182 adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe);
183 else
184 adpa |= ADPA_PIPE_SEL(crtc->pipe);
185
186 if (!HAS_PCH_SPLIT(dev_priv))
187 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
188
189 switch (mode) {
190 case DRM_MODE_DPMS_ON:
191 adpa |= ADPA_DAC_ENABLE;
192 break;
193 case DRM_MODE_DPMS_STANDBY:
194 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
195 break;
196 case DRM_MODE_DPMS_SUSPEND:
197 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
198 break;
199 case DRM_MODE_DPMS_OFF:
200 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
201 break;
202 }
203
204 intel_de_write(dev_priv, crt->adpa_reg, adpa);
205 }
206
intel_disable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)207 static void intel_disable_crt(struct intel_atomic_state *state,
208 struct intel_encoder *encoder,
209 const struct intel_crtc_state *old_crtc_state,
210 const struct drm_connector_state *old_conn_state)
211 {
212 intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF);
213 }
214
pch_disable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)215 static void pch_disable_crt(struct intel_atomic_state *state,
216 struct intel_encoder *encoder,
217 const struct intel_crtc_state *old_crtc_state,
218 const struct drm_connector_state *old_conn_state)
219 {
220 }
221
pch_post_disable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)222 static void pch_post_disable_crt(struct intel_atomic_state *state,
223 struct intel_encoder *encoder,
224 const struct intel_crtc_state *old_crtc_state,
225 const struct drm_connector_state *old_conn_state)
226 {
227 intel_disable_crt(state, encoder, old_crtc_state, old_conn_state);
228 }
229
hsw_disable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)230 static void hsw_disable_crt(struct intel_atomic_state *state,
231 struct intel_encoder *encoder,
232 const struct intel_crtc_state *old_crtc_state,
233 const struct drm_connector_state *old_conn_state)
234 {
235 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
236
237 drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder);
238
239 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
240 }
241
hsw_post_disable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)242 static void hsw_post_disable_crt(struct intel_atomic_state *state,
243 struct intel_encoder *encoder,
244 const struct intel_crtc_state *old_crtc_state,
245 const struct drm_connector_state *old_conn_state)
246 {
247 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
248
249 intel_crtc_vblank_off(old_crtc_state);
250
251 intel_disable_pipe(old_crtc_state);
252
253 intel_ddi_disable_transcoder_func(old_crtc_state);
254
255 ilk_pfit_disable(old_crtc_state);
256
257 intel_ddi_disable_pipe_clock(old_crtc_state);
258
259 pch_post_disable_crt(state, encoder, old_crtc_state, old_conn_state);
260
261 lpt_disable_pch_transcoder(dev_priv);
262 lpt_disable_iclkip(dev_priv);
263
264 intel_ddi_fdi_post_disable(state, encoder, old_crtc_state, old_conn_state);
265
266 drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder);
267
268 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
269 }
270
hsw_pre_pll_enable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)271 static void hsw_pre_pll_enable_crt(struct intel_atomic_state *state,
272 struct intel_encoder *encoder,
273 const struct intel_crtc_state *crtc_state,
274 const struct drm_connector_state *conn_state)
275 {
276 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
277
278 drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
279
280 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
281 }
282
hsw_pre_enable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)283 static void hsw_pre_enable_crt(struct intel_atomic_state *state,
284 struct intel_encoder *encoder,
285 const struct intel_crtc_state *crtc_state,
286 const struct drm_connector_state *conn_state)
287 {
288 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
289 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
290 enum pipe pipe = crtc->pipe;
291
292 drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
293
294 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
295
296 hsw_fdi_link_train(encoder, crtc_state);
297
298 intel_ddi_enable_pipe_clock(encoder, crtc_state);
299 }
300
hsw_enable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)301 static void hsw_enable_crt(struct intel_atomic_state *state,
302 struct intel_encoder *encoder,
303 const struct intel_crtc_state *crtc_state,
304 const struct drm_connector_state *conn_state)
305 {
306 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
307 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
308 enum pipe pipe = crtc->pipe;
309
310 drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
311
312 intel_ddi_enable_transcoder_func(encoder, crtc_state);
313
314 intel_enable_pipe(crtc_state);
315
316 lpt_pch_enable(crtc_state);
317
318 intel_crtc_vblank_on(crtc_state);
319
320 intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
321
322 intel_wait_for_vblank(dev_priv, pipe);
323 intel_wait_for_vblank(dev_priv, pipe);
324 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
325 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
326 }
327
intel_enable_crt(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)328 static void intel_enable_crt(struct intel_atomic_state *state,
329 struct intel_encoder *encoder,
330 const struct intel_crtc_state *crtc_state,
331 const struct drm_connector_state *conn_state)
332 {
333 intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
334 }
335
336 static enum drm_mode_status
intel_crt_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)337 intel_crt_mode_valid(struct drm_connector *connector,
338 struct drm_display_mode *mode)
339 {
340 struct drm_device *dev = connector->dev;
341 struct drm_i915_private *dev_priv = to_i915(dev);
342 int max_dotclk = dev_priv->max_dotclk_freq;
343 int max_clock;
344
345 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
346 return MODE_NO_DBLESCAN;
347
348 if (mode->clock < 25000)
349 return MODE_CLOCK_LOW;
350
351 if (HAS_PCH_LPT(dev_priv))
352 max_clock = 180000;
353 else if (IS_VALLEYVIEW(dev_priv))
354 /*
355 * 270 MHz due to current DPLL limits,
356 * DAC limit supposedly 355 MHz.
357 */
358 max_clock = 270000;
359 else if (IS_DISPLAY_RANGE(dev_priv, 3, 4))
360 max_clock = 400000;
361 else
362 max_clock = 350000;
363 if (mode->clock > max_clock)
364 return MODE_CLOCK_HIGH;
365
366 if (mode->clock > max_dotclk)
367 return MODE_CLOCK_HIGH;
368
369 /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
370 if (HAS_PCH_LPT(dev_priv) &&
371 ilk_get_lanes_required(mode->clock, 270000, 24) > 2)
372 return MODE_CLOCK_HIGH;
373
374 /* HSW/BDW FDI limited to 4k */
375 if (mode->hdisplay > 4096)
376 return MODE_H_ILLEGAL;
377
378 return MODE_OK;
379 }
380
intel_crt_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)381 static int intel_crt_compute_config(struct intel_encoder *encoder,
382 struct intel_crtc_state *pipe_config,
383 struct drm_connector_state *conn_state)
384 {
385 struct drm_display_mode *adjusted_mode =
386 &pipe_config->hw.adjusted_mode;
387
388 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
389 return -EINVAL;
390
391 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
392
393 return 0;
394 }
395
pch_crt_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)396 static int pch_crt_compute_config(struct intel_encoder *encoder,
397 struct intel_crtc_state *pipe_config,
398 struct drm_connector_state *conn_state)
399 {
400 struct drm_display_mode *adjusted_mode =
401 &pipe_config->hw.adjusted_mode;
402
403 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
404 return -EINVAL;
405
406 pipe_config->has_pch_encoder = true;
407 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
408
409 return 0;
410 }
411
hsw_crt_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)412 static int hsw_crt_compute_config(struct intel_encoder *encoder,
413 struct intel_crtc_state *pipe_config,
414 struct drm_connector_state *conn_state)
415 {
416 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
417 struct drm_display_mode *adjusted_mode =
418 &pipe_config->hw.adjusted_mode;
419
420 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
421 return -EINVAL;
422
423 /* HSW/BDW FDI limited to 4k */
424 if (adjusted_mode->crtc_hdisplay > 4096 ||
425 adjusted_mode->crtc_hblank_start > 4096)
426 return -EINVAL;
427
428 pipe_config->has_pch_encoder = true;
429 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
430
431 /* LPT FDI RX only supports 8bpc. */
432 if (HAS_PCH_LPT(dev_priv)) {
433 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) {
434 drm_dbg_kms(&dev_priv->drm,
435 "LPT only supports 24bpp\n");
436 return -EINVAL;
437 }
438
439 pipe_config->pipe_bpp = 24;
440 }
441
442 /* FDI must always be 2.7 GHz */
443 pipe_config->port_clock = 135000 * 2;
444
445 return 0;
446 }
447
ilk_crt_detect_hotplug(struct drm_connector * connector)448 static bool ilk_crt_detect_hotplug(struct drm_connector *connector)
449 {
450 struct drm_device *dev = connector->dev;
451 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
452 struct drm_i915_private *dev_priv = to_i915(dev);
453 u32 adpa;
454 bool ret;
455
456 /* The first time through, trigger an explicit detection cycle */
457 if (crt->force_hotplug_required) {
458 bool turn_off_dac = HAS_PCH_SPLIT(dev_priv);
459 u32 save_adpa;
460
461 crt->force_hotplug_required = false;
462
463 save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg);
464 drm_dbg_kms(&dev_priv->drm,
465 "trigger hotplug detect cycle: adpa=0x%x\n", adpa);
466
467 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
468 if (turn_off_dac)
469 adpa &= ~ADPA_DAC_ENABLE;
470
471 intel_de_write(dev_priv, crt->adpa_reg, adpa);
472
473 if (intel_de_wait_for_clear(dev_priv,
474 crt->adpa_reg,
475 ADPA_CRT_HOTPLUG_FORCE_TRIGGER,
476 1000))
477 drm_dbg_kms(&dev_priv->drm,
478 "timed out waiting for FORCE_TRIGGER");
479
480 if (turn_off_dac) {
481 intel_de_write(dev_priv, crt->adpa_reg, save_adpa);
482 intel_de_posting_read(dev_priv, crt->adpa_reg);
483 }
484 }
485
486 /* Check the status to see if both blue and green are on now */
487 adpa = intel_de_read(dev_priv, crt->adpa_reg);
488 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
489 ret = true;
490 else
491 ret = false;
492 drm_dbg_kms(&dev_priv->drm, "ironlake hotplug adpa=0x%x, result %d\n",
493 adpa, ret);
494
495 return ret;
496 }
497
valleyview_crt_detect_hotplug(struct drm_connector * connector)498 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
499 {
500 struct drm_device *dev = connector->dev;
501 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
502 struct drm_i915_private *dev_priv = to_i915(dev);
503 bool reenable_hpd;
504 u32 adpa;
505 bool ret;
506 u32 save_adpa;
507
508 /*
509 * Doing a force trigger causes a hpd interrupt to get sent, which can
510 * get us stuck in a loop if we're polling:
511 * - We enable power wells and reset the ADPA
512 * - output_poll_exec does force probe on VGA, triggering a hpd
513 * - HPD handler waits for poll to unlock dev->mode_config.mutex
514 * - output_poll_exec shuts off the ADPA, unlocks
515 * dev->mode_config.mutex
516 * - HPD handler runs, resets ADPA and brings us back to the start
517 *
518 * Just disable HPD interrupts here to prevent this
519 */
520 reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin);
521
522 save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg);
523 drm_dbg_kms(&dev_priv->drm,
524 "trigger hotplug detect cycle: adpa=0x%x\n", adpa);
525
526 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
527
528 intel_de_write(dev_priv, crt->adpa_reg, adpa);
529
530 if (intel_de_wait_for_clear(dev_priv, crt->adpa_reg,
531 ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 1000)) {
532 drm_dbg_kms(&dev_priv->drm,
533 "timed out waiting for FORCE_TRIGGER");
534 intel_de_write(dev_priv, crt->adpa_reg, save_adpa);
535 }
536
537 /* Check the status to see if both blue and green are on now */
538 adpa = intel_de_read(dev_priv, crt->adpa_reg);
539 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
540 ret = true;
541 else
542 ret = false;
543
544 drm_dbg_kms(&dev_priv->drm,
545 "valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
546
547 if (reenable_hpd)
548 intel_hpd_enable(dev_priv, crt->base.hpd_pin);
549
550 return ret;
551 }
552
intel_crt_detect_hotplug(struct drm_connector * connector)553 static bool intel_crt_detect_hotplug(struct drm_connector *connector)
554 {
555 struct drm_device *dev = connector->dev;
556 struct drm_i915_private *dev_priv = to_i915(dev);
557 u32 stat;
558 bool ret = false;
559 int i, tries = 0;
560
561 if (HAS_PCH_SPLIT(dev_priv))
562 return ilk_crt_detect_hotplug(connector);
563
564 if (IS_VALLEYVIEW(dev_priv))
565 return valleyview_crt_detect_hotplug(connector);
566
567 /*
568 * On 4 series desktop, CRT detect sequence need to be done twice
569 * to get a reliable result.
570 */
571
572 if (IS_G45(dev_priv))
573 tries = 2;
574 else
575 tries = 1;
576
577 for (i = 0; i < tries ; i++) {
578 /* turn on the FORCE_DETECT */
579 i915_hotplug_interrupt_update(dev_priv,
580 CRT_HOTPLUG_FORCE_DETECT,
581 CRT_HOTPLUG_FORCE_DETECT);
582 /* wait for FORCE_DETECT to go off */
583 if (intel_de_wait_for_clear(dev_priv, PORT_HOTPLUG_EN,
584 CRT_HOTPLUG_FORCE_DETECT, 1000))
585 drm_dbg_kms(&dev_priv->drm,
586 "timed out waiting for FORCE_DETECT to go off");
587 }
588
589 stat = intel_de_read(dev_priv, PORT_HOTPLUG_STAT);
590 if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
591 ret = true;
592
593 /* clear the interrupt we just generated, if any */
594 intel_de_write(dev_priv, PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
595
596 i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0);
597
598 return ret;
599 }
600
intel_crt_get_edid(struct drm_connector * connector,struct i2c_adapter * i2c)601 static struct edid *intel_crt_get_edid(struct drm_connector *connector,
602 struct i2c_adapter *i2c)
603 {
604 struct edid *edid;
605
606 edid = drm_get_edid(connector, i2c);
607
608 if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
609 drm_dbg_kms(connector->dev,
610 "CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
611 intel_gmbus_force_bit(i2c, true);
612 edid = drm_get_edid(connector, i2c);
613 intel_gmbus_force_bit(i2c, false);
614 }
615
616 return edid;
617 }
618
619 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
intel_crt_ddc_get_modes(struct drm_connector * connector,struct i2c_adapter * adapter)620 static int intel_crt_ddc_get_modes(struct drm_connector *connector,
621 struct i2c_adapter *adapter)
622 {
623 struct edid *edid;
624 int ret;
625
626 edid = intel_crt_get_edid(connector, adapter);
627 if (!edid)
628 return 0;
629
630 ret = intel_connector_update_modes(connector, edid);
631 kfree(edid);
632
633 return ret;
634 }
635
intel_crt_detect_ddc(struct drm_connector * connector)636 static bool intel_crt_detect_ddc(struct drm_connector *connector)
637 {
638 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
639 struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev);
640 struct edid *edid;
641 struct i2c_adapter *i2c;
642 bool ret = false;
643
644 BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
645
646 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
647 edid = intel_crt_get_edid(connector, i2c);
648
649 if (edid) {
650 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
651
652 /*
653 * This may be a DVI-I connector with a shared DDC
654 * link between analog and digital outputs, so we
655 * have to check the EDID input spec of the attached device.
656 */
657 if (!is_digital) {
658 drm_dbg_kms(&dev_priv->drm,
659 "CRT detected via DDC:0x50 [EDID]\n");
660 ret = true;
661 } else {
662 drm_dbg_kms(&dev_priv->drm,
663 "CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
664 }
665 } else {
666 drm_dbg_kms(&dev_priv->drm,
667 "CRT not detected via DDC:0x50 [no valid EDID found]\n");
668 }
669
670 kfree(edid);
671
672 return ret;
673 }
674
675 static enum drm_connector_status
intel_crt_load_detect(struct intel_crt * crt,u32 pipe)676 intel_crt_load_detect(struct intel_crt *crt, u32 pipe)
677 {
678 struct drm_device *dev = crt->base.base.dev;
679 struct drm_i915_private *dev_priv = to_i915(dev);
680 struct intel_uncore *uncore = &dev_priv->uncore;
681 u32 save_bclrpat;
682 u32 save_vtotal;
683 u32 vtotal, vactive;
684 u32 vsample;
685 u32 vblank, vblank_start, vblank_end;
686 u32 dsl;
687 i915_reg_t bclrpat_reg, vtotal_reg,
688 vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg;
689 u8 st00;
690 enum drm_connector_status status;
691
692 drm_dbg_kms(&dev_priv->drm, "starting load-detect on CRT\n");
693
694 bclrpat_reg = BCLRPAT(pipe);
695 vtotal_reg = VTOTAL(pipe);
696 vblank_reg = VBLANK(pipe);
697 vsync_reg = VSYNC(pipe);
698 pipeconf_reg = PIPECONF(pipe);
699 pipe_dsl_reg = PIPEDSL(pipe);
700
701 save_bclrpat = intel_uncore_read(uncore, bclrpat_reg);
702 save_vtotal = intel_uncore_read(uncore, vtotal_reg);
703 vblank = intel_uncore_read(uncore, vblank_reg);
704
705 vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
706 vactive = (save_vtotal & 0x7ff) + 1;
707
708 vblank_start = (vblank & 0xfff) + 1;
709 vblank_end = ((vblank >> 16) & 0xfff) + 1;
710
711 /* Set the border color to purple. */
712 intel_uncore_write(uncore, bclrpat_reg, 0x500050);
713
714 if (!IS_DISPLAY_VER(dev_priv, 2)) {
715 u32 pipeconf = intel_uncore_read(uncore, pipeconf_reg);
716 intel_uncore_write(uncore,
717 pipeconf_reg,
718 pipeconf | PIPECONF_FORCE_BORDER);
719 intel_uncore_posting_read(uncore, pipeconf_reg);
720 /* Wait for next Vblank to substitue
721 * border color for Color info */
722 intel_wait_for_vblank(dev_priv, pipe);
723 st00 = intel_uncore_read8(uncore, _VGA_MSR_WRITE);
724 status = ((st00 & (1 << 4)) != 0) ?
725 connector_status_connected :
726 connector_status_disconnected;
727
728 intel_uncore_write(uncore, pipeconf_reg, pipeconf);
729 } else {
730 bool restore_vblank = false;
731 int count, detect;
732
733 /*
734 * If there isn't any border, add some.
735 * Yes, this will flicker
736 */
737 if (vblank_start <= vactive && vblank_end >= vtotal) {
738 u32 vsync = intel_de_read(dev_priv, vsync_reg);
739 u32 vsync_start = (vsync & 0xffff) + 1;
740
741 vblank_start = vsync_start;
742 intel_uncore_write(uncore,
743 vblank_reg,
744 (vblank_start - 1) |
745 ((vblank_end - 1) << 16));
746 restore_vblank = true;
747 }
748 /* sample in the vertical border, selecting the larger one */
749 if (vblank_start - vactive >= vtotal - vblank_end)
750 vsample = (vblank_start + vactive) >> 1;
751 else
752 vsample = (vtotal + vblank_end) >> 1;
753
754 /*
755 * Wait for the border to be displayed
756 */
757 while (intel_uncore_read(uncore, pipe_dsl_reg) >= vactive)
758 ;
759 while ((dsl = intel_uncore_read(uncore, pipe_dsl_reg)) <=
760 vsample)
761 ;
762 /*
763 * Watch ST00 for an entire scanline
764 */
765 detect = 0;
766 count = 0;
767 do {
768 count++;
769 /* Read the ST00 VGA status register */
770 st00 = intel_uncore_read8(uncore, _VGA_MSR_WRITE);
771 if (st00 & (1 << 4))
772 detect++;
773 } while ((intel_uncore_read(uncore, pipe_dsl_reg) == dsl));
774
775 /* restore vblank if necessary */
776 if (restore_vblank)
777 intel_uncore_write(uncore, vblank_reg, vblank);
778 /*
779 * If more than 3/4 of the scanline detected a monitor,
780 * then it is assumed to be present. This works even on i830,
781 * where there isn't any way to force the border color across
782 * the screen
783 */
784 status = detect * 4 > count * 3 ?
785 connector_status_connected :
786 connector_status_disconnected;
787 }
788
789 /* Restore previous settings */
790 intel_uncore_write(uncore, bclrpat_reg, save_bclrpat);
791
792 return status;
793 }
794
intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id * id)795 static int intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id *id)
796 {
797 DRM_DEBUG_DRIVER("Skipping CRT detection for %s\n", id->ident);
798 return 1;
799 }
800
801 static const struct dmi_system_id intel_spurious_crt_detect[] = {
802 {
803 .callback = intel_spurious_crt_detect_dmi_callback,
804 .ident = "ACER ZGB",
805 .matches = {
806 DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
807 DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
808 },
809 },
810 {
811 .callback = intel_spurious_crt_detect_dmi_callback,
812 .ident = "Intel DZ77BH-55K",
813 .matches = {
814 DMI_MATCH(DMI_BOARD_VENDOR, "Intel Corporation"),
815 DMI_MATCH(DMI_BOARD_NAME, "DZ77BH-55K"),
816 },
817 },
818 { }
819 };
820
821 static int
intel_crt_detect(struct drm_connector * connector,struct drm_modeset_acquire_ctx * ctx,bool force)822 intel_crt_detect(struct drm_connector *connector,
823 struct drm_modeset_acquire_ctx *ctx,
824 bool force)
825 {
826 struct drm_i915_private *dev_priv = to_i915(connector->dev);
827 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
828 struct intel_encoder *intel_encoder = &crt->base;
829 intel_wakeref_t wakeref;
830 int status, ret;
831 struct intel_load_detect_pipe tmp;
832
833 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s] force=%d\n",
834 connector->base.id, connector->name,
835 force);
836
837 if (!INTEL_DISPLAY_ENABLED(dev_priv))
838 return connector_status_disconnected;
839
840 if (dev_priv->params.load_detect_test) {
841 wakeref = intel_display_power_get(dev_priv,
842 intel_encoder->power_domain);
843 goto load_detect;
844 }
845
846 /* Skip machines without VGA that falsely report hotplug events */
847 if (dmi_check_system(intel_spurious_crt_detect))
848 return connector_status_disconnected;
849
850 wakeref = intel_display_power_get(dev_priv,
851 intel_encoder->power_domain);
852
853 if (I915_HAS_HOTPLUG(dev_priv)) {
854 /* We can not rely on the HPD pin always being correctly wired
855 * up, for example many KVM do not pass it through, and so
856 * only trust an assertion that the monitor is connected.
857 */
858 if (intel_crt_detect_hotplug(connector)) {
859 drm_dbg_kms(&dev_priv->drm,
860 "CRT detected via hotplug\n");
861 status = connector_status_connected;
862 goto out;
863 } else
864 drm_dbg_kms(&dev_priv->drm,
865 "CRT not detected via hotplug\n");
866 }
867
868 if (intel_crt_detect_ddc(connector)) {
869 status = connector_status_connected;
870 goto out;
871 }
872
873 /* Load detection is broken on HPD capable machines. Whoever wants a
874 * broken monitor (without edid) to work behind a broken kvm (that fails
875 * to have the right resistors for HP detection) needs to fix this up.
876 * For now just bail out. */
877 if (I915_HAS_HOTPLUG(dev_priv)) {
878 status = connector_status_disconnected;
879 goto out;
880 }
881
882 load_detect:
883 if (!force) {
884 status = connector->status;
885 goto out;
886 }
887
888 /* for pre-945g platforms use load detect */
889 ret = intel_get_load_detect_pipe(connector, &tmp, ctx);
890 if (ret > 0) {
891 if (intel_crt_detect_ddc(connector))
892 status = connector_status_connected;
893 else if (DISPLAY_VER(dev_priv) < 4)
894 status = intel_crt_load_detect(crt,
895 to_intel_crtc(connector->state->crtc)->pipe);
896 else if (dev_priv->params.load_detect_test)
897 status = connector_status_disconnected;
898 else
899 status = connector_status_unknown;
900 intel_release_load_detect_pipe(connector, &tmp, ctx);
901 } else if (ret == 0) {
902 status = connector_status_unknown;
903 } else {
904 status = ret;
905 }
906
907 out:
908 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
909
910 /*
911 * Make sure the refs for power wells enabled during detect are
912 * dropped to avoid a new detect cycle triggered by HPD polling.
913 */
914 intel_display_power_flush_work(dev_priv);
915
916 return status;
917 }
918
intel_crt_get_modes(struct drm_connector * connector)919 static int intel_crt_get_modes(struct drm_connector *connector)
920 {
921 struct drm_device *dev = connector->dev;
922 struct drm_i915_private *dev_priv = to_i915(dev);
923 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
924 struct intel_encoder *intel_encoder = &crt->base;
925 intel_wakeref_t wakeref;
926 struct i2c_adapter *i2c;
927 int ret;
928
929 wakeref = intel_display_power_get(dev_priv,
930 intel_encoder->power_domain);
931
932 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
933 ret = intel_crt_ddc_get_modes(connector, i2c);
934 if (ret || !IS_G4X(dev_priv))
935 goto out;
936
937 /* Try to probe digital port for output in DVI-I -> VGA mode. */
938 i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB);
939 ret = intel_crt_ddc_get_modes(connector, i2c);
940
941 out:
942 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
943
944 return ret;
945 }
946
intel_crt_reset(struct drm_encoder * encoder)947 void intel_crt_reset(struct drm_encoder *encoder)
948 {
949 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
950 struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder));
951
952 if (DISPLAY_VER(dev_priv) >= 5) {
953 u32 adpa;
954
955 adpa = intel_de_read(dev_priv, crt->adpa_reg);
956 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
957 adpa |= ADPA_HOTPLUG_BITS;
958 intel_de_write(dev_priv, crt->adpa_reg, adpa);
959 intel_de_posting_read(dev_priv, crt->adpa_reg);
960
961 drm_dbg_kms(&dev_priv->drm, "crt adpa set to 0x%x\n", adpa);
962 crt->force_hotplug_required = true;
963 }
964
965 }
966
967 /*
968 * Routines for controlling stuff on the analog port
969 */
970
971 static const struct drm_connector_funcs intel_crt_connector_funcs = {
972 .fill_modes = drm_helper_probe_single_connector_modes,
973 .late_register = intel_connector_register,
974 .early_unregister = intel_connector_unregister,
975 .destroy = intel_connector_destroy,
976 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
977 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
978 };
979
980 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
981 .detect_ctx = intel_crt_detect,
982 .mode_valid = intel_crt_mode_valid,
983 .get_modes = intel_crt_get_modes,
984 };
985
986 static const struct drm_encoder_funcs intel_crt_enc_funcs = {
987 .reset = intel_crt_reset,
988 .destroy = intel_encoder_destroy,
989 };
990
intel_crt_init(struct drm_i915_private * dev_priv)991 void intel_crt_init(struct drm_i915_private *dev_priv)
992 {
993 struct drm_connector *connector;
994 struct intel_crt *crt;
995 struct intel_connector *intel_connector;
996 i915_reg_t adpa_reg;
997 u32 adpa;
998
999 if (HAS_PCH_SPLIT(dev_priv))
1000 adpa_reg = PCH_ADPA;
1001 else if (IS_VALLEYVIEW(dev_priv))
1002 adpa_reg = VLV_ADPA;
1003 else
1004 adpa_reg = ADPA;
1005
1006 adpa = intel_de_read(dev_priv, adpa_reg);
1007 if ((adpa & ADPA_DAC_ENABLE) == 0) {
1008 /*
1009 * On some machines (some IVB at least) CRT can be
1010 * fused off, but there's no known fuse bit to
1011 * indicate that. On these machine the ADPA register
1012 * works normally, except the DAC enable bit won't
1013 * take. So the only way to tell is attempt to enable
1014 * it and see what happens.
1015 */
1016 intel_de_write(dev_priv, adpa_reg,
1017 adpa | ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
1018 if ((intel_de_read(dev_priv, adpa_reg) & ADPA_DAC_ENABLE) == 0)
1019 return;
1020 intel_de_write(dev_priv, adpa_reg, adpa);
1021 }
1022
1023 crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
1024 if (!crt)
1025 return;
1026
1027 intel_connector = intel_connector_alloc();
1028 if (!intel_connector) {
1029 kfree(crt);
1030 return;
1031 }
1032
1033 connector = &intel_connector->base;
1034 crt->connector = intel_connector;
1035 drm_connector_init(&dev_priv->drm, &intel_connector->base,
1036 &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
1037
1038 drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs,
1039 DRM_MODE_ENCODER_DAC, "CRT");
1040
1041 intel_connector_attach_encoder(intel_connector, &crt->base);
1042
1043 crt->base.type = INTEL_OUTPUT_ANALOG;
1044 crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI);
1045 if (IS_I830(dev_priv))
1046 crt->base.pipe_mask = BIT(PIPE_A);
1047 else
1048 crt->base.pipe_mask = ~0;
1049
1050 if (IS_DISPLAY_VER(dev_priv, 2))
1051 connector->interlace_allowed = 0;
1052 else
1053 connector->interlace_allowed = 1;
1054 connector->doublescan_allowed = 0;
1055
1056 crt->adpa_reg = adpa_reg;
1057
1058 crt->base.power_domain = POWER_DOMAIN_PORT_CRT;
1059
1060 if (I915_HAS_HOTPLUG(dev_priv) &&
1061 !dmi_check_system(intel_spurious_crt_detect)) {
1062 crt->base.hpd_pin = HPD_CRT;
1063 crt->base.hotplug = intel_encoder_hotplug;
1064 intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
1065 } else {
1066 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1067 }
1068
1069 if (HAS_DDI(dev_priv)) {
1070 crt->base.port = PORT_E;
1071 crt->base.get_config = hsw_crt_get_config;
1072 crt->base.get_hw_state = intel_ddi_get_hw_state;
1073 crt->base.compute_config = hsw_crt_compute_config;
1074 crt->base.pre_pll_enable = hsw_pre_pll_enable_crt;
1075 crt->base.pre_enable = hsw_pre_enable_crt;
1076 crt->base.enable = hsw_enable_crt;
1077 crt->base.disable = hsw_disable_crt;
1078 crt->base.post_disable = hsw_post_disable_crt;
1079 crt->base.enable_clock = hsw_ddi_enable_clock;
1080 crt->base.disable_clock = hsw_ddi_disable_clock;
1081 crt->base.is_clock_enabled = hsw_ddi_is_clock_enabled;
1082 } else {
1083 if (HAS_PCH_SPLIT(dev_priv)) {
1084 crt->base.compute_config = pch_crt_compute_config;
1085 crt->base.disable = pch_disable_crt;
1086 crt->base.post_disable = pch_post_disable_crt;
1087 } else {
1088 crt->base.compute_config = intel_crt_compute_config;
1089 crt->base.disable = intel_disable_crt;
1090 }
1091 crt->base.port = PORT_NONE;
1092 crt->base.get_config = intel_crt_get_config;
1093 crt->base.get_hw_state = intel_crt_get_hw_state;
1094 crt->base.enable = intel_enable_crt;
1095 }
1096 intel_connector->get_hw_state = intel_connector_get_hw_state;
1097
1098 drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
1099
1100 /*
1101 * TODO: find a proper way to discover whether we need to set the the
1102 * polarity and link reversal bits or not, instead of relying on the
1103 * BIOS.
1104 */
1105 if (HAS_PCH_LPT(dev_priv)) {
1106 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
1107 FDI_RX_LINK_REVERSAL_OVERRIDE;
1108
1109 dev_priv->fdi_rx_config = intel_de_read(dev_priv,
1110 FDI_RX_CTL(PIPE_A)) & fdi_config;
1111 }
1112
1113 intel_crt_reset(&crt->base.base);
1114 }
1115