1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2015 Broadcom
4 */
5
6 /**
7 * DOC: VC4 CRTC module
8 *
9 * In VC4, the Pixel Valve is what most closely corresponds to the
10 * DRM's concept of a CRTC. The PV generates video timings from the
11 * encoder's clock plus its configuration. It pulls scaled pixels from
12 * the HVS at that timing, and feeds it to the encoder.
13 *
14 * However, the DRM CRTC also collects the configuration of all the
15 * DRM planes attached to it. As a result, the CRTC is also
16 * responsible for writing the display list for the HVS channel that
17 * the CRTC will use.
18 *
19 * The 2835 has 3 different pixel valves. pv0 in the audio power
20 * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI. pv2 in the
21 * image domain can feed either HDMI or the SDTV controller. The
22 * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
23 * SDTV, etc.) according to which output type is chosen in the mux.
24 *
25 * For power management, the pixel valve's registers are all clocked
26 * by the AXI clock, while the timings and FIFOs make use of the
27 * output-specific clock. Since the encoders also directly consume
28 * the CPRMAN clocks, and know what timings they need, they are the
29 * ones that set the clock.
30 */
31
32 #include <linux/clk.h>
33 #include <linux/component.h>
34 #include <linux/of_device.h>
35
36 #include <drm/drm_atomic.h>
37 #include <drm/drm_atomic_helper.h>
38 #include <drm/drm_atomic_uapi.h>
39 #include <drm/drm_fb_cma_helper.h>
40 #include <drm/drm_print.h>
41 #include <drm/drm_probe_helper.h>
42 #include <drm/drm_vblank.h>
43
44 #include "vc4_drv.h"
45 #include "vc4_regs.h"
46
47 #define HVS_FIFO_LATENCY_PIX 6
48
49 #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
50 #define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
51
52 static const struct debugfs_reg32 crtc_regs[] = {
53 VC4_REG32(PV_CONTROL),
54 VC4_REG32(PV_V_CONTROL),
55 VC4_REG32(PV_VSYNCD_EVEN),
56 VC4_REG32(PV_HORZA),
57 VC4_REG32(PV_HORZB),
58 VC4_REG32(PV_VERTA),
59 VC4_REG32(PV_VERTB),
60 VC4_REG32(PV_VERTA_EVEN),
61 VC4_REG32(PV_VERTB_EVEN),
62 VC4_REG32(PV_INTEN),
63 VC4_REG32(PV_INTSTAT),
64 VC4_REG32(PV_STAT),
65 VC4_REG32(PV_HACT_ACT),
66 };
67
68 static unsigned int
vc4_crtc_get_cob_allocation(struct vc4_dev * vc4,unsigned int channel)69 vc4_crtc_get_cob_allocation(struct vc4_dev *vc4, unsigned int channel)
70 {
71 u32 dispbase = HVS_READ(SCALER_DISPBASEX(channel));
72 /* Top/base are supposed to be 4-pixel aligned, but the
73 * Raspberry Pi firmware fills the low bits (which are
74 * presumably ignored).
75 */
76 u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
77 u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
78
79 return top - base + 4;
80 }
81
vc4_crtc_get_scanout_position(struct drm_crtc * crtc,bool in_vblank_irq,int * vpos,int * hpos,ktime_t * stime,ktime_t * etime,const struct drm_display_mode * mode)82 static bool vc4_crtc_get_scanout_position(struct drm_crtc *crtc,
83 bool in_vblank_irq,
84 int *vpos, int *hpos,
85 ktime_t *stime, ktime_t *etime,
86 const struct drm_display_mode *mode)
87 {
88 struct drm_device *dev = crtc->dev;
89 struct vc4_dev *vc4 = to_vc4_dev(dev);
90 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
91 struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state);
92 unsigned int cob_size;
93 u32 val;
94 int fifo_lines;
95 int vblank_lines;
96 bool ret = false;
97
98 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
99
100 /* Get optional system timestamp before query. */
101 if (stime)
102 *stime = ktime_get();
103
104 /*
105 * Read vertical scanline which is currently composed for our
106 * pixelvalve by the HVS, and also the scaler status.
107 */
108 val = HVS_READ(SCALER_DISPSTATX(vc4_crtc_state->assigned_channel));
109
110 /* Get optional system timestamp after query. */
111 if (etime)
112 *etime = ktime_get();
113
114 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
115
116 /* Vertical position of hvs composed scanline. */
117 *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE);
118 *hpos = 0;
119
120 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
121 *vpos /= 2;
122
123 /* Use hpos to correct for field offset in interlaced mode. */
124 if (VC4_GET_FIELD(val, SCALER_DISPSTATX_FRAME_COUNT) % 2)
125 *hpos += mode->crtc_htotal / 2;
126 }
127
128 cob_size = vc4_crtc_get_cob_allocation(vc4, vc4_crtc_state->assigned_channel);
129 /* This is the offset we need for translating hvs -> pv scanout pos. */
130 fifo_lines = cob_size / mode->crtc_hdisplay;
131
132 if (fifo_lines > 0)
133 ret = true;
134
135 /* HVS more than fifo_lines into frame for compositing? */
136 if (*vpos > fifo_lines) {
137 /*
138 * We are in active scanout and can get some meaningful results
139 * from HVS. The actual PV scanout can not trail behind more
140 * than fifo_lines as that is the fifo's capacity. Assume that
141 * in active scanout the HVS and PV work in lockstep wrt. HVS
142 * refilling the fifo and PV consuming from the fifo, ie.
143 * whenever the PV consumes and frees up a scanline in the
144 * fifo, the HVS will immediately refill it, therefore
145 * incrementing vpos. Therefore we choose HVS read position -
146 * fifo size in scanlines as a estimate of the real scanout
147 * position of the PV.
148 */
149 *vpos -= fifo_lines + 1;
150
151 return ret;
152 }
153
154 /*
155 * Less: This happens when we are in vblank and the HVS, after getting
156 * the VSTART restart signal from the PV, just started refilling its
157 * fifo with new lines from the top-most lines of the new framebuffers.
158 * The PV does not scan out in vblank, so does not remove lines from
159 * the fifo, so the fifo will be full quickly and the HVS has to pause.
160 * We can't get meaningful readings wrt. scanline position of the PV
161 * and need to make things up in a approximative but consistent way.
162 */
163 vblank_lines = mode->vtotal - mode->vdisplay;
164
165 if (in_vblank_irq) {
166 /*
167 * Assume the irq handler got called close to first
168 * line of vblank, so PV has about a full vblank
169 * scanlines to go, and as a base timestamp use the
170 * one taken at entry into vblank irq handler, so it
171 * is not affected by random delays due to lock
172 * contention on event_lock or vblank_time lock in
173 * the core.
174 */
175 *vpos = -vblank_lines;
176
177 if (stime)
178 *stime = vc4_crtc->t_vblank;
179 if (etime)
180 *etime = vc4_crtc->t_vblank;
181
182 /*
183 * If the HVS fifo is not yet full then we know for certain
184 * we are at the very beginning of vblank, as the hvs just
185 * started refilling, and the stime and etime timestamps
186 * truly correspond to start of vblank.
187 *
188 * Unfortunately there's no way to report this to upper levels
189 * and make it more useful.
190 */
191 } else {
192 /*
193 * No clue where we are inside vblank. Return a vpos of zero,
194 * which will cause calling code to just return the etime
195 * timestamp uncorrected. At least this is no worse than the
196 * standard fallback.
197 */
198 *vpos = 0;
199 }
200
201 return ret;
202 }
203
vc4_crtc_destroy(struct drm_crtc * crtc)204 void vc4_crtc_destroy(struct drm_crtc *crtc)
205 {
206 drm_crtc_cleanup(crtc);
207 }
208
vc4_get_fifo_full_level(struct vc4_crtc * vc4_crtc,u32 format)209 static u32 vc4_get_fifo_full_level(struct vc4_crtc *vc4_crtc, u32 format)
210 {
211 const struct vc4_crtc_data *crtc_data = vc4_crtc_to_vc4_crtc_data(vc4_crtc);
212 const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
213 struct vc4_dev *vc4 = to_vc4_dev(vc4_crtc->base.dev);
214 u32 fifo_len_bytes = pv_data->fifo_depth;
215
216 /*
217 * Pixels are pulled from the HVS if the number of bytes is
218 * lower than the FIFO full level.
219 *
220 * The latency of the pixel fetch mechanism is 6 pixels, so we
221 * need to convert those 6 pixels in bytes, depending on the
222 * format, and then subtract that from the length of the FIFO
223 * to make sure we never end up in a situation where the FIFO
224 * is full.
225 */
226 switch (format) {
227 case PV_CONTROL_FORMAT_DSIV_16:
228 case PV_CONTROL_FORMAT_DSIC_16:
229 return fifo_len_bytes - 2 * HVS_FIFO_LATENCY_PIX;
230 case PV_CONTROL_FORMAT_DSIV_18:
231 return fifo_len_bytes - 14;
232 case PV_CONTROL_FORMAT_24:
233 case PV_CONTROL_FORMAT_DSIV_24:
234 default:
235 /*
236 * For some reason, the pixelvalve4 doesn't work with
237 * the usual formula and will only work with 32.
238 */
239 if (crtc_data->hvs_output == 5)
240 return 32;
241
242 /*
243 * It looks like in some situations, we will overflow
244 * the PixelValve FIFO (with the bit 10 of PV stat being
245 * set) and stall the HVS / PV, eventually resulting in
246 * a page flip timeout.
247 *
248 * Displaying the video overlay during a playback with
249 * Kodi on an RPi3 seems to be a great solution with a
250 * failure rate around 50%.
251 *
252 * Removing 1 from the FIFO full level however
253 * seems to completely remove that issue.
254 */
255 if (!vc4->hvs->hvs5)
256 return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX - 1;
257
258 return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX;
259 }
260 }
261
vc4_crtc_get_fifo_full_level_bits(struct vc4_crtc * vc4_crtc,u32 format)262 static u32 vc4_crtc_get_fifo_full_level_bits(struct vc4_crtc *vc4_crtc,
263 u32 format)
264 {
265 u32 level = vc4_get_fifo_full_level(vc4_crtc, format);
266 u32 ret = 0;
267
268 ret |= VC4_SET_FIELD((level >> 6),
269 PV5_CONTROL_FIFO_LEVEL_HIGH);
270
271 return ret | VC4_SET_FIELD(level & 0x3f,
272 PV_CONTROL_FIFO_LEVEL);
273 }
274
275 /*
276 * Returns the encoder attached to the CRTC.
277 *
278 * VC4 can only scan out to one encoder at a time, while the DRM core
279 * allows drivers to push pixels to more than one encoder from the
280 * same CRTC.
281 */
vc4_get_crtc_encoder(struct drm_crtc * crtc)282 static struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc)
283 {
284 struct drm_connector *connector;
285 struct drm_connector_list_iter conn_iter;
286
287 drm_connector_list_iter_begin(crtc->dev, &conn_iter);
288 drm_for_each_connector_iter(connector, &conn_iter) {
289 if (connector->state->crtc == crtc) {
290 drm_connector_list_iter_end(&conn_iter);
291 return connector->encoder;
292 }
293 }
294 drm_connector_list_iter_end(&conn_iter);
295
296 return NULL;
297 }
298
vc4_crtc_pixelvalve_reset(struct drm_crtc * crtc)299 static void vc4_crtc_pixelvalve_reset(struct drm_crtc *crtc)
300 {
301 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
302
303 /* The PV needs to be disabled before it can be flushed */
304 CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) & ~PV_CONTROL_EN);
305 CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_FIFO_CLR);
306 }
307
vc4_crtc_config_pv(struct drm_crtc * crtc)308 static void vc4_crtc_config_pv(struct drm_crtc *crtc)
309 {
310 struct drm_device *dev = crtc->dev;
311 struct vc4_dev *vc4 = to_vc4_dev(dev);
312 struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);
313 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
314 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
315 const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
316 struct drm_crtc_state *state = crtc->state;
317 struct drm_display_mode *mode = &state->adjusted_mode;
318 bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
319 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
320 bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
321 vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
322 u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
323 u8 ppc = pv_data->pixels_per_clock;
324 bool debug_dump_regs = false;
325
326 if (debug_dump_regs) {
327 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);
328 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs before:\n",
329 drm_crtc_index(crtc));
330 drm_print_regset32(&p, &vc4_crtc->regset);
331 }
332
333 vc4_crtc_pixelvalve_reset(crtc);
334
335 CRTC_WRITE(PV_HORZA,
336 VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc,
337 PV_HORZA_HBP) |
338 VC4_SET_FIELD((mode->hsync_end - mode->hsync_start) * pixel_rep / ppc,
339 PV_HORZA_HSYNC));
340
341 CRTC_WRITE(PV_HORZB,
342 VC4_SET_FIELD((mode->hsync_start - mode->hdisplay) * pixel_rep / ppc,
343 PV_HORZB_HFP) |
344 VC4_SET_FIELD(mode->hdisplay * pixel_rep / ppc,
345 PV_HORZB_HACTIVE));
346
347 CRTC_WRITE(PV_VERTA,
348 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
349 PV_VERTA_VBP) |
350 VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
351 PV_VERTA_VSYNC));
352 CRTC_WRITE(PV_VERTB,
353 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
354 PV_VERTB_VFP) |
355 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
356
357 if (interlace) {
358 CRTC_WRITE(PV_VERTA_EVEN,
359 VC4_SET_FIELD(mode->crtc_vtotal -
360 mode->crtc_vsync_end - 1,
361 PV_VERTA_VBP) |
362 VC4_SET_FIELD(mode->crtc_vsync_end -
363 mode->crtc_vsync_start,
364 PV_VERTA_VSYNC));
365 CRTC_WRITE(PV_VERTB_EVEN,
366 VC4_SET_FIELD(mode->crtc_vsync_start -
367 mode->crtc_vdisplay,
368 PV_VERTB_VFP) |
369 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
370
371 /* We set up first field even mode for HDMI. VEC's
372 * NTSC mode would want first field odd instead, once
373 * we support it (to do so, set ODD_FIRST and put the
374 * delay in VSYNCD_EVEN instead).
375 */
376 CRTC_WRITE(PV_V_CONTROL,
377 PV_VCONTROL_CONTINUOUS |
378 (is_dsi ? PV_VCONTROL_DSI : 0) |
379 PV_VCONTROL_INTERLACE |
380 VC4_SET_FIELD(mode->htotal * pixel_rep / 2,
381 PV_VCONTROL_ODD_DELAY));
382 CRTC_WRITE(PV_VSYNCD_EVEN, 0);
383 } else {
384 CRTC_WRITE(PV_V_CONTROL,
385 PV_VCONTROL_CONTINUOUS |
386 (is_dsi ? PV_VCONTROL_DSI : 0));
387 }
388
389 if (is_dsi)
390 CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
391
392 if (vc4->hvs->hvs5)
393 CRTC_WRITE(PV_MUX_CFG,
394 VC4_SET_FIELD(PV_MUX_CFG_RGB_PIXEL_MUX_MODE_NO_SWAP,
395 PV_MUX_CFG_RGB_PIXEL_MUX_MODE));
396
397 CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR |
398 vc4_crtc_get_fifo_full_level_bits(vc4_crtc, format) |
399 VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
400 VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
401 PV_CONTROL_CLR_AT_START |
402 PV_CONTROL_TRIGGER_UNDERFLOW |
403 PV_CONTROL_WAIT_HSTART |
404 VC4_SET_FIELD(vc4_encoder->clock_select,
405 PV_CONTROL_CLK_SELECT));
406
407 if (debug_dump_regs) {
408 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);
409 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs after:\n",
410 drm_crtc_index(crtc));
411 drm_print_regset32(&p, &vc4_crtc->regset);
412 }
413 }
414
require_hvs_enabled(struct drm_device * dev)415 static void require_hvs_enabled(struct drm_device *dev)
416 {
417 struct vc4_dev *vc4 = to_vc4_dev(dev);
418
419 WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) !=
420 SCALER_DISPCTRL_ENABLE);
421 }
422
vc4_crtc_disable(struct drm_crtc * crtc,struct drm_atomic_state * state,unsigned int channel)423 static int vc4_crtc_disable(struct drm_crtc *crtc,
424 struct drm_atomic_state *state,
425 unsigned int channel)
426 {
427 struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);
428 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
429 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
430 struct drm_device *dev = crtc->dev;
431 int ret;
432
433 CRTC_WRITE(PV_V_CONTROL,
434 CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
435 ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
436 WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
437
438 /*
439 * This delay is needed to avoid to get a pixel stuck in an
440 * unflushable FIFO between the pixelvalve and the HDMI
441 * controllers on the BCM2711.
442 *
443 * Timing is fairly sensitive here, so mdelay is the safest
444 * approach.
445 *
446 * If it was to be reworked, the stuck pixel happens on a
447 * BCM2711 when changing mode with a good probability, so a
448 * script that changes mode on a regular basis should trigger
449 * the bug after less than 10 attempts. It manifests itself with
450 * every pixels being shifted by one to the right, and thus the
451 * last pixel of a line actually being displayed as the first
452 * pixel on the next line.
453 */
454 mdelay(20);
455
456 if (vc4_encoder && vc4_encoder->post_crtc_disable)
457 vc4_encoder->post_crtc_disable(encoder, state);
458
459 vc4_crtc_pixelvalve_reset(crtc);
460 vc4_hvs_stop_channel(dev, channel);
461
462 if (vc4_encoder && vc4_encoder->post_crtc_powerdown)
463 vc4_encoder->post_crtc_powerdown(encoder, state);
464
465 return 0;
466 }
467
vc4_crtc_disable_at_boot(struct drm_crtc * crtc)468 int vc4_crtc_disable_at_boot(struct drm_crtc *crtc)
469 {
470 struct drm_device *drm = crtc->dev;
471 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
472 int channel;
473
474 if (!(of_device_is_compatible(vc4_crtc->pdev->dev.of_node,
475 "brcm,bcm2711-pixelvalve2") ||
476 of_device_is_compatible(vc4_crtc->pdev->dev.of_node,
477 "brcm,bcm2711-pixelvalve4")))
478 return 0;
479
480 if (!(CRTC_READ(PV_CONTROL) & PV_CONTROL_EN))
481 return 0;
482
483 if (!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN))
484 return 0;
485
486 channel = vc4_hvs_get_fifo_from_output(drm, vc4_crtc->data->hvs_output);
487 if (channel < 0)
488 return 0;
489
490 return vc4_crtc_disable(crtc, NULL, channel);
491 }
492
vc4_crtc_atomic_disable(struct drm_crtc * crtc,struct drm_atomic_state * state)493 static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,
494 struct drm_atomic_state *state)
495 {
496 struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state,
497 crtc);
498 struct vc4_crtc_state *old_vc4_state = to_vc4_crtc_state(old_state);
499 struct drm_device *dev = crtc->dev;
500
501 require_hvs_enabled(dev);
502
503 /* Disable vblank irq handling before crtc is disabled. */
504 drm_crtc_vblank_off(crtc);
505
506 vc4_crtc_disable(crtc, state, old_vc4_state->assigned_channel);
507
508 /*
509 * Make sure we issue a vblank event after disabling the CRTC if
510 * someone was waiting it.
511 */
512 if (crtc->state->event) {
513 unsigned long flags;
514
515 spin_lock_irqsave(&dev->event_lock, flags);
516 drm_crtc_send_vblank_event(crtc, crtc->state->event);
517 crtc->state->event = NULL;
518 spin_unlock_irqrestore(&dev->event_lock, flags);
519 }
520 }
521
vc4_crtc_atomic_enable(struct drm_crtc * crtc,struct drm_atomic_state * state)522 static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
523 struct drm_atomic_state *state)
524 {
525 struct drm_device *dev = crtc->dev;
526 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
527 struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);
528 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
529
530 require_hvs_enabled(dev);
531
532 /* Enable vblank irq handling before crtc is started otherwise
533 * drm_crtc_get_vblank() fails in vc4_crtc_update_dlist().
534 */
535 drm_crtc_vblank_on(crtc);
536
537 vc4_hvs_atomic_enable(crtc, state);
538
539 if (vc4_encoder->pre_crtc_configure)
540 vc4_encoder->pre_crtc_configure(encoder, state);
541
542 vc4_crtc_config_pv(crtc);
543
544 CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_EN);
545
546 if (vc4_encoder->pre_crtc_enable)
547 vc4_encoder->pre_crtc_enable(encoder, state);
548
549 /* When feeding the transposer block the pixelvalve is unneeded and
550 * should not be enabled.
551 */
552 CRTC_WRITE(PV_V_CONTROL,
553 CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
554
555 if (vc4_encoder->post_crtc_enable)
556 vc4_encoder->post_crtc_enable(encoder, state);
557 }
558
vc4_crtc_mode_valid(struct drm_crtc * crtc,const struct drm_display_mode * mode)559 static enum drm_mode_status vc4_crtc_mode_valid(struct drm_crtc *crtc,
560 const struct drm_display_mode *mode)
561 {
562 /* Do not allow doublescan modes from user space */
563 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
564 DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n",
565 crtc->base.id);
566 return MODE_NO_DBLESCAN;
567 }
568
569 return MODE_OK;
570 }
571
vc4_crtc_get_margins(struct drm_crtc_state * state,unsigned int * left,unsigned int * right,unsigned int * top,unsigned int * bottom)572 void vc4_crtc_get_margins(struct drm_crtc_state *state,
573 unsigned int *left, unsigned int *right,
574 unsigned int *top, unsigned int *bottom)
575 {
576 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
577 struct drm_connector_state *conn_state;
578 struct drm_connector *conn;
579 int i;
580
581 *left = vc4_state->margins.left;
582 *right = vc4_state->margins.right;
583 *top = vc4_state->margins.top;
584 *bottom = vc4_state->margins.bottom;
585
586 /* We have to interate over all new connector states because
587 * vc4_crtc_get_margins() might be called before
588 * vc4_crtc_atomic_check() which means margins info in vc4_crtc_state
589 * might be outdated.
590 */
591 for_each_new_connector_in_state(state->state, conn, conn_state, i) {
592 if (conn_state->crtc != state->crtc)
593 continue;
594
595 *left = conn_state->tv.margins.left;
596 *right = conn_state->tv.margins.right;
597 *top = conn_state->tv.margins.top;
598 *bottom = conn_state->tv.margins.bottom;
599 break;
600 }
601 }
602
vc4_crtc_atomic_check(struct drm_crtc * crtc,struct drm_atomic_state * state)603 static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
604 struct drm_atomic_state *state)
605 {
606 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
607 crtc);
608 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
609 struct drm_connector *conn;
610 struct drm_connector_state *conn_state;
611 int ret, i;
612
613 ret = vc4_hvs_atomic_check(crtc, state);
614 if (ret)
615 return ret;
616
617 for_each_new_connector_in_state(state, conn, conn_state,
618 i) {
619 if (conn_state->crtc != crtc)
620 continue;
621
622 vc4_state->margins.left = conn_state->tv.margins.left;
623 vc4_state->margins.right = conn_state->tv.margins.right;
624 vc4_state->margins.top = conn_state->tv.margins.top;
625 vc4_state->margins.bottom = conn_state->tv.margins.bottom;
626 break;
627 }
628
629 return 0;
630 }
631
vc4_enable_vblank(struct drm_crtc * crtc)632 static int vc4_enable_vblank(struct drm_crtc *crtc)
633 {
634 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
635
636 CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);
637
638 return 0;
639 }
640
vc4_disable_vblank(struct drm_crtc * crtc)641 static void vc4_disable_vblank(struct drm_crtc *crtc)
642 {
643 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
644
645 CRTC_WRITE(PV_INTEN, 0);
646 }
647
vc4_crtc_handle_page_flip(struct vc4_crtc * vc4_crtc)648 static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
649 {
650 struct drm_crtc *crtc = &vc4_crtc->base;
651 struct drm_device *dev = crtc->dev;
652 struct vc4_dev *vc4 = to_vc4_dev(dev);
653 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
654 u32 chan = vc4_state->assigned_channel;
655 unsigned long flags;
656
657 spin_lock_irqsave(&dev->event_lock, flags);
658 if (vc4_crtc->event &&
659 (vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)) ||
660 vc4_state->feed_txp)) {
661 drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
662 vc4_crtc->event = NULL;
663 drm_crtc_vblank_put(crtc);
664
665 /* Wait for the page flip to unmask the underrun to ensure that
666 * the display list was updated by the hardware. Before that
667 * happens, the HVS will be using the previous display list with
668 * the CRTC and encoder already reconfigured, leading to
669 * underruns. This can be seen when reconfiguring the CRTC.
670 */
671 vc4_hvs_unmask_underrun(dev, chan);
672 }
673 spin_unlock_irqrestore(&dev->event_lock, flags);
674 }
675
vc4_crtc_handle_vblank(struct vc4_crtc * crtc)676 void vc4_crtc_handle_vblank(struct vc4_crtc *crtc)
677 {
678 crtc->t_vblank = ktime_get();
679 drm_crtc_handle_vblank(&crtc->base);
680 vc4_crtc_handle_page_flip(crtc);
681 }
682
vc4_crtc_irq_handler(int irq,void * data)683 static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
684 {
685 struct vc4_crtc *vc4_crtc = data;
686 u32 stat = CRTC_READ(PV_INTSTAT);
687 irqreturn_t ret = IRQ_NONE;
688
689 if (stat & PV_INT_VFP_START) {
690 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
691 vc4_crtc_handle_vblank(vc4_crtc);
692 ret = IRQ_HANDLED;
693 }
694
695 return ret;
696 }
697
698 struct vc4_async_flip_state {
699 struct drm_crtc *crtc;
700 struct drm_framebuffer *fb;
701 struct drm_framebuffer *old_fb;
702 struct drm_pending_vblank_event *event;
703
704 struct vc4_seqno_cb cb;
705 };
706
707 /* Called when the V3D execution for the BO being flipped to is done, so that
708 * we can actually update the plane's address to point to it.
709 */
710 static void
vc4_async_page_flip_complete(struct vc4_seqno_cb * cb)711 vc4_async_page_flip_complete(struct vc4_seqno_cb *cb)
712 {
713 struct vc4_async_flip_state *flip_state =
714 container_of(cb, struct vc4_async_flip_state, cb);
715 struct drm_crtc *crtc = flip_state->crtc;
716 struct drm_device *dev = crtc->dev;
717 struct drm_plane *plane = crtc->primary;
718
719 vc4_plane_async_set_fb(plane, flip_state->fb);
720 if (flip_state->event) {
721 unsigned long flags;
722
723 spin_lock_irqsave(&dev->event_lock, flags);
724 drm_crtc_send_vblank_event(crtc, flip_state->event);
725 spin_unlock_irqrestore(&dev->event_lock, flags);
726 }
727
728 drm_crtc_vblank_put(crtc);
729 drm_framebuffer_put(flip_state->fb);
730
731 /* Decrement the BO usecnt in order to keep the inc/dec calls balanced
732 * when the planes are updated through the async update path.
733 * FIXME: we should move to generic async-page-flip when it's
734 * available, so that we can get rid of this hand-made cleanup_fb()
735 * logic.
736 */
737 if (flip_state->old_fb) {
738 struct drm_gem_cma_object *cma_bo;
739 struct vc4_bo *bo;
740
741 cma_bo = drm_fb_cma_get_gem_obj(flip_state->old_fb, 0);
742 bo = to_vc4_bo(&cma_bo->base);
743 vc4_bo_dec_usecnt(bo);
744 drm_framebuffer_put(flip_state->old_fb);
745 }
746
747 kfree(flip_state);
748 }
749
750 /* Implements async (non-vblank-synced) page flips.
751 *
752 * The page flip ioctl needs to return immediately, so we grab the
753 * modeset semaphore on the pipe, and queue the address update for
754 * when V3D is done with the BO being flipped to.
755 */
vc4_async_page_flip(struct drm_crtc * crtc,struct drm_framebuffer * fb,struct drm_pending_vblank_event * event,uint32_t flags)756 static int vc4_async_page_flip(struct drm_crtc *crtc,
757 struct drm_framebuffer *fb,
758 struct drm_pending_vblank_event *event,
759 uint32_t flags)
760 {
761 struct drm_device *dev = crtc->dev;
762 struct drm_plane *plane = crtc->primary;
763 int ret = 0;
764 struct vc4_async_flip_state *flip_state;
765 struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
766 struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
767
768 /* Increment the BO usecnt here, so that we never end up with an
769 * unbalanced number of vc4_bo_{dec,inc}_usecnt() calls when the
770 * plane is later updated through the non-async path.
771 * FIXME: we should move to generic async-page-flip when it's
772 * available, so that we can get rid of this hand-made prepare_fb()
773 * logic.
774 */
775 ret = vc4_bo_inc_usecnt(bo);
776 if (ret)
777 return ret;
778
779 flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL);
780 if (!flip_state) {
781 vc4_bo_dec_usecnt(bo);
782 return -ENOMEM;
783 }
784
785 drm_framebuffer_get(fb);
786 flip_state->fb = fb;
787 flip_state->crtc = crtc;
788 flip_state->event = event;
789
790 /* Save the current FB before it's replaced by the new one in
791 * drm_atomic_set_fb_for_plane(). We'll need the old FB in
792 * vc4_async_page_flip_complete() to decrement the BO usecnt and keep
793 * it consistent.
794 * FIXME: we should move to generic async-page-flip when it's
795 * available, so that we can get rid of this hand-made cleanup_fb()
796 * logic.
797 */
798 flip_state->old_fb = plane->state->fb;
799 if (flip_state->old_fb)
800 drm_framebuffer_get(flip_state->old_fb);
801
802 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
803
804 /* Immediately update the plane's legacy fb pointer, so that later
805 * modeset prep sees the state that will be present when the semaphore
806 * is released.
807 */
808 drm_atomic_set_fb_for_plane(plane->state, fb);
809
810 vc4_queue_seqno_cb(dev, &flip_state->cb, bo->seqno,
811 vc4_async_page_flip_complete);
812
813 /* Driver takes ownership of state on successful async commit. */
814 return 0;
815 }
816
vc4_page_flip(struct drm_crtc * crtc,struct drm_framebuffer * fb,struct drm_pending_vblank_event * event,uint32_t flags,struct drm_modeset_acquire_ctx * ctx)817 int vc4_page_flip(struct drm_crtc *crtc,
818 struct drm_framebuffer *fb,
819 struct drm_pending_vblank_event *event,
820 uint32_t flags,
821 struct drm_modeset_acquire_ctx *ctx)
822 {
823 if (flags & DRM_MODE_PAGE_FLIP_ASYNC)
824 return vc4_async_page_flip(crtc, fb, event, flags);
825 else
826 return drm_atomic_helper_page_flip(crtc, fb, event, flags, ctx);
827 }
828
vc4_crtc_duplicate_state(struct drm_crtc * crtc)829 struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
830 {
831 struct vc4_crtc_state *vc4_state, *old_vc4_state;
832
833 vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
834 if (!vc4_state)
835 return NULL;
836
837 old_vc4_state = to_vc4_crtc_state(crtc->state);
838 vc4_state->feed_txp = old_vc4_state->feed_txp;
839 vc4_state->margins = old_vc4_state->margins;
840 vc4_state->assigned_channel = old_vc4_state->assigned_channel;
841
842 __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
843 return &vc4_state->base;
844 }
845
vc4_crtc_destroy_state(struct drm_crtc * crtc,struct drm_crtc_state * state)846 void vc4_crtc_destroy_state(struct drm_crtc *crtc,
847 struct drm_crtc_state *state)
848 {
849 struct vc4_dev *vc4 = to_vc4_dev(crtc->dev);
850 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
851
852 if (drm_mm_node_allocated(&vc4_state->mm)) {
853 unsigned long flags;
854
855 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
856 drm_mm_remove_node(&vc4_state->mm);
857 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
858
859 }
860
861 drm_atomic_helper_crtc_destroy_state(crtc, state);
862 }
863
vc4_crtc_reset(struct drm_crtc * crtc)864 void vc4_crtc_reset(struct drm_crtc *crtc)
865 {
866 struct vc4_crtc_state *vc4_crtc_state;
867
868 if (crtc->state)
869 vc4_crtc_destroy_state(crtc, crtc->state);
870
871 vc4_crtc_state = kzalloc(sizeof(*vc4_crtc_state), GFP_KERNEL);
872 if (!vc4_crtc_state) {
873 crtc->state = NULL;
874 return;
875 }
876
877 vc4_crtc_state->assigned_channel = VC4_HVS_CHANNEL_DISABLED;
878 __drm_atomic_helper_crtc_reset(crtc, &vc4_crtc_state->base);
879 }
880
881 static const struct drm_crtc_funcs vc4_crtc_funcs = {
882 .set_config = drm_atomic_helper_set_config,
883 .destroy = vc4_crtc_destroy,
884 .page_flip = vc4_page_flip,
885 .set_property = NULL,
886 .cursor_set = NULL, /* handled by drm_mode_cursor_universal */
887 .cursor_move = NULL, /* handled by drm_mode_cursor_universal */
888 .reset = vc4_crtc_reset,
889 .atomic_duplicate_state = vc4_crtc_duplicate_state,
890 .atomic_destroy_state = vc4_crtc_destroy_state,
891 .enable_vblank = vc4_enable_vblank,
892 .disable_vblank = vc4_disable_vblank,
893 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
894 };
895
896 static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
897 .mode_valid = vc4_crtc_mode_valid,
898 .atomic_check = vc4_crtc_atomic_check,
899 .atomic_flush = vc4_hvs_atomic_flush,
900 .atomic_enable = vc4_crtc_atomic_enable,
901 .atomic_disable = vc4_crtc_atomic_disable,
902 .get_scanout_position = vc4_crtc_get_scanout_position,
903 };
904
905 static const struct vc4_pv_data bcm2835_pv0_data = {
906 .base = {
907 .hvs_available_channels = BIT(0),
908 .hvs_output = 0,
909 },
910 .debugfs_name = "crtc0_regs",
911 .fifo_depth = 64,
912 .pixels_per_clock = 1,
913 .encoder_types = {
914 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
915 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
916 },
917 };
918
919 static const struct vc4_pv_data bcm2835_pv1_data = {
920 .base = {
921 .hvs_available_channels = BIT(2),
922 .hvs_output = 2,
923 },
924 .debugfs_name = "crtc1_regs",
925 .fifo_depth = 64,
926 .pixels_per_clock = 1,
927 .encoder_types = {
928 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
929 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
930 },
931 };
932
933 static const struct vc4_pv_data bcm2835_pv2_data = {
934 .base = {
935 .hvs_available_channels = BIT(1),
936 .hvs_output = 1,
937 },
938 .debugfs_name = "crtc2_regs",
939 .fifo_depth = 64,
940 .pixels_per_clock = 1,
941 .encoder_types = {
942 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI0,
943 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
944 },
945 };
946
947 static const struct vc4_pv_data bcm2711_pv0_data = {
948 .base = {
949 .hvs_available_channels = BIT(0),
950 .hvs_output = 0,
951 },
952 .debugfs_name = "crtc0_regs",
953 .fifo_depth = 64,
954 .pixels_per_clock = 1,
955 .encoder_types = {
956 [0] = VC4_ENCODER_TYPE_DSI0,
957 [1] = VC4_ENCODER_TYPE_DPI,
958 },
959 };
960
961 static const struct vc4_pv_data bcm2711_pv1_data = {
962 .base = {
963 .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
964 .hvs_output = 3,
965 },
966 .debugfs_name = "crtc1_regs",
967 .fifo_depth = 64,
968 .pixels_per_clock = 1,
969 .encoder_types = {
970 [0] = VC4_ENCODER_TYPE_DSI1,
971 [1] = VC4_ENCODER_TYPE_SMI,
972 },
973 };
974
975 static const struct vc4_pv_data bcm2711_pv2_data = {
976 .base = {
977 .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
978 .hvs_output = 4,
979 },
980 .debugfs_name = "crtc2_regs",
981 .fifo_depth = 256,
982 .pixels_per_clock = 2,
983 .encoder_types = {
984 [0] = VC4_ENCODER_TYPE_HDMI0,
985 },
986 };
987
988 static const struct vc4_pv_data bcm2711_pv3_data = {
989 .base = {
990 .hvs_available_channels = BIT(1),
991 .hvs_output = 1,
992 },
993 .debugfs_name = "crtc3_regs",
994 .fifo_depth = 64,
995 .pixels_per_clock = 1,
996 .encoder_types = {
997 [0] = VC4_ENCODER_TYPE_VEC,
998 },
999 };
1000
1001 static const struct vc4_pv_data bcm2711_pv4_data = {
1002 .base = {
1003 .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
1004 .hvs_output = 5,
1005 },
1006 .debugfs_name = "crtc4_regs",
1007 .fifo_depth = 64,
1008 .pixels_per_clock = 2,
1009 .encoder_types = {
1010 [0] = VC4_ENCODER_TYPE_HDMI1,
1011 },
1012 };
1013
1014 static const struct of_device_id vc4_crtc_dt_match[] = {
1015 { .compatible = "brcm,bcm2835-pixelvalve0", .data = &bcm2835_pv0_data },
1016 { .compatible = "brcm,bcm2835-pixelvalve1", .data = &bcm2835_pv1_data },
1017 { .compatible = "brcm,bcm2835-pixelvalve2", .data = &bcm2835_pv2_data },
1018 { .compatible = "brcm,bcm2711-pixelvalve0", .data = &bcm2711_pv0_data },
1019 { .compatible = "brcm,bcm2711-pixelvalve1", .data = &bcm2711_pv1_data },
1020 { .compatible = "brcm,bcm2711-pixelvalve2", .data = &bcm2711_pv2_data },
1021 { .compatible = "brcm,bcm2711-pixelvalve3", .data = &bcm2711_pv3_data },
1022 { .compatible = "brcm,bcm2711-pixelvalve4", .data = &bcm2711_pv4_data },
1023 {}
1024 };
1025
vc4_set_crtc_possible_masks(struct drm_device * drm,struct drm_crtc * crtc)1026 static void vc4_set_crtc_possible_masks(struct drm_device *drm,
1027 struct drm_crtc *crtc)
1028 {
1029 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
1030 const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
1031 const enum vc4_encoder_type *encoder_types = pv_data->encoder_types;
1032 struct drm_encoder *encoder;
1033
1034 drm_for_each_encoder(encoder, drm) {
1035 struct vc4_encoder *vc4_encoder;
1036 int i;
1037
1038 vc4_encoder = to_vc4_encoder(encoder);
1039 for (i = 0; i < ARRAY_SIZE(pv_data->encoder_types); i++) {
1040 if (vc4_encoder->type == encoder_types[i]) {
1041 vc4_encoder->clock_select = i;
1042 encoder->possible_crtcs |= drm_crtc_mask(crtc);
1043 break;
1044 }
1045 }
1046 }
1047 }
1048
vc4_crtc_init(struct drm_device * drm,struct vc4_crtc * vc4_crtc,const struct drm_crtc_funcs * crtc_funcs,const struct drm_crtc_helper_funcs * crtc_helper_funcs)1049 int vc4_crtc_init(struct drm_device *drm, struct vc4_crtc *vc4_crtc,
1050 const struct drm_crtc_funcs *crtc_funcs,
1051 const struct drm_crtc_helper_funcs *crtc_helper_funcs)
1052 {
1053 struct vc4_dev *vc4 = to_vc4_dev(drm);
1054 struct drm_crtc *crtc = &vc4_crtc->base;
1055 struct drm_plane *primary_plane;
1056 unsigned int i;
1057
1058 /* For now, we create just the primary and the legacy cursor
1059 * planes. We should be able to stack more planes on easily,
1060 * but to do that we would need to compute the bandwidth
1061 * requirement of the plane configuration, and reject ones
1062 * that will take too much.
1063 */
1064 primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY);
1065 if (IS_ERR(primary_plane)) {
1066 dev_err(drm->dev, "failed to construct primary plane\n");
1067 return PTR_ERR(primary_plane);
1068 }
1069
1070 drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
1071 crtc_funcs, NULL);
1072 drm_crtc_helper_add(crtc, crtc_helper_funcs);
1073
1074 if (!vc4->hvs->hvs5) {
1075 drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
1076
1077 drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size);
1078
1079 /* We support CTM, but only for one CRTC at a time. It's therefore
1080 * implemented as private driver state in vc4_kms, not here.
1081 */
1082 drm_crtc_enable_color_mgmt(crtc, 0, true, crtc->gamma_size);
1083 }
1084
1085 for (i = 0; i < crtc->gamma_size; i++) {
1086 vc4_crtc->lut_r[i] = i;
1087 vc4_crtc->lut_g[i] = i;
1088 vc4_crtc->lut_b[i] = i;
1089 }
1090
1091 return 0;
1092 }
1093
vc4_crtc_bind(struct device * dev,struct device * master,void * data)1094 static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
1095 {
1096 struct platform_device *pdev = to_platform_device(dev);
1097 struct drm_device *drm = dev_get_drvdata(master);
1098 const struct vc4_pv_data *pv_data;
1099 struct vc4_crtc *vc4_crtc;
1100 struct drm_crtc *crtc;
1101 struct drm_plane *destroy_plane, *temp;
1102 int ret;
1103
1104 vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL);
1105 if (!vc4_crtc)
1106 return -ENOMEM;
1107 crtc = &vc4_crtc->base;
1108
1109 pv_data = of_device_get_match_data(dev);
1110 if (!pv_data)
1111 return -ENODEV;
1112 vc4_crtc->data = &pv_data->base;
1113 vc4_crtc->pdev = pdev;
1114
1115 vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);
1116 if (IS_ERR(vc4_crtc->regs))
1117 return PTR_ERR(vc4_crtc->regs);
1118
1119 vc4_crtc->regset.base = vc4_crtc->regs;
1120 vc4_crtc->regset.regs = crtc_regs;
1121 vc4_crtc->regset.nregs = ARRAY_SIZE(crtc_regs);
1122
1123 ret = vc4_crtc_init(drm, vc4_crtc,
1124 &vc4_crtc_funcs, &vc4_crtc_helper_funcs);
1125 if (ret)
1126 return ret;
1127 vc4_set_crtc_possible_masks(drm, crtc);
1128
1129 CRTC_WRITE(PV_INTEN, 0);
1130 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
1131 ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1132 vc4_crtc_irq_handler,
1133 IRQF_SHARED,
1134 "vc4 crtc", vc4_crtc);
1135 if (ret)
1136 goto err_destroy_planes;
1137
1138 platform_set_drvdata(pdev, vc4_crtc);
1139
1140 vc4_debugfs_add_regset32(drm, pv_data->debugfs_name,
1141 &vc4_crtc->regset);
1142
1143 return 0;
1144
1145 err_destroy_planes:
1146 list_for_each_entry_safe(destroy_plane, temp,
1147 &drm->mode_config.plane_list, head) {
1148 if (destroy_plane->possible_crtcs == drm_crtc_mask(crtc))
1149 destroy_plane->funcs->destroy(destroy_plane);
1150 }
1151
1152 return ret;
1153 }
1154
vc4_crtc_unbind(struct device * dev,struct device * master,void * data)1155 static void vc4_crtc_unbind(struct device *dev, struct device *master,
1156 void *data)
1157 {
1158 struct platform_device *pdev = to_platform_device(dev);
1159 struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev);
1160
1161 vc4_crtc_destroy(&vc4_crtc->base);
1162
1163 CRTC_WRITE(PV_INTEN, 0);
1164
1165 platform_set_drvdata(pdev, NULL);
1166 }
1167
1168 static const struct component_ops vc4_crtc_ops = {
1169 .bind = vc4_crtc_bind,
1170 .unbind = vc4_crtc_unbind,
1171 };
1172
vc4_crtc_dev_probe(struct platform_device * pdev)1173 static int vc4_crtc_dev_probe(struct platform_device *pdev)
1174 {
1175 return component_add(&pdev->dev, &vc4_crtc_ops);
1176 }
1177
vc4_crtc_dev_remove(struct platform_device * pdev)1178 static int vc4_crtc_dev_remove(struct platform_device *pdev)
1179 {
1180 component_del(&pdev->dev, &vc4_crtc_ops);
1181 return 0;
1182 }
1183
1184 struct platform_driver vc4_crtc_driver = {
1185 .probe = vc4_crtc_dev_probe,
1186 .remove = vc4_crtc_dev_remove,
1187 .driver = {
1188 .name = "vc4_crtc",
1189 .of_match_table = vc4_crtc_dt_match,
1190 },
1191 };
1192