1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Analog Devices AD5766, AD5767
4 * Digital to Analog Converters driver
5 * Copyright 2019-2020 Analog Devices Inc.
6 */
7 #include <linux/bitfield.h>
8 #include <linux/delay.h>
9 #include <linux/device.h>
10 #include <linux/gpio/consumer.h>
11 #include <linux/iio/iio.h>
12 #include <linux/module.h>
13 #include <linux/spi/spi.h>
14 #include <asm/unaligned.h>
15
16 #define AD5766_UPPER_WORD_SPI_MASK GENMASK(31, 16)
17 #define AD5766_LOWER_WORD_SPI_MASK GENMASK(15, 0)
18 #define AD5766_DITHER_SOURCE_MASK(ch) GENMASK(((2 * ch) + 1), (2 * ch))
19 #define AD5766_DITHER_SOURCE(ch, source) BIT((ch * 2) + source)
20 #define AD5766_DITHER_SCALE_MASK(x) AD5766_DITHER_SOURCE_MASK(x)
21 #define AD5766_DITHER_SCALE(ch, scale) (scale << (ch * 2))
22 #define AD5766_DITHER_ENABLE_MASK(ch) BIT(ch)
23 #define AD5766_DITHER_ENABLE(ch, state) ((!state) << ch)
24 #define AD5766_DITHER_INVERT_MASK(ch) BIT(ch)
25 #define AD5766_DITHER_INVERT(ch, state) (state << ch)
26
27 #define AD5766_CMD_NOP_MUX_OUT 0x00
28 #define AD5766_CMD_SDO_CNTRL 0x01
29 #define AD5766_CMD_WR_IN_REG(x) (0x10 | ((x) & GENMASK(3, 0)))
30 #define AD5766_CMD_WR_DAC_REG(x) (0x20 | ((x) & GENMASK(3, 0)))
31 #define AD5766_CMD_SW_LDAC 0x30
32 #define AD5766_CMD_SPAN_REG 0x40
33 #define AD5766_CMD_WR_PWR_DITHER 0x51
34 #define AD5766_CMD_WR_DAC_REG_ALL 0x60
35 #define AD5766_CMD_SW_FULL_RESET 0x70
36 #define AD5766_CMD_READBACK_REG(x) (0x80 | ((x) & GENMASK(3, 0)))
37 #define AD5766_CMD_DITHER_SIG_1 0x90
38 #define AD5766_CMD_DITHER_SIG_2 0xA0
39 #define AD5766_CMD_INV_DITHER 0xB0
40 #define AD5766_CMD_DITHER_SCALE_1 0xC0
41 #define AD5766_CMD_DITHER_SCALE_2 0xD0
42
43 #define AD5766_FULL_RESET_CODE 0x1234
44
45 enum ad5766_type {
46 ID_AD5766,
47 ID_AD5767,
48 };
49
50 enum ad5766_voltage_range {
51 AD5766_VOLTAGE_RANGE_M20V_0V,
52 AD5766_VOLTAGE_RANGE_M16V_to_0V,
53 AD5766_VOLTAGE_RANGE_M10V_to_0V,
54 AD5766_VOLTAGE_RANGE_M12V_to_14V,
55 AD5766_VOLTAGE_RANGE_M16V_to_10V,
56 AD5766_VOLTAGE_RANGE_M10V_to_6V,
57 AD5766_VOLTAGE_RANGE_M5V_to_5V,
58 AD5766_VOLTAGE_RANGE_M10V_to_10V,
59 };
60
61 /**
62 * struct ad5766_chip_info - chip specific information
63 * @num_channels: number of channels
64 * @channels: channel specification
65 */
66 struct ad5766_chip_info {
67 unsigned int num_channels;
68 const struct iio_chan_spec *channels;
69 };
70
71 enum {
72 AD5766_DITHER_ENABLE,
73 AD5766_DITHER_INVERT,
74 AD5766_DITHER_SOURCE,
75 };
76
77 /*
78 * Dither signal can also be scaled.
79 * Available dither scale strings corresponding to "dither_scale" field in
80 * "struct ad5766_state".
81 */
82 static const char * const ad5766_dither_scales[] = {
83 "1",
84 "0.75",
85 "0.5",
86 "0.25",
87 };
88
89 /**
90 * struct ad5766_state - driver instance specific data
91 * @spi: SPI device
92 * @lock: Lock used to restrict concurrent access to SPI device
93 * @chip_info: Chip model specific constants
94 * @gpio_reset: Reset GPIO, used to reset the device
95 * @crt_range: Current selected output range
96 * @dither_enable: Power enable bit for each channel dither block (for
97 * example, D15 = DAC 15,D8 = DAC 8, and D0 = DAC 0)
98 * 0 - Normal operation, 1 - Power down
99 * @dither_invert: Inverts the dither signal applied to the selected DAC
100 * outputs
101 * @dither_source: Selects between 2 possible sources:
102 * 1: N0, 2: N1
103 * Two bits are used for each channel
104 * @dither_scale: Two bits are used for each of the 16 channels:
105 * 0: 1 SCALING, 1: 0.75 SCALING, 2: 0.5 SCALING,
106 * 3: 0.25 SCALING.
107 * @data: SPI transfer buffers
108 */
109 struct ad5766_state {
110 struct spi_device *spi;
111 struct mutex lock;
112 const struct ad5766_chip_info *chip_info;
113 struct gpio_desc *gpio_reset;
114 enum ad5766_voltage_range crt_range;
115 u16 dither_enable;
116 u16 dither_invert;
117 u32 dither_source;
118 u32 dither_scale;
119 union {
120 u32 d32;
121 u16 w16[2];
122 u8 b8[4];
123 } data[3] ____cacheline_aligned;
124 };
125
126 struct ad5766_span_tbl {
127 int min;
128 int max;
129 };
130
131 static const struct ad5766_span_tbl ad5766_span_tbl[] = {
132 [AD5766_VOLTAGE_RANGE_M20V_0V] = {-20, 0},
133 [AD5766_VOLTAGE_RANGE_M16V_to_0V] = {-16, 0},
134 [AD5766_VOLTAGE_RANGE_M10V_to_0V] = {-10, 0},
135 [AD5766_VOLTAGE_RANGE_M12V_to_14V] = {-12, 14},
136 [AD5766_VOLTAGE_RANGE_M16V_to_10V] = {-16, 10},
137 [AD5766_VOLTAGE_RANGE_M10V_to_6V] = {-10, 6},
138 [AD5766_VOLTAGE_RANGE_M5V_to_5V] = {-5, 5},
139 [AD5766_VOLTAGE_RANGE_M10V_to_10V] = {-10, 10},
140 };
141
__ad5766_spi_read(struct ad5766_state * st,u8 dac,int * val)142 static int __ad5766_spi_read(struct ad5766_state *st, u8 dac, int *val)
143 {
144 int ret;
145 struct spi_transfer xfers[] = {
146 {
147 .tx_buf = &st->data[0].d32,
148 .bits_per_word = 8,
149 .len = 3,
150 .cs_change = 1,
151 }, {
152 .tx_buf = &st->data[1].d32,
153 .rx_buf = &st->data[2].d32,
154 .bits_per_word = 8,
155 .len = 3,
156 },
157 };
158
159 st->data[0].d32 = AD5766_CMD_READBACK_REG(dac);
160 st->data[1].d32 = AD5766_CMD_NOP_MUX_OUT;
161
162 ret = spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers));
163 if (ret)
164 return ret;
165
166 *val = st->data[2].w16[1];
167
168 return ret;
169 }
170
__ad5766_spi_write(struct ad5766_state * st,u8 command,u16 data)171 static int __ad5766_spi_write(struct ad5766_state *st, u8 command, u16 data)
172 {
173 st->data[0].b8[0] = command;
174 put_unaligned_be16(data, &st->data[0].b8[1]);
175
176 return spi_write(st->spi, &st->data[0].b8[0], 3);
177 }
178
ad5766_read(struct iio_dev * indio_dev,u8 dac,int * val)179 static int ad5766_read(struct iio_dev *indio_dev, u8 dac, int *val)
180 {
181 struct ad5766_state *st = iio_priv(indio_dev);
182 int ret;
183
184 mutex_lock(&st->lock);
185 ret = __ad5766_spi_read(st, dac, val);
186 mutex_unlock(&st->lock);
187
188 return ret;
189 }
190
ad5766_write(struct iio_dev * indio_dev,u8 dac,u16 data)191 static int ad5766_write(struct iio_dev *indio_dev, u8 dac, u16 data)
192 {
193 struct ad5766_state *st = iio_priv(indio_dev);
194 int ret;
195
196 mutex_lock(&st->lock);
197 ret = __ad5766_spi_write(st, AD5766_CMD_WR_DAC_REG(dac), data);
198 mutex_unlock(&st->lock);
199
200 return ret;
201 }
202
ad5766_reset(struct ad5766_state * st)203 static int ad5766_reset(struct ad5766_state *st)
204 {
205 int ret;
206
207 if (st->gpio_reset) {
208 gpiod_set_value_cansleep(st->gpio_reset, 1);
209 ndelay(100); /* t_reset >= 100ns */
210 gpiod_set_value_cansleep(st->gpio_reset, 0);
211 } else {
212 ret = __ad5766_spi_write(st, AD5766_CMD_SW_FULL_RESET,
213 AD5766_FULL_RESET_CODE);
214 if (ret < 0)
215 return ret;
216 }
217
218 /*
219 * Minimum time between a reset and the subsequent successful write is
220 * typically 25 ns
221 */
222 ndelay(25);
223
224 return 0;
225 }
226
ad5766_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)227 static int ad5766_read_raw(struct iio_dev *indio_dev,
228 struct iio_chan_spec const *chan,
229 int *val,
230 int *val2,
231 long m)
232 {
233 struct ad5766_state *st = iio_priv(indio_dev);
234 int ret;
235
236 switch (m) {
237 case IIO_CHAN_INFO_RAW:
238 ret = ad5766_read(indio_dev, chan->address, val);
239 if (ret)
240 return ret;
241
242 return IIO_VAL_INT;
243 case IIO_CHAN_INFO_OFFSET:
244 *val = ad5766_span_tbl[st->crt_range].min;
245
246 return IIO_VAL_INT;
247 case IIO_CHAN_INFO_SCALE:
248 *val = ad5766_span_tbl[st->crt_range].max -
249 ad5766_span_tbl[st->crt_range].min;
250 *val2 = st->chip_info->channels[0].scan_type.realbits;
251
252 return IIO_VAL_FRACTIONAL_LOG2;
253 default:
254 return -EINVAL;
255 }
256 }
257
ad5766_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)258 static int ad5766_write_raw(struct iio_dev *indio_dev,
259 struct iio_chan_spec const *chan,
260 int val,
261 int val2,
262 long info)
263 {
264 switch (info) {
265 case IIO_CHAN_INFO_RAW:
266 {
267 const int max_val = GENMASK(chan->scan_type.realbits - 1, 0);
268
269 if (val > max_val || val < 0)
270 return -EINVAL;
271 val <<= chan->scan_type.shift;
272 return ad5766_write(indio_dev, chan->address, val);
273 }
274 default:
275 return -EINVAL;
276 }
277 }
278
279 static const struct iio_info ad5766_info = {
280 .read_raw = ad5766_read_raw,
281 .write_raw = ad5766_write_raw,
282 };
283
ad5766_get_dither_source(struct iio_dev * dev,const struct iio_chan_spec * chan)284 static int ad5766_get_dither_source(struct iio_dev *dev,
285 const struct iio_chan_spec *chan)
286 {
287 struct ad5766_state *st = iio_priv(dev);
288 u32 source;
289
290 source = st->dither_source & AD5766_DITHER_SOURCE_MASK(chan->channel);
291 source = source >> (chan->channel * 2);
292 source -= 1;
293
294 return source;
295 }
296
ad5766_set_dither_source(struct iio_dev * dev,const struct iio_chan_spec * chan,unsigned int source)297 static int ad5766_set_dither_source(struct iio_dev *dev,
298 const struct iio_chan_spec *chan,
299 unsigned int source)
300 {
301 struct ad5766_state *st = iio_priv(dev);
302 uint16_t val;
303 int ret;
304
305 st->dither_source &= ~AD5766_DITHER_SOURCE_MASK(chan->channel);
306 st->dither_source |= AD5766_DITHER_SOURCE(chan->channel, source);
307
308 val = FIELD_GET(AD5766_LOWER_WORD_SPI_MASK, st->dither_source);
309 ret = ad5766_write(dev, AD5766_CMD_DITHER_SIG_1, val);
310 if (ret)
311 return ret;
312
313 val = FIELD_GET(AD5766_UPPER_WORD_SPI_MASK, st->dither_source);
314
315 return ad5766_write(dev, AD5766_CMD_DITHER_SIG_2, val);
316 }
317
ad5766_get_dither_scale(struct iio_dev * dev,const struct iio_chan_spec * chan)318 static int ad5766_get_dither_scale(struct iio_dev *dev,
319 const struct iio_chan_spec *chan)
320 {
321 struct ad5766_state *st = iio_priv(dev);
322 u32 scale;
323
324 scale = st->dither_scale & AD5766_DITHER_SCALE_MASK(chan->channel);
325
326 return (scale >> (chan->channel * 2));
327 }
328
ad5766_set_dither_scale(struct iio_dev * dev,const struct iio_chan_spec * chan,unsigned int scale)329 static int ad5766_set_dither_scale(struct iio_dev *dev,
330 const struct iio_chan_spec *chan,
331 unsigned int scale)
332 {
333 int ret;
334 struct ad5766_state *st = iio_priv(dev);
335 uint16_t val;
336
337 st->dither_scale &= ~AD5766_DITHER_SCALE_MASK(chan->channel);
338 st->dither_scale |= AD5766_DITHER_SCALE(chan->channel, scale);
339
340 val = FIELD_GET(AD5766_LOWER_WORD_SPI_MASK, st->dither_scale);
341 ret = ad5766_write(dev, AD5766_CMD_DITHER_SCALE_1, val);
342 if (ret)
343 return ret;
344 val = FIELD_GET(AD5766_UPPER_WORD_SPI_MASK, st->dither_scale);
345
346 return ad5766_write(dev, AD5766_CMD_DITHER_SCALE_2, val);
347 }
348
349 static const struct iio_enum ad5766_dither_scale_enum = {
350 .items = ad5766_dither_scales,
351 .num_items = ARRAY_SIZE(ad5766_dither_scales),
352 .set = ad5766_set_dither_scale,
353 .get = ad5766_get_dither_scale,
354 };
355
ad5766_read_ext(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * chan,char * buf)356 static ssize_t ad5766_read_ext(struct iio_dev *indio_dev,
357 uintptr_t private,
358 const struct iio_chan_spec *chan,
359 char *buf)
360 {
361 struct ad5766_state *st = iio_priv(indio_dev);
362
363 switch (private) {
364 case AD5766_DITHER_ENABLE:
365 return sprintf(buf, "%u\n",
366 !(st->dither_enable & BIT(chan->channel)));
367 break;
368 case AD5766_DITHER_INVERT:
369 return sprintf(buf, "%u\n",
370 !!(st->dither_invert & BIT(chan->channel)));
371 break;
372 case AD5766_DITHER_SOURCE:
373 return sprintf(buf, "%d\n",
374 ad5766_get_dither_source(indio_dev, chan));
375 default:
376 return -EINVAL;
377 }
378 }
379
ad5766_write_ext(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * chan,const char * buf,size_t len)380 static ssize_t ad5766_write_ext(struct iio_dev *indio_dev,
381 uintptr_t private,
382 const struct iio_chan_spec *chan,
383 const char *buf, size_t len)
384 {
385 struct ad5766_state *st = iio_priv(indio_dev);
386 bool readin;
387 int ret;
388
389 ret = kstrtobool(buf, &readin);
390 if (ret)
391 return ret;
392
393 switch (private) {
394 case AD5766_DITHER_ENABLE:
395 st->dither_enable &= ~AD5766_DITHER_ENABLE_MASK(chan->channel);
396 st->dither_enable |= AD5766_DITHER_ENABLE(chan->channel,
397 readin);
398 ret = ad5766_write(indio_dev, AD5766_CMD_WR_PWR_DITHER,
399 st->dither_enable);
400 break;
401 case AD5766_DITHER_INVERT:
402 st->dither_invert &= ~AD5766_DITHER_INVERT_MASK(chan->channel);
403 st->dither_invert |= AD5766_DITHER_INVERT(chan->channel,
404 readin);
405 ret = ad5766_write(indio_dev, AD5766_CMD_INV_DITHER,
406 st->dither_invert);
407 break;
408 case AD5766_DITHER_SOURCE:
409 ret = ad5766_set_dither_source(indio_dev, chan, readin);
410 break;
411 default:
412 return -EINVAL;
413 }
414
415 return ret ? ret : len;
416 }
417
418 #define _AD5766_CHAN_EXT_INFO(_name, _what, _shared) { \
419 .name = _name, \
420 .read = ad5766_read_ext, \
421 .write = ad5766_write_ext, \
422 .private = _what, \
423 .shared = _shared, \
424 }
425
426 #define IIO_ENUM_AVAILABLE_SHARED(_name, _shared, _e) \
427 { \
428 .name = (_name "_available"), \
429 .shared = _shared, \
430 .read = iio_enum_available_read, \
431 .private = (uintptr_t)(_e), \
432 }
433
434 static const struct iio_chan_spec_ext_info ad5766_ext_info[] = {
435
436 _AD5766_CHAN_EXT_INFO("dither_enable", AD5766_DITHER_ENABLE,
437 IIO_SEPARATE),
438 _AD5766_CHAN_EXT_INFO("dither_invert", AD5766_DITHER_INVERT,
439 IIO_SEPARATE),
440 _AD5766_CHAN_EXT_INFO("dither_source", AD5766_DITHER_SOURCE,
441 IIO_SEPARATE),
442 IIO_ENUM("dither_scale", IIO_SEPARATE, &ad5766_dither_scale_enum),
443 IIO_ENUM_AVAILABLE_SHARED("dither_scale",
444 IIO_SEPARATE,
445 &ad5766_dither_scale_enum),
446 {}
447 };
448
449 #define AD576x_CHANNEL(_chan, _bits) { \
450 .type = IIO_VOLTAGE, \
451 .indexed = 1, \
452 .output = 1, \
453 .channel = (_chan), \
454 .address = (_chan), \
455 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
456 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | \
457 BIT(IIO_CHAN_INFO_SCALE), \
458 .scan_type = { \
459 .sign = 'u', \
460 .realbits = (_bits), \
461 .storagebits = 16, \
462 .shift = 16 - (_bits), \
463 }, \
464 .ext_info = ad5766_ext_info, \
465 }
466
467 #define DECLARE_AD576x_CHANNELS(_name, _bits) \
468 const struct iio_chan_spec _name[] = { \
469 AD576x_CHANNEL(0, (_bits)), \
470 AD576x_CHANNEL(1, (_bits)), \
471 AD576x_CHANNEL(2, (_bits)), \
472 AD576x_CHANNEL(3, (_bits)), \
473 AD576x_CHANNEL(4, (_bits)), \
474 AD576x_CHANNEL(5, (_bits)), \
475 AD576x_CHANNEL(6, (_bits)), \
476 AD576x_CHANNEL(7, (_bits)), \
477 AD576x_CHANNEL(8, (_bits)), \
478 AD576x_CHANNEL(9, (_bits)), \
479 AD576x_CHANNEL(10, (_bits)), \
480 AD576x_CHANNEL(11, (_bits)), \
481 AD576x_CHANNEL(12, (_bits)), \
482 AD576x_CHANNEL(13, (_bits)), \
483 AD576x_CHANNEL(14, (_bits)), \
484 AD576x_CHANNEL(15, (_bits)), \
485 }
486
487 static DECLARE_AD576x_CHANNELS(ad5766_channels, 16);
488 static DECLARE_AD576x_CHANNELS(ad5767_channels, 12);
489
490 static const struct ad5766_chip_info ad5766_chip_infos[] = {
491 [ID_AD5766] = {
492 .num_channels = ARRAY_SIZE(ad5766_channels),
493 .channels = ad5766_channels,
494 },
495 [ID_AD5767] = {
496 .num_channels = ARRAY_SIZE(ad5767_channels),
497 .channels = ad5767_channels,
498 },
499 };
500
ad5766_get_output_range(struct ad5766_state * st)501 static int ad5766_get_output_range(struct ad5766_state *st)
502 {
503 int i, ret, min, max, tmp[2];
504
505 ret = device_property_read_u32_array(&st->spi->dev,
506 "output-range-voltage",
507 tmp, 2);
508 if (ret)
509 return ret;
510
511 min = tmp[0] / 1000;
512 max = tmp[1] / 1000;
513 for (i = 0; i < ARRAY_SIZE(ad5766_span_tbl); i++) {
514 if (ad5766_span_tbl[i].min != min ||
515 ad5766_span_tbl[i].max != max)
516 continue;
517
518 st->crt_range = i;
519
520 return 0;
521 }
522
523 return -EINVAL;
524 }
525
ad5766_default_setup(struct ad5766_state * st)526 static int ad5766_default_setup(struct ad5766_state *st)
527 {
528 uint16_t val;
529 int ret, i;
530
531 /* Always issue a reset before writing to the span register. */
532 ret = ad5766_reset(st);
533 if (ret)
534 return ret;
535
536 ret = ad5766_get_output_range(st);
537 if (ret)
538 return ret;
539
540 /* Dither power down */
541 st->dither_enable = GENMASK(15, 0);
542 ret = __ad5766_spi_write(st, AD5766_CMD_WR_PWR_DITHER,
543 st->dither_enable);
544 if (ret)
545 return ret;
546
547 st->dither_source = 0;
548 for (i = 0; i < ARRAY_SIZE(ad5766_channels); i++)
549 st->dither_source |= AD5766_DITHER_SOURCE(i, 0);
550 val = FIELD_GET(AD5766_LOWER_WORD_SPI_MASK, st->dither_source);
551 ret = __ad5766_spi_write(st, AD5766_CMD_DITHER_SIG_1, val);
552 if (ret)
553 return ret;
554
555 val = FIELD_GET(AD5766_UPPER_WORD_SPI_MASK, st->dither_source);
556 ret = __ad5766_spi_write(st, AD5766_CMD_DITHER_SIG_2, val);
557 if (ret)
558 return ret;
559
560 st->dither_scale = 0;
561 val = FIELD_GET(AD5766_LOWER_WORD_SPI_MASK, st->dither_scale);
562 ret = __ad5766_spi_write(st, AD5766_CMD_DITHER_SCALE_1, val);
563 if (ret)
564 return ret;
565
566 val = FIELD_GET(AD5766_UPPER_WORD_SPI_MASK, st->dither_scale);
567 ret = __ad5766_spi_write(st, AD5766_CMD_DITHER_SCALE_2, val);
568 if (ret)
569 return ret;
570
571 st->dither_invert = 0;
572 ret = __ad5766_spi_write(st, AD5766_CMD_INV_DITHER, st->dither_invert);
573 if (ret)
574 return ret;
575
576 return __ad5766_spi_write(st, AD5766_CMD_SPAN_REG, st->crt_range);
577 }
578
ad5766_probe(struct spi_device * spi)579 static int ad5766_probe(struct spi_device *spi)
580 {
581 enum ad5766_type type;
582 struct iio_dev *indio_dev;
583 struct ad5766_state *st;
584 int ret;
585
586 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
587 if (!indio_dev)
588 return -ENOMEM;
589
590 st = iio_priv(indio_dev);
591 mutex_init(&st->lock);
592
593 st->spi = spi;
594 type = spi_get_device_id(spi)->driver_data;
595 st->chip_info = &ad5766_chip_infos[type];
596
597 indio_dev->channels = st->chip_info->channels;
598 indio_dev->num_channels = st->chip_info->num_channels;
599 indio_dev->info = &ad5766_info;
600 indio_dev->dev.parent = &spi->dev;
601 indio_dev->dev.of_node = spi->dev.of_node;
602 indio_dev->name = spi_get_device_id(spi)->name;
603 indio_dev->modes = INDIO_DIRECT_MODE;
604
605 st->gpio_reset = devm_gpiod_get_optional(&st->spi->dev, "reset",
606 GPIOD_OUT_LOW);
607 if (IS_ERR(st->gpio_reset))
608 return PTR_ERR(st->gpio_reset);
609
610 ret = ad5766_default_setup(st);
611 if (ret)
612 return ret;
613
614 return devm_iio_device_register(&spi->dev, indio_dev);
615 }
616
617 static const struct of_device_id ad5766_dt_match[] = {
618 { .compatible = "adi,ad5766" },
619 { .compatible = "adi,ad5767" },
620 {}
621 };
622 MODULE_DEVICE_TABLE(of, ad5766_dt_match);
623
624 static const struct spi_device_id ad5766_spi_ids[] = {
625 { "ad5766", ID_AD5766 },
626 { "ad5767", ID_AD5767 },
627 {}
628 };
629 MODULE_DEVICE_TABLE(spi, ad5766_spi_ids);
630
631 static struct spi_driver ad5766_driver = {
632 .driver = {
633 .name = "ad5766",
634 .of_match_table = ad5766_dt_match,
635 },
636 .probe = ad5766_probe,
637 .id_table = ad5766_spi_ids,
638 };
639 module_spi_driver(ad5766_driver);
640
641 MODULE_AUTHOR("Denis-Gabriel Gheorghescu <denis.gheorghescu@analog.com>");
642 MODULE_DESCRIPTION("Analog Devices AD5766/AD5767 DACs");
643 MODULE_LICENSE("GPL v2");
644