1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (c) 2019 Pengutronix, Oleksij Rempel <kernel@pengutronix.de>
3 /*
4 * +----------------------+
5 * GMAC1----RGMII----|--MAC0 |
6 * \---MDIO1----|--REGs |----MDIO3----\
7 * | | | +------+
8 * | | +--| |
9 * | MAC1-|----RMII--M-----| PHY0 |-o P0
10 * | | | | +------+
11 * | | | +--| |
12 * | MAC2-|----RMII--------| PHY1 |-o P1
13 * | | | | +------+
14 * | | | +--| |
15 * | MAC3-|----RMII--------| PHY2 |-o P2
16 * | | | | +------+
17 * | | | +--| |
18 * | MAC4-|----RMII--------| PHY3 |-o P3
19 * | | | | +------+
20 * | | | +--| |
21 * | MAC5-|--+-RMII--M-----|-PHY4-|-o P4
22 * | | | | +------+
23 * +----------------------+ | \--CFG_SW_PHY_SWAP
24 * GMAC0---------------RMII--------------------/ \-CFG_SW_PHY_ADDR_SWAP
25 * \---MDIO0--NC
26 *
27 * GMAC0 and MAC5 are connected together and use same PHY. Depending on
28 * configuration it can be PHY4 (default) or PHY0. Only GMAC0 or MAC5 can be
29 * used at same time. If GMAC0 is used (default) then MAC5 should be disabled.
30 *
31 * CFG_SW_PHY_SWAP - swap connections of PHY0 and PHY4. If this bit is not set
32 * PHY4 is connected to GMAC0/MAC5 bundle and PHY0 is connected to MAC1. If this
33 * bit is set, PHY4 is connected to MAC1 and PHY0 is connected to GMAC0/MAC5
34 * bundle.
35 *
36 * CFG_SW_PHY_ADDR_SWAP - swap addresses of PHY0 and PHY4
37 *
38 * CFG_SW_PHY_SWAP and CFG_SW_PHY_ADDR_SWAP are part of SoC specific register
39 * set and not related to switch internal registers.
40 */
41
42 #include <linux/bitfield.h>
43 #include <linux/module.h>
44 #include <linux/of_irq.h>
45 #include <linux/of_mdio.h>
46 #include <linux/regmap.h>
47 #include <linux/reset.h>
48 #include <net/dsa.h>
49
50 #define AR9331_SW_NAME "ar9331_switch"
51 #define AR9331_SW_PORTS 6
52
53 /* dummy reg to change page */
54 #define AR9331_SW_REG_PAGE 0x40000
55
56 /* Global Interrupt */
57 #define AR9331_SW_REG_GINT 0x10
58 #define AR9331_SW_REG_GINT_MASK 0x14
59 #define AR9331_SW_GINT_PHY_INT BIT(2)
60
61 #define AR9331_SW_REG_FLOOD_MASK 0x2c
62 #define AR9331_SW_FLOOD_MASK_BROAD_TO_CPU BIT(26)
63
64 #define AR9331_SW_REG_GLOBAL_CTRL 0x30
65 #define AR9331_SW_GLOBAL_CTRL_MFS_M GENMASK(13, 0)
66
67 #define AR9331_SW_REG_MDIO_CTRL 0x98
68 #define AR9331_SW_MDIO_CTRL_BUSY BIT(31)
69 #define AR9331_SW_MDIO_CTRL_MASTER_EN BIT(30)
70 #define AR9331_SW_MDIO_CTRL_CMD_READ BIT(27)
71 #define AR9331_SW_MDIO_CTRL_PHY_ADDR_M GENMASK(25, 21)
72 #define AR9331_SW_MDIO_CTRL_REG_ADDR_M GENMASK(20, 16)
73 #define AR9331_SW_MDIO_CTRL_DATA_M GENMASK(16, 0)
74
75 #define AR9331_SW_REG_PORT_STATUS(_port) (0x100 + (_port) * 0x100)
76
77 /* FLOW_LINK_EN - enable mac flow control config auto-neg with phy.
78 * If not set, mac can be config by software.
79 */
80 #define AR9331_SW_PORT_STATUS_FLOW_LINK_EN BIT(12)
81
82 /* LINK_EN - If set, MAC is configured from PHY link status.
83 * If not set, MAC should be configured by software.
84 */
85 #define AR9331_SW_PORT_STATUS_LINK_EN BIT(9)
86 #define AR9331_SW_PORT_STATUS_DUPLEX_MODE BIT(6)
87 #define AR9331_SW_PORT_STATUS_RX_FLOW_EN BIT(5)
88 #define AR9331_SW_PORT_STATUS_TX_FLOW_EN BIT(4)
89 #define AR9331_SW_PORT_STATUS_RXMAC BIT(3)
90 #define AR9331_SW_PORT_STATUS_TXMAC BIT(2)
91 #define AR9331_SW_PORT_STATUS_SPEED_M GENMASK(1, 0)
92 #define AR9331_SW_PORT_STATUS_SPEED_1000 2
93 #define AR9331_SW_PORT_STATUS_SPEED_100 1
94 #define AR9331_SW_PORT_STATUS_SPEED_10 0
95
96 #define AR9331_SW_PORT_STATUS_MAC_MASK \
97 (AR9331_SW_PORT_STATUS_TXMAC | AR9331_SW_PORT_STATUS_RXMAC)
98
99 #define AR9331_SW_PORT_STATUS_LINK_MASK \
100 (AR9331_SW_PORT_STATUS_DUPLEX_MODE | \
101 AR9331_SW_PORT_STATUS_RX_FLOW_EN | AR9331_SW_PORT_STATUS_TX_FLOW_EN | \
102 AR9331_SW_PORT_STATUS_SPEED_M)
103
104 /* MIB registers */
105 #define AR9331_MIB_COUNTER(x) (0x20000 + ((x) * 0x100))
106
107 /* Phy bypass mode
108 * ------------------------------------------------------------------------
109 * Bit: | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |10 |11 |12 |13 |14 |15 |
110 *
111 * real | start | OP | PhyAddr | Reg Addr | TA |
112 * atheros| start | OP | 2'b00 |PhyAdd[2:0]| Reg Addr[4:0] | TA |
113 *
114 *
115 * Bit: |16 |17 |18 |19 |20 |21 |22 |23 |24 |25 |26 |27 |28 |29 |30 |31 |
116 * real | Data |
117 * atheros| Data |
118 *
119 * ------------------------------------------------------------------------
120 * Page address mode
121 * ------------------------------------------------------------------------
122 * Bit: | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |10 |11 |12 |13 |14 |15 |
123 * real | start | OP | PhyAddr | Reg Addr | TA |
124 * atheros| start | OP | 2'b11 | 8'b0 | TA |
125 *
126 * Bit: |16 |17 |18 |19 |20 |21 |22 |23 |24 |25 |26 |27 |28 |29 |30 |31 |
127 * real | Data |
128 * atheros| | Page [9:0] |
129 */
130 /* In case of Page Address mode, Bit[18:9] of 32 bit register address should be
131 * written to bits[9:0] of mdio data register.
132 */
133 #define AR9331_SW_ADDR_PAGE GENMASK(18, 9)
134
135 /* ------------------------------------------------------------------------
136 * Normal register access mode
137 * ------------------------------------------------------------------------
138 * Bit: | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |10 |11 |12 |13 |14 |15 |
139 * real | start | OP | PhyAddr | Reg Addr | TA |
140 * atheros| start | OP | 2'b10 | low_addr[7:0] | TA |
141 *
142 * Bit: |16 |17 |18 |19 |20 |21 |22 |23 |24 |25 |26 |27 |28 |29 |30 |31 |
143 * real | Data |
144 * atheros| Data |
145 * ------------------------------------------------------------------------
146 */
147 #define AR9331_SW_LOW_ADDR_PHY GENMASK(8, 6)
148 #define AR9331_SW_LOW_ADDR_REG GENMASK(5, 1)
149
150 #define AR9331_SW_MDIO_PHY_MODE_M GENMASK(4, 3)
151 #define AR9331_SW_MDIO_PHY_MODE_PAGE 3
152 #define AR9331_SW_MDIO_PHY_MODE_REG 2
153 #define AR9331_SW_MDIO_PHY_MODE_BYPASS 0
154 #define AR9331_SW_MDIO_PHY_ADDR_M GENMASK(2, 0)
155
156 /* Empirical determined values */
157 #define AR9331_SW_MDIO_POLL_SLEEP_US 1
158 #define AR9331_SW_MDIO_POLL_TIMEOUT_US 20
159
160 /* The interval should be small enough to avoid overflow of 32bit MIBs */
161 /*
162 * FIXME: until we can read MIBs from stats64 call directly (i.e. sleep
163 * there), we have to poll stats more frequently then it is actually needed.
164 * For overflow protection, normally, 100 sec interval should have been OK.
165 */
166 #define STATS_INTERVAL_JIFFIES (3 * HZ)
167
168 struct ar9331_sw_stats_raw {
169 u32 rxbroad; /* 0x00 */
170 u32 rxpause; /* 0x04 */
171 u32 rxmulti; /* 0x08 */
172 u32 rxfcserr; /* 0x0c */
173 u32 rxalignerr; /* 0x10 */
174 u32 rxrunt; /* 0x14 */
175 u32 rxfragment; /* 0x18 */
176 u32 rx64byte; /* 0x1c */
177 u32 rx128byte; /* 0x20 */
178 u32 rx256byte; /* 0x24 */
179 u32 rx512byte; /* 0x28 */
180 u32 rx1024byte; /* 0x2c */
181 u32 rx1518byte; /* 0x30 */
182 u32 rxmaxbyte; /* 0x34 */
183 u32 rxtoolong; /* 0x38 */
184 u32 rxgoodbyte; /* 0x3c */
185 u32 rxgoodbyte_hi;
186 u32 rxbadbyte; /* 0x44 */
187 u32 rxbadbyte_hi;
188 u32 rxoverflow; /* 0x4c */
189 u32 filtered; /* 0x50 */
190 u32 txbroad; /* 0x54 */
191 u32 txpause; /* 0x58 */
192 u32 txmulti; /* 0x5c */
193 u32 txunderrun; /* 0x60 */
194 u32 tx64byte; /* 0x64 */
195 u32 tx128byte; /* 0x68 */
196 u32 tx256byte; /* 0x6c */
197 u32 tx512byte; /* 0x70 */
198 u32 tx1024byte; /* 0x74 */
199 u32 tx1518byte; /* 0x78 */
200 u32 txmaxbyte; /* 0x7c */
201 u32 txoversize; /* 0x80 */
202 u32 txbyte; /* 0x84 */
203 u32 txbyte_hi;
204 u32 txcollision; /* 0x8c */
205 u32 txabortcol; /* 0x90 */
206 u32 txmulticol; /* 0x94 */
207 u32 txsinglecol; /* 0x98 */
208 u32 txexcdefer; /* 0x9c */
209 u32 txdefer; /* 0xa0 */
210 u32 txlatecol; /* 0xa4 */
211 };
212
213 struct ar9331_sw_port {
214 int idx;
215 struct delayed_work mib_read;
216 struct rtnl_link_stats64 stats;
217 struct spinlock stats_lock;
218 };
219
220 struct ar9331_sw_priv {
221 struct device *dev;
222 struct dsa_switch ds;
223 struct dsa_switch_ops ops;
224 struct irq_domain *irqdomain;
225 u32 irq_mask;
226 struct mutex lock_irq;
227 struct mii_bus *mbus; /* mdio master */
228 struct mii_bus *sbus; /* mdio slave */
229 struct regmap *regmap;
230 struct reset_control *sw_reset;
231 struct ar9331_sw_port port[AR9331_SW_PORTS];
232 };
233
ar9331_sw_port_to_priv(struct ar9331_sw_port * port)234 static struct ar9331_sw_priv *ar9331_sw_port_to_priv(struct ar9331_sw_port *port)
235 {
236 struct ar9331_sw_port *p = port - port->idx;
237
238 return (struct ar9331_sw_priv *)((void *)p -
239 offsetof(struct ar9331_sw_priv, port));
240 }
241
242 /* Warning: switch reset will reset last AR9331_SW_MDIO_PHY_MODE_PAGE request
243 * If some kind of optimization is used, the request should be repeated.
244 */
ar9331_sw_reset(struct ar9331_sw_priv * priv)245 static int ar9331_sw_reset(struct ar9331_sw_priv *priv)
246 {
247 int ret;
248
249 ret = reset_control_assert(priv->sw_reset);
250 if (ret)
251 goto error;
252
253 /* AR9331 doc do not provide any information about proper reset
254 * sequence. The AR8136 (the closes switch to the AR9331) doc says:
255 * reset duration should be greater than 10ms. So, let's use this value
256 * for now.
257 */
258 usleep_range(10000, 15000);
259 ret = reset_control_deassert(priv->sw_reset);
260 if (ret)
261 goto error;
262 /* There is no information on how long should we wait after reset.
263 * AR8136 has an EEPROM and there is an Interrupt for EEPROM load
264 * status. AR9331 has no EEPROM support.
265 * For now, do not wait. In case AR8136 will be needed, the after
266 * reset delay can be added as well.
267 */
268
269 return 0;
270 error:
271 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
272 return ret;
273 }
274
ar9331_sw_mbus_write(struct mii_bus * mbus,int port,int regnum,u16 data)275 static int ar9331_sw_mbus_write(struct mii_bus *mbus, int port, int regnum,
276 u16 data)
277 {
278 struct ar9331_sw_priv *priv = mbus->priv;
279 struct regmap *regmap = priv->regmap;
280 u32 val;
281 int ret;
282
283 ret = regmap_write(regmap, AR9331_SW_REG_MDIO_CTRL,
284 AR9331_SW_MDIO_CTRL_BUSY |
285 AR9331_SW_MDIO_CTRL_MASTER_EN |
286 FIELD_PREP(AR9331_SW_MDIO_CTRL_PHY_ADDR_M, port) |
287 FIELD_PREP(AR9331_SW_MDIO_CTRL_REG_ADDR_M, regnum) |
288 FIELD_PREP(AR9331_SW_MDIO_CTRL_DATA_M, data));
289 if (ret)
290 goto error;
291
292 ret = regmap_read_poll_timeout(regmap, AR9331_SW_REG_MDIO_CTRL, val,
293 !(val & AR9331_SW_MDIO_CTRL_BUSY),
294 AR9331_SW_MDIO_POLL_SLEEP_US,
295 AR9331_SW_MDIO_POLL_TIMEOUT_US);
296 if (ret)
297 goto error;
298
299 return 0;
300 error:
301 dev_err_ratelimited(priv->dev, "PHY write error: %i\n", ret);
302 return ret;
303 }
304
ar9331_sw_mbus_read(struct mii_bus * mbus,int port,int regnum)305 static int ar9331_sw_mbus_read(struct mii_bus *mbus, int port, int regnum)
306 {
307 struct ar9331_sw_priv *priv = mbus->priv;
308 struct regmap *regmap = priv->regmap;
309 u32 val;
310 int ret;
311
312 ret = regmap_write(regmap, AR9331_SW_REG_MDIO_CTRL,
313 AR9331_SW_MDIO_CTRL_BUSY |
314 AR9331_SW_MDIO_CTRL_MASTER_EN |
315 AR9331_SW_MDIO_CTRL_CMD_READ |
316 FIELD_PREP(AR9331_SW_MDIO_CTRL_PHY_ADDR_M, port) |
317 FIELD_PREP(AR9331_SW_MDIO_CTRL_REG_ADDR_M, regnum));
318 if (ret)
319 goto error;
320
321 ret = regmap_read_poll_timeout(regmap, AR9331_SW_REG_MDIO_CTRL, val,
322 !(val & AR9331_SW_MDIO_CTRL_BUSY),
323 AR9331_SW_MDIO_POLL_SLEEP_US,
324 AR9331_SW_MDIO_POLL_TIMEOUT_US);
325 if (ret)
326 goto error;
327
328 ret = regmap_read(regmap, AR9331_SW_REG_MDIO_CTRL, &val);
329 if (ret)
330 goto error;
331
332 return FIELD_GET(AR9331_SW_MDIO_CTRL_DATA_M, val);
333
334 error:
335 dev_err_ratelimited(priv->dev, "PHY read error: %i\n", ret);
336 return ret;
337 }
338
ar9331_sw_mbus_init(struct ar9331_sw_priv * priv)339 static int ar9331_sw_mbus_init(struct ar9331_sw_priv *priv)
340 {
341 struct device *dev = priv->dev;
342 struct mii_bus *mbus;
343 struct device_node *np, *mnp;
344 int ret;
345
346 np = dev->of_node;
347
348 mbus = devm_mdiobus_alloc(dev);
349 if (!mbus)
350 return -ENOMEM;
351
352 mbus->name = np->full_name;
353 snprintf(mbus->id, MII_BUS_ID_SIZE, "%pOF", np);
354
355 mbus->read = ar9331_sw_mbus_read;
356 mbus->write = ar9331_sw_mbus_write;
357 mbus->priv = priv;
358 mbus->parent = dev;
359
360 mnp = of_get_child_by_name(np, "mdio");
361 if (!mnp)
362 return -ENODEV;
363
364 ret = of_mdiobus_register(mbus, mnp);
365 of_node_put(mnp);
366 if (ret)
367 return ret;
368
369 priv->mbus = mbus;
370
371 return 0;
372 }
373
ar9331_sw_setup(struct dsa_switch * ds)374 static int ar9331_sw_setup(struct dsa_switch *ds)
375 {
376 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv;
377 struct regmap *regmap = priv->regmap;
378 int ret;
379
380 ret = ar9331_sw_reset(priv);
381 if (ret)
382 return ret;
383
384 /* Reset will set proper defaults. CPU - Port0 will be enabled and
385 * configured. All other ports (ports 1 - 5) are disabled
386 */
387 ret = ar9331_sw_mbus_init(priv);
388 if (ret)
389 return ret;
390
391 /* Do not drop broadcast frames */
392 ret = regmap_write_bits(regmap, AR9331_SW_REG_FLOOD_MASK,
393 AR9331_SW_FLOOD_MASK_BROAD_TO_CPU,
394 AR9331_SW_FLOOD_MASK_BROAD_TO_CPU);
395 if (ret)
396 goto error;
397
398 /* Set max frame size to the maximum supported value */
399 ret = regmap_write_bits(regmap, AR9331_SW_REG_GLOBAL_CTRL,
400 AR9331_SW_GLOBAL_CTRL_MFS_M,
401 AR9331_SW_GLOBAL_CTRL_MFS_M);
402 if (ret)
403 goto error;
404
405 ds->configure_vlan_while_not_filtering = false;
406
407 return 0;
408 error:
409 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
410 return ret;
411 }
412
ar9331_sw_port_disable(struct dsa_switch * ds,int port)413 static void ar9331_sw_port_disable(struct dsa_switch *ds, int port)
414 {
415 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv;
416 struct regmap *regmap = priv->regmap;
417 int ret;
418
419 ret = regmap_write(regmap, AR9331_SW_REG_PORT_STATUS(port), 0);
420 if (ret)
421 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
422 }
423
ar9331_sw_get_tag_protocol(struct dsa_switch * ds,int port,enum dsa_tag_protocol m)424 static enum dsa_tag_protocol ar9331_sw_get_tag_protocol(struct dsa_switch *ds,
425 int port,
426 enum dsa_tag_protocol m)
427 {
428 return DSA_TAG_PROTO_AR9331;
429 }
430
ar9331_sw_phylink_validate(struct dsa_switch * ds,int port,unsigned long * supported,struct phylink_link_state * state)431 static void ar9331_sw_phylink_validate(struct dsa_switch *ds, int port,
432 unsigned long *supported,
433 struct phylink_link_state *state)
434 {
435 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
436
437 switch (port) {
438 case 0:
439 if (state->interface != PHY_INTERFACE_MODE_GMII)
440 goto unsupported;
441
442 phylink_set(mask, 1000baseT_Full);
443 phylink_set(mask, 1000baseT_Half);
444 break;
445 case 1:
446 case 2:
447 case 3:
448 case 4:
449 case 5:
450 if (state->interface != PHY_INTERFACE_MODE_INTERNAL)
451 goto unsupported;
452 break;
453 default:
454 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
455 dev_err(ds->dev, "Unsupported port: %i\n", port);
456 return;
457 }
458
459 phylink_set_port_modes(mask);
460 phylink_set(mask, Pause);
461 phylink_set(mask, Asym_Pause);
462
463 phylink_set(mask, 10baseT_Half);
464 phylink_set(mask, 10baseT_Full);
465 phylink_set(mask, 100baseT_Half);
466 phylink_set(mask, 100baseT_Full);
467
468 bitmap_and(supported, supported, mask,
469 __ETHTOOL_LINK_MODE_MASK_NBITS);
470 bitmap_and(state->advertising, state->advertising, mask,
471 __ETHTOOL_LINK_MODE_MASK_NBITS);
472
473 return;
474
475 unsupported:
476 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
477 dev_err(ds->dev, "Unsupported interface: %d, port: %d\n",
478 state->interface, port);
479 }
480
ar9331_sw_phylink_mac_config(struct dsa_switch * ds,int port,unsigned int mode,const struct phylink_link_state * state)481 static void ar9331_sw_phylink_mac_config(struct dsa_switch *ds, int port,
482 unsigned int mode,
483 const struct phylink_link_state *state)
484 {
485 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv;
486 struct regmap *regmap = priv->regmap;
487 int ret;
488
489 ret = regmap_update_bits(regmap, AR9331_SW_REG_PORT_STATUS(port),
490 AR9331_SW_PORT_STATUS_LINK_EN |
491 AR9331_SW_PORT_STATUS_FLOW_LINK_EN, 0);
492 if (ret)
493 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
494 }
495
ar9331_sw_phylink_mac_link_down(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface)496 static void ar9331_sw_phylink_mac_link_down(struct dsa_switch *ds, int port,
497 unsigned int mode,
498 phy_interface_t interface)
499 {
500 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv;
501 struct ar9331_sw_port *p = &priv->port[port];
502 struct regmap *regmap = priv->regmap;
503 int ret;
504
505 ret = regmap_update_bits(regmap, AR9331_SW_REG_PORT_STATUS(port),
506 AR9331_SW_PORT_STATUS_MAC_MASK, 0);
507 if (ret)
508 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
509
510 cancel_delayed_work_sync(&p->mib_read);
511 }
512
ar9331_sw_phylink_mac_link_up(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface,struct phy_device * phydev,int speed,int duplex,bool tx_pause,bool rx_pause)513 static void ar9331_sw_phylink_mac_link_up(struct dsa_switch *ds, int port,
514 unsigned int mode,
515 phy_interface_t interface,
516 struct phy_device *phydev,
517 int speed, int duplex,
518 bool tx_pause, bool rx_pause)
519 {
520 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv;
521 struct ar9331_sw_port *p = &priv->port[port];
522 struct regmap *regmap = priv->regmap;
523 u32 val;
524 int ret;
525
526 schedule_delayed_work(&p->mib_read, 0);
527
528 val = AR9331_SW_PORT_STATUS_MAC_MASK;
529 switch (speed) {
530 case SPEED_1000:
531 val |= AR9331_SW_PORT_STATUS_SPEED_1000;
532 break;
533 case SPEED_100:
534 val |= AR9331_SW_PORT_STATUS_SPEED_100;
535 break;
536 case SPEED_10:
537 val |= AR9331_SW_PORT_STATUS_SPEED_10;
538 break;
539 default:
540 return;
541 }
542
543 if (duplex)
544 val |= AR9331_SW_PORT_STATUS_DUPLEX_MODE;
545
546 if (tx_pause)
547 val |= AR9331_SW_PORT_STATUS_TX_FLOW_EN;
548
549 if (rx_pause)
550 val |= AR9331_SW_PORT_STATUS_RX_FLOW_EN;
551
552 ret = regmap_update_bits(regmap, AR9331_SW_REG_PORT_STATUS(port),
553 AR9331_SW_PORT_STATUS_MAC_MASK |
554 AR9331_SW_PORT_STATUS_LINK_MASK,
555 val);
556 if (ret)
557 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
558 }
559
ar9331_read_stats(struct ar9331_sw_port * port)560 static void ar9331_read_stats(struct ar9331_sw_port *port)
561 {
562 struct ar9331_sw_priv *priv = ar9331_sw_port_to_priv(port);
563 struct rtnl_link_stats64 *stats = &port->stats;
564 struct ar9331_sw_stats_raw raw;
565 int ret;
566
567 /* Do the slowest part first, to avoid needless locking for long time */
568 ret = regmap_bulk_read(priv->regmap, AR9331_MIB_COUNTER(port->idx),
569 &raw, sizeof(raw) / sizeof(u32));
570 if (ret) {
571 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
572 return;
573 }
574 /* All MIB counters are cleared automatically on read */
575
576 spin_lock(&port->stats_lock);
577
578 stats->rx_bytes += raw.rxgoodbyte;
579 stats->tx_bytes += raw.txbyte;
580
581 stats->rx_packets += raw.rx64byte + raw.rx128byte + raw.rx256byte +
582 raw.rx512byte + raw.rx1024byte + raw.rx1518byte + raw.rxmaxbyte;
583 stats->tx_packets += raw.tx64byte + raw.tx128byte + raw.tx256byte +
584 raw.tx512byte + raw.tx1024byte + raw.tx1518byte + raw.txmaxbyte;
585
586 stats->rx_length_errors += raw.rxrunt + raw.rxfragment + raw.rxtoolong;
587 stats->rx_crc_errors += raw.rxfcserr;
588 stats->rx_frame_errors += raw.rxalignerr;
589 stats->rx_missed_errors += raw.rxoverflow;
590 stats->rx_dropped += raw.filtered;
591 stats->rx_errors += raw.rxfcserr + raw.rxalignerr + raw.rxrunt +
592 raw.rxfragment + raw.rxoverflow + raw.rxtoolong;
593
594 stats->tx_window_errors += raw.txlatecol;
595 stats->tx_fifo_errors += raw.txunderrun;
596 stats->tx_aborted_errors += raw.txabortcol;
597 stats->tx_errors += raw.txoversize + raw.txabortcol + raw.txunderrun +
598 raw.txlatecol;
599
600 stats->multicast += raw.rxmulti;
601 stats->collisions += raw.txcollision;
602
603 spin_unlock(&port->stats_lock);
604 }
605
ar9331_do_stats_poll(struct work_struct * work)606 static void ar9331_do_stats_poll(struct work_struct *work)
607 {
608 struct ar9331_sw_port *port = container_of(work, struct ar9331_sw_port,
609 mib_read.work);
610
611 ar9331_read_stats(port);
612
613 schedule_delayed_work(&port->mib_read, STATS_INTERVAL_JIFFIES);
614 }
615
ar9331_get_stats64(struct dsa_switch * ds,int port,struct rtnl_link_stats64 * s)616 static void ar9331_get_stats64(struct dsa_switch *ds, int port,
617 struct rtnl_link_stats64 *s)
618 {
619 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv;
620 struct ar9331_sw_port *p = &priv->port[port];
621
622 spin_lock(&p->stats_lock);
623 memcpy(s, &p->stats, sizeof(*s));
624 spin_unlock(&p->stats_lock);
625 }
626
627 static const struct dsa_switch_ops ar9331_sw_ops = {
628 .get_tag_protocol = ar9331_sw_get_tag_protocol,
629 .setup = ar9331_sw_setup,
630 .port_disable = ar9331_sw_port_disable,
631 .phylink_validate = ar9331_sw_phylink_validate,
632 .phylink_mac_config = ar9331_sw_phylink_mac_config,
633 .phylink_mac_link_down = ar9331_sw_phylink_mac_link_down,
634 .phylink_mac_link_up = ar9331_sw_phylink_mac_link_up,
635 .get_stats64 = ar9331_get_stats64,
636 };
637
ar9331_sw_irq(int irq,void * data)638 static irqreturn_t ar9331_sw_irq(int irq, void *data)
639 {
640 struct ar9331_sw_priv *priv = data;
641 struct regmap *regmap = priv->regmap;
642 u32 stat;
643 int ret;
644
645 ret = regmap_read(regmap, AR9331_SW_REG_GINT, &stat);
646 if (ret) {
647 dev_err(priv->dev, "can't read interrupt status\n");
648 return IRQ_NONE;
649 }
650
651 if (!stat)
652 return IRQ_NONE;
653
654 if (stat & AR9331_SW_GINT_PHY_INT) {
655 int child_irq;
656
657 child_irq = irq_find_mapping(priv->irqdomain, 0);
658 handle_nested_irq(child_irq);
659 }
660
661 ret = regmap_write(regmap, AR9331_SW_REG_GINT, stat);
662 if (ret) {
663 dev_err(priv->dev, "can't write interrupt status\n");
664 return IRQ_NONE;
665 }
666
667 return IRQ_HANDLED;
668 }
669
ar9331_sw_mask_irq(struct irq_data * d)670 static void ar9331_sw_mask_irq(struct irq_data *d)
671 {
672 struct ar9331_sw_priv *priv = irq_data_get_irq_chip_data(d);
673
674 priv->irq_mask = 0;
675 }
676
ar9331_sw_unmask_irq(struct irq_data * d)677 static void ar9331_sw_unmask_irq(struct irq_data *d)
678 {
679 struct ar9331_sw_priv *priv = irq_data_get_irq_chip_data(d);
680
681 priv->irq_mask = AR9331_SW_GINT_PHY_INT;
682 }
683
ar9331_sw_irq_bus_lock(struct irq_data * d)684 static void ar9331_sw_irq_bus_lock(struct irq_data *d)
685 {
686 struct ar9331_sw_priv *priv = irq_data_get_irq_chip_data(d);
687
688 mutex_lock(&priv->lock_irq);
689 }
690
ar9331_sw_irq_bus_sync_unlock(struct irq_data * d)691 static void ar9331_sw_irq_bus_sync_unlock(struct irq_data *d)
692 {
693 struct ar9331_sw_priv *priv = irq_data_get_irq_chip_data(d);
694 struct regmap *regmap = priv->regmap;
695 int ret;
696
697 ret = regmap_update_bits(regmap, AR9331_SW_REG_GINT_MASK,
698 AR9331_SW_GINT_PHY_INT, priv->irq_mask);
699 if (ret)
700 dev_err(priv->dev, "failed to change IRQ mask\n");
701
702 mutex_unlock(&priv->lock_irq);
703 }
704
705 static struct irq_chip ar9331_sw_irq_chip = {
706 .name = AR9331_SW_NAME,
707 .irq_mask = ar9331_sw_mask_irq,
708 .irq_unmask = ar9331_sw_unmask_irq,
709 .irq_bus_lock = ar9331_sw_irq_bus_lock,
710 .irq_bus_sync_unlock = ar9331_sw_irq_bus_sync_unlock,
711 };
712
ar9331_sw_irq_map(struct irq_domain * domain,unsigned int irq,irq_hw_number_t hwirq)713 static int ar9331_sw_irq_map(struct irq_domain *domain, unsigned int irq,
714 irq_hw_number_t hwirq)
715 {
716 irq_set_chip_data(irq, domain->host_data);
717 irq_set_chip_and_handler(irq, &ar9331_sw_irq_chip, handle_simple_irq);
718 irq_set_nested_thread(irq, 1);
719 irq_set_noprobe(irq);
720
721 return 0;
722 }
723
ar9331_sw_irq_unmap(struct irq_domain * d,unsigned int irq)724 static void ar9331_sw_irq_unmap(struct irq_domain *d, unsigned int irq)
725 {
726 irq_set_nested_thread(irq, 0);
727 irq_set_chip_and_handler(irq, NULL, NULL);
728 irq_set_chip_data(irq, NULL);
729 }
730
731 static const struct irq_domain_ops ar9331_sw_irqdomain_ops = {
732 .map = ar9331_sw_irq_map,
733 .unmap = ar9331_sw_irq_unmap,
734 .xlate = irq_domain_xlate_onecell,
735 };
736
ar9331_sw_irq_init(struct ar9331_sw_priv * priv)737 static int ar9331_sw_irq_init(struct ar9331_sw_priv *priv)
738 {
739 struct device_node *np = priv->dev->of_node;
740 struct device *dev = priv->dev;
741 int ret, irq;
742
743 irq = of_irq_get(np, 0);
744 if (irq <= 0) {
745 dev_err(dev, "failed to get parent IRQ\n");
746 return irq ? irq : -EINVAL;
747 }
748
749 mutex_init(&priv->lock_irq);
750 ret = devm_request_threaded_irq(dev, irq, NULL, ar9331_sw_irq,
751 IRQF_ONESHOT, AR9331_SW_NAME, priv);
752 if (ret) {
753 dev_err(dev, "unable to request irq: %d\n", ret);
754 return ret;
755 }
756
757 priv->irqdomain = irq_domain_add_linear(np, 1, &ar9331_sw_irqdomain_ops,
758 priv);
759 if (!priv->irqdomain) {
760 dev_err(dev, "failed to create IRQ domain\n");
761 return -EINVAL;
762 }
763
764 irq_set_parent(irq_create_mapping(priv->irqdomain, 0), irq);
765
766 return 0;
767 }
768
__ar9331_mdio_write(struct mii_bus * sbus,u8 mode,u16 reg,u16 val)769 static int __ar9331_mdio_write(struct mii_bus *sbus, u8 mode, u16 reg, u16 val)
770 {
771 u8 r, p;
772
773 p = FIELD_PREP(AR9331_SW_MDIO_PHY_MODE_M, mode) |
774 FIELD_GET(AR9331_SW_LOW_ADDR_PHY, reg);
775 r = FIELD_GET(AR9331_SW_LOW_ADDR_REG, reg);
776
777 return mdiobus_write(sbus, p, r, val);
778 }
779
__ar9331_mdio_read(struct mii_bus * sbus,u16 reg)780 static int __ar9331_mdio_read(struct mii_bus *sbus, u16 reg)
781 {
782 u8 r, p;
783
784 p = FIELD_PREP(AR9331_SW_MDIO_PHY_MODE_M, AR9331_SW_MDIO_PHY_MODE_REG) |
785 FIELD_GET(AR9331_SW_LOW_ADDR_PHY, reg);
786 r = FIELD_GET(AR9331_SW_LOW_ADDR_REG, reg);
787
788 return mdiobus_read(sbus, p, r);
789 }
790
ar9331_mdio_read(void * ctx,const void * reg_buf,size_t reg_len,void * val_buf,size_t val_len)791 static int ar9331_mdio_read(void *ctx, const void *reg_buf, size_t reg_len,
792 void *val_buf, size_t val_len)
793 {
794 struct ar9331_sw_priv *priv = ctx;
795 struct mii_bus *sbus = priv->sbus;
796 u32 reg = *(u32 *)reg_buf;
797 int ret;
798
799 if (reg == AR9331_SW_REG_PAGE) {
800 /* We cannot read the page selector register from hardware and
801 * we cache its value in regmap. Return all bits set here,
802 * that regmap will always write the page on first use.
803 */
804 *(u32 *)val_buf = GENMASK(9, 0);
805 return 0;
806 }
807
808 ret = __ar9331_mdio_read(sbus, reg);
809 if (ret < 0)
810 goto error;
811
812 *(u32 *)val_buf = ret;
813 ret = __ar9331_mdio_read(sbus, reg + 2);
814 if (ret < 0)
815 goto error;
816
817 *(u32 *)val_buf |= ret << 16;
818
819 return 0;
820 error:
821 dev_err_ratelimited(&sbus->dev, "Bus error. Failed to read register.\n");
822 return ret;
823 }
824
ar9331_mdio_write(void * ctx,u32 reg,u32 val)825 static int ar9331_mdio_write(void *ctx, u32 reg, u32 val)
826 {
827 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ctx;
828 struct mii_bus *sbus = priv->sbus;
829 int ret;
830
831 if (reg == AR9331_SW_REG_PAGE) {
832 ret = __ar9331_mdio_write(sbus, AR9331_SW_MDIO_PHY_MODE_PAGE,
833 0, val);
834 if (ret < 0)
835 goto error;
836
837 return 0;
838 }
839
840 ret = __ar9331_mdio_write(sbus, AR9331_SW_MDIO_PHY_MODE_REG, reg, val);
841 if (ret < 0)
842 goto error;
843
844 ret = __ar9331_mdio_write(sbus, AR9331_SW_MDIO_PHY_MODE_REG, reg + 2,
845 val >> 16);
846 if (ret < 0)
847 goto error;
848
849 return 0;
850 error:
851 dev_err_ratelimited(&sbus->dev, "Bus error. Failed to write register.\n");
852 return ret;
853 }
854
ar9331_sw_bus_write(void * context,const void * data,size_t count)855 static int ar9331_sw_bus_write(void *context, const void *data, size_t count)
856 {
857 u32 reg = *(u32 *)data;
858 u32 val = *((u32 *)data + 1);
859
860 return ar9331_mdio_write(context, reg, val);
861 }
862
863 static const struct regmap_range ar9331_valid_regs[] = {
864 regmap_reg_range(0x0, 0x0),
865 regmap_reg_range(0x10, 0x14),
866 regmap_reg_range(0x20, 0x24),
867 regmap_reg_range(0x2c, 0x30),
868 regmap_reg_range(0x40, 0x44),
869 regmap_reg_range(0x50, 0x78),
870 regmap_reg_range(0x80, 0x98),
871
872 regmap_reg_range(0x100, 0x120),
873 regmap_reg_range(0x200, 0x220),
874 regmap_reg_range(0x300, 0x320),
875 regmap_reg_range(0x400, 0x420),
876 regmap_reg_range(0x500, 0x520),
877 regmap_reg_range(0x600, 0x620),
878
879 regmap_reg_range(0x20000, 0x200a4),
880 regmap_reg_range(0x20100, 0x201a4),
881 regmap_reg_range(0x20200, 0x202a4),
882 regmap_reg_range(0x20300, 0x203a4),
883 regmap_reg_range(0x20400, 0x204a4),
884 regmap_reg_range(0x20500, 0x205a4),
885
886 /* dummy page selector reg */
887 regmap_reg_range(AR9331_SW_REG_PAGE, AR9331_SW_REG_PAGE),
888 };
889
890 static const struct regmap_range ar9331_nonvolatile_regs[] = {
891 regmap_reg_range(AR9331_SW_REG_PAGE, AR9331_SW_REG_PAGE),
892 };
893
894 static const struct regmap_range_cfg ar9331_regmap_range[] = {
895 {
896 .selector_reg = AR9331_SW_REG_PAGE,
897 .selector_mask = GENMASK(9, 0),
898 .selector_shift = 0,
899
900 .window_start = 0,
901 .window_len = 512,
902
903 .range_min = 0,
904 .range_max = AR9331_SW_REG_PAGE - 4,
905 },
906 };
907
908 static const struct regmap_access_table ar9331_register_set = {
909 .yes_ranges = ar9331_valid_regs,
910 .n_yes_ranges = ARRAY_SIZE(ar9331_valid_regs),
911 };
912
913 static const struct regmap_access_table ar9331_volatile_set = {
914 .no_ranges = ar9331_nonvolatile_regs,
915 .n_no_ranges = ARRAY_SIZE(ar9331_nonvolatile_regs),
916 };
917
918 static const struct regmap_config ar9331_mdio_regmap_config = {
919 .reg_bits = 32,
920 .val_bits = 32,
921 .reg_stride = 4,
922 .max_register = AR9331_SW_REG_PAGE,
923
924 .ranges = ar9331_regmap_range,
925 .num_ranges = ARRAY_SIZE(ar9331_regmap_range),
926
927 .volatile_table = &ar9331_volatile_set,
928 .wr_table = &ar9331_register_set,
929 .rd_table = &ar9331_register_set,
930
931 .cache_type = REGCACHE_RBTREE,
932 };
933
934 static struct regmap_bus ar9331_sw_bus = {
935 .reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
936 .val_format_endian_default = REGMAP_ENDIAN_NATIVE,
937 .read = ar9331_mdio_read,
938 .write = ar9331_sw_bus_write,
939 .max_raw_read = 4,
940 .max_raw_write = 4,
941 };
942
ar9331_sw_probe(struct mdio_device * mdiodev)943 static int ar9331_sw_probe(struct mdio_device *mdiodev)
944 {
945 struct ar9331_sw_priv *priv;
946 struct dsa_switch *ds;
947 int ret, i;
948
949 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
950 if (!priv)
951 return -ENOMEM;
952
953 priv->regmap = devm_regmap_init(&mdiodev->dev, &ar9331_sw_bus, priv,
954 &ar9331_mdio_regmap_config);
955 if (IS_ERR(priv->regmap)) {
956 ret = PTR_ERR(priv->regmap);
957 dev_err(&mdiodev->dev, "regmap init failed: %d\n", ret);
958 return ret;
959 }
960
961 priv->sw_reset = devm_reset_control_get(&mdiodev->dev, "switch");
962 if (IS_ERR(priv->sw_reset)) {
963 dev_err(&mdiodev->dev, "missing switch reset\n");
964 return PTR_ERR(priv->sw_reset);
965 }
966
967 priv->sbus = mdiodev->bus;
968 priv->dev = &mdiodev->dev;
969
970 ret = ar9331_sw_irq_init(priv);
971 if (ret)
972 return ret;
973
974 ds = &priv->ds;
975 ds->dev = &mdiodev->dev;
976 ds->num_ports = AR9331_SW_PORTS;
977 ds->priv = priv;
978 priv->ops = ar9331_sw_ops;
979 ds->ops = &priv->ops;
980 dev_set_drvdata(&mdiodev->dev, priv);
981
982 for (i = 0; i < ARRAY_SIZE(priv->port); i++) {
983 struct ar9331_sw_port *port = &priv->port[i];
984
985 port->idx = i;
986 spin_lock_init(&port->stats_lock);
987 INIT_DELAYED_WORK(&port->mib_read, ar9331_do_stats_poll);
988 }
989
990 ret = dsa_register_switch(ds);
991 if (ret)
992 goto err_remove_irq;
993
994 return 0;
995
996 err_remove_irq:
997 irq_domain_remove(priv->irqdomain);
998
999 return ret;
1000 }
1001
ar9331_sw_remove(struct mdio_device * mdiodev)1002 static void ar9331_sw_remove(struct mdio_device *mdiodev)
1003 {
1004 struct ar9331_sw_priv *priv = dev_get_drvdata(&mdiodev->dev);
1005 unsigned int i;
1006
1007 for (i = 0; i < ARRAY_SIZE(priv->port); i++) {
1008 struct ar9331_sw_port *port = &priv->port[i];
1009
1010 cancel_delayed_work_sync(&port->mib_read);
1011 }
1012
1013 irq_domain_remove(priv->irqdomain);
1014 mdiobus_unregister(priv->mbus);
1015 dsa_unregister_switch(&priv->ds);
1016
1017 reset_control_assert(priv->sw_reset);
1018 }
1019
1020 static const struct of_device_id ar9331_sw_of_match[] = {
1021 { .compatible = "qca,ar9331-switch" },
1022 { },
1023 };
1024
1025 static struct mdio_driver ar9331_sw_mdio_driver = {
1026 .probe = ar9331_sw_probe,
1027 .remove = ar9331_sw_remove,
1028 .mdiodrv.driver = {
1029 .name = AR9331_SW_NAME,
1030 .of_match_table = ar9331_sw_of_match,
1031 },
1032 };
1033
1034 mdio_module_driver(ar9331_sw_mdio_driver);
1035
1036 MODULE_AUTHOR("Oleksij Rempel <kernel@pengutronix.de>");
1037 MODULE_DESCRIPTION("Driver for Atheros AR9331 switch");
1038 MODULE_LICENSE("GPL v2");
1039