1 /*
2 * AMD 10Gb Ethernet driver
3 *
4 * This file is available to you under your choice of the following two
5 * licenses:
6 *
7 * License 1: GPLv2
8 *
9 * Copyright (c) 2016 Advanced Micro Devices, Inc.
10 *
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 *
24 * This file incorporates work covered by the following copyright and
25 * permission notice:
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
29 * and you.
30 *
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
40 *
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
43 *
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
55 *
56 *
57 * License 2: Modified BSD
58 *
59 * Copyright (c) 2016 Advanced Micro Devices, Inc.
60 * All rights reserved.
61 *
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
72 *
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
83 *
84 * This file incorporates work covered by the following copyright and
85 * permission notice:
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
89 * and you.
90 *
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
100 *
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
103 *
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
115 */
116
117 #include <linux/module.h>
118 #include <linux/device.h>
119 #include <linux/kmod.h>
120 #include <linux/mdio.h>
121 #include <linux/phy.h>
122 #include <linux/ethtool.h>
123
124 #include "xgbe.h"
125 #include "xgbe-common.h"
126
127 #define XGBE_PHY_PORT_SPEED_100 BIT(0)
128 #define XGBE_PHY_PORT_SPEED_1000 BIT(1)
129 #define XGBE_PHY_PORT_SPEED_2500 BIT(2)
130 #define XGBE_PHY_PORT_SPEED_10000 BIT(3)
131
132 #define XGBE_MUTEX_RELEASE 0x80000000
133
134 #define XGBE_SFP_DIRECT 7
135
136 /* I2C target addresses */
137 #define XGBE_SFP_SERIAL_ID_ADDRESS 0x50
138 #define XGBE_SFP_DIAG_INFO_ADDRESS 0x51
139 #define XGBE_SFP_PHY_ADDRESS 0x56
140 #define XGBE_GPIO_ADDRESS_PCA9555 0x20
141
142 /* SFP sideband signal indicators */
143 #define XGBE_GPIO_NO_TX_FAULT BIT(0)
144 #define XGBE_GPIO_NO_RATE_SELECT BIT(1)
145 #define XGBE_GPIO_NO_MOD_ABSENT BIT(2)
146 #define XGBE_GPIO_NO_RX_LOS BIT(3)
147
148 /* Rate-change complete wait/retry count */
149 #define XGBE_RATECHANGE_COUNT 500
150
151 /* CDR delay values for KR support (in usec) */
152 #define XGBE_CDR_DELAY_INIT 10000
153 #define XGBE_CDR_DELAY_INC 10000
154 #define XGBE_CDR_DELAY_MAX 100000
155
156 /* RRC frequency during link status check */
157 #define XGBE_RRC_FREQUENCY 10
158
159 enum xgbe_port_mode {
160 XGBE_PORT_MODE_RSVD = 0,
161 XGBE_PORT_MODE_BACKPLANE,
162 XGBE_PORT_MODE_BACKPLANE_2500,
163 XGBE_PORT_MODE_1000BASE_T,
164 XGBE_PORT_MODE_1000BASE_X,
165 XGBE_PORT_MODE_NBASE_T,
166 XGBE_PORT_MODE_10GBASE_T,
167 XGBE_PORT_MODE_10GBASE_R,
168 XGBE_PORT_MODE_SFP,
169 XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG,
170 XGBE_PORT_MODE_MAX,
171 };
172
173 enum xgbe_conn_type {
174 XGBE_CONN_TYPE_NONE = 0,
175 XGBE_CONN_TYPE_SFP,
176 XGBE_CONN_TYPE_MDIO,
177 XGBE_CONN_TYPE_RSVD1,
178 XGBE_CONN_TYPE_BACKPLANE,
179 XGBE_CONN_TYPE_MAX,
180 };
181
182 /* SFP/SFP+ related definitions */
183 enum xgbe_sfp_comm {
184 XGBE_SFP_COMM_DIRECT = 0,
185 XGBE_SFP_COMM_PCA9545,
186 };
187
188 enum xgbe_sfp_cable {
189 XGBE_SFP_CABLE_UNKNOWN = 0,
190 XGBE_SFP_CABLE_ACTIVE,
191 XGBE_SFP_CABLE_PASSIVE,
192 };
193
194 enum xgbe_sfp_base {
195 XGBE_SFP_BASE_UNKNOWN = 0,
196 XGBE_SFP_BASE_1000_T,
197 XGBE_SFP_BASE_1000_SX,
198 XGBE_SFP_BASE_1000_LX,
199 XGBE_SFP_BASE_1000_CX,
200 XGBE_SFP_BASE_10000_SR,
201 XGBE_SFP_BASE_10000_LR,
202 XGBE_SFP_BASE_10000_LRM,
203 XGBE_SFP_BASE_10000_ER,
204 XGBE_SFP_BASE_10000_CR,
205 };
206
207 enum xgbe_sfp_speed {
208 XGBE_SFP_SPEED_UNKNOWN = 0,
209 XGBE_SFP_SPEED_100_1000,
210 XGBE_SFP_SPEED_1000,
211 XGBE_SFP_SPEED_10000,
212 };
213
214 /* SFP Serial ID Base ID values relative to an offset of 0 */
215 #define XGBE_SFP_BASE_ID 0
216 #define XGBE_SFP_ID_SFP 0x03
217
218 #define XGBE_SFP_BASE_EXT_ID 1
219 #define XGBE_SFP_EXT_ID_SFP 0x04
220
221 #define XGBE_SFP_BASE_10GBE_CC 3
222 #define XGBE_SFP_BASE_10GBE_CC_SR BIT(4)
223 #define XGBE_SFP_BASE_10GBE_CC_LR BIT(5)
224 #define XGBE_SFP_BASE_10GBE_CC_LRM BIT(6)
225 #define XGBE_SFP_BASE_10GBE_CC_ER BIT(7)
226
227 #define XGBE_SFP_BASE_1GBE_CC 6
228 #define XGBE_SFP_BASE_1GBE_CC_SX BIT(0)
229 #define XGBE_SFP_BASE_1GBE_CC_LX BIT(1)
230 #define XGBE_SFP_BASE_1GBE_CC_CX BIT(2)
231 #define XGBE_SFP_BASE_1GBE_CC_T BIT(3)
232
233 #define XGBE_SFP_BASE_CABLE 8
234 #define XGBE_SFP_BASE_CABLE_PASSIVE BIT(2)
235 #define XGBE_SFP_BASE_CABLE_ACTIVE BIT(3)
236
237 #define XGBE_SFP_BASE_BR 12
238 #define XGBE_SFP_BASE_BR_1GBE_MIN 0x0a
239 #define XGBE_SFP_BASE_BR_1GBE_MAX 0x0d
240 #define XGBE_SFP_BASE_BR_10GBE_MIN 0x64
241 #define XGBE_SFP_BASE_BR_10GBE_MAX 0x68
242
243 #define XGBE_SFP_BASE_CU_CABLE_LEN 18
244
245 #define XGBE_SFP_BASE_VENDOR_NAME 20
246 #define XGBE_SFP_BASE_VENDOR_NAME_LEN 16
247 #define XGBE_SFP_BASE_VENDOR_PN 40
248 #define XGBE_SFP_BASE_VENDOR_PN_LEN 16
249 #define XGBE_SFP_BASE_VENDOR_REV 56
250 #define XGBE_SFP_BASE_VENDOR_REV_LEN 4
251
252 #define XGBE_SFP_BASE_CC 63
253
254 /* SFP Serial ID Extended ID values relative to an offset of 64 */
255 #define XGBE_SFP_BASE_VENDOR_SN 4
256 #define XGBE_SFP_BASE_VENDOR_SN_LEN 16
257
258 #define XGBE_SFP_EXTD_OPT1 1
259 #define XGBE_SFP_EXTD_OPT1_RX_LOS BIT(1)
260 #define XGBE_SFP_EXTD_OPT1_TX_FAULT BIT(3)
261
262 #define XGBE_SFP_EXTD_DIAG 28
263 #define XGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2)
264
265 #define XGBE_SFP_EXTD_SFF_8472 30
266
267 #define XGBE_SFP_EXTD_CC 31
268
269 struct xgbe_sfp_eeprom {
270 u8 base[64];
271 u8 extd[32];
272 u8 vendor[32];
273 };
274
275 #define XGBE_SFP_DIAGS_SUPPORTED(_x) \
276 ((_x)->extd[XGBE_SFP_EXTD_SFF_8472] && \
277 !((_x)->extd[XGBE_SFP_EXTD_DIAG] & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE))
278
279 #define XGBE_SFP_EEPROM_BASE_LEN 256
280 #define XGBE_SFP_EEPROM_DIAG_LEN 256
281 #define XGBE_SFP_EEPROM_MAX (XGBE_SFP_EEPROM_BASE_LEN + \
282 XGBE_SFP_EEPROM_DIAG_LEN)
283
284 #define XGBE_BEL_FUSE_VENDOR "BEL-FUSE "
285 #define XGBE_BEL_FUSE_PARTNO "1GBT-SFP06 "
286
287 struct xgbe_sfp_ascii {
288 union {
289 char vendor[XGBE_SFP_BASE_VENDOR_NAME_LEN + 1];
290 char partno[XGBE_SFP_BASE_VENDOR_PN_LEN + 1];
291 char rev[XGBE_SFP_BASE_VENDOR_REV_LEN + 1];
292 char serno[XGBE_SFP_BASE_VENDOR_SN_LEN + 1];
293 } u;
294 };
295
296 /* MDIO PHY reset types */
297 enum xgbe_mdio_reset {
298 XGBE_MDIO_RESET_NONE = 0,
299 XGBE_MDIO_RESET_I2C_GPIO,
300 XGBE_MDIO_RESET_INT_GPIO,
301 XGBE_MDIO_RESET_MAX,
302 };
303
304 /* Re-driver related definitions */
305 enum xgbe_phy_redrv_if {
306 XGBE_PHY_REDRV_IF_MDIO = 0,
307 XGBE_PHY_REDRV_IF_I2C,
308 XGBE_PHY_REDRV_IF_MAX,
309 };
310
311 enum xgbe_phy_redrv_model {
312 XGBE_PHY_REDRV_MODEL_4223 = 0,
313 XGBE_PHY_REDRV_MODEL_4227,
314 XGBE_PHY_REDRV_MODEL_MAX,
315 };
316
317 enum xgbe_phy_redrv_mode {
318 XGBE_PHY_REDRV_MODE_CX = 5,
319 XGBE_PHY_REDRV_MODE_SR = 9,
320 };
321
322 #define XGBE_PHY_REDRV_MODE_REG 0x12b0
323
324 /* PHY related configuration information */
325 struct xgbe_phy_data {
326 enum xgbe_port_mode port_mode;
327
328 unsigned int port_id;
329
330 unsigned int port_speeds;
331
332 enum xgbe_conn_type conn_type;
333
334 enum xgbe_mode cur_mode;
335 enum xgbe_mode start_mode;
336
337 unsigned int rrc_count;
338
339 unsigned int mdio_addr;
340
341 /* SFP Support */
342 enum xgbe_sfp_comm sfp_comm;
343 unsigned int sfp_mux_address;
344 unsigned int sfp_mux_channel;
345
346 unsigned int sfp_gpio_address;
347 unsigned int sfp_gpio_mask;
348 unsigned int sfp_gpio_inputs;
349 unsigned int sfp_gpio_rx_los;
350 unsigned int sfp_gpio_tx_fault;
351 unsigned int sfp_gpio_mod_absent;
352 unsigned int sfp_gpio_rate_select;
353
354 unsigned int sfp_rx_los;
355 unsigned int sfp_tx_fault;
356 unsigned int sfp_mod_absent;
357 unsigned int sfp_changed;
358 unsigned int sfp_phy_avail;
359 unsigned int sfp_cable_len;
360 enum xgbe_sfp_base sfp_base;
361 enum xgbe_sfp_cable sfp_cable;
362 enum xgbe_sfp_speed sfp_speed;
363 struct xgbe_sfp_eeprom sfp_eeprom;
364
365 /* External PHY support */
366 enum xgbe_mdio_mode phydev_mode;
367 struct mii_bus *mii;
368 struct phy_device *phydev;
369 enum xgbe_mdio_reset mdio_reset;
370 unsigned int mdio_reset_addr;
371 unsigned int mdio_reset_gpio;
372
373 /* Re-driver support */
374 unsigned int redrv;
375 unsigned int redrv_if;
376 unsigned int redrv_addr;
377 unsigned int redrv_lane;
378 unsigned int redrv_model;
379
380 /* KR AN support */
381 unsigned int phy_cdr_notrack;
382 unsigned int phy_cdr_delay;
383 };
384
385 /* I2C, MDIO and GPIO lines are muxed, so only one device at a time */
386 static DEFINE_MUTEX(xgbe_phy_comm_lock);
387
388 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata);
389
xgbe_phy_i2c_xfer(struct xgbe_prv_data * pdata,struct xgbe_i2c_op * i2c_op)390 static int xgbe_phy_i2c_xfer(struct xgbe_prv_data *pdata,
391 struct xgbe_i2c_op *i2c_op)
392 {
393 return pdata->i2c_if.i2c_xfer(pdata, i2c_op);
394 }
395
xgbe_phy_redrv_write(struct xgbe_prv_data * pdata,unsigned int reg,unsigned int val)396 static int xgbe_phy_redrv_write(struct xgbe_prv_data *pdata, unsigned int reg,
397 unsigned int val)
398 {
399 struct xgbe_phy_data *phy_data = pdata->phy_data;
400 struct xgbe_i2c_op i2c_op;
401 __be16 *redrv_val;
402 u8 redrv_data[5], csum;
403 unsigned int i, retry;
404 int ret;
405
406 /* High byte of register contains read/write indicator */
407 redrv_data[0] = ((reg >> 8) & 0xff) << 1;
408 redrv_data[1] = reg & 0xff;
409 redrv_val = (__be16 *)&redrv_data[2];
410 *redrv_val = cpu_to_be16(val);
411
412 /* Calculate 1 byte checksum */
413 csum = 0;
414 for (i = 0; i < 4; i++) {
415 csum += redrv_data[i];
416 if (redrv_data[i] > csum)
417 csum++;
418 }
419 redrv_data[4] = ~csum;
420
421 retry = 1;
422 again1:
423 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
424 i2c_op.target = phy_data->redrv_addr;
425 i2c_op.len = sizeof(redrv_data);
426 i2c_op.buf = redrv_data;
427 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
428 if (ret) {
429 if ((ret == -EAGAIN) && retry--)
430 goto again1;
431
432 return ret;
433 }
434
435 retry = 1;
436 again2:
437 i2c_op.cmd = XGBE_I2C_CMD_READ;
438 i2c_op.target = phy_data->redrv_addr;
439 i2c_op.len = 1;
440 i2c_op.buf = redrv_data;
441 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
442 if (ret) {
443 if ((ret == -EAGAIN) && retry--)
444 goto again2;
445
446 return ret;
447 }
448
449 if (redrv_data[0] != 0xff) {
450 netif_dbg(pdata, drv, pdata->netdev,
451 "Redriver write checksum error\n");
452 ret = -EIO;
453 }
454
455 return ret;
456 }
457
xgbe_phy_i2c_write(struct xgbe_prv_data * pdata,unsigned int target,void * val,unsigned int val_len)458 static int xgbe_phy_i2c_write(struct xgbe_prv_data *pdata, unsigned int target,
459 void *val, unsigned int val_len)
460 {
461 struct xgbe_i2c_op i2c_op;
462 int retry, ret;
463
464 retry = 1;
465 again:
466 /* Write the specfied register */
467 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
468 i2c_op.target = target;
469 i2c_op.len = val_len;
470 i2c_op.buf = val;
471 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
472 if ((ret == -EAGAIN) && retry--)
473 goto again;
474
475 return ret;
476 }
477
xgbe_phy_i2c_read(struct xgbe_prv_data * pdata,unsigned int target,void * reg,unsigned int reg_len,void * val,unsigned int val_len)478 static int xgbe_phy_i2c_read(struct xgbe_prv_data *pdata, unsigned int target,
479 void *reg, unsigned int reg_len,
480 void *val, unsigned int val_len)
481 {
482 struct xgbe_i2c_op i2c_op;
483 int retry, ret;
484
485 retry = 1;
486 again1:
487 /* Set the specified register to read */
488 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
489 i2c_op.target = target;
490 i2c_op.len = reg_len;
491 i2c_op.buf = reg;
492 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
493 if (ret) {
494 if ((ret == -EAGAIN) && retry--)
495 goto again1;
496
497 return ret;
498 }
499
500 retry = 1;
501 again2:
502 /* Read the specfied register */
503 i2c_op.cmd = XGBE_I2C_CMD_READ;
504 i2c_op.target = target;
505 i2c_op.len = val_len;
506 i2c_op.buf = val;
507 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
508 if ((ret == -EAGAIN) && retry--)
509 goto again2;
510
511 return ret;
512 }
513
xgbe_phy_sfp_put_mux(struct xgbe_prv_data * pdata)514 static int xgbe_phy_sfp_put_mux(struct xgbe_prv_data *pdata)
515 {
516 struct xgbe_phy_data *phy_data = pdata->phy_data;
517 struct xgbe_i2c_op i2c_op;
518 u8 mux_channel;
519
520 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
521 return 0;
522
523 /* Select no mux channels */
524 mux_channel = 0;
525 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
526 i2c_op.target = phy_data->sfp_mux_address;
527 i2c_op.len = sizeof(mux_channel);
528 i2c_op.buf = &mux_channel;
529
530 return xgbe_phy_i2c_xfer(pdata, &i2c_op);
531 }
532
xgbe_phy_sfp_get_mux(struct xgbe_prv_data * pdata)533 static int xgbe_phy_sfp_get_mux(struct xgbe_prv_data *pdata)
534 {
535 struct xgbe_phy_data *phy_data = pdata->phy_data;
536 struct xgbe_i2c_op i2c_op;
537 u8 mux_channel;
538
539 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
540 return 0;
541
542 /* Select desired mux channel */
543 mux_channel = 1 << phy_data->sfp_mux_channel;
544 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
545 i2c_op.target = phy_data->sfp_mux_address;
546 i2c_op.len = sizeof(mux_channel);
547 i2c_op.buf = &mux_channel;
548
549 return xgbe_phy_i2c_xfer(pdata, &i2c_op);
550 }
551
xgbe_phy_put_comm_ownership(struct xgbe_prv_data * pdata)552 static void xgbe_phy_put_comm_ownership(struct xgbe_prv_data *pdata)
553 {
554 mutex_unlock(&xgbe_phy_comm_lock);
555 }
556
xgbe_phy_get_comm_ownership(struct xgbe_prv_data * pdata)557 static int xgbe_phy_get_comm_ownership(struct xgbe_prv_data *pdata)
558 {
559 struct xgbe_phy_data *phy_data = pdata->phy_data;
560 unsigned long timeout;
561 unsigned int mutex_id;
562
563 /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices,
564 * the driver needs to take the software mutex and then the hardware
565 * mutexes before being able to use the busses.
566 */
567 mutex_lock(&xgbe_phy_comm_lock);
568
569 /* Clear the mutexes */
570 XP_IOWRITE(pdata, XP_I2C_MUTEX, XGBE_MUTEX_RELEASE);
571 XP_IOWRITE(pdata, XP_MDIO_MUTEX, XGBE_MUTEX_RELEASE);
572
573 /* Mutex formats are the same for I2C and MDIO/GPIO */
574 mutex_id = 0;
575 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id);
576 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1);
577
578 timeout = jiffies + (5 * HZ);
579 while (time_before(jiffies, timeout)) {
580 /* Must be all zeroes in order to obtain the mutex */
581 if (XP_IOREAD(pdata, XP_I2C_MUTEX) ||
582 XP_IOREAD(pdata, XP_MDIO_MUTEX)) {
583 usleep_range(100, 200);
584 continue;
585 }
586
587 /* Obtain the mutex */
588 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id);
589 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id);
590
591 return 0;
592 }
593
594 mutex_unlock(&xgbe_phy_comm_lock);
595
596 netdev_err(pdata->netdev, "unable to obtain hardware mutexes\n");
597
598 return -ETIMEDOUT;
599 }
600
xgbe_phy_mdio_mii_write(struct xgbe_prv_data * pdata,int addr,int reg,u16 val)601 static int xgbe_phy_mdio_mii_write(struct xgbe_prv_data *pdata, int addr,
602 int reg, u16 val)
603 {
604 struct xgbe_phy_data *phy_data = pdata->phy_data;
605
606 if (reg & MII_ADDR_C45) {
607 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
608 return -ENOTSUPP;
609 } else {
610 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
611 return -ENOTSUPP;
612 }
613
614 return pdata->hw_if.write_ext_mii_regs(pdata, addr, reg, val);
615 }
616
xgbe_phy_i2c_mii_write(struct xgbe_prv_data * pdata,int reg,u16 val)617 static int xgbe_phy_i2c_mii_write(struct xgbe_prv_data *pdata, int reg, u16 val)
618 {
619 __be16 *mii_val;
620 u8 mii_data[3];
621 int ret;
622
623 ret = xgbe_phy_sfp_get_mux(pdata);
624 if (ret)
625 return ret;
626
627 mii_data[0] = reg & 0xff;
628 mii_val = (__be16 *)&mii_data[1];
629 *mii_val = cpu_to_be16(val);
630
631 ret = xgbe_phy_i2c_write(pdata, XGBE_SFP_PHY_ADDRESS,
632 mii_data, sizeof(mii_data));
633
634 xgbe_phy_sfp_put_mux(pdata);
635
636 return ret;
637 }
638
xgbe_phy_mii_write(struct mii_bus * mii,int addr,int reg,u16 val)639 static int xgbe_phy_mii_write(struct mii_bus *mii, int addr, int reg, u16 val)
640 {
641 struct xgbe_prv_data *pdata = mii->priv;
642 struct xgbe_phy_data *phy_data = pdata->phy_data;
643 int ret;
644
645 ret = xgbe_phy_get_comm_ownership(pdata);
646 if (ret)
647 return ret;
648
649 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
650 ret = xgbe_phy_i2c_mii_write(pdata, reg, val);
651 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
652 ret = xgbe_phy_mdio_mii_write(pdata, addr, reg, val);
653 else
654 ret = -ENOTSUPP;
655
656 xgbe_phy_put_comm_ownership(pdata);
657
658 return ret;
659 }
660
xgbe_phy_mdio_mii_read(struct xgbe_prv_data * pdata,int addr,int reg)661 static int xgbe_phy_mdio_mii_read(struct xgbe_prv_data *pdata, int addr,
662 int reg)
663 {
664 struct xgbe_phy_data *phy_data = pdata->phy_data;
665
666 if (reg & MII_ADDR_C45) {
667 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
668 return -ENOTSUPP;
669 } else {
670 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
671 return -ENOTSUPP;
672 }
673
674 return pdata->hw_if.read_ext_mii_regs(pdata, addr, reg);
675 }
676
xgbe_phy_i2c_mii_read(struct xgbe_prv_data * pdata,int reg)677 static int xgbe_phy_i2c_mii_read(struct xgbe_prv_data *pdata, int reg)
678 {
679 __be16 mii_val;
680 u8 mii_reg;
681 int ret;
682
683 ret = xgbe_phy_sfp_get_mux(pdata);
684 if (ret)
685 return ret;
686
687 mii_reg = reg;
688 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_PHY_ADDRESS,
689 &mii_reg, sizeof(mii_reg),
690 &mii_val, sizeof(mii_val));
691 if (!ret)
692 ret = be16_to_cpu(mii_val);
693
694 xgbe_phy_sfp_put_mux(pdata);
695
696 return ret;
697 }
698
xgbe_phy_mii_read(struct mii_bus * mii,int addr,int reg)699 static int xgbe_phy_mii_read(struct mii_bus *mii, int addr, int reg)
700 {
701 struct xgbe_prv_data *pdata = mii->priv;
702 struct xgbe_phy_data *phy_data = pdata->phy_data;
703 int ret;
704
705 ret = xgbe_phy_get_comm_ownership(pdata);
706 if (ret)
707 return ret;
708
709 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
710 ret = xgbe_phy_i2c_mii_read(pdata, reg);
711 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
712 ret = xgbe_phy_mdio_mii_read(pdata, addr, reg);
713 else
714 ret = -ENOTSUPP;
715
716 xgbe_phy_put_comm_ownership(pdata);
717
718 return ret;
719 }
720
xgbe_phy_sfp_phy_settings(struct xgbe_prv_data * pdata)721 static void xgbe_phy_sfp_phy_settings(struct xgbe_prv_data *pdata)
722 {
723 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
724 struct xgbe_phy_data *phy_data = pdata->phy_data;
725
726 if (!phy_data->sfp_mod_absent && !phy_data->sfp_changed)
727 return;
728
729 XGBE_ZERO_SUP(lks);
730
731 if (phy_data->sfp_mod_absent) {
732 pdata->phy.speed = SPEED_UNKNOWN;
733 pdata->phy.duplex = DUPLEX_UNKNOWN;
734 pdata->phy.autoneg = AUTONEG_ENABLE;
735 pdata->phy.pause_autoneg = AUTONEG_ENABLE;
736
737 XGBE_SET_SUP(lks, Autoneg);
738 XGBE_SET_SUP(lks, Pause);
739 XGBE_SET_SUP(lks, Asym_Pause);
740 XGBE_SET_SUP(lks, TP);
741 XGBE_SET_SUP(lks, FIBRE);
742
743 XGBE_LM_COPY(lks, advertising, lks, supported);
744
745 return;
746 }
747
748 switch (phy_data->sfp_base) {
749 case XGBE_SFP_BASE_1000_T:
750 case XGBE_SFP_BASE_1000_SX:
751 case XGBE_SFP_BASE_1000_LX:
752 case XGBE_SFP_BASE_1000_CX:
753 pdata->phy.speed = SPEED_UNKNOWN;
754 pdata->phy.duplex = DUPLEX_UNKNOWN;
755 pdata->phy.autoneg = AUTONEG_ENABLE;
756 pdata->phy.pause_autoneg = AUTONEG_ENABLE;
757 XGBE_SET_SUP(lks, Autoneg);
758 XGBE_SET_SUP(lks, Pause);
759 XGBE_SET_SUP(lks, Asym_Pause);
760 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) {
761 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
762 XGBE_SET_SUP(lks, 100baseT_Full);
763 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
764 XGBE_SET_SUP(lks, 1000baseT_Full);
765 } else {
766 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
767 XGBE_SET_SUP(lks, 1000baseX_Full);
768 }
769 break;
770 case XGBE_SFP_BASE_10000_SR:
771 case XGBE_SFP_BASE_10000_LR:
772 case XGBE_SFP_BASE_10000_LRM:
773 case XGBE_SFP_BASE_10000_ER:
774 case XGBE_SFP_BASE_10000_CR:
775 pdata->phy.speed = SPEED_10000;
776 pdata->phy.duplex = DUPLEX_FULL;
777 pdata->phy.autoneg = AUTONEG_DISABLE;
778 pdata->phy.pause_autoneg = AUTONEG_DISABLE;
779 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
780 switch (phy_data->sfp_base) {
781 case XGBE_SFP_BASE_10000_SR:
782 XGBE_SET_SUP(lks, 10000baseSR_Full);
783 break;
784 case XGBE_SFP_BASE_10000_LR:
785 XGBE_SET_SUP(lks, 10000baseLR_Full);
786 break;
787 case XGBE_SFP_BASE_10000_LRM:
788 XGBE_SET_SUP(lks, 10000baseLRM_Full);
789 break;
790 case XGBE_SFP_BASE_10000_ER:
791 XGBE_SET_SUP(lks, 10000baseER_Full);
792 break;
793 case XGBE_SFP_BASE_10000_CR:
794 XGBE_SET_SUP(lks, 10000baseCR_Full);
795 break;
796 default:
797 break;
798 }
799 }
800 break;
801 default:
802 pdata->phy.speed = SPEED_UNKNOWN;
803 pdata->phy.duplex = DUPLEX_UNKNOWN;
804 pdata->phy.autoneg = AUTONEG_DISABLE;
805 pdata->phy.pause_autoneg = AUTONEG_DISABLE;
806 break;
807 }
808
809 switch (phy_data->sfp_base) {
810 case XGBE_SFP_BASE_1000_T:
811 case XGBE_SFP_BASE_1000_CX:
812 case XGBE_SFP_BASE_10000_CR:
813 XGBE_SET_SUP(lks, TP);
814 break;
815 default:
816 XGBE_SET_SUP(lks, FIBRE);
817 break;
818 }
819
820 XGBE_LM_COPY(lks, advertising, lks, supported);
821 }
822
xgbe_phy_sfp_bit_rate(struct xgbe_sfp_eeprom * sfp_eeprom,enum xgbe_sfp_speed sfp_speed)823 static bool xgbe_phy_sfp_bit_rate(struct xgbe_sfp_eeprom *sfp_eeprom,
824 enum xgbe_sfp_speed sfp_speed)
825 {
826 u8 *sfp_base, min, max;
827
828 sfp_base = sfp_eeprom->base;
829
830 switch (sfp_speed) {
831 case XGBE_SFP_SPEED_1000:
832 min = XGBE_SFP_BASE_BR_1GBE_MIN;
833 max = XGBE_SFP_BASE_BR_1GBE_MAX;
834 break;
835 case XGBE_SFP_SPEED_10000:
836 min = XGBE_SFP_BASE_BR_10GBE_MIN;
837 max = XGBE_SFP_BASE_BR_10GBE_MAX;
838 break;
839 default:
840 return false;
841 }
842
843 return ((sfp_base[XGBE_SFP_BASE_BR] >= min) &&
844 (sfp_base[XGBE_SFP_BASE_BR] <= max));
845 }
846
xgbe_phy_free_phy_device(struct xgbe_prv_data * pdata)847 static void xgbe_phy_free_phy_device(struct xgbe_prv_data *pdata)
848 {
849 struct xgbe_phy_data *phy_data = pdata->phy_data;
850
851 if (phy_data->phydev) {
852 phy_detach(phy_data->phydev);
853 phy_device_remove(phy_data->phydev);
854 phy_device_free(phy_data->phydev);
855 phy_data->phydev = NULL;
856 }
857 }
858
xgbe_phy_finisar_phy_quirks(struct xgbe_prv_data * pdata)859 static bool xgbe_phy_finisar_phy_quirks(struct xgbe_prv_data *pdata)
860 {
861 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, };
862 struct xgbe_phy_data *phy_data = pdata->phy_data;
863 unsigned int phy_id = phy_data->phydev->phy_id;
864
865 if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
866 return false;
867
868 if ((phy_id & 0xfffffff0) != 0x01ff0cc0)
869 return false;
870
871 /* Enable Base-T AN */
872 phy_write(phy_data->phydev, 0x16, 0x0001);
873 phy_write(phy_data->phydev, 0x00, 0x9140);
874 phy_write(phy_data->phydev, 0x16, 0x0000);
875
876 /* Enable SGMII at 100Base-T/1000Base-T Full Duplex */
877 phy_write(phy_data->phydev, 0x1b, 0x9084);
878 phy_write(phy_data->phydev, 0x09, 0x0e00);
879 phy_write(phy_data->phydev, 0x00, 0x8140);
880 phy_write(phy_data->phydev, 0x04, 0x0d01);
881 phy_write(phy_data->phydev, 0x00, 0x9140);
882
883 linkmode_set_bit_array(phy_10_100_features_array,
884 ARRAY_SIZE(phy_10_100_features_array),
885 supported);
886 linkmode_set_bit_array(phy_gbit_features_array,
887 ARRAY_SIZE(phy_gbit_features_array),
888 supported);
889
890 linkmode_copy(phy_data->phydev->supported, supported);
891
892 phy_support_asym_pause(phy_data->phydev);
893
894 netif_dbg(pdata, drv, pdata->netdev,
895 "Finisar PHY quirk in place\n");
896
897 return true;
898 }
899
xgbe_phy_belfuse_phy_quirks(struct xgbe_prv_data * pdata)900 static bool xgbe_phy_belfuse_phy_quirks(struct xgbe_prv_data *pdata)
901 {
902 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, };
903 struct xgbe_phy_data *phy_data = pdata->phy_data;
904 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
905 unsigned int phy_id = phy_data->phydev->phy_id;
906 int reg;
907
908 if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
909 return false;
910
911 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
912 XGBE_BEL_FUSE_VENDOR, XGBE_SFP_BASE_VENDOR_NAME_LEN))
913 return false;
914
915 /* For Bel-Fuse, use the extra AN flag */
916 pdata->an_again = 1;
917
918 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
919 XGBE_BEL_FUSE_PARTNO, XGBE_SFP_BASE_VENDOR_PN_LEN))
920 return false;
921
922 if ((phy_id & 0xfffffff0) != 0x03625d10)
923 return false;
924
925 /* Reset PHY - wait for self-clearing reset bit to clear */
926 genphy_soft_reset(phy_data->phydev);
927
928 /* Disable RGMII mode */
929 phy_write(phy_data->phydev, 0x18, 0x7007);
930 reg = phy_read(phy_data->phydev, 0x18);
931 phy_write(phy_data->phydev, 0x18, reg & ~0x0080);
932
933 /* Enable fiber register bank */
934 phy_write(phy_data->phydev, 0x1c, 0x7c00);
935 reg = phy_read(phy_data->phydev, 0x1c);
936 reg &= 0x03ff;
937 reg &= ~0x0001;
938 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg | 0x0001);
939
940 /* Power down SerDes */
941 reg = phy_read(phy_data->phydev, 0x00);
942 phy_write(phy_data->phydev, 0x00, reg | 0x00800);
943
944 /* Configure SGMII-to-Copper mode */
945 phy_write(phy_data->phydev, 0x1c, 0x7c00);
946 reg = phy_read(phy_data->phydev, 0x1c);
947 reg &= 0x03ff;
948 reg &= ~0x0006;
949 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg | 0x0004);
950
951 /* Power up SerDes */
952 reg = phy_read(phy_data->phydev, 0x00);
953 phy_write(phy_data->phydev, 0x00, reg & ~0x00800);
954
955 /* Enable copper register bank */
956 phy_write(phy_data->phydev, 0x1c, 0x7c00);
957 reg = phy_read(phy_data->phydev, 0x1c);
958 reg &= 0x03ff;
959 reg &= ~0x0001;
960 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg);
961
962 /* Power up SerDes */
963 reg = phy_read(phy_data->phydev, 0x00);
964 phy_write(phy_data->phydev, 0x00, reg & ~0x00800);
965
966 linkmode_set_bit_array(phy_10_100_features_array,
967 ARRAY_SIZE(phy_10_100_features_array),
968 supported);
969 linkmode_set_bit_array(phy_gbit_features_array,
970 ARRAY_SIZE(phy_gbit_features_array),
971 supported);
972 linkmode_copy(phy_data->phydev->supported, supported);
973 phy_support_asym_pause(phy_data->phydev);
974
975 netif_dbg(pdata, drv, pdata->netdev,
976 "BelFuse PHY quirk in place\n");
977
978 return true;
979 }
980
xgbe_phy_external_phy_quirks(struct xgbe_prv_data * pdata)981 static void xgbe_phy_external_phy_quirks(struct xgbe_prv_data *pdata)
982 {
983 if (xgbe_phy_belfuse_phy_quirks(pdata))
984 return;
985
986 if (xgbe_phy_finisar_phy_quirks(pdata))
987 return;
988 }
989
xgbe_phy_find_phy_device(struct xgbe_prv_data * pdata)990 static int xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata)
991 {
992 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
993 struct xgbe_phy_data *phy_data = pdata->phy_data;
994 struct phy_device *phydev;
995 int ret;
996
997 /* If we already have a PHY, just return */
998 if (phy_data->phydev)
999 return 0;
1000
1001 /* Clear the extra AN flag */
1002 pdata->an_again = 0;
1003
1004 /* Check for the use of an external PHY */
1005 if (phy_data->phydev_mode == XGBE_MDIO_MODE_NONE)
1006 return 0;
1007
1008 /* For SFP, only use an external PHY if available */
1009 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
1010 !phy_data->sfp_phy_avail)
1011 return 0;
1012
1013 /* Set the proper MDIO mode for the PHY */
1014 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
1015 phy_data->phydev_mode);
1016 if (ret) {
1017 netdev_err(pdata->netdev,
1018 "mdio port/clause not compatible (%u/%u)\n",
1019 phy_data->mdio_addr, phy_data->phydev_mode);
1020 return ret;
1021 }
1022
1023 /* Create and connect to the PHY device */
1024 phydev = get_phy_device(phy_data->mii, phy_data->mdio_addr,
1025 (phy_data->phydev_mode == XGBE_MDIO_MODE_CL45));
1026 if (IS_ERR(phydev)) {
1027 netdev_err(pdata->netdev, "get_phy_device failed\n");
1028 return -ENODEV;
1029 }
1030 netif_dbg(pdata, drv, pdata->netdev, "external PHY id is %#010x\n",
1031 phydev->phy_id);
1032
1033 /*TODO: If c45, add request_module based on one of the MMD ids? */
1034
1035 ret = phy_device_register(phydev);
1036 if (ret) {
1037 netdev_err(pdata->netdev, "phy_device_register failed\n");
1038 phy_device_free(phydev);
1039 return ret;
1040 }
1041
1042 ret = phy_attach_direct(pdata->netdev, phydev, phydev->dev_flags,
1043 PHY_INTERFACE_MODE_SGMII);
1044 if (ret) {
1045 netdev_err(pdata->netdev, "phy_attach_direct failed\n");
1046 phy_device_remove(phydev);
1047 phy_device_free(phydev);
1048 return ret;
1049 }
1050 phy_data->phydev = phydev;
1051
1052 xgbe_phy_external_phy_quirks(pdata);
1053
1054 linkmode_and(phydev->advertising, phydev->advertising,
1055 lks->link_modes.advertising);
1056
1057 phy_start_aneg(phy_data->phydev);
1058
1059 return 0;
1060 }
1061
xgbe_phy_sfp_external_phy(struct xgbe_prv_data * pdata)1062 static void xgbe_phy_sfp_external_phy(struct xgbe_prv_data *pdata)
1063 {
1064 struct xgbe_phy_data *phy_data = pdata->phy_data;
1065 int ret;
1066
1067 if (!phy_data->sfp_changed)
1068 return;
1069
1070 phy_data->sfp_phy_avail = 0;
1071
1072 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
1073 return;
1074
1075 /* Check access to the PHY by reading CTRL1 */
1076 ret = xgbe_phy_i2c_mii_read(pdata, MII_BMCR);
1077 if (ret < 0)
1078 return;
1079
1080 /* Successfully accessed the PHY */
1081 phy_data->sfp_phy_avail = 1;
1082 }
1083
xgbe_phy_check_sfp_rx_los(struct xgbe_phy_data * phy_data)1084 static bool xgbe_phy_check_sfp_rx_los(struct xgbe_phy_data *phy_data)
1085 {
1086 u8 *sfp_extd = phy_data->sfp_eeprom.extd;
1087
1088 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_RX_LOS))
1089 return false;
1090
1091 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_RX_LOS)
1092 return false;
1093
1094 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_rx_los))
1095 return true;
1096
1097 return false;
1098 }
1099
xgbe_phy_check_sfp_tx_fault(struct xgbe_phy_data * phy_data)1100 static bool xgbe_phy_check_sfp_tx_fault(struct xgbe_phy_data *phy_data)
1101 {
1102 u8 *sfp_extd = phy_data->sfp_eeprom.extd;
1103
1104 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_TX_FAULT))
1105 return false;
1106
1107 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_TX_FAULT)
1108 return false;
1109
1110 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_tx_fault))
1111 return true;
1112
1113 return false;
1114 }
1115
xgbe_phy_check_sfp_mod_absent(struct xgbe_phy_data * phy_data)1116 static bool xgbe_phy_check_sfp_mod_absent(struct xgbe_phy_data *phy_data)
1117 {
1118 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_MOD_ABSENT)
1119 return false;
1120
1121 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_mod_absent))
1122 return true;
1123
1124 return false;
1125 }
1126
xgbe_phy_sfp_parse_eeprom(struct xgbe_prv_data * pdata)1127 static void xgbe_phy_sfp_parse_eeprom(struct xgbe_prv_data *pdata)
1128 {
1129 struct xgbe_phy_data *phy_data = pdata->phy_data;
1130 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
1131 u8 *sfp_base;
1132
1133 sfp_base = sfp_eeprom->base;
1134
1135 if (sfp_base[XGBE_SFP_BASE_ID] != XGBE_SFP_ID_SFP)
1136 return;
1137
1138 if (sfp_base[XGBE_SFP_BASE_EXT_ID] != XGBE_SFP_EXT_ID_SFP)
1139 return;
1140
1141 /* Update transceiver signals (eeprom extd/options) */
1142 phy_data->sfp_tx_fault = xgbe_phy_check_sfp_tx_fault(phy_data);
1143 phy_data->sfp_rx_los = xgbe_phy_check_sfp_rx_los(phy_data);
1144
1145 /* Assume ACTIVE cable unless told it is PASSIVE */
1146 if (sfp_base[XGBE_SFP_BASE_CABLE] & XGBE_SFP_BASE_CABLE_PASSIVE) {
1147 phy_data->sfp_cable = XGBE_SFP_CABLE_PASSIVE;
1148 phy_data->sfp_cable_len = sfp_base[XGBE_SFP_BASE_CU_CABLE_LEN];
1149 } else {
1150 phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE;
1151 }
1152
1153 /* Determine the type of SFP */
1154 if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_SR)
1155 phy_data->sfp_base = XGBE_SFP_BASE_10000_SR;
1156 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LR)
1157 phy_data->sfp_base = XGBE_SFP_BASE_10000_LR;
1158 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LRM)
1159 phy_data->sfp_base = XGBE_SFP_BASE_10000_LRM;
1160 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_ER)
1161 phy_data->sfp_base = XGBE_SFP_BASE_10000_ER;
1162 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_SX)
1163 phy_data->sfp_base = XGBE_SFP_BASE_1000_SX;
1164 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_LX)
1165 phy_data->sfp_base = XGBE_SFP_BASE_1000_LX;
1166 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_CX)
1167 phy_data->sfp_base = XGBE_SFP_BASE_1000_CX;
1168 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_T)
1169 phy_data->sfp_base = XGBE_SFP_BASE_1000_T;
1170 else if ((phy_data->sfp_cable == XGBE_SFP_CABLE_PASSIVE) &&
1171 xgbe_phy_sfp_bit_rate(sfp_eeprom, XGBE_SFP_SPEED_10000))
1172 phy_data->sfp_base = XGBE_SFP_BASE_10000_CR;
1173
1174 switch (phy_data->sfp_base) {
1175 case XGBE_SFP_BASE_1000_T:
1176 phy_data->sfp_speed = XGBE_SFP_SPEED_100_1000;
1177 break;
1178 case XGBE_SFP_BASE_1000_SX:
1179 case XGBE_SFP_BASE_1000_LX:
1180 case XGBE_SFP_BASE_1000_CX:
1181 phy_data->sfp_speed = XGBE_SFP_SPEED_1000;
1182 break;
1183 case XGBE_SFP_BASE_10000_SR:
1184 case XGBE_SFP_BASE_10000_LR:
1185 case XGBE_SFP_BASE_10000_LRM:
1186 case XGBE_SFP_BASE_10000_ER:
1187 case XGBE_SFP_BASE_10000_CR:
1188 phy_data->sfp_speed = XGBE_SFP_SPEED_10000;
1189 break;
1190 default:
1191 break;
1192 }
1193 }
1194
xgbe_phy_sfp_eeprom_info(struct xgbe_prv_data * pdata,struct xgbe_sfp_eeprom * sfp_eeprom)1195 static void xgbe_phy_sfp_eeprom_info(struct xgbe_prv_data *pdata,
1196 struct xgbe_sfp_eeprom *sfp_eeprom)
1197 {
1198 struct xgbe_sfp_ascii sfp_ascii;
1199 char *sfp_data = (char *)&sfp_ascii;
1200
1201 netif_dbg(pdata, drv, pdata->netdev, "SFP detected:\n");
1202 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
1203 XGBE_SFP_BASE_VENDOR_NAME_LEN);
1204 sfp_data[XGBE_SFP_BASE_VENDOR_NAME_LEN] = '\0';
1205 netif_dbg(pdata, drv, pdata->netdev, " vendor: %s\n",
1206 sfp_data);
1207
1208 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
1209 XGBE_SFP_BASE_VENDOR_PN_LEN);
1210 sfp_data[XGBE_SFP_BASE_VENDOR_PN_LEN] = '\0';
1211 netif_dbg(pdata, drv, pdata->netdev, " part number: %s\n",
1212 sfp_data);
1213
1214 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_REV],
1215 XGBE_SFP_BASE_VENDOR_REV_LEN);
1216 sfp_data[XGBE_SFP_BASE_VENDOR_REV_LEN] = '\0';
1217 netif_dbg(pdata, drv, pdata->netdev, " revision level: %s\n",
1218 sfp_data);
1219
1220 memcpy(sfp_data, &sfp_eeprom->extd[XGBE_SFP_BASE_VENDOR_SN],
1221 XGBE_SFP_BASE_VENDOR_SN_LEN);
1222 sfp_data[XGBE_SFP_BASE_VENDOR_SN_LEN] = '\0';
1223 netif_dbg(pdata, drv, pdata->netdev, " serial number: %s\n",
1224 sfp_data);
1225 }
1226
xgbe_phy_sfp_verify_eeprom(u8 cc_in,u8 * buf,unsigned int len)1227 static bool xgbe_phy_sfp_verify_eeprom(u8 cc_in, u8 *buf, unsigned int len)
1228 {
1229 u8 cc;
1230
1231 for (cc = 0; len; buf++, len--)
1232 cc += *buf;
1233
1234 return cc == cc_in;
1235 }
1236
xgbe_phy_sfp_read_eeprom(struct xgbe_prv_data * pdata)1237 static int xgbe_phy_sfp_read_eeprom(struct xgbe_prv_data *pdata)
1238 {
1239 struct xgbe_phy_data *phy_data = pdata->phy_data;
1240 struct xgbe_sfp_eeprom sfp_eeprom;
1241 u8 eeprom_addr;
1242 int ret;
1243
1244 ret = xgbe_phy_sfp_get_mux(pdata);
1245 if (ret) {
1246 dev_err_once(pdata->dev, "%s: I2C error setting SFP MUX\n",
1247 netdev_name(pdata->netdev));
1248 return ret;
1249 }
1250
1251 /* Read the SFP serial ID eeprom */
1252 eeprom_addr = 0;
1253 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS,
1254 &eeprom_addr, sizeof(eeprom_addr),
1255 &sfp_eeprom, sizeof(sfp_eeprom));
1256 if (ret) {
1257 dev_err_once(pdata->dev, "%s: I2C error reading SFP EEPROM\n",
1258 netdev_name(pdata->netdev));
1259 goto put;
1260 }
1261
1262 /* Validate the contents read */
1263 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[XGBE_SFP_BASE_CC],
1264 sfp_eeprom.base,
1265 sizeof(sfp_eeprom.base) - 1)) {
1266 ret = -EINVAL;
1267 goto put;
1268 }
1269
1270 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[XGBE_SFP_EXTD_CC],
1271 sfp_eeprom.extd,
1272 sizeof(sfp_eeprom.extd) - 1)) {
1273 ret = -EINVAL;
1274 goto put;
1275 }
1276
1277 /* Check for an added or changed SFP */
1278 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) {
1279 phy_data->sfp_changed = 1;
1280
1281 if (netif_msg_drv(pdata))
1282 xgbe_phy_sfp_eeprom_info(pdata, &sfp_eeprom);
1283
1284 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom));
1285
1286 xgbe_phy_free_phy_device(pdata);
1287 } else {
1288 phy_data->sfp_changed = 0;
1289 }
1290
1291 put:
1292 xgbe_phy_sfp_put_mux(pdata);
1293
1294 return ret;
1295 }
1296
xgbe_phy_sfp_signals(struct xgbe_prv_data * pdata)1297 static void xgbe_phy_sfp_signals(struct xgbe_prv_data *pdata)
1298 {
1299 struct xgbe_phy_data *phy_data = pdata->phy_data;
1300 u8 gpio_reg, gpio_ports[2];
1301 int ret;
1302
1303 /* Read the input port registers */
1304 gpio_reg = 0;
1305 ret = xgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address,
1306 &gpio_reg, sizeof(gpio_reg),
1307 gpio_ports, sizeof(gpio_ports));
1308 if (ret) {
1309 dev_err_once(pdata->dev, "%s: I2C error reading SFP GPIOs\n",
1310 netdev_name(pdata->netdev));
1311 return;
1312 }
1313
1314 phy_data->sfp_gpio_inputs = (gpio_ports[1] << 8) | gpio_ports[0];
1315
1316 phy_data->sfp_mod_absent = xgbe_phy_check_sfp_mod_absent(phy_data);
1317 }
1318
xgbe_phy_sfp_mod_absent(struct xgbe_prv_data * pdata)1319 static void xgbe_phy_sfp_mod_absent(struct xgbe_prv_data *pdata)
1320 {
1321 struct xgbe_phy_data *phy_data = pdata->phy_data;
1322
1323 xgbe_phy_free_phy_device(pdata);
1324
1325 phy_data->sfp_mod_absent = 1;
1326 phy_data->sfp_phy_avail = 0;
1327 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom));
1328 }
1329
xgbe_phy_sfp_reset(struct xgbe_phy_data * phy_data)1330 static void xgbe_phy_sfp_reset(struct xgbe_phy_data *phy_data)
1331 {
1332 phy_data->sfp_rx_los = 0;
1333 phy_data->sfp_tx_fault = 0;
1334 phy_data->sfp_mod_absent = 1;
1335 phy_data->sfp_base = XGBE_SFP_BASE_UNKNOWN;
1336 phy_data->sfp_cable = XGBE_SFP_CABLE_UNKNOWN;
1337 phy_data->sfp_speed = XGBE_SFP_SPEED_UNKNOWN;
1338 }
1339
xgbe_phy_sfp_detect(struct xgbe_prv_data * pdata)1340 static void xgbe_phy_sfp_detect(struct xgbe_prv_data *pdata)
1341 {
1342 struct xgbe_phy_data *phy_data = pdata->phy_data;
1343 int ret;
1344
1345 /* Reset the SFP signals and info */
1346 xgbe_phy_sfp_reset(phy_data);
1347
1348 ret = xgbe_phy_get_comm_ownership(pdata);
1349 if (ret)
1350 return;
1351
1352 /* Read the SFP signals and check for module presence */
1353 xgbe_phy_sfp_signals(pdata);
1354 if (phy_data->sfp_mod_absent) {
1355 xgbe_phy_sfp_mod_absent(pdata);
1356 goto put;
1357 }
1358
1359 ret = xgbe_phy_sfp_read_eeprom(pdata);
1360 if (ret) {
1361 /* Treat any error as if there isn't an SFP plugged in */
1362 xgbe_phy_sfp_reset(phy_data);
1363 xgbe_phy_sfp_mod_absent(pdata);
1364 goto put;
1365 }
1366
1367 xgbe_phy_sfp_parse_eeprom(pdata);
1368
1369 xgbe_phy_sfp_external_phy(pdata);
1370
1371 put:
1372 xgbe_phy_sfp_phy_settings(pdata);
1373
1374 xgbe_phy_put_comm_ownership(pdata);
1375 }
1376
xgbe_phy_module_eeprom(struct xgbe_prv_data * pdata,struct ethtool_eeprom * eeprom,u8 * data)1377 static int xgbe_phy_module_eeprom(struct xgbe_prv_data *pdata,
1378 struct ethtool_eeprom *eeprom, u8 *data)
1379 {
1380 struct xgbe_phy_data *phy_data = pdata->phy_data;
1381 u8 eeprom_addr, eeprom_data[XGBE_SFP_EEPROM_MAX];
1382 struct xgbe_sfp_eeprom *sfp_eeprom;
1383 unsigned int i, j, rem;
1384 int ret;
1385
1386 rem = eeprom->len;
1387
1388 if (!eeprom->len) {
1389 ret = -EINVAL;
1390 goto done;
1391 }
1392
1393 if ((eeprom->offset + eeprom->len) > XGBE_SFP_EEPROM_MAX) {
1394 ret = -EINVAL;
1395 goto done;
1396 }
1397
1398 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) {
1399 ret = -ENXIO;
1400 goto done;
1401 }
1402
1403 if (!netif_running(pdata->netdev)) {
1404 ret = -EIO;
1405 goto done;
1406 }
1407
1408 if (phy_data->sfp_mod_absent) {
1409 ret = -EIO;
1410 goto done;
1411 }
1412
1413 ret = xgbe_phy_get_comm_ownership(pdata);
1414 if (ret) {
1415 ret = -EIO;
1416 goto done;
1417 }
1418
1419 ret = xgbe_phy_sfp_get_mux(pdata);
1420 if (ret) {
1421 netdev_err(pdata->netdev, "I2C error setting SFP MUX\n");
1422 ret = -EIO;
1423 goto put_own;
1424 }
1425
1426 /* Read the SFP serial ID eeprom */
1427 eeprom_addr = 0;
1428 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS,
1429 &eeprom_addr, sizeof(eeprom_addr),
1430 eeprom_data, XGBE_SFP_EEPROM_BASE_LEN);
1431 if (ret) {
1432 netdev_err(pdata->netdev,
1433 "I2C error reading SFP EEPROM\n");
1434 ret = -EIO;
1435 goto put_mux;
1436 }
1437
1438 sfp_eeprom = (struct xgbe_sfp_eeprom *)eeprom_data;
1439
1440 if (XGBE_SFP_DIAGS_SUPPORTED(sfp_eeprom)) {
1441 /* Read the SFP diagnostic eeprom */
1442 eeprom_addr = 0;
1443 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_DIAG_INFO_ADDRESS,
1444 &eeprom_addr, sizeof(eeprom_addr),
1445 eeprom_data + XGBE_SFP_EEPROM_BASE_LEN,
1446 XGBE_SFP_EEPROM_DIAG_LEN);
1447 if (ret) {
1448 netdev_err(pdata->netdev,
1449 "I2C error reading SFP DIAGS\n");
1450 ret = -EIO;
1451 goto put_mux;
1452 }
1453 }
1454
1455 for (i = 0, j = eeprom->offset; i < eeprom->len; i++, j++) {
1456 if ((j >= XGBE_SFP_EEPROM_BASE_LEN) &&
1457 !XGBE_SFP_DIAGS_SUPPORTED(sfp_eeprom))
1458 break;
1459
1460 data[i] = eeprom_data[j];
1461 rem--;
1462 }
1463
1464 put_mux:
1465 xgbe_phy_sfp_put_mux(pdata);
1466
1467 put_own:
1468 xgbe_phy_put_comm_ownership(pdata);
1469
1470 done:
1471 eeprom->len -= rem;
1472
1473 return ret;
1474 }
1475
xgbe_phy_module_info(struct xgbe_prv_data * pdata,struct ethtool_modinfo * modinfo)1476 static int xgbe_phy_module_info(struct xgbe_prv_data *pdata,
1477 struct ethtool_modinfo *modinfo)
1478 {
1479 struct xgbe_phy_data *phy_data = pdata->phy_data;
1480
1481 if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
1482 return -ENXIO;
1483
1484 if (!netif_running(pdata->netdev))
1485 return -EIO;
1486
1487 if (phy_data->sfp_mod_absent)
1488 return -EIO;
1489
1490 if (XGBE_SFP_DIAGS_SUPPORTED(&phy_data->sfp_eeprom)) {
1491 modinfo->type = ETH_MODULE_SFF_8472;
1492 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1493 } else {
1494 modinfo->type = ETH_MODULE_SFF_8079;
1495 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
1496 }
1497
1498 return 0;
1499 }
1500
xgbe_phy_phydev_flowctrl(struct xgbe_prv_data * pdata)1501 static void xgbe_phy_phydev_flowctrl(struct xgbe_prv_data *pdata)
1502 {
1503 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1504 struct xgbe_phy_data *phy_data = pdata->phy_data;
1505 u16 lcl_adv = 0, rmt_adv = 0;
1506 u8 fc;
1507
1508 pdata->phy.tx_pause = 0;
1509 pdata->phy.rx_pause = 0;
1510
1511 if (!phy_data->phydev)
1512 return;
1513
1514 lcl_adv = linkmode_adv_to_lcl_adv_t(phy_data->phydev->advertising);
1515
1516 if (phy_data->phydev->pause) {
1517 XGBE_SET_LP_ADV(lks, Pause);
1518 rmt_adv |= LPA_PAUSE_CAP;
1519 }
1520 if (phy_data->phydev->asym_pause) {
1521 XGBE_SET_LP_ADV(lks, Asym_Pause);
1522 rmt_adv |= LPA_PAUSE_ASYM;
1523 }
1524
1525 fc = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
1526 if (fc & FLOW_CTRL_TX)
1527 pdata->phy.tx_pause = 1;
1528 if (fc & FLOW_CTRL_RX)
1529 pdata->phy.rx_pause = 1;
1530 }
1531
xgbe_phy_an37_sgmii_outcome(struct xgbe_prv_data * pdata)1532 static enum xgbe_mode xgbe_phy_an37_sgmii_outcome(struct xgbe_prv_data *pdata)
1533 {
1534 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1535 enum xgbe_mode mode;
1536
1537 XGBE_SET_LP_ADV(lks, Autoneg);
1538 XGBE_SET_LP_ADV(lks, TP);
1539
1540 /* Use external PHY to determine flow control */
1541 if (pdata->phy.pause_autoneg)
1542 xgbe_phy_phydev_flowctrl(pdata);
1543
1544 switch (pdata->an_status & XGBE_SGMII_AN_LINK_SPEED) {
1545 case XGBE_SGMII_AN_LINK_SPEED_100:
1546 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
1547 XGBE_SET_LP_ADV(lks, 100baseT_Full);
1548 mode = XGBE_MODE_SGMII_100;
1549 } else {
1550 /* Half-duplex not supported */
1551 XGBE_SET_LP_ADV(lks, 100baseT_Half);
1552 mode = XGBE_MODE_UNKNOWN;
1553 }
1554 break;
1555 case XGBE_SGMII_AN_LINK_SPEED_1000:
1556 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
1557 XGBE_SET_LP_ADV(lks, 1000baseT_Full);
1558 mode = XGBE_MODE_SGMII_1000;
1559 } else {
1560 /* Half-duplex not supported */
1561 XGBE_SET_LP_ADV(lks, 1000baseT_Half);
1562 mode = XGBE_MODE_UNKNOWN;
1563 }
1564 break;
1565 default:
1566 mode = XGBE_MODE_UNKNOWN;
1567 }
1568
1569 return mode;
1570 }
1571
xgbe_phy_an37_outcome(struct xgbe_prv_data * pdata)1572 static enum xgbe_mode xgbe_phy_an37_outcome(struct xgbe_prv_data *pdata)
1573 {
1574 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1575 enum xgbe_mode mode;
1576 unsigned int ad_reg, lp_reg;
1577
1578 XGBE_SET_LP_ADV(lks, Autoneg);
1579 XGBE_SET_LP_ADV(lks, FIBRE);
1580
1581 /* Compare Advertisement and Link Partner register */
1582 ad_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE);
1583 lp_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_LP_ABILITY);
1584 if (lp_reg & 0x100)
1585 XGBE_SET_LP_ADV(lks, Pause);
1586 if (lp_reg & 0x80)
1587 XGBE_SET_LP_ADV(lks, Asym_Pause);
1588
1589 if (pdata->phy.pause_autoneg) {
1590 /* Set flow control based on auto-negotiation result */
1591 pdata->phy.tx_pause = 0;
1592 pdata->phy.rx_pause = 0;
1593
1594 if (ad_reg & lp_reg & 0x100) {
1595 pdata->phy.tx_pause = 1;
1596 pdata->phy.rx_pause = 1;
1597 } else if (ad_reg & lp_reg & 0x80) {
1598 if (ad_reg & 0x100)
1599 pdata->phy.rx_pause = 1;
1600 else if (lp_reg & 0x100)
1601 pdata->phy.tx_pause = 1;
1602 }
1603 }
1604
1605 if (lp_reg & 0x20)
1606 XGBE_SET_LP_ADV(lks, 1000baseX_Full);
1607
1608 /* Half duplex is not supported */
1609 ad_reg &= lp_reg;
1610 mode = (ad_reg & 0x20) ? XGBE_MODE_X : XGBE_MODE_UNKNOWN;
1611
1612 return mode;
1613 }
1614
xgbe_phy_an73_redrv_outcome(struct xgbe_prv_data * pdata)1615 static enum xgbe_mode xgbe_phy_an73_redrv_outcome(struct xgbe_prv_data *pdata)
1616 {
1617 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1618 struct xgbe_phy_data *phy_data = pdata->phy_data;
1619 enum xgbe_mode mode;
1620 unsigned int ad_reg, lp_reg;
1621
1622 XGBE_SET_LP_ADV(lks, Autoneg);
1623 XGBE_SET_LP_ADV(lks, Backplane);
1624
1625 /* Use external PHY to determine flow control */
1626 if (pdata->phy.pause_autoneg)
1627 xgbe_phy_phydev_flowctrl(pdata);
1628
1629 /* Compare Advertisement and Link Partner register 2 */
1630 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1631 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
1632 if (lp_reg & 0x80)
1633 XGBE_SET_LP_ADV(lks, 10000baseKR_Full);
1634 if (lp_reg & 0x20)
1635 XGBE_SET_LP_ADV(lks, 1000baseKX_Full);
1636
1637 ad_reg &= lp_reg;
1638 if (ad_reg & 0x80) {
1639 switch (phy_data->port_mode) {
1640 case XGBE_PORT_MODE_BACKPLANE:
1641 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
1642 mode = XGBE_MODE_KR;
1643 break;
1644 default:
1645 mode = XGBE_MODE_SFI;
1646 break;
1647 }
1648 } else if (ad_reg & 0x20) {
1649 switch (phy_data->port_mode) {
1650 case XGBE_PORT_MODE_BACKPLANE:
1651 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
1652 mode = XGBE_MODE_KX_1000;
1653 break;
1654 case XGBE_PORT_MODE_1000BASE_X:
1655 mode = XGBE_MODE_X;
1656 break;
1657 case XGBE_PORT_MODE_SFP:
1658 switch (phy_data->sfp_base) {
1659 case XGBE_SFP_BASE_1000_T:
1660 if (phy_data->phydev &&
1661 (phy_data->phydev->speed == SPEED_100))
1662 mode = XGBE_MODE_SGMII_100;
1663 else
1664 mode = XGBE_MODE_SGMII_1000;
1665 break;
1666 case XGBE_SFP_BASE_1000_SX:
1667 case XGBE_SFP_BASE_1000_LX:
1668 case XGBE_SFP_BASE_1000_CX:
1669 default:
1670 mode = XGBE_MODE_X;
1671 break;
1672 }
1673 break;
1674 default:
1675 if (phy_data->phydev &&
1676 (phy_data->phydev->speed == SPEED_100))
1677 mode = XGBE_MODE_SGMII_100;
1678 else
1679 mode = XGBE_MODE_SGMII_1000;
1680 break;
1681 }
1682 } else {
1683 mode = XGBE_MODE_UNKNOWN;
1684 }
1685
1686 /* Compare Advertisement and Link Partner register 3 */
1687 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1688 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
1689 if (lp_reg & 0xc000)
1690 XGBE_SET_LP_ADV(lks, 10000baseR_FEC);
1691
1692 return mode;
1693 }
1694
xgbe_phy_an73_outcome(struct xgbe_prv_data * pdata)1695 static enum xgbe_mode xgbe_phy_an73_outcome(struct xgbe_prv_data *pdata)
1696 {
1697 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1698 enum xgbe_mode mode;
1699 unsigned int ad_reg, lp_reg;
1700
1701 XGBE_SET_LP_ADV(lks, Autoneg);
1702 XGBE_SET_LP_ADV(lks, Backplane);
1703
1704 /* Compare Advertisement and Link Partner register 1 */
1705 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
1706 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
1707 if (lp_reg & 0x400)
1708 XGBE_SET_LP_ADV(lks, Pause);
1709 if (lp_reg & 0x800)
1710 XGBE_SET_LP_ADV(lks, Asym_Pause);
1711
1712 if (pdata->phy.pause_autoneg) {
1713 /* Set flow control based on auto-negotiation result */
1714 pdata->phy.tx_pause = 0;
1715 pdata->phy.rx_pause = 0;
1716
1717 if (ad_reg & lp_reg & 0x400) {
1718 pdata->phy.tx_pause = 1;
1719 pdata->phy.rx_pause = 1;
1720 } else if (ad_reg & lp_reg & 0x800) {
1721 if (ad_reg & 0x400)
1722 pdata->phy.rx_pause = 1;
1723 else if (lp_reg & 0x400)
1724 pdata->phy.tx_pause = 1;
1725 }
1726 }
1727
1728 /* Compare Advertisement and Link Partner register 2 */
1729 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1730 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
1731 if (lp_reg & 0x80)
1732 XGBE_SET_LP_ADV(lks, 10000baseKR_Full);
1733 if (lp_reg & 0x20)
1734 XGBE_SET_LP_ADV(lks, 1000baseKX_Full);
1735
1736 ad_reg &= lp_reg;
1737 if (ad_reg & 0x80)
1738 mode = XGBE_MODE_KR;
1739 else if (ad_reg & 0x20)
1740 mode = XGBE_MODE_KX_1000;
1741 else
1742 mode = XGBE_MODE_UNKNOWN;
1743
1744 /* Compare Advertisement and Link Partner register 3 */
1745 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1746 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
1747 if (lp_reg & 0xc000)
1748 XGBE_SET_LP_ADV(lks, 10000baseR_FEC);
1749
1750 return mode;
1751 }
1752
xgbe_phy_an_outcome(struct xgbe_prv_data * pdata)1753 static enum xgbe_mode xgbe_phy_an_outcome(struct xgbe_prv_data *pdata)
1754 {
1755 switch (pdata->an_mode) {
1756 case XGBE_AN_MODE_CL73:
1757 return xgbe_phy_an73_outcome(pdata);
1758 case XGBE_AN_MODE_CL73_REDRV:
1759 return xgbe_phy_an73_redrv_outcome(pdata);
1760 case XGBE_AN_MODE_CL37:
1761 return xgbe_phy_an37_outcome(pdata);
1762 case XGBE_AN_MODE_CL37_SGMII:
1763 return xgbe_phy_an37_sgmii_outcome(pdata);
1764 default:
1765 return XGBE_MODE_UNKNOWN;
1766 }
1767 }
1768
xgbe_phy_an_advertising(struct xgbe_prv_data * pdata,struct ethtool_link_ksettings * dlks)1769 static void xgbe_phy_an_advertising(struct xgbe_prv_data *pdata,
1770 struct ethtool_link_ksettings *dlks)
1771 {
1772 struct ethtool_link_ksettings *slks = &pdata->phy.lks;
1773 struct xgbe_phy_data *phy_data = pdata->phy_data;
1774
1775 XGBE_LM_COPY(dlks, advertising, slks, advertising);
1776
1777 /* Without a re-driver, just return current advertising */
1778 if (!phy_data->redrv)
1779 return;
1780
1781 /* With the KR re-driver we need to advertise a single speed */
1782 XGBE_CLR_ADV(dlks, 1000baseKX_Full);
1783 XGBE_CLR_ADV(dlks, 10000baseKR_Full);
1784
1785 /* Advertise FEC support is present */
1786 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
1787 XGBE_SET_ADV(dlks, 10000baseR_FEC);
1788
1789 switch (phy_data->port_mode) {
1790 case XGBE_PORT_MODE_BACKPLANE:
1791 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
1792 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1793 break;
1794 case XGBE_PORT_MODE_BACKPLANE_2500:
1795 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1796 break;
1797 case XGBE_PORT_MODE_1000BASE_T:
1798 case XGBE_PORT_MODE_1000BASE_X:
1799 case XGBE_PORT_MODE_NBASE_T:
1800 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1801 break;
1802 case XGBE_PORT_MODE_10GBASE_T:
1803 if (phy_data->phydev &&
1804 (phy_data->phydev->speed == SPEED_10000))
1805 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1806 else
1807 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1808 break;
1809 case XGBE_PORT_MODE_10GBASE_R:
1810 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1811 break;
1812 case XGBE_PORT_MODE_SFP:
1813 switch (phy_data->sfp_base) {
1814 case XGBE_SFP_BASE_1000_T:
1815 case XGBE_SFP_BASE_1000_SX:
1816 case XGBE_SFP_BASE_1000_LX:
1817 case XGBE_SFP_BASE_1000_CX:
1818 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1819 break;
1820 default:
1821 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1822 break;
1823 }
1824 break;
1825 default:
1826 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1827 break;
1828 }
1829 }
1830
xgbe_phy_an_config(struct xgbe_prv_data * pdata)1831 static int xgbe_phy_an_config(struct xgbe_prv_data *pdata)
1832 {
1833 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1834 struct xgbe_phy_data *phy_data = pdata->phy_data;
1835 int ret;
1836
1837 ret = xgbe_phy_find_phy_device(pdata);
1838 if (ret)
1839 return ret;
1840
1841 if (!phy_data->phydev)
1842 return 0;
1843
1844 phy_data->phydev->autoneg = pdata->phy.autoneg;
1845 linkmode_and(phy_data->phydev->advertising,
1846 phy_data->phydev->supported,
1847 lks->link_modes.advertising);
1848
1849 if (pdata->phy.autoneg != AUTONEG_ENABLE) {
1850 phy_data->phydev->speed = pdata->phy.speed;
1851 phy_data->phydev->duplex = pdata->phy.duplex;
1852 }
1853
1854 ret = phy_start_aneg(phy_data->phydev);
1855
1856 return ret;
1857 }
1858
xgbe_phy_an_sfp_mode(struct xgbe_phy_data * phy_data)1859 static enum xgbe_an_mode xgbe_phy_an_sfp_mode(struct xgbe_phy_data *phy_data)
1860 {
1861 switch (phy_data->sfp_base) {
1862 case XGBE_SFP_BASE_1000_T:
1863 return XGBE_AN_MODE_CL37_SGMII;
1864 case XGBE_SFP_BASE_1000_SX:
1865 case XGBE_SFP_BASE_1000_LX:
1866 case XGBE_SFP_BASE_1000_CX:
1867 return XGBE_AN_MODE_CL37;
1868 default:
1869 return XGBE_AN_MODE_NONE;
1870 }
1871 }
1872
xgbe_phy_an_mode(struct xgbe_prv_data * pdata)1873 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata)
1874 {
1875 struct xgbe_phy_data *phy_data = pdata->phy_data;
1876
1877 /* A KR re-driver will always require CL73 AN */
1878 if (phy_data->redrv)
1879 return XGBE_AN_MODE_CL73_REDRV;
1880
1881 switch (phy_data->port_mode) {
1882 case XGBE_PORT_MODE_BACKPLANE:
1883 return XGBE_AN_MODE_CL73;
1884 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
1885 case XGBE_PORT_MODE_BACKPLANE_2500:
1886 return XGBE_AN_MODE_NONE;
1887 case XGBE_PORT_MODE_1000BASE_T:
1888 return XGBE_AN_MODE_CL37_SGMII;
1889 case XGBE_PORT_MODE_1000BASE_X:
1890 return XGBE_AN_MODE_CL37;
1891 case XGBE_PORT_MODE_NBASE_T:
1892 return XGBE_AN_MODE_CL37_SGMII;
1893 case XGBE_PORT_MODE_10GBASE_T:
1894 return XGBE_AN_MODE_CL73;
1895 case XGBE_PORT_MODE_10GBASE_R:
1896 return XGBE_AN_MODE_NONE;
1897 case XGBE_PORT_MODE_SFP:
1898 return xgbe_phy_an_sfp_mode(phy_data);
1899 default:
1900 return XGBE_AN_MODE_NONE;
1901 }
1902 }
1903
xgbe_phy_set_redrv_mode_mdio(struct xgbe_prv_data * pdata,enum xgbe_phy_redrv_mode mode)1904 static int xgbe_phy_set_redrv_mode_mdio(struct xgbe_prv_data *pdata,
1905 enum xgbe_phy_redrv_mode mode)
1906 {
1907 struct xgbe_phy_data *phy_data = pdata->phy_data;
1908 u16 redrv_reg, redrv_val;
1909
1910 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1911 redrv_val = (u16)mode;
1912
1913 return pdata->hw_if.write_ext_mii_regs(pdata, phy_data->redrv_addr,
1914 redrv_reg, redrv_val);
1915 }
1916
xgbe_phy_set_redrv_mode_i2c(struct xgbe_prv_data * pdata,enum xgbe_phy_redrv_mode mode)1917 static int xgbe_phy_set_redrv_mode_i2c(struct xgbe_prv_data *pdata,
1918 enum xgbe_phy_redrv_mode mode)
1919 {
1920 struct xgbe_phy_data *phy_data = pdata->phy_data;
1921 unsigned int redrv_reg;
1922 int ret;
1923
1924 /* Calculate the register to write */
1925 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1926
1927 ret = xgbe_phy_redrv_write(pdata, redrv_reg, mode);
1928
1929 return ret;
1930 }
1931
xgbe_phy_set_redrv_mode(struct xgbe_prv_data * pdata)1932 static void xgbe_phy_set_redrv_mode(struct xgbe_prv_data *pdata)
1933 {
1934 struct xgbe_phy_data *phy_data = pdata->phy_data;
1935 enum xgbe_phy_redrv_mode mode;
1936 int ret;
1937
1938 if (!phy_data->redrv)
1939 return;
1940
1941 mode = XGBE_PHY_REDRV_MODE_CX;
1942 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
1943 (phy_data->sfp_base != XGBE_SFP_BASE_1000_CX) &&
1944 (phy_data->sfp_base != XGBE_SFP_BASE_10000_CR))
1945 mode = XGBE_PHY_REDRV_MODE_SR;
1946
1947 ret = xgbe_phy_get_comm_ownership(pdata);
1948 if (ret)
1949 return;
1950
1951 if (phy_data->redrv_if)
1952 xgbe_phy_set_redrv_mode_i2c(pdata, mode);
1953 else
1954 xgbe_phy_set_redrv_mode_mdio(pdata, mode);
1955
1956 xgbe_phy_put_comm_ownership(pdata);
1957 }
1958
xgbe_phy_rx_reset(struct xgbe_prv_data * pdata)1959 static void xgbe_phy_rx_reset(struct xgbe_prv_data *pdata)
1960 {
1961 int reg;
1962
1963 reg = XMDIO_READ_BITS(pdata, MDIO_MMD_PCS, MDIO_PCS_DIGITAL_STAT,
1964 XGBE_PCS_PSEQ_STATE_MASK);
1965 if (reg == XGBE_PCS_PSEQ_STATE_POWER_GOOD) {
1966 /* Mailbox command timed out, reset of RX block is required.
1967 * This can be done by asseting the reset bit and wait for
1968 * its compeletion.
1969 */
1970 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1,
1971 XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_ON);
1972 ndelay(20);
1973 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1,
1974 XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_OFF);
1975 usleep_range(40, 50);
1976 netif_err(pdata, link, pdata->netdev, "firmware mailbox reset performed\n");
1977 }
1978 }
1979
xgbe_phy_perform_ratechange(struct xgbe_prv_data * pdata,unsigned int cmd,unsigned int sub_cmd)1980 static void xgbe_phy_perform_ratechange(struct xgbe_prv_data *pdata,
1981 unsigned int cmd, unsigned int sub_cmd)
1982 {
1983 unsigned int s0 = 0;
1984 unsigned int wait;
1985
1986 /* Log if a previous command did not complete */
1987 if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) {
1988 netif_dbg(pdata, link, pdata->netdev,
1989 "firmware mailbox not ready for command\n");
1990 xgbe_phy_rx_reset(pdata);
1991 }
1992
1993 /* Construct the command */
1994 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd);
1995 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, sub_cmd);
1996
1997 /* Issue the command */
1998 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
1999 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
2000 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
2001
2002 /* Wait for command to complete */
2003 wait = XGBE_RATECHANGE_COUNT;
2004 while (wait--) {
2005 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
2006 return;
2007
2008 usleep_range(1000, 2000);
2009 }
2010
2011 netif_dbg(pdata, link, pdata->netdev,
2012 "firmware mailbox command did not complete\n");
2013
2014 /* Reset on error */
2015 xgbe_phy_rx_reset(pdata);
2016 }
2017
xgbe_phy_rrc(struct xgbe_prv_data * pdata)2018 static void xgbe_phy_rrc(struct xgbe_prv_data *pdata)
2019 {
2020 /* Receiver Reset Cycle */
2021 xgbe_phy_perform_ratechange(pdata, 5, 0);
2022
2023 netif_dbg(pdata, link, pdata->netdev, "receiver reset complete\n");
2024 }
2025
xgbe_phy_power_off(struct xgbe_prv_data * pdata)2026 static void xgbe_phy_power_off(struct xgbe_prv_data *pdata)
2027 {
2028 struct xgbe_phy_data *phy_data = pdata->phy_data;
2029
2030 /* Power off */
2031 xgbe_phy_perform_ratechange(pdata, 0, 0);
2032
2033 phy_data->cur_mode = XGBE_MODE_UNKNOWN;
2034
2035 netif_dbg(pdata, link, pdata->netdev, "phy powered off\n");
2036 }
2037
xgbe_phy_sfi_mode(struct xgbe_prv_data * pdata)2038 static void xgbe_phy_sfi_mode(struct xgbe_prv_data *pdata)
2039 {
2040 struct xgbe_phy_data *phy_data = pdata->phy_data;
2041
2042 xgbe_phy_set_redrv_mode(pdata);
2043
2044 /* 10G/SFI */
2045 if (phy_data->sfp_cable != XGBE_SFP_CABLE_PASSIVE) {
2046 xgbe_phy_perform_ratechange(pdata, 3, 0);
2047 } else {
2048 if (phy_data->sfp_cable_len <= 1)
2049 xgbe_phy_perform_ratechange(pdata, 3, 1);
2050 else if (phy_data->sfp_cable_len <= 3)
2051 xgbe_phy_perform_ratechange(pdata, 3, 2);
2052 else
2053 xgbe_phy_perform_ratechange(pdata, 3, 3);
2054 }
2055
2056 phy_data->cur_mode = XGBE_MODE_SFI;
2057
2058 netif_dbg(pdata, link, pdata->netdev, "10GbE SFI mode set\n");
2059 }
2060
xgbe_phy_x_mode(struct xgbe_prv_data * pdata)2061 static void xgbe_phy_x_mode(struct xgbe_prv_data *pdata)
2062 {
2063 struct xgbe_phy_data *phy_data = pdata->phy_data;
2064
2065 xgbe_phy_set_redrv_mode(pdata);
2066
2067 /* 1G/X */
2068 xgbe_phy_perform_ratechange(pdata, 1, 3);
2069
2070 phy_data->cur_mode = XGBE_MODE_X;
2071
2072 netif_dbg(pdata, link, pdata->netdev, "1GbE X mode set\n");
2073 }
2074
xgbe_phy_sgmii_1000_mode(struct xgbe_prv_data * pdata)2075 static void xgbe_phy_sgmii_1000_mode(struct xgbe_prv_data *pdata)
2076 {
2077 struct xgbe_phy_data *phy_data = pdata->phy_data;
2078
2079 xgbe_phy_set_redrv_mode(pdata);
2080
2081 /* 1G/SGMII */
2082 xgbe_phy_perform_ratechange(pdata, 1, 2);
2083
2084 phy_data->cur_mode = XGBE_MODE_SGMII_1000;
2085
2086 netif_dbg(pdata, link, pdata->netdev, "1GbE SGMII mode set\n");
2087 }
2088
xgbe_phy_sgmii_100_mode(struct xgbe_prv_data * pdata)2089 static void xgbe_phy_sgmii_100_mode(struct xgbe_prv_data *pdata)
2090 {
2091 struct xgbe_phy_data *phy_data = pdata->phy_data;
2092
2093 xgbe_phy_set_redrv_mode(pdata);
2094
2095 /* 100M/SGMII */
2096 xgbe_phy_perform_ratechange(pdata, 1, 1);
2097
2098 phy_data->cur_mode = XGBE_MODE_SGMII_100;
2099
2100 netif_dbg(pdata, link, pdata->netdev, "100MbE SGMII mode set\n");
2101 }
2102
xgbe_phy_kr_mode(struct xgbe_prv_data * pdata)2103 static void xgbe_phy_kr_mode(struct xgbe_prv_data *pdata)
2104 {
2105 struct xgbe_phy_data *phy_data = pdata->phy_data;
2106
2107 xgbe_phy_set_redrv_mode(pdata);
2108
2109 /* 10G/KR */
2110 xgbe_phy_perform_ratechange(pdata, 4, 0);
2111
2112 phy_data->cur_mode = XGBE_MODE_KR;
2113
2114 netif_dbg(pdata, link, pdata->netdev, "10GbE KR mode set\n");
2115 }
2116
xgbe_phy_kx_2500_mode(struct xgbe_prv_data * pdata)2117 static void xgbe_phy_kx_2500_mode(struct xgbe_prv_data *pdata)
2118 {
2119 struct xgbe_phy_data *phy_data = pdata->phy_data;
2120
2121 xgbe_phy_set_redrv_mode(pdata);
2122
2123 /* 2.5G/KX */
2124 xgbe_phy_perform_ratechange(pdata, 2, 0);
2125
2126 phy_data->cur_mode = XGBE_MODE_KX_2500;
2127
2128 netif_dbg(pdata, link, pdata->netdev, "2.5GbE KX mode set\n");
2129 }
2130
xgbe_phy_kx_1000_mode(struct xgbe_prv_data * pdata)2131 static void xgbe_phy_kx_1000_mode(struct xgbe_prv_data *pdata)
2132 {
2133 struct xgbe_phy_data *phy_data = pdata->phy_data;
2134
2135 xgbe_phy_set_redrv_mode(pdata);
2136
2137 /* 1G/KX */
2138 xgbe_phy_perform_ratechange(pdata, 1, 3);
2139
2140 phy_data->cur_mode = XGBE_MODE_KX_1000;
2141
2142 netif_dbg(pdata, link, pdata->netdev, "1GbE KX mode set\n");
2143 }
2144
xgbe_phy_cur_mode(struct xgbe_prv_data * pdata)2145 static enum xgbe_mode xgbe_phy_cur_mode(struct xgbe_prv_data *pdata)
2146 {
2147 struct xgbe_phy_data *phy_data = pdata->phy_data;
2148
2149 return phy_data->cur_mode;
2150 }
2151
xgbe_phy_switch_baset_mode(struct xgbe_prv_data * pdata)2152 static enum xgbe_mode xgbe_phy_switch_baset_mode(struct xgbe_prv_data *pdata)
2153 {
2154 struct xgbe_phy_data *phy_data = pdata->phy_data;
2155
2156 /* No switching if not 10GBase-T */
2157 if (phy_data->port_mode != XGBE_PORT_MODE_10GBASE_T)
2158 return xgbe_phy_cur_mode(pdata);
2159
2160 switch (xgbe_phy_cur_mode(pdata)) {
2161 case XGBE_MODE_SGMII_100:
2162 case XGBE_MODE_SGMII_1000:
2163 return XGBE_MODE_KR;
2164 case XGBE_MODE_KR:
2165 default:
2166 return XGBE_MODE_SGMII_1000;
2167 }
2168 }
2169
xgbe_phy_switch_bp_2500_mode(struct xgbe_prv_data * pdata)2170 static enum xgbe_mode xgbe_phy_switch_bp_2500_mode(struct xgbe_prv_data *pdata)
2171 {
2172 return XGBE_MODE_KX_2500;
2173 }
2174
xgbe_phy_switch_bp_mode(struct xgbe_prv_data * pdata)2175 static enum xgbe_mode xgbe_phy_switch_bp_mode(struct xgbe_prv_data *pdata)
2176 {
2177 /* If we are in KR switch to KX, and vice-versa */
2178 switch (xgbe_phy_cur_mode(pdata)) {
2179 case XGBE_MODE_KX_1000:
2180 return XGBE_MODE_KR;
2181 case XGBE_MODE_KR:
2182 default:
2183 return XGBE_MODE_KX_1000;
2184 }
2185 }
2186
xgbe_phy_switch_mode(struct xgbe_prv_data * pdata)2187 static enum xgbe_mode xgbe_phy_switch_mode(struct xgbe_prv_data *pdata)
2188 {
2189 struct xgbe_phy_data *phy_data = pdata->phy_data;
2190
2191 switch (phy_data->port_mode) {
2192 case XGBE_PORT_MODE_BACKPLANE:
2193 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
2194 return xgbe_phy_switch_bp_mode(pdata);
2195 case XGBE_PORT_MODE_BACKPLANE_2500:
2196 return xgbe_phy_switch_bp_2500_mode(pdata);
2197 case XGBE_PORT_MODE_1000BASE_T:
2198 case XGBE_PORT_MODE_NBASE_T:
2199 case XGBE_PORT_MODE_10GBASE_T:
2200 return xgbe_phy_switch_baset_mode(pdata);
2201 case XGBE_PORT_MODE_1000BASE_X:
2202 case XGBE_PORT_MODE_10GBASE_R:
2203 case XGBE_PORT_MODE_SFP:
2204 /* No switching, so just return current mode */
2205 return xgbe_phy_cur_mode(pdata);
2206 default:
2207 return XGBE_MODE_UNKNOWN;
2208 }
2209 }
2210
xgbe_phy_get_basex_mode(struct xgbe_phy_data * phy_data,int speed)2211 static enum xgbe_mode xgbe_phy_get_basex_mode(struct xgbe_phy_data *phy_data,
2212 int speed)
2213 {
2214 switch (speed) {
2215 case SPEED_1000:
2216 return XGBE_MODE_X;
2217 case SPEED_10000:
2218 return XGBE_MODE_KR;
2219 default:
2220 return XGBE_MODE_UNKNOWN;
2221 }
2222 }
2223
xgbe_phy_get_baset_mode(struct xgbe_phy_data * phy_data,int speed)2224 static enum xgbe_mode xgbe_phy_get_baset_mode(struct xgbe_phy_data *phy_data,
2225 int speed)
2226 {
2227 switch (speed) {
2228 case SPEED_100:
2229 return XGBE_MODE_SGMII_100;
2230 case SPEED_1000:
2231 return XGBE_MODE_SGMII_1000;
2232 case SPEED_2500:
2233 return XGBE_MODE_KX_2500;
2234 case SPEED_10000:
2235 return XGBE_MODE_KR;
2236 default:
2237 return XGBE_MODE_UNKNOWN;
2238 }
2239 }
2240
xgbe_phy_get_sfp_mode(struct xgbe_phy_data * phy_data,int speed)2241 static enum xgbe_mode xgbe_phy_get_sfp_mode(struct xgbe_phy_data *phy_data,
2242 int speed)
2243 {
2244 switch (speed) {
2245 case SPEED_100:
2246 return XGBE_MODE_SGMII_100;
2247 case SPEED_1000:
2248 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
2249 return XGBE_MODE_SGMII_1000;
2250 else
2251 return XGBE_MODE_X;
2252 case SPEED_10000:
2253 case SPEED_UNKNOWN:
2254 return XGBE_MODE_SFI;
2255 default:
2256 return XGBE_MODE_UNKNOWN;
2257 }
2258 }
2259
xgbe_phy_get_bp_2500_mode(int speed)2260 static enum xgbe_mode xgbe_phy_get_bp_2500_mode(int speed)
2261 {
2262 switch (speed) {
2263 case SPEED_2500:
2264 return XGBE_MODE_KX_2500;
2265 default:
2266 return XGBE_MODE_UNKNOWN;
2267 }
2268 }
2269
xgbe_phy_get_bp_mode(int speed)2270 static enum xgbe_mode xgbe_phy_get_bp_mode(int speed)
2271 {
2272 switch (speed) {
2273 case SPEED_1000:
2274 return XGBE_MODE_KX_1000;
2275 case SPEED_10000:
2276 return XGBE_MODE_KR;
2277 default:
2278 return XGBE_MODE_UNKNOWN;
2279 }
2280 }
2281
xgbe_phy_get_mode(struct xgbe_prv_data * pdata,int speed)2282 static enum xgbe_mode xgbe_phy_get_mode(struct xgbe_prv_data *pdata,
2283 int speed)
2284 {
2285 struct xgbe_phy_data *phy_data = pdata->phy_data;
2286
2287 switch (phy_data->port_mode) {
2288 case XGBE_PORT_MODE_BACKPLANE:
2289 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
2290 return xgbe_phy_get_bp_mode(speed);
2291 case XGBE_PORT_MODE_BACKPLANE_2500:
2292 return xgbe_phy_get_bp_2500_mode(speed);
2293 case XGBE_PORT_MODE_1000BASE_T:
2294 case XGBE_PORT_MODE_NBASE_T:
2295 case XGBE_PORT_MODE_10GBASE_T:
2296 return xgbe_phy_get_baset_mode(phy_data, speed);
2297 case XGBE_PORT_MODE_1000BASE_X:
2298 case XGBE_PORT_MODE_10GBASE_R:
2299 return xgbe_phy_get_basex_mode(phy_data, speed);
2300 case XGBE_PORT_MODE_SFP:
2301 return xgbe_phy_get_sfp_mode(phy_data, speed);
2302 default:
2303 return XGBE_MODE_UNKNOWN;
2304 }
2305 }
2306
xgbe_phy_set_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)2307 static void xgbe_phy_set_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2308 {
2309 switch (mode) {
2310 case XGBE_MODE_KX_1000:
2311 xgbe_phy_kx_1000_mode(pdata);
2312 break;
2313 case XGBE_MODE_KX_2500:
2314 xgbe_phy_kx_2500_mode(pdata);
2315 break;
2316 case XGBE_MODE_KR:
2317 xgbe_phy_kr_mode(pdata);
2318 break;
2319 case XGBE_MODE_SGMII_100:
2320 xgbe_phy_sgmii_100_mode(pdata);
2321 break;
2322 case XGBE_MODE_SGMII_1000:
2323 xgbe_phy_sgmii_1000_mode(pdata);
2324 break;
2325 case XGBE_MODE_X:
2326 xgbe_phy_x_mode(pdata);
2327 break;
2328 case XGBE_MODE_SFI:
2329 xgbe_phy_sfi_mode(pdata);
2330 break;
2331 default:
2332 break;
2333 }
2334 }
2335
xgbe_phy_check_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode,bool advert)2336 static bool xgbe_phy_check_mode(struct xgbe_prv_data *pdata,
2337 enum xgbe_mode mode, bool advert)
2338 {
2339 if (pdata->phy.autoneg == AUTONEG_ENABLE) {
2340 return advert;
2341 } else {
2342 enum xgbe_mode cur_mode;
2343
2344 cur_mode = xgbe_phy_get_mode(pdata, pdata->phy.speed);
2345 if (cur_mode == mode)
2346 return true;
2347 }
2348
2349 return false;
2350 }
2351
xgbe_phy_use_basex_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)2352 static bool xgbe_phy_use_basex_mode(struct xgbe_prv_data *pdata,
2353 enum xgbe_mode mode)
2354 {
2355 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2356
2357 switch (mode) {
2358 case XGBE_MODE_X:
2359 return xgbe_phy_check_mode(pdata, mode,
2360 XGBE_ADV(lks, 1000baseX_Full));
2361 case XGBE_MODE_KR:
2362 return xgbe_phy_check_mode(pdata, mode,
2363 XGBE_ADV(lks, 10000baseKR_Full));
2364 default:
2365 return false;
2366 }
2367 }
2368
xgbe_phy_use_baset_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)2369 static bool xgbe_phy_use_baset_mode(struct xgbe_prv_data *pdata,
2370 enum xgbe_mode mode)
2371 {
2372 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2373
2374 switch (mode) {
2375 case XGBE_MODE_SGMII_100:
2376 return xgbe_phy_check_mode(pdata, mode,
2377 XGBE_ADV(lks, 100baseT_Full));
2378 case XGBE_MODE_SGMII_1000:
2379 return xgbe_phy_check_mode(pdata, mode,
2380 XGBE_ADV(lks, 1000baseT_Full));
2381 case XGBE_MODE_KX_2500:
2382 return xgbe_phy_check_mode(pdata, mode,
2383 XGBE_ADV(lks, 2500baseT_Full));
2384 case XGBE_MODE_KR:
2385 return xgbe_phy_check_mode(pdata, mode,
2386 XGBE_ADV(lks, 10000baseT_Full));
2387 default:
2388 return false;
2389 }
2390 }
2391
xgbe_phy_use_sfp_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)2392 static bool xgbe_phy_use_sfp_mode(struct xgbe_prv_data *pdata,
2393 enum xgbe_mode mode)
2394 {
2395 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2396 struct xgbe_phy_data *phy_data = pdata->phy_data;
2397
2398 switch (mode) {
2399 case XGBE_MODE_X:
2400 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
2401 return false;
2402 return xgbe_phy_check_mode(pdata, mode,
2403 XGBE_ADV(lks, 1000baseX_Full));
2404 case XGBE_MODE_SGMII_100:
2405 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2406 return false;
2407 return xgbe_phy_check_mode(pdata, mode,
2408 XGBE_ADV(lks, 100baseT_Full));
2409 case XGBE_MODE_SGMII_1000:
2410 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2411 return false;
2412 return xgbe_phy_check_mode(pdata, mode,
2413 XGBE_ADV(lks, 1000baseT_Full));
2414 case XGBE_MODE_SFI:
2415 if (phy_data->sfp_mod_absent)
2416 return true;
2417 return xgbe_phy_check_mode(pdata, mode,
2418 XGBE_ADV(lks, 10000baseSR_Full) ||
2419 XGBE_ADV(lks, 10000baseLR_Full) ||
2420 XGBE_ADV(lks, 10000baseLRM_Full) ||
2421 XGBE_ADV(lks, 10000baseER_Full) ||
2422 XGBE_ADV(lks, 10000baseCR_Full));
2423 default:
2424 return false;
2425 }
2426 }
2427
xgbe_phy_use_bp_2500_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)2428 static bool xgbe_phy_use_bp_2500_mode(struct xgbe_prv_data *pdata,
2429 enum xgbe_mode mode)
2430 {
2431 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2432
2433 switch (mode) {
2434 case XGBE_MODE_KX_2500:
2435 return xgbe_phy_check_mode(pdata, mode,
2436 XGBE_ADV(lks, 2500baseX_Full));
2437 default:
2438 return false;
2439 }
2440 }
2441
xgbe_phy_use_bp_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)2442 static bool xgbe_phy_use_bp_mode(struct xgbe_prv_data *pdata,
2443 enum xgbe_mode mode)
2444 {
2445 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2446
2447 switch (mode) {
2448 case XGBE_MODE_KX_1000:
2449 return xgbe_phy_check_mode(pdata, mode,
2450 XGBE_ADV(lks, 1000baseKX_Full));
2451 case XGBE_MODE_KR:
2452 return xgbe_phy_check_mode(pdata, mode,
2453 XGBE_ADV(lks, 10000baseKR_Full));
2454 default:
2455 return false;
2456 }
2457 }
2458
xgbe_phy_use_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)2459 static bool xgbe_phy_use_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2460 {
2461 struct xgbe_phy_data *phy_data = pdata->phy_data;
2462
2463 switch (phy_data->port_mode) {
2464 case XGBE_PORT_MODE_BACKPLANE:
2465 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
2466 return xgbe_phy_use_bp_mode(pdata, mode);
2467 case XGBE_PORT_MODE_BACKPLANE_2500:
2468 return xgbe_phy_use_bp_2500_mode(pdata, mode);
2469 case XGBE_PORT_MODE_1000BASE_T:
2470 case XGBE_PORT_MODE_NBASE_T:
2471 case XGBE_PORT_MODE_10GBASE_T:
2472 return xgbe_phy_use_baset_mode(pdata, mode);
2473 case XGBE_PORT_MODE_1000BASE_X:
2474 case XGBE_PORT_MODE_10GBASE_R:
2475 return xgbe_phy_use_basex_mode(pdata, mode);
2476 case XGBE_PORT_MODE_SFP:
2477 return xgbe_phy_use_sfp_mode(pdata, mode);
2478 default:
2479 return false;
2480 }
2481 }
2482
xgbe_phy_valid_speed_basex_mode(struct xgbe_phy_data * phy_data,int speed)2483 static bool xgbe_phy_valid_speed_basex_mode(struct xgbe_phy_data *phy_data,
2484 int speed)
2485 {
2486 switch (speed) {
2487 case SPEED_1000:
2488 return (phy_data->port_mode == XGBE_PORT_MODE_1000BASE_X);
2489 case SPEED_10000:
2490 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_R);
2491 default:
2492 return false;
2493 }
2494 }
2495
xgbe_phy_valid_speed_baset_mode(struct xgbe_phy_data * phy_data,int speed)2496 static bool xgbe_phy_valid_speed_baset_mode(struct xgbe_phy_data *phy_data,
2497 int speed)
2498 {
2499 switch (speed) {
2500 case SPEED_100:
2501 case SPEED_1000:
2502 return true;
2503 case SPEED_2500:
2504 return (phy_data->port_mode == XGBE_PORT_MODE_NBASE_T);
2505 case SPEED_10000:
2506 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T);
2507 default:
2508 return false;
2509 }
2510 }
2511
xgbe_phy_valid_speed_sfp_mode(struct xgbe_phy_data * phy_data,int speed)2512 static bool xgbe_phy_valid_speed_sfp_mode(struct xgbe_phy_data *phy_data,
2513 int speed)
2514 {
2515 switch (speed) {
2516 case SPEED_100:
2517 return (phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000);
2518 case SPEED_1000:
2519 return ((phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000) ||
2520 (phy_data->sfp_speed == XGBE_SFP_SPEED_1000));
2521 case SPEED_10000:
2522 return (phy_data->sfp_speed == XGBE_SFP_SPEED_10000);
2523 default:
2524 return false;
2525 }
2526 }
2527
xgbe_phy_valid_speed_bp_2500_mode(int speed)2528 static bool xgbe_phy_valid_speed_bp_2500_mode(int speed)
2529 {
2530 switch (speed) {
2531 case SPEED_2500:
2532 return true;
2533 default:
2534 return false;
2535 }
2536 }
2537
xgbe_phy_valid_speed_bp_mode(int speed)2538 static bool xgbe_phy_valid_speed_bp_mode(int speed)
2539 {
2540 switch (speed) {
2541 case SPEED_1000:
2542 case SPEED_10000:
2543 return true;
2544 default:
2545 return false;
2546 }
2547 }
2548
xgbe_phy_valid_speed(struct xgbe_prv_data * pdata,int speed)2549 static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed)
2550 {
2551 struct xgbe_phy_data *phy_data = pdata->phy_data;
2552
2553 switch (phy_data->port_mode) {
2554 case XGBE_PORT_MODE_BACKPLANE:
2555 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
2556 return xgbe_phy_valid_speed_bp_mode(speed);
2557 case XGBE_PORT_MODE_BACKPLANE_2500:
2558 return xgbe_phy_valid_speed_bp_2500_mode(speed);
2559 case XGBE_PORT_MODE_1000BASE_T:
2560 case XGBE_PORT_MODE_NBASE_T:
2561 case XGBE_PORT_MODE_10GBASE_T:
2562 return xgbe_phy_valid_speed_baset_mode(phy_data, speed);
2563 case XGBE_PORT_MODE_1000BASE_X:
2564 case XGBE_PORT_MODE_10GBASE_R:
2565 return xgbe_phy_valid_speed_basex_mode(phy_data, speed);
2566 case XGBE_PORT_MODE_SFP:
2567 return xgbe_phy_valid_speed_sfp_mode(phy_data, speed);
2568 default:
2569 return false;
2570 }
2571 }
2572
xgbe_phy_link_status(struct xgbe_prv_data * pdata,int * an_restart)2573 static int xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart)
2574 {
2575 struct xgbe_phy_data *phy_data = pdata->phy_data;
2576 unsigned int reg;
2577 int ret;
2578
2579 *an_restart = 0;
2580
2581 if (phy_data->port_mode == XGBE_PORT_MODE_SFP) {
2582 /* Check SFP signals */
2583 xgbe_phy_sfp_detect(pdata);
2584
2585 if (phy_data->sfp_changed) {
2586 *an_restart = 1;
2587 return 0;
2588 }
2589
2590 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los)
2591 return 0;
2592 }
2593
2594 if (phy_data->phydev) {
2595 /* Check external PHY */
2596 ret = phy_read_status(phy_data->phydev);
2597 if (ret < 0)
2598 return 0;
2599
2600 if ((pdata->phy.autoneg == AUTONEG_ENABLE) &&
2601 !phy_aneg_done(phy_data->phydev))
2602 return 0;
2603
2604 if (!phy_data->phydev->link)
2605 return 0;
2606 }
2607
2608 /* Link status is latched low, so read once to clear
2609 * and then read again to get current state
2610 */
2611 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
2612 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
2613 if (reg & MDIO_STAT1_LSTATUS)
2614 return 1;
2615
2616 if (pdata->phy.autoneg == AUTONEG_ENABLE &&
2617 phy_data->port_mode == XGBE_PORT_MODE_BACKPLANE) {
2618 if (!test_bit(XGBE_LINK_INIT, &pdata->dev_state)) {
2619 netif_carrier_off(pdata->netdev);
2620 *an_restart = 1;
2621 }
2622 }
2623
2624 /* No link, attempt a receiver reset cycle */
2625 if (phy_data->rrc_count++ > XGBE_RRC_FREQUENCY) {
2626 phy_data->rrc_count = 0;
2627 xgbe_phy_rrc(pdata);
2628 }
2629
2630 return 0;
2631 }
2632
xgbe_phy_sfp_gpio_setup(struct xgbe_prv_data * pdata)2633 static void xgbe_phy_sfp_gpio_setup(struct xgbe_prv_data *pdata)
2634 {
2635 struct xgbe_phy_data *phy_data = pdata->phy_data;
2636
2637 phy_data->sfp_gpio_address = XGBE_GPIO_ADDRESS_PCA9555 +
2638 XP_GET_BITS(pdata->pp3, XP_PROP_3,
2639 GPIO_ADDR);
2640
2641 phy_data->sfp_gpio_mask = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2642 GPIO_MASK);
2643
2644 phy_data->sfp_gpio_rx_los = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2645 GPIO_RX_LOS);
2646 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2647 GPIO_TX_FAULT);
2648 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2649 GPIO_MOD_ABS);
2650 phy_data->sfp_gpio_rate_select = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2651 GPIO_RATE_SELECT);
2652
2653 if (netif_msg_probe(pdata)) {
2654 dev_dbg(pdata->dev, "SFP: gpio_address=%#x\n",
2655 phy_data->sfp_gpio_address);
2656 dev_dbg(pdata->dev, "SFP: gpio_mask=%#x\n",
2657 phy_data->sfp_gpio_mask);
2658 dev_dbg(pdata->dev, "SFP: gpio_rx_los=%u\n",
2659 phy_data->sfp_gpio_rx_los);
2660 dev_dbg(pdata->dev, "SFP: gpio_tx_fault=%u\n",
2661 phy_data->sfp_gpio_tx_fault);
2662 dev_dbg(pdata->dev, "SFP: gpio_mod_absent=%u\n",
2663 phy_data->sfp_gpio_mod_absent);
2664 dev_dbg(pdata->dev, "SFP: gpio_rate_select=%u\n",
2665 phy_data->sfp_gpio_rate_select);
2666 }
2667 }
2668
xgbe_phy_sfp_comm_setup(struct xgbe_prv_data * pdata)2669 static void xgbe_phy_sfp_comm_setup(struct xgbe_prv_data *pdata)
2670 {
2671 struct xgbe_phy_data *phy_data = pdata->phy_data;
2672 unsigned int mux_addr_hi, mux_addr_lo;
2673
2674 mux_addr_hi = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_HI);
2675 mux_addr_lo = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_LO);
2676 if (mux_addr_lo == XGBE_SFP_DIRECT)
2677 return;
2678
2679 phy_data->sfp_comm = XGBE_SFP_COMM_PCA9545;
2680 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo;
2681 phy_data->sfp_mux_channel = XP_GET_BITS(pdata->pp4, XP_PROP_4,
2682 MUX_CHAN);
2683
2684 if (netif_msg_probe(pdata)) {
2685 dev_dbg(pdata->dev, "SFP: mux_address=%#x\n",
2686 phy_data->sfp_mux_address);
2687 dev_dbg(pdata->dev, "SFP: mux_channel=%u\n",
2688 phy_data->sfp_mux_channel);
2689 }
2690 }
2691
xgbe_phy_sfp_setup(struct xgbe_prv_data * pdata)2692 static void xgbe_phy_sfp_setup(struct xgbe_prv_data *pdata)
2693 {
2694 xgbe_phy_sfp_comm_setup(pdata);
2695 xgbe_phy_sfp_gpio_setup(pdata);
2696 }
2697
xgbe_phy_int_mdio_reset(struct xgbe_prv_data * pdata)2698 static int xgbe_phy_int_mdio_reset(struct xgbe_prv_data *pdata)
2699 {
2700 struct xgbe_phy_data *phy_data = pdata->phy_data;
2701 unsigned int ret;
2702
2703 ret = pdata->hw_if.set_gpio(pdata, phy_data->mdio_reset_gpio);
2704 if (ret)
2705 return ret;
2706
2707 ret = pdata->hw_if.clr_gpio(pdata, phy_data->mdio_reset_gpio);
2708
2709 return ret;
2710 }
2711
xgbe_phy_i2c_mdio_reset(struct xgbe_prv_data * pdata)2712 static int xgbe_phy_i2c_mdio_reset(struct xgbe_prv_data *pdata)
2713 {
2714 struct xgbe_phy_data *phy_data = pdata->phy_data;
2715 u8 gpio_reg, gpio_ports[2], gpio_data[3];
2716 int ret;
2717
2718 /* Read the output port registers */
2719 gpio_reg = 2;
2720 ret = xgbe_phy_i2c_read(pdata, phy_data->mdio_reset_addr,
2721 &gpio_reg, sizeof(gpio_reg),
2722 gpio_ports, sizeof(gpio_ports));
2723 if (ret)
2724 return ret;
2725
2726 /* Prepare to write the GPIO data */
2727 gpio_data[0] = 2;
2728 gpio_data[1] = gpio_ports[0];
2729 gpio_data[2] = gpio_ports[1];
2730
2731 /* Set the GPIO pin */
2732 if (phy_data->mdio_reset_gpio < 8)
2733 gpio_data[1] |= (1 << (phy_data->mdio_reset_gpio % 8));
2734 else
2735 gpio_data[2] |= (1 << (phy_data->mdio_reset_gpio % 8));
2736
2737 /* Write the output port registers */
2738 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
2739 gpio_data, sizeof(gpio_data));
2740 if (ret)
2741 return ret;
2742
2743 /* Clear the GPIO pin */
2744 if (phy_data->mdio_reset_gpio < 8)
2745 gpio_data[1] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
2746 else
2747 gpio_data[2] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
2748
2749 /* Write the output port registers */
2750 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
2751 gpio_data, sizeof(gpio_data));
2752
2753 return ret;
2754 }
2755
xgbe_phy_mdio_reset(struct xgbe_prv_data * pdata)2756 static int xgbe_phy_mdio_reset(struct xgbe_prv_data *pdata)
2757 {
2758 struct xgbe_phy_data *phy_data = pdata->phy_data;
2759 int ret;
2760
2761 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
2762 return 0;
2763
2764 ret = xgbe_phy_get_comm_ownership(pdata);
2765 if (ret)
2766 return ret;
2767
2768 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO)
2769 ret = xgbe_phy_i2c_mdio_reset(pdata);
2770 else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO)
2771 ret = xgbe_phy_int_mdio_reset(pdata);
2772
2773 xgbe_phy_put_comm_ownership(pdata);
2774
2775 return ret;
2776 }
2777
xgbe_phy_redrv_error(struct xgbe_phy_data * phy_data)2778 static bool xgbe_phy_redrv_error(struct xgbe_phy_data *phy_data)
2779 {
2780 if (!phy_data->redrv)
2781 return false;
2782
2783 if (phy_data->redrv_if >= XGBE_PHY_REDRV_IF_MAX)
2784 return true;
2785
2786 switch (phy_data->redrv_model) {
2787 case XGBE_PHY_REDRV_MODEL_4223:
2788 if (phy_data->redrv_lane > 3)
2789 return true;
2790 break;
2791 case XGBE_PHY_REDRV_MODEL_4227:
2792 if (phy_data->redrv_lane > 1)
2793 return true;
2794 break;
2795 default:
2796 return true;
2797 }
2798
2799 return false;
2800 }
2801
xgbe_phy_mdio_reset_setup(struct xgbe_prv_data * pdata)2802 static int xgbe_phy_mdio_reset_setup(struct xgbe_prv_data *pdata)
2803 {
2804 struct xgbe_phy_data *phy_data = pdata->phy_data;
2805
2806 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
2807 return 0;
2808
2809 phy_data->mdio_reset = XP_GET_BITS(pdata->pp3, XP_PROP_3, MDIO_RESET);
2810 switch (phy_data->mdio_reset) {
2811 case XGBE_MDIO_RESET_NONE:
2812 case XGBE_MDIO_RESET_I2C_GPIO:
2813 case XGBE_MDIO_RESET_INT_GPIO:
2814 break;
2815 default:
2816 dev_err(pdata->dev, "unsupported MDIO reset (%#x)\n",
2817 phy_data->mdio_reset);
2818 return -EINVAL;
2819 }
2820
2821 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) {
2822 phy_data->mdio_reset_addr = XGBE_GPIO_ADDRESS_PCA9555 +
2823 XP_GET_BITS(pdata->pp3, XP_PROP_3,
2824 MDIO_RESET_I2C_ADDR);
2825 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2826 MDIO_RESET_I2C_GPIO);
2827 } else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO) {
2828 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2829 MDIO_RESET_INT_GPIO);
2830 }
2831
2832 return 0;
2833 }
2834
xgbe_phy_port_mode_mismatch(struct xgbe_prv_data * pdata)2835 static bool xgbe_phy_port_mode_mismatch(struct xgbe_prv_data *pdata)
2836 {
2837 struct xgbe_phy_data *phy_data = pdata->phy_data;
2838
2839 switch (phy_data->port_mode) {
2840 case XGBE_PORT_MODE_BACKPLANE:
2841 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
2842 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2843 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
2844 return false;
2845 break;
2846 case XGBE_PORT_MODE_BACKPLANE_2500:
2847 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500)
2848 return false;
2849 break;
2850 case XGBE_PORT_MODE_1000BASE_T:
2851 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2852 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000))
2853 return false;
2854 break;
2855 case XGBE_PORT_MODE_1000BASE_X:
2856 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
2857 return false;
2858 break;
2859 case XGBE_PORT_MODE_NBASE_T:
2860 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2861 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2862 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500))
2863 return false;
2864 break;
2865 case XGBE_PORT_MODE_10GBASE_T:
2866 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2867 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2868 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
2869 return false;
2870 break;
2871 case XGBE_PORT_MODE_10GBASE_R:
2872 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
2873 return false;
2874 break;
2875 case XGBE_PORT_MODE_SFP:
2876 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2877 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2878 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
2879 return false;
2880 break;
2881 default:
2882 break;
2883 }
2884
2885 return true;
2886 }
2887
xgbe_phy_conn_type_mismatch(struct xgbe_prv_data * pdata)2888 static bool xgbe_phy_conn_type_mismatch(struct xgbe_prv_data *pdata)
2889 {
2890 struct xgbe_phy_data *phy_data = pdata->phy_data;
2891
2892 switch (phy_data->port_mode) {
2893 case XGBE_PORT_MODE_BACKPLANE:
2894 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
2895 case XGBE_PORT_MODE_BACKPLANE_2500:
2896 if (phy_data->conn_type == XGBE_CONN_TYPE_BACKPLANE)
2897 return false;
2898 break;
2899 case XGBE_PORT_MODE_1000BASE_T:
2900 case XGBE_PORT_MODE_1000BASE_X:
2901 case XGBE_PORT_MODE_NBASE_T:
2902 case XGBE_PORT_MODE_10GBASE_T:
2903 case XGBE_PORT_MODE_10GBASE_R:
2904 if (phy_data->conn_type == XGBE_CONN_TYPE_MDIO)
2905 return false;
2906 break;
2907 case XGBE_PORT_MODE_SFP:
2908 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
2909 return false;
2910 break;
2911 default:
2912 break;
2913 }
2914
2915 return true;
2916 }
2917
xgbe_phy_port_enabled(struct xgbe_prv_data * pdata)2918 static bool xgbe_phy_port_enabled(struct xgbe_prv_data *pdata)
2919 {
2920 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS))
2921 return false;
2922 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE))
2923 return false;
2924
2925 return true;
2926 }
2927
xgbe_phy_cdr_track(struct xgbe_prv_data * pdata)2928 static void xgbe_phy_cdr_track(struct xgbe_prv_data *pdata)
2929 {
2930 struct xgbe_phy_data *phy_data = pdata->phy_data;
2931
2932 if (!pdata->debugfs_an_cdr_workaround)
2933 return;
2934
2935 if (!phy_data->phy_cdr_notrack)
2936 return;
2937
2938 usleep_range(phy_data->phy_cdr_delay,
2939 phy_data->phy_cdr_delay + 500);
2940
2941 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
2942 XGBE_PMA_CDR_TRACK_EN_MASK,
2943 XGBE_PMA_CDR_TRACK_EN_ON);
2944
2945 phy_data->phy_cdr_notrack = 0;
2946 }
2947
xgbe_phy_cdr_notrack(struct xgbe_prv_data * pdata)2948 static void xgbe_phy_cdr_notrack(struct xgbe_prv_data *pdata)
2949 {
2950 struct xgbe_phy_data *phy_data = pdata->phy_data;
2951
2952 if (!pdata->debugfs_an_cdr_workaround)
2953 return;
2954
2955 if (phy_data->phy_cdr_notrack)
2956 return;
2957
2958 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
2959 XGBE_PMA_CDR_TRACK_EN_MASK,
2960 XGBE_PMA_CDR_TRACK_EN_OFF);
2961
2962 xgbe_phy_rrc(pdata);
2963
2964 phy_data->phy_cdr_notrack = 1;
2965 }
2966
xgbe_phy_kr_training_post(struct xgbe_prv_data * pdata)2967 static void xgbe_phy_kr_training_post(struct xgbe_prv_data *pdata)
2968 {
2969 if (!pdata->debugfs_an_cdr_track_early)
2970 xgbe_phy_cdr_track(pdata);
2971 }
2972
xgbe_phy_kr_training_pre(struct xgbe_prv_data * pdata)2973 static void xgbe_phy_kr_training_pre(struct xgbe_prv_data *pdata)
2974 {
2975 if (pdata->debugfs_an_cdr_track_early)
2976 xgbe_phy_cdr_track(pdata);
2977 }
2978
xgbe_phy_an_post(struct xgbe_prv_data * pdata)2979 static void xgbe_phy_an_post(struct xgbe_prv_data *pdata)
2980 {
2981 struct xgbe_phy_data *phy_data = pdata->phy_data;
2982
2983 switch (pdata->an_mode) {
2984 case XGBE_AN_MODE_CL73:
2985 case XGBE_AN_MODE_CL73_REDRV:
2986 if (phy_data->cur_mode != XGBE_MODE_KR)
2987 break;
2988
2989 xgbe_phy_cdr_track(pdata);
2990
2991 switch (pdata->an_result) {
2992 case XGBE_AN_READY:
2993 case XGBE_AN_COMPLETE:
2994 break;
2995 default:
2996 if (phy_data->phy_cdr_delay < XGBE_CDR_DELAY_MAX)
2997 phy_data->phy_cdr_delay += XGBE_CDR_DELAY_INC;
2998 else
2999 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT;
3000 break;
3001 }
3002 break;
3003 default:
3004 break;
3005 }
3006 }
3007
xgbe_phy_an_pre(struct xgbe_prv_data * pdata)3008 static void xgbe_phy_an_pre(struct xgbe_prv_data *pdata)
3009 {
3010 struct xgbe_phy_data *phy_data = pdata->phy_data;
3011
3012 switch (pdata->an_mode) {
3013 case XGBE_AN_MODE_CL73:
3014 case XGBE_AN_MODE_CL73_REDRV:
3015 if (phy_data->cur_mode != XGBE_MODE_KR)
3016 break;
3017
3018 xgbe_phy_cdr_notrack(pdata);
3019 break;
3020 default:
3021 break;
3022 }
3023 }
3024
xgbe_phy_stop(struct xgbe_prv_data * pdata)3025 static void xgbe_phy_stop(struct xgbe_prv_data *pdata)
3026 {
3027 struct xgbe_phy_data *phy_data = pdata->phy_data;
3028
3029 /* If we have an external PHY, free it */
3030 xgbe_phy_free_phy_device(pdata);
3031
3032 /* Reset SFP data */
3033 xgbe_phy_sfp_reset(phy_data);
3034 xgbe_phy_sfp_mod_absent(pdata);
3035
3036 /* Reset CDR support */
3037 xgbe_phy_cdr_track(pdata);
3038
3039 /* Power off the PHY */
3040 xgbe_phy_power_off(pdata);
3041
3042 /* Stop the I2C controller */
3043 pdata->i2c_if.i2c_stop(pdata);
3044 }
3045
xgbe_phy_start(struct xgbe_prv_data * pdata)3046 static int xgbe_phy_start(struct xgbe_prv_data *pdata)
3047 {
3048 struct xgbe_phy_data *phy_data = pdata->phy_data;
3049 int ret;
3050
3051 /* Start the I2C controller */
3052 ret = pdata->i2c_if.i2c_start(pdata);
3053 if (ret)
3054 return ret;
3055
3056 /* Set the proper MDIO mode for the re-driver */
3057 if (phy_data->redrv && !phy_data->redrv_if) {
3058 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
3059 XGBE_MDIO_MODE_CL22);
3060 if (ret) {
3061 netdev_err(pdata->netdev,
3062 "redriver mdio port not compatible (%u)\n",
3063 phy_data->redrv_addr);
3064 return ret;
3065 }
3066 }
3067
3068 /* Start in highest supported mode */
3069 xgbe_phy_set_mode(pdata, phy_data->start_mode);
3070
3071 /* Reset CDR support */
3072 xgbe_phy_cdr_track(pdata);
3073
3074 /* After starting the I2C controller, we can check for an SFP */
3075 switch (phy_data->port_mode) {
3076 case XGBE_PORT_MODE_SFP:
3077 xgbe_phy_sfp_detect(pdata);
3078 break;
3079 default:
3080 break;
3081 }
3082
3083 /* If we have an external PHY, start it */
3084 ret = xgbe_phy_find_phy_device(pdata);
3085 if (ret)
3086 goto err_i2c;
3087
3088 return 0;
3089
3090 err_i2c:
3091 pdata->i2c_if.i2c_stop(pdata);
3092
3093 return ret;
3094 }
3095
xgbe_phy_reset(struct xgbe_prv_data * pdata)3096 static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
3097 {
3098 struct xgbe_phy_data *phy_data = pdata->phy_data;
3099 enum xgbe_mode cur_mode;
3100 int ret;
3101
3102 /* Reset by power cycling the PHY */
3103 cur_mode = phy_data->cur_mode;
3104 xgbe_phy_power_off(pdata);
3105 xgbe_phy_set_mode(pdata, cur_mode);
3106
3107 if (!phy_data->phydev)
3108 return 0;
3109
3110 /* Reset the external PHY */
3111 ret = xgbe_phy_mdio_reset(pdata);
3112 if (ret)
3113 return ret;
3114
3115 return phy_init_hw(phy_data->phydev);
3116 }
3117
xgbe_phy_exit(struct xgbe_prv_data * pdata)3118 static void xgbe_phy_exit(struct xgbe_prv_data *pdata)
3119 {
3120 struct xgbe_phy_data *phy_data = pdata->phy_data;
3121
3122 /* Unregister for driving external PHYs */
3123 mdiobus_unregister(phy_data->mii);
3124 }
3125
xgbe_phy_init(struct xgbe_prv_data * pdata)3126 static int xgbe_phy_init(struct xgbe_prv_data *pdata)
3127 {
3128 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
3129 struct xgbe_phy_data *phy_data;
3130 struct mii_bus *mii;
3131 int ret;
3132
3133 /* Check if enabled */
3134 if (!xgbe_phy_port_enabled(pdata)) {
3135 dev_info(pdata->dev, "device is not enabled\n");
3136 return -ENODEV;
3137 }
3138
3139 /* Initialize the I2C controller */
3140 ret = pdata->i2c_if.i2c_init(pdata);
3141 if (ret)
3142 return ret;
3143
3144 phy_data = devm_kzalloc(pdata->dev, sizeof(*phy_data), GFP_KERNEL);
3145 if (!phy_data)
3146 return -ENOMEM;
3147 pdata->phy_data = phy_data;
3148
3149 phy_data->port_mode = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_MODE);
3150 phy_data->port_id = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_ID);
3151 phy_data->port_speeds = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS);
3152 phy_data->conn_type = XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE);
3153 phy_data->mdio_addr = XP_GET_BITS(pdata->pp0, XP_PROP_0, MDIO_ADDR);
3154 if (netif_msg_probe(pdata)) {
3155 dev_dbg(pdata->dev, "port mode=%u\n", phy_data->port_mode);
3156 dev_dbg(pdata->dev, "port id=%u\n", phy_data->port_id);
3157 dev_dbg(pdata->dev, "port speeds=%#x\n", phy_data->port_speeds);
3158 dev_dbg(pdata->dev, "conn type=%u\n", phy_data->conn_type);
3159 dev_dbg(pdata->dev, "mdio addr=%u\n", phy_data->mdio_addr);
3160 }
3161
3162 phy_data->redrv = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_PRESENT);
3163 phy_data->redrv_if = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_IF);
3164 phy_data->redrv_addr = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_ADDR);
3165 phy_data->redrv_lane = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_LANE);
3166 phy_data->redrv_model = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_MODEL);
3167 if (phy_data->redrv && netif_msg_probe(pdata)) {
3168 dev_dbg(pdata->dev, "redrv present\n");
3169 dev_dbg(pdata->dev, "redrv i/f=%u\n", phy_data->redrv_if);
3170 dev_dbg(pdata->dev, "redrv addr=%#x\n", phy_data->redrv_addr);
3171 dev_dbg(pdata->dev, "redrv lane=%u\n", phy_data->redrv_lane);
3172 dev_dbg(pdata->dev, "redrv model=%u\n", phy_data->redrv_model);
3173 }
3174
3175 /* Validate the connection requested */
3176 if (xgbe_phy_conn_type_mismatch(pdata)) {
3177 dev_err(pdata->dev, "phy mode/connection mismatch (%#x/%#x)\n",
3178 phy_data->port_mode, phy_data->conn_type);
3179 return -EINVAL;
3180 }
3181
3182 /* Validate the mode requested */
3183 if (xgbe_phy_port_mode_mismatch(pdata)) {
3184 dev_err(pdata->dev, "phy mode/speed mismatch (%#x/%#x)\n",
3185 phy_data->port_mode, phy_data->port_speeds);
3186 return -EINVAL;
3187 }
3188
3189 /* Check for and validate MDIO reset support */
3190 ret = xgbe_phy_mdio_reset_setup(pdata);
3191 if (ret)
3192 return ret;
3193
3194 /* Validate the re-driver information */
3195 if (xgbe_phy_redrv_error(phy_data)) {
3196 dev_err(pdata->dev, "phy re-driver settings error\n");
3197 return -EINVAL;
3198 }
3199 pdata->kr_redrv = phy_data->redrv;
3200
3201 /* Indicate current mode is unknown */
3202 phy_data->cur_mode = XGBE_MODE_UNKNOWN;
3203
3204 /* Initialize supported features */
3205 XGBE_ZERO_SUP(lks);
3206
3207 switch (phy_data->port_mode) {
3208 /* Backplane support */
3209 case XGBE_PORT_MODE_BACKPLANE:
3210 XGBE_SET_SUP(lks, Autoneg);
3211 fallthrough;
3212 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
3213 XGBE_SET_SUP(lks, Pause);
3214 XGBE_SET_SUP(lks, Asym_Pause);
3215 XGBE_SET_SUP(lks, Backplane);
3216 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3217 XGBE_SET_SUP(lks, 1000baseKX_Full);
3218 phy_data->start_mode = XGBE_MODE_KX_1000;
3219 }
3220 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
3221 XGBE_SET_SUP(lks, 10000baseKR_Full);
3222 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
3223 XGBE_SET_SUP(lks, 10000baseR_FEC);
3224 phy_data->start_mode = XGBE_MODE_KR;
3225 }
3226
3227 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3228 break;
3229 case XGBE_PORT_MODE_BACKPLANE_2500:
3230 XGBE_SET_SUP(lks, Pause);
3231 XGBE_SET_SUP(lks, Asym_Pause);
3232 XGBE_SET_SUP(lks, Backplane);
3233 XGBE_SET_SUP(lks, 2500baseX_Full);
3234 phy_data->start_mode = XGBE_MODE_KX_2500;
3235
3236 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3237 break;
3238
3239 /* MDIO 1GBase-T support */
3240 case XGBE_PORT_MODE_1000BASE_T:
3241 XGBE_SET_SUP(lks, Autoneg);
3242 XGBE_SET_SUP(lks, Pause);
3243 XGBE_SET_SUP(lks, Asym_Pause);
3244 XGBE_SET_SUP(lks, TP);
3245 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3246 XGBE_SET_SUP(lks, 100baseT_Full);
3247 phy_data->start_mode = XGBE_MODE_SGMII_100;
3248 }
3249 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3250 XGBE_SET_SUP(lks, 1000baseT_Full);
3251 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3252 }
3253
3254 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3255 break;
3256
3257 /* MDIO Base-X support */
3258 case XGBE_PORT_MODE_1000BASE_X:
3259 XGBE_SET_SUP(lks, Autoneg);
3260 XGBE_SET_SUP(lks, Pause);
3261 XGBE_SET_SUP(lks, Asym_Pause);
3262 XGBE_SET_SUP(lks, FIBRE);
3263 XGBE_SET_SUP(lks, 1000baseX_Full);
3264 phy_data->start_mode = XGBE_MODE_X;
3265
3266 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3267 break;
3268
3269 /* MDIO NBase-T support */
3270 case XGBE_PORT_MODE_NBASE_T:
3271 XGBE_SET_SUP(lks, Autoneg);
3272 XGBE_SET_SUP(lks, Pause);
3273 XGBE_SET_SUP(lks, Asym_Pause);
3274 XGBE_SET_SUP(lks, TP);
3275 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3276 XGBE_SET_SUP(lks, 100baseT_Full);
3277 phy_data->start_mode = XGBE_MODE_SGMII_100;
3278 }
3279 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3280 XGBE_SET_SUP(lks, 1000baseT_Full);
3281 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3282 }
3283 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) {
3284 XGBE_SET_SUP(lks, 2500baseT_Full);
3285 phy_data->start_mode = XGBE_MODE_KX_2500;
3286 }
3287
3288 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
3289 break;
3290
3291 /* 10GBase-T support */
3292 case XGBE_PORT_MODE_10GBASE_T:
3293 XGBE_SET_SUP(lks, Autoneg);
3294 XGBE_SET_SUP(lks, Pause);
3295 XGBE_SET_SUP(lks, Asym_Pause);
3296 XGBE_SET_SUP(lks, TP);
3297 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3298 XGBE_SET_SUP(lks, 100baseT_Full);
3299 phy_data->start_mode = XGBE_MODE_SGMII_100;
3300 }
3301 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3302 XGBE_SET_SUP(lks, 1000baseT_Full);
3303 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3304 }
3305 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
3306 XGBE_SET_SUP(lks, 10000baseT_Full);
3307 phy_data->start_mode = XGBE_MODE_KR;
3308 }
3309
3310 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
3311 break;
3312
3313 /* 10GBase-R support */
3314 case XGBE_PORT_MODE_10GBASE_R:
3315 XGBE_SET_SUP(lks, Autoneg);
3316 XGBE_SET_SUP(lks, Pause);
3317 XGBE_SET_SUP(lks, Asym_Pause);
3318 XGBE_SET_SUP(lks, FIBRE);
3319 XGBE_SET_SUP(lks, 10000baseSR_Full);
3320 XGBE_SET_SUP(lks, 10000baseLR_Full);
3321 XGBE_SET_SUP(lks, 10000baseLRM_Full);
3322 XGBE_SET_SUP(lks, 10000baseER_Full);
3323 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
3324 XGBE_SET_SUP(lks, 10000baseR_FEC);
3325 phy_data->start_mode = XGBE_MODE_SFI;
3326
3327 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3328 break;
3329
3330 /* SFP support */
3331 case XGBE_PORT_MODE_SFP:
3332 XGBE_SET_SUP(lks, Autoneg);
3333 XGBE_SET_SUP(lks, Pause);
3334 XGBE_SET_SUP(lks, Asym_Pause);
3335 XGBE_SET_SUP(lks, TP);
3336 XGBE_SET_SUP(lks, FIBRE);
3337 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
3338 phy_data->start_mode = XGBE_MODE_SGMII_100;
3339 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
3340 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3341 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
3342 phy_data->start_mode = XGBE_MODE_SFI;
3343
3344 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3345
3346 xgbe_phy_sfp_setup(pdata);
3347 break;
3348 default:
3349 return -EINVAL;
3350 }
3351
3352 if (netif_msg_probe(pdata))
3353 dev_dbg(pdata->dev, "phy supported=0x%*pb\n",
3354 __ETHTOOL_LINK_MODE_MASK_NBITS,
3355 lks->link_modes.supported);
3356
3357 if ((phy_data->conn_type & XGBE_CONN_TYPE_MDIO) &&
3358 (phy_data->phydev_mode != XGBE_MDIO_MODE_NONE)) {
3359 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
3360 phy_data->phydev_mode);
3361 if (ret) {
3362 dev_err(pdata->dev,
3363 "mdio port/clause not compatible (%d/%u)\n",
3364 phy_data->mdio_addr, phy_data->phydev_mode);
3365 return -EINVAL;
3366 }
3367 }
3368
3369 if (phy_data->redrv && !phy_data->redrv_if) {
3370 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
3371 XGBE_MDIO_MODE_CL22);
3372 if (ret) {
3373 dev_err(pdata->dev,
3374 "redriver mdio port not compatible (%u)\n",
3375 phy_data->redrv_addr);
3376 return -EINVAL;
3377 }
3378 }
3379
3380 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT;
3381
3382 /* Register for driving external PHYs */
3383 mii = devm_mdiobus_alloc(pdata->dev);
3384 if (!mii) {
3385 dev_err(pdata->dev, "mdiobus_alloc failed\n");
3386 return -ENOMEM;
3387 }
3388
3389 mii->priv = pdata;
3390 mii->name = "amd-xgbe-mii";
3391 mii->read = xgbe_phy_mii_read;
3392 mii->write = xgbe_phy_mii_write;
3393 mii->parent = pdata->dev;
3394 mii->phy_mask = ~0;
3395 snprintf(mii->id, sizeof(mii->id), "%s", dev_name(pdata->dev));
3396 ret = mdiobus_register(mii);
3397 if (ret) {
3398 dev_err(pdata->dev, "mdiobus_register failed\n");
3399 return ret;
3400 }
3401 phy_data->mii = mii;
3402
3403 return 0;
3404 }
3405
xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if * phy_if)3406 void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *phy_if)
3407 {
3408 struct xgbe_phy_impl_if *phy_impl = &phy_if->phy_impl;
3409
3410 phy_impl->init = xgbe_phy_init;
3411 phy_impl->exit = xgbe_phy_exit;
3412
3413 phy_impl->reset = xgbe_phy_reset;
3414 phy_impl->start = xgbe_phy_start;
3415 phy_impl->stop = xgbe_phy_stop;
3416
3417 phy_impl->link_status = xgbe_phy_link_status;
3418
3419 phy_impl->valid_speed = xgbe_phy_valid_speed;
3420
3421 phy_impl->use_mode = xgbe_phy_use_mode;
3422 phy_impl->set_mode = xgbe_phy_set_mode;
3423 phy_impl->get_mode = xgbe_phy_get_mode;
3424 phy_impl->switch_mode = xgbe_phy_switch_mode;
3425 phy_impl->cur_mode = xgbe_phy_cur_mode;
3426
3427 phy_impl->an_mode = xgbe_phy_an_mode;
3428
3429 phy_impl->an_config = xgbe_phy_an_config;
3430
3431 phy_impl->an_advertising = xgbe_phy_an_advertising;
3432
3433 phy_impl->an_outcome = xgbe_phy_an_outcome;
3434
3435 phy_impl->an_pre = xgbe_phy_an_pre;
3436 phy_impl->an_post = xgbe_phy_an_post;
3437
3438 phy_impl->kr_training_pre = xgbe_phy_kr_training_pre;
3439 phy_impl->kr_training_post = xgbe_phy_kr_training_post;
3440
3441 phy_impl->module_info = xgbe_phy_module_info;
3442 phy_impl->module_eeprom = xgbe_phy_module_eeprom;
3443 }
3444