1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell OcteonTx2 RVU Admin Function driver
3 *
4 * Copyright (C) 2018 Marvell International Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #include <linux/bitfield.h>
12 #include <linux/module.h>
13 #include <linux/pci.h>
14
15 #include "rvu_struct.h"
16 #include "rvu_reg.h"
17 #include "rvu.h"
18 #include "npc.h"
19 #include "cgx.h"
20 #include "npc_profile.h"
21
22 #define RSVD_MCAM_ENTRIES_PER_PF 2 /* Bcast & Promisc */
23 #define RSVD_MCAM_ENTRIES_PER_NIXLF 1 /* Ucast for LFs */
24
25 #define NPC_PARSE_RESULT_DMAC_OFFSET 8
26 #define NPC_HW_TSTAMP_OFFSET 8
27 #define NPC_KEX_CHAN_MASK 0xFFFULL
28 #define NPC_KEX_PF_FUNC_MASK 0xFFFFULL
29
30 static const char def_pfl_name[] = "default";
31
32 static void npc_mcam_free_all_entries(struct rvu *rvu, struct npc_mcam *mcam,
33 int blkaddr, u16 pcifunc);
34 static void npc_mcam_free_all_counters(struct rvu *rvu, struct npc_mcam *mcam,
35 u16 pcifunc);
36
is_npc_intf_tx(u8 intf)37 bool is_npc_intf_tx(u8 intf)
38 {
39 return !!(intf & 0x1);
40 }
41
is_npc_intf_rx(u8 intf)42 bool is_npc_intf_rx(u8 intf)
43 {
44 return !(intf & 0x1);
45 }
46
is_npc_interface_valid(struct rvu * rvu,u8 intf)47 bool is_npc_interface_valid(struct rvu *rvu, u8 intf)
48 {
49 struct rvu_hwinfo *hw = rvu->hw;
50
51 return intf < hw->npc_intfs;
52 }
53
rvu_npc_get_tx_nibble_cfg(struct rvu * rvu,u64 nibble_ena)54 int rvu_npc_get_tx_nibble_cfg(struct rvu *rvu, u64 nibble_ena)
55 {
56 /* Due to a HW issue in these silicon versions, parse nibble enable
57 * configuration has to be identical for both Rx and Tx interfaces.
58 */
59 if (is_rvu_96xx_B0(rvu))
60 return nibble_ena;
61 return 0;
62 }
63
npc_mcam_verify_pf_func(struct rvu * rvu,struct mcam_entry * entry_data,u8 intf,u16 pcifunc)64 static int npc_mcam_verify_pf_func(struct rvu *rvu,
65 struct mcam_entry *entry_data, u8 intf,
66 u16 pcifunc)
67 {
68 u16 pf_func, pf_func_mask;
69
70 if (is_npc_intf_rx(intf))
71 return 0;
72
73 pf_func_mask = (entry_data->kw_mask[0] >> 32) &
74 NPC_KEX_PF_FUNC_MASK;
75 pf_func = (entry_data->kw[0] >> 32) & NPC_KEX_PF_FUNC_MASK;
76
77 pf_func = be16_to_cpu((__force __be16)pf_func);
78 if (pf_func_mask != NPC_KEX_PF_FUNC_MASK ||
79 ((pf_func & ~RVU_PFVF_FUNC_MASK) !=
80 (pcifunc & ~RVU_PFVF_FUNC_MASK)))
81 return -EINVAL;
82
83 return 0;
84 }
85
npc_mcam_verify_channel(struct rvu * rvu,u16 pcifunc,u8 intf,u16 channel)86 int npc_mcam_verify_channel(struct rvu *rvu, u16 pcifunc, u8 intf, u16 channel)
87 {
88 int pf = rvu_get_pf(pcifunc);
89 u8 cgx_id, lmac_id;
90 int base = 0, end;
91
92 if (is_npc_intf_tx(intf))
93 return 0;
94
95 /* return in case of AF installed rules */
96 if (is_pffunc_af(pcifunc))
97 return 0;
98
99 if (is_afvf(pcifunc)) {
100 end = rvu_get_num_lbk_chans();
101 if (end < 0)
102 return -EINVAL;
103 } else {
104 rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
105 base = rvu_nix_chan_cgx(rvu, cgx_id, lmac_id, 0x0);
106 /* CGX mapped functions has maximum of 16 channels */
107 end = rvu_nix_chan_cgx(rvu, cgx_id, lmac_id, 0xF);
108 }
109
110 if (channel < base || channel > end)
111 return -EINVAL;
112
113 return 0;
114 }
115
rvu_npc_set_pkind(struct rvu * rvu,int pkind,struct rvu_pfvf * pfvf)116 void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf)
117 {
118 int blkaddr;
119 u64 val = 0;
120
121 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
122 if (blkaddr < 0)
123 return;
124
125 /* Config CPI base for the PKIND */
126 val = pkind | 1ULL << 62;
127 rvu_write64(rvu, blkaddr, NPC_AF_PKINDX_CPI_DEFX(pkind, 0), val);
128 }
129
rvu_npc_get_pkind(struct rvu * rvu,u16 pf)130 int rvu_npc_get_pkind(struct rvu *rvu, u16 pf)
131 {
132 struct npc_pkind *pkind = &rvu->hw->pkind;
133 u32 map;
134 int i;
135
136 for (i = 0; i < pkind->rsrc.max; i++) {
137 map = pkind->pfchan_map[i];
138 if (((map >> 16) & 0x3F) == pf)
139 return i;
140 }
141 return -1;
142 }
143
144 #define NPC_AF_ACTION0_PTR_ADVANCE GENMASK_ULL(27, 20)
145
npc_config_ts_kpuaction(struct rvu * rvu,int pf,u16 pcifunc,bool enable)146 int npc_config_ts_kpuaction(struct rvu *rvu, int pf, u16 pcifunc, bool enable)
147 {
148 int pkind, blkaddr;
149 u64 val;
150
151 pkind = rvu_npc_get_pkind(rvu, pf);
152 if (pkind < 0) {
153 dev_err(rvu->dev, "%s: pkind not mapped\n", __func__);
154 return -EINVAL;
155 }
156
157 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, pcifunc);
158 if (blkaddr < 0) {
159 dev_err(rvu->dev, "%s: NPC block not implemented\n", __func__);
160 return -EINVAL;
161 }
162
163 val = rvu_read64(rvu, blkaddr, NPC_AF_PKINDX_ACTION0(pkind));
164 val &= ~NPC_AF_ACTION0_PTR_ADVANCE;
165 /* If timestamp is enabled then configure NPC to shift 8 bytes */
166 if (enable)
167 val |= FIELD_PREP(NPC_AF_ACTION0_PTR_ADVANCE,
168 NPC_HW_TSTAMP_OFFSET);
169 rvu_write64(rvu, blkaddr, NPC_AF_PKINDX_ACTION0(pkind), val);
170
171 return 0;
172 }
173
npc_get_ucast_mcam_index(struct npc_mcam * mcam,u16 pcifunc,int nixlf)174 static int npc_get_ucast_mcam_index(struct npc_mcam *mcam, u16 pcifunc,
175 int nixlf)
176 {
177 struct rvu_hwinfo *hw = container_of(mcam, struct rvu_hwinfo, mcam);
178 struct rvu *rvu = hw->rvu;
179 int blkaddr = 0, max = 0;
180 struct rvu_block *block;
181 struct rvu_pfvf *pfvf;
182
183 pfvf = rvu_get_pfvf(rvu, pcifunc);
184 /* Given a PF/VF and NIX LF number calculate the unicast mcam
185 * entry index based on the NIX block assigned to the PF/VF.
186 */
187 blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr);
188 while (blkaddr) {
189 if (pfvf->nix_blkaddr == blkaddr)
190 break;
191 block = &rvu->hw->block[blkaddr];
192 max += block->lf.max;
193 blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr);
194 }
195
196 return mcam->nixlf_offset + (max + nixlf) * RSVD_MCAM_ENTRIES_PER_NIXLF;
197 }
198
npc_get_nixlf_mcam_index(struct npc_mcam * mcam,u16 pcifunc,int nixlf,int type)199 int npc_get_nixlf_mcam_index(struct npc_mcam *mcam,
200 u16 pcifunc, int nixlf, int type)
201 {
202 int pf = rvu_get_pf(pcifunc);
203 int index;
204
205 /* Check if this is for a PF */
206 if (pf && !(pcifunc & RVU_PFVF_FUNC_MASK)) {
207 /* Reserved entries exclude PF0 */
208 pf--;
209 index = mcam->pf_offset + (pf * RSVD_MCAM_ENTRIES_PER_PF);
210 /* Broadcast address matching entry should be first so
211 * that the packet can be replicated to all VFs.
212 */
213 if (type == NIXLF_BCAST_ENTRY)
214 return index;
215 else if (type == NIXLF_PROMISC_ENTRY)
216 return index + 1;
217 }
218
219 return npc_get_ucast_mcam_index(mcam, pcifunc, nixlf);
220 }
221
npc_get_bank(struct npc_mcam * mcam,int index)222 int npc_get_bank(struct npc_mcam *mcam, int index)
223 {
224 int bank = index / mcam->banksize;
225
226 /* 0,1 & 2,3 banks are combined for this keysize */
227 if (mcam->keysize == NPC_MCAM_KEY_X2)
228 return bank ? 2 : 0;
229
230 return bank;
231 }
232
is_mcam_entry_enabled(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,int index)233 bool is_mcam_entry_enabled(struct rvu *rvu, struct npc_mcam *mcam,
234 int blkaddr, int index)
235 {
236 int bank = npc_get_bank(mcam, index);
237 u64 cfg;
238
239 index &= (mcam->banksize - 1);
240 cfg = rvu_read64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_CFG(index, bank));
241 return (cfg & 1);
242 }
243
npc_enable_mcam_entry(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,int index,bool enable)244 void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
245 int blkaddr, int index, bool enable)
246 {
247 int bank = npc_get_bank(mcam, index);
248 int actbank = bank;
249
250 index &= (mcam->banksize - 1);
251 for (; bank < (actbank + mcam->banks_per_entry); bank++) {
252 rvu_write64(rvu, blkaddr,
253 NPC_AF_MCAMEX_BANKX_CFG(index, bank),
254 enable ? 1 : 0);
255 }
256 }
257
npc_clear_mcam_entry(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,int index)258 static void npc_clear_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
259 int blkaddr, int index)
260 {
261 int bank = npc_get_bank(mcam, index);
262 int actbank = bank;
263
264 index &= (mcam->banksize - 1);
265 for (; bank < (actbank + mcam->banks_per_entry); bank++) {
266 rvu_write64(rvu, blkaddr,
267 NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 1), 0);
268 rvu_write64(rvu, blkaddr,
269 NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 0), 0);
270
271 rvu_write64(rvu, blkaddr,
272 NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 1), 0);
273 rvu_write64(rvu, blkaddr,
274 NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 0), 0);
275
276 rvu_write64(rvu, blkaddr,
277 NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 1), 0);
278 rvu_write64(rvu, blkaddr,
279 NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 0), 0);
280 }
281 }
282
npc_get_keyword(struct mcam_entry * entry,int idx,u64 * cam0,u64 * cam1)283 static void npc_get_keyword(struct mcam_entry *entry, int idx,
284 u64 *cam0, u64 *cam1)
285 {
286 u64 kw_mask = 0x00;
287
288 #define CAM_MASK(n) (BIT_ULL(n) - 1)
289
290 /* 0, 2, 4, 6 indices refer to BANKX_CAMX_W0 and
291 * 1, 3, 5, 7 indices refer to BANKX_CAMX_W1.
292 *
293 * Also, only 48 bits of BANKX_CAMX_W1 are valid.
294 */
295 switch (idx) {
296 case 0:
297 /* BANK(X)_CAM_W0<63:0> = MCAM_KEY[KW0]<63:0> */
298 *cam1 = entry->kw[0];
299 kw_mask = entry->kw_mask[0];
300 break;
301 case 1:
302 /* BANK(X)_CAM_W1<47:0> = MCAM_KEY[KW1]<47:0> */
303 *cam1 = entry->kw[1] & CAM_MASK(48);
304 kw_mask = entry->kw_mask[1] & CAM_MASK(48);
305 break;
306 case 2:
307 /* BANK(X + 1)_CAM_W0<15:0> = MCAM_KEY[KW1]<63:48>
308 * BANK(X + 1)_CAM_W0<63:16> = MCAM_KEY[KW2]<47:0>
309 */
310 *cam1 = (entry->kw[1] >> 48) & CAM_MASK(16);
311 *cam1 |= ((entry->kw[2] & CAM_MASK(48)) << 16);
312 kw_mask = (entry->kw_mask[1] >> 48) & CAM_MASK(16);
313 kw_mask |= ((entry->kw_mask[2] & CAM_MASK(48)) << 16);
314 break;
315 case 3:
316 /* BANK(X + 1)_CAM_W1<15:0> = MCAM_KEY[KW2]<63:48>
317 * BANK(X + 1)_CAM_W1<47:16> = MCAM_KEY[KW3]<31:0>
318 */
319 *cam1 = (entry->kw[2] >> 48) & CAM_MASK(16);
320 *cam1 |= ((entry->kw[3] & CAM_MASK(32)) << 16);
321 kw_mask = (entry->kw_mask[2] >> 48) & CAM_MASK(16);
322 kw_mask |= ((entry->kw_mask[3] & CAM_MASK(32)) << 16);
323 break;
324 case 4:
325 /* BANK(X + 2)_CAM_W0<31:0> = MCAM_KEY[KW3]<63:32>
326 * BANK(X + 2)_CAM_W0<63:32> = MCAM_KEY[KW4]<31:0>
327 */
328 *cam1 = (entry->kw[3] >> 32) & CAM_MASK(32);
329 *cam1 |= ((entry->kw[4] & CAM_MASK(32)) << 32);
330 kw_mask = (entry->kw_mask[3] >> 32) & CAM_MASK(32);
331 kw_mask |= ((entry->kw_mask[4] & CAM_MASK(32)) << 32);
332 break;
333 case 5:
334 /* BANK(X + 2)_CAM_W1<31:0> = MCAM_KEY[KW4]<63:32>
335 * BANK(X + 2)_CAM_W1<47:32> = MCAM_KEY[KW5]<15:0>
336 */
337 *cam1 = (entry->kw[4] >> 32) & CAM_MASK(32);
338 *cam1 |= ((entry->kw[5] & CAM_MASK(16)) << 32);
339 kw_mask = (entry->kw_mask[4] >> 32) & CAM_MASK(32);
340 kw_mask |= ((entry->kw_mask[5] & CAM_MASK(16)) << 32);
341 break;
342 case 6:
343 /* BANK(X + 3)_CAM_W0<47:0> = MCAM_KEY[KW5]<63:16>
344 * BANK(X + 3)_CAM_W0<63:48> = MCAM_KEY[KW6]<15:0>
345 */
346 *cam1 = (entry->kw[5] >> 16) & CAM_MASK(48);
347 *cam1 |= ((entry->kw[6] & CAM_MASK(16)) << 48);
348 kw_mask = (entry->kw_mask[5] >> 16) & CAM_MASK(48);
349 kw_mask |= ((entry->kw_mask[6] & CAM_MASK(16)) << 48);
350 break;
351 case 7:
352 /* BANK(X + 3)_CAM_W1<47:0> = MCAM_KEY[KW6]<63:16> */
353 *cam1 = (entry->kw[6] >> 16) & CAM_MASK(48);
354 kw_mask = (entry->kw_mask[6] >> 16) & CAM_MASK(48);
355 break;
356 }
357
358 *cam1 &= kw_mask;
359 *cam0 = ~*cam1 & kw_mask;
360 }
361
npc_fill_entryword(struct mcam_entry * entry,int idx,u64 cam0,u64 cam1)362 static void npc_fill_entryword(struct mcam_entry *entry, int idx,
363 u64 cam0, u64 cam1)
364 {
365 /* Similar to npc_get_keyword, but fills mcam_entry structure from
366 * CAM registers.
367 */
368 switch (idx) {
369 case 0:
370 entry->kw[0] = cam1;
371 entry->kw_mask[0] = cam1 ^ cam0;
372 break;
373 case 1:
374 entry->kw[1] = cam1;
375 entry->kw_mask[1] = cam1 ^ cam0;
376 break;
377 case 2:
378 entry->kw[1] |= (cam1 & CAM_MASK(16)) << 48;
379 entry->kw[2] = (cam1 >> 16) & CAM_MASK(48);
380 entry->kw_mask[1] |= ((cam1 ^ cam0) & CAM_MASK(16)) << 48;
381 entry->kw_mask[2] = ((cam1 ^ cam0) >> 16) & CAM_MASK(48);
382 break;
383 case 3:
384 entry->kw[2] |= (cam1 & CAM_MASK(16)) << 48;
385 entry->kw[3] = (cam1 >> 16) & CAM_MASK(32);
386 entry->kw_mask[2] |= ((cam1 ^ cam0) & CAM_MASK(16)) << 48;
387 entry->kw_mask[3] = ((cam1 ^ cam0) >> 16) & CAM_MASK(32);
388 break;
389 case 4:
390 entry->kw[3] |= (cam1 & CAM_MASK(32)) << 32;
391 entry->kw[4] = (cam1 >> 32) & CAM_MASK(32);
392 entry->kw_mask[3] |= ((cam1 ^ cam0) & CAM_MASK(32)) << 32;
393 entry->kw_mask[4] = ((cam1 ^ cam0) >> 32) & CAM_MASK(32);
394 break;
395 case 5:
396 entry->kw[4] |= (cam1 & CAM_MASK(32)) << 32;
397 entry->kw[5] = (cam1 >> 32) & CAM_MASK(16);
398 entry->kw_mask[4] |= ((cam1 ^ cam0) & CAM_MASK(32)) << 32;
399 entry->kw_mask[5] = ((cam1 ^ cam0) >> 32) & CAM_MASK(16);
400 break;
401 case 6:
402 entry->kw[5] |= (cam1 & CAM_MASK(48)) << 16;
403 entry->kw[6] = (cam1 >> 48) & CAM_MASK(16);
404 entry->kw_mask[5] |= ((cam1 ^ cam0) & CAM_MASK(48)) << 16;
405 entry->kw_mask[6] = ((cam1 ^ cam0) >> 48) & CAM_MASK(16);
406 break;
407 case 7:
408 entry->kw[6] |= (cam1 & CAM_MASK(48)) << 16;
409 entry->kw_mask[6] |= ((cam1 ^ cam0) & CAM_MASK(48)) << 16;
410 break;
411 }
412 }
413
npc_get_default_entry_action(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,int index,struct mcam_entry * entry)414 static void npc_get_default_entry_action(struct rvu *rvu, struct npc_mcam *mcam,
415 int blkaddr, int index,
416 struct mcam_entry *entry)
417 {
418 u16 owner, target_func;
419 struct rvu_pfvf *pfvf;
420 int bank, nixlf;
421 u64 rx_action;
422
423 owner = mcam->entry2pfvf_map[index];
424 target_func = (entry->action >> 4) & 0xffff;
425 /* return incase target is PF or LBK or rule owner is not PF */
426 if (is_afvf(target_func) || (owner & RVU_PFVF_FUNC_MASK) ||
427 !(target_func & RVU_PFVF_FUNC_MASK))
428 return;
429
430 pfvf = rvu_get_pfvf(rvu, target_func);
431 mcam->entry2target_pffunc[index] = target_func;
432 /* return if nixlf is not attached or initialized */
433 if (!is_nixlf_attached(rvu, target_func) || !pfvf->def_ucast_rule)
434 return;
435
436 /* get VF ucast entry rule */
437 nix_get_nixlf(rvu, target_func, &nixlf, NULL);
438 index = npc_get_nixlf_mcam_index(mcam, target_func,
439 nixlf, NIXLF_UCAST_ENTRY);
440 bank = npc_get_bank(mcam, index);
441 index &= (mcam->banksize - 1);
442
443 rx_action = rvu_read64(rvu, blkaddr,
444 NPC_AF_MCAMEX_BANKX_ACTION(index, bank));
445 if (rx_action)
446 entry->action = rx_action;
447 }
448
npc_config_mcam_entry(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,int index,u8 intf,struct mcam_entry * entry,bool enable)449 static void npc_config_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
450 int blkaddr, int index, u8 intf,
451 struct mcam_entry *entry, bool enable)
452 {
453 int bank = npc_get_bank(mcam, index);
454 int kw = 0, actbank, actindex;
455 u64 cam0, cam1;
456
457 actbank = bank; /* Save bank id, to set action later on */
458 actindex = index;
459 index &= (mcam->banksize - 1);
460
461 /* Disable before mcam entry update */
462 npc_enable_mcam_entry(rvu, mcam, blkaddr, actindex, false);
463
464 /* Clear mcam entry to avoid writes being suppressed by NPC */
465 npc_clear_mcam_entry(rvu, mcam, blkaddr, actindex);
466
467 /* CAM1 takes the comparison value and
468 * CAM0 specifies match for a bit in key being '0' or '1' or 'dontcare'.
469 * CAM1<n> = 0 & CAM0<n> = 1 => match if key<n> = 0
470 * CAM1<n> = 1 & CAM0<n> = 0 => match if key<n> = 1
471 * CAM1<n> = 0 & CAM0<n> = 0 => always match i.e dontcare.
472 */
473 for (; bank < (actbank + mcam->banks_per_entry); bank++, kw = kw + 2) {
474 /* Interface should be set in all banks */
475 rvu_write64(rvu, blkaddr,
476 NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 1),
477 intf);
478 rvu_write64(rvu, blkaddr,
479 NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 0),
480 ~intf & 0x3);
481
482 /* Set the match key */
483 npc_get_keyword(entry, kw, &cam0, &cam1);
484 rvu_write64(rvu, blkaddr,
485 NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 1), cam1);
486 rvu_write64(rvu, blkaddr,
487 NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 0), cam0);
488
489 npc_get_keyword(entry, kw + 1, &cam0, &cam1);
490 rvu_write64(rvu, blkaddr,
491 NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 1), cam1);
492 rvu_write64(rvu, blkaddr,
493 NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 0), cam0);
494 }
495
496 /* copy VF default entry action to the VF mcam entry */
497 if (intf == NIX_INTF_RX && actindex < mcam->bmap_entries)
498 npc_get_default_entry_action(rvu, mcam, blkaddr, actindex,
499 entry);
500
501 /* Set 'action' */
502 rvu_write64(rvu, blkaddr,
503 NPC_AF_MCAMEX_BANKX_ACTION(index, actbank), entry->action);
504
505 /* Set TAG 'action' */
506 rvu_write64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_TAG_ACT(index, actbank),
507 entry->vtag_action);
508
509 /* Enable the entry */
510 if (enable)
511 npc_enable_mcam_entry(rvu, mcam, blkaddr, actindex, true);
512 }
513
npc_read_mcam_entry(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,u16 src,struct mcam_entry * entry,u8 * intf,u8 * ena)514 void npc_read_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
515 int blkaddr, u16 src,
516 struct mcam_entry *entry, u8 *intf, u8 *ena)
517 {
518 int sbank = npc_get_bank(mcam, src);
519 int bank, kw = 0;
520 u64 cam0, cam1;
521
522 src &= (mcam->banksize - 1);
523 bank = sbank;
524
525 for (; bank < (sbank + mcam->banks_per_entry); bank++, kw = kw + 2) {
526 cam1 = rvu_read64(rvu, blkaddr,
527 NPC_AF_MCAMEX_BANKX_CAMX_W0(src, bank, 1));
528 cam0 = rvu_read64(rvu, blkaddr,
529 NPC_AF_MCAMEX_BANKX_CAMX_W0(src, bank, 0));
530 npc_fill_entryword(entry, kw, cam0, cam1);
531
532 cam1 = rvu_read64(rvu, blkaddr,
533 NPC_AF_MCAMEX_BANKX_CAMX_W1(src, bank, 1));
534 cam0 = rvu_read64(rvu, blkaddr,
535 NPC_AF_MCAMEX_BANKX_CAMX_W1(src, bank, 0));
536 npc_fill_entryword(entry, kw + 1, cam0, cam1);
537 }
538
539 entry->action = rvu_read64(rvu, blkaddr,
540 NPC_AF_MCAMEX_BANKX_ACTION(src, sbank));
541 entry->vtag_action =
542 rvu_read64(rvu, blkaddr,
543 NPC_AF_MCAMEX_BANKX_TAG_ACT(src, sbank));
544 *intf = rvu_read64(rvu, blkaddr,
545 NPC_AF_MCAMEX_BANKX_CAMX_INTF(src, sbank, 1)) & 3;
546 *ena = rvu_read64(rvu, blkaddr,
547 NPC_AF_MCAMEX_BANKX_CFG(src, sbank)) & 1;
548 }
549
npc_copy_mcam_entry(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,u16 src,u16 dest)550 static void npc_copy_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
551 int blkaddr, u16 src, u16 dest)
552 {
553 int dbank = npc_get_bank(mcam, dest);
554 int sbank = npc_get_bank(mcam, src);
555 u64 cfg, sreg, dreg;
556 int bank, i;
557
558 src &= (mcam->banksize - 1);
559 dest &= (mcam->banksize - 1);
560
561 /* Copy INTF's, W0's, W1's CAM0 and CAM1 configuration */
562 for (bank = 0; bank < mcam->banks_per_entry; bank++) {
563 sreg = NPC_AF_MCAMEX_BANKX_CAMX_INTF(src, sbank + bank, 0);
564 dreg = NPC_AF_MCAMEX_BANKX_CAMX_INTF(dest, dbank + bank, 0);
565 for (i = 0; i < 6; i++) {
566 cfg = rvu_read64(rvu, blkaddr, sreg + (i * 8));
567 rvu_write64(rvu, blkaddr, dreg + (i * 8), cfg);
568 }
569 }
570
571 /* Copy action */
572 cfg = rvu_read64(rvu, blkaddr,
573 NPC_AF_MCAMEX_BANKX_ACTION(src, sbank));
574 rvu_write64(rvu, blkaddr,
575 NPC_AF_MCAMEX_BANKX_ACTION(dest, dbank), cfg);
576
577 /* Copy TAG action */
578 cfg = rvu_read64(rvu, blkaddr,
579 NPC_AF_MCAMEX_BANKX_TAG_ACT(src, sbank));
580 rvu_write64(rvu, blkaddr,
581 NPC_AF_MCAMEX_BANKX_TAG_ACT(dest, dbank), cfg);
582
583 /* Enable or disable */
584 cfg = rvu_read64(rvu, blkaddr,
585 NPC_AF_MCAMEX_BANKX_CFG(src, sbank));
586 rvu_write64(rvu, blkaddr,
587 NPC_AF_MCAMEX_BANKX_CFG(dest, dbank), cfg);
588 }
589
npc_get_mcam_action(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,int index)590 static u64 npc_get_mcam_action(struct rvu *rvu, struct npc_mcam *mcam,
591 int blkaddr, int index)
592 {
593 int bank = npc_get_bank(mcam, index);
594
595 index &= (mcam->banksize - 1);
596 return rvu_read64(rvu, blkaddr,
597 NPC_AF_MCAMEX_BANKX_ACTION(index, bank));
598 }
599
rvu_npc_install_ucast_entry(struct rvu * rvu,u16 pcifunc,int nixlf,u64 chan,u8 * mac_addr)600 void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc,
601 int nixlf, u64 chan, u8 *mac_addr)
602 {
603 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
604 struct npc_install_flow_req req = { 0 };
605 struct npc_install_flow_rsp rsp = { 0 };
606 struct npc_mcam *mcam = &rvu->hw->mcam;
607 struct nix_rx_action action;
608 int blkaddr, index;
609
610 /* AF's VFs work in promiscuous mode */
611 if (is_afvf(pcifunc))
612 return;
613
614 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
615 if (blkaddr < 0)
616 return;
617
618 index = npc_get_nixlf_mcam_index(mcam, pcifunc,
619 nixlf, NIXLF_UCAST_ENTRY);
620
621 /* Don't change the action if entry is already enabled
622 * Otherwise RSS action may get overwritten.
623 */
624 if (is_mcam_entry_enabled(rvu, mcam, blkaddr, index)) {
625 *(u64 *)&action = npc_get_mcam_action(rvu, mcam,
626 blkaddr, index);
627 } else {
628 *(u64 *)&action = 0x00;
629 action.op = NIX_RX_ACTIONOP_UCAST;
630 action.pf_func = pcifunc;
631 }
632
633 req.default_rule = 1;
634 ether_addr_copy(req.packet.dmac, mac_addr);
635 eth_broadcast_addr((u8 *)&req.mask.dmac);
636 req.features = BIT_ULL(NPC_DMAC);
637 req.channel = chan;
638 req.intf = pfvf->nix_rx_intf;
639 req.op = action.op;
640 req.hdr.pcifunc = 0; /* AF is requester */
641 req.vf = action.pf_func;
642 req.index = action.index;
643 req.match_id = action.match_id;
644 req.flow_key_alg = action.flow_key_alg;
645
646 rvu_mbox_handler_npc_install_flow(rvu, &req, &rsp);
647 }
648
rvu_npc_install_promisc_entry(struct rvu * rvu,u16 pcifunc,int nixlf,u64 chan,u8 chan_cnt,bool allmulti)649 void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc,
650 int nixlf, u64 chan, u8 chan_cnt,
651 bool allmulti)
652 {
653 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
654 struct npc_install_flow_req req = { 0 };
655 struct npc_install_flow_rsp rsp = { 0 };
656 struct npc_mcam *mcam = &rvu->hw->mcam;
657 int blkaddr, ucast_idx, index;
658 u8 mac_addr[ETH_ALEN] = { 0 };
659 struct nix_rx_action action;
660 u64 relaxed_mask;
661
662 /* Only PF or AF VF can add a promiscuous entry */
663 if ((pcifunc & RVU_PFVF_FUNC_MASK) && !is_afvf(pcifunc))
664 return;
665
666 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
667 if (blkaddr < 0)
668 return;
669
670 *(u64 *)&action = 0x00;
671 index = npc_get_nixlf_mcam_index(mcam, pcifunc,
672 nixlf, NIXLF_PROMISC_ENTRY);
673
674 /* If the corresponding PF's ucast action is RSS,
675 * use the same action for promisc also
676 */
677 ucast_idx = npc_get_nixlf_mcam_index(mcam, pcifunc,
678 nixlf, NIXLF_UCAST_ENTRY);
679 if (is_mcam_entry_enabled(rvu, mcam, blkaddr, ucast_idx))
680 *(u64 *)&action = npc_get_mcam_action(rvu, mcam,
681 blkaddr, ucast_idx);
682
683 if (action.op != NIX_RX_ACTIONOP_RSS) {
684 *(u64 *)&action = 0x00;
685 action.op = NIX_RX_ACTIONOP_UCAST;
686 action.pf_func = pcifunc;
687 }
688
689 if (allmulti) {
690 mac_addr[0] = 0x01; /* LSB bit of 1st byte in DMAC */
691 ether_addr_copy(req.packet.dmac, mac_addr);
692 ether_addr_copy(req.mask.dmac, mac_addr);
693 req.features = BIT_ULL(NPC_DMAC);
694 }
695
696 req.chan_mask = 0xFFFU;
697 if (chan_cnt > 1) {
698 if (!is_power_of_2(chan_cnt)) {
699 dev_err(rvu->dev,
700 "%s: channel count more than 1, must be power of 2\n", __func__);
701 return;
702 }
703 relaxed_mask = GENMASK_ULL(BITS_PER_LONG_LONG - 1,
704 ilog2(chan_cnt));
705 req.chan_mask &= relaxed_mask;
706 }
707
708 req.channel = chan;
709 req.intf = pfvf->nix_rx_intf;
710 req.entry = index;
711 req.op = action.op;
712 req.hdr.pcifunc = 0; /* AF is requester */
713 req.vf = pcifunc;
714 req.index = action.index;
715 req.match_id = action.match_id;
716 req.flow_key_alg = action.flow_key_alg;
717
718 rvu_mbox_handler_npc_install_flow(rvu, &req, &rsp);
719 }
720
npc_enadis_promisc_entry(struct rvu * rvu,u16 pcifunc,int nixlf,bool enable)721 static void npc_enadis_promisc_entry(struct rvu *rvu, u16 pcifunc,
722 int nixlf, bool enable)
723 {
724 struct npc_mcam *mcam = &rvu->hw->mcam;
725 int blkaddr, index;
726
727 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
728 if (blkaddr < 0)
729 return;
730
731 /* Only PF's have a promiscuous entry */
732 if (pcifunc & RVU_PFVF_FUNC_MASK)
733 return;
734
735 index = npc_get_nixlf_mcam_index(mcam, pcifunc,
736 nixlf, NIXLF_PROMISC_ENTRY);
737 npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable);
738 }
739
rvu_npc_disable_promisc_entry(struct rvu * rvu,u16 pcifunc,int nixlf)740 void rvu_npc_disable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf)
741 {
742 npc_enadis_promisc_entry(rvu, pcifunc, nixlf, false);
743 }
744
rvu_npc_enable_promisc_entry(struct rvu * rvu,u16 pcifunc,int nixlf)745 void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf)
746 {
747 npc_enadis_promisc_entry(rvu, pcifunc, nixlf, true);
748 }
749
rvu_npc_install_bcast_match_entry(struct rvu * rvu,u16 pcifunc,int nixlf,u64 chan)750 void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc,
751 int nixlf, u64 chan)
752 {
753 struct rvu_pfvf *pfvf;
754 struct npc_install_flow_req req = { 0 };
755 struct npc_install_flow_rsp rsp = { 0 };
756 struct npc_mcam *mcam = &rvu->hw->mcam;
757 struct rvu_hwinfo *hw = rvu->hw;
758 int blkaddr, index;
759 u32 req_index = 0;
760 u8 op;
761
762 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
763 if (blkaddr < 0)
764 return;
765
766 /* Skip LBK VFs */
767 if (is_afvf(pcifunc))
768 return;
769
770 /* If pkt replication is not supported,
771 * then only PF is allowed to add a bcast match entry.
772 */
773 if (!hw->cap.nix_rx_multicast && pcifunc & RVU_PFVF_FUNC_MASK)
774 return;
775
776 /* Get 'pcifunc' of PF device */
777 pcifunc = pcifunc & ~RVU_PFVF_FUNC_MASK;
778 pfvf = rvu_get_pfvf(rvu, pcifunc);
779 index = npc_get_nixlf_mcam_index(mcam, pcifunc,
780 nixlf, NIXLF_BCAST_ENTRY);
781
782 if (!hw->cap.nix_rx_multicast) {
783 /* Early silicon doesn't support pkt replication,
784 * so install entry with UCAST action, so that PF
785 * receives all broadcast packets.
786 */
787 op = NIX_RX_ACTIONOP_UCAST;
788 } else {
789 op = NIX_RX_ACTIONOP_MCAST;
790 req_index = pfvf->bcast_mce_idx;
791 }
792
793 eth_broadcast_addr((u8 *)&req.packet.dmac);
794 eth_broadcast_addr((u8 *)&req.mask.dmac);
795 req.features = BIT_ULL(NPC_DMAC);
796 req.channel = chan;
797 req.intf = pfvf->nix_rx_intf;
798 req.entry = index;
799 req.op = op;
800 req.hdr.pcifunc = 0; /* AF is requester */
801 req.vf = pcifunc;
802 req.index = req_index;
803
804 rvu_mbox_handler_npc_install_flow(rvu, &req, &rsp);
805 }
806
rvu_npc_enable_bcast_entry(struct rvu * rvu,u16 pcifunc,bool enable)807 void rvu_npc_enable_bcast_entry(struct rvu *rvu, u16 pcifunc, bool enable)
808 {
809 struct npc_mcam *mcam = &rvu->hw->mcam;
810 int blkaddr, index;
811
812 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
813 if (blkaddr < 0)
814 return;
815
816 /* Get 'pcifunc' of PF device */
817 pcifunc = pcifunc & ~RVU_PFVF_FUNC_MASK;
818
819 index = npc_get_nixlf_mcam_index(mcam, pcifunc, 0, NIXLF_BCAST_ENTRY);
820 npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable);
821 }
822
npc_update_vf_flow_entry(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,u16 pcifunc,u64 rx_action)823 static void npc_update_vf_flow_entry(struct rvu *rvu, struct npc_mcam *mcam,
824 int blkaddr, u16 pcifunc, u64 rx_action)
825 {
826 int actindex, index, bank;
827 bool enable;
828
829 if (!(pcifunc & RVU_PFVF_FUNC_MASK))
830 return;
831
832 mutex_lock(&mcam->lock);
833 for (index = 0; index < mcam->bmap_entries; index++) {
834 if (mcam->entry2target_pffunc[index] == pcifunc) {
835 bank = npc_get_bank(mcam, index);
836 actindex = index;
837 index &= (mcam->banksize - 1);
838
839 /* read vf flow entry enable status */
840 enable = is_mcam_entry_enabled(rvu, mcam, blkaddr,
841 actindex);
842 /* disable before mcam entry update */
843 npc_enable_mcam_entry(rvu, mcam, blkaddr, actindex,
844 false);
845 /* update 'action' */
846 rvu_write64(rvu, blkaddr,
847 NPC_AF_MCAMEX_BANKX_ACTION(index, bank),
848 rx_action);
849 if (enable)
850 npc_enable_mcam_entry(rvu, mcam, blkaddr,
851 actindex, true);
852 }
853 }
854 mutex_unlock(&mcam->lock);
855 }
856
rvu_npc_update_flowkey_alg_idx(struct rvu * rvu,u16 pcifunc,int nixlf,int group,int alg_idx,int mcam_index)857 void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf,
858 int group, int alg_idx, int mcam_index)
859 {
860 struct npc_mcam *mcam = &rvu->hw->mcam;
861 struct nix_rx_action action;
862 int blkaddr, index, bank;
863 struct rvu_pfvf *pfvf;
864
865 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
866 if (blkaddr < 0)
867 return;
868
869 /* Check if this is for reserved default entry */
870 if (mcam_index < 0) {
871 if (group != DEFAULT_RSS_CONTEXT_GROUP)
872 return;
873 index = npc_get_nixlf_mcam_index(mcam, pcifunc,
874 nixlf, NIXLF_UCAST_ENTRY);
875 } else {
876 /* TODO: validate this mcam index */
877 index = mcam_index;
878 }
879
880 if (index >= mcam->total_entries)
881 return;
882
883 bank = npc_get_bank(mcam, index);
884 index &= (mcam->banksize - 1);
885
886 *(u64 *)&action = rvu_read64(rvu, blkaddr,
887 NPC_AF_MCAMEX_BANKX_ACTION(index, bank));
888 /* Ignore if no action was set earlier */
889 if (!*(u64 *)&action)
890 return;
891
892 action.op = NIX_RX_ACTIONOP_RSS;
893 action.pf_func = pcifunc;
894 action.index = group;
895 action.flow_key_alg = alg_idx;
896
897 rvu_write64(rvu, blkaddr,
898 NPC_AF_MCAMEX_BANKX_ACTION(index, bank), *(u64 *)&action);
899
900 /* update the VF flow rule action with the VF default entry action */
901 if (mcam_index < 0)
902 npc_update_vf_flow_entry(rvu, mcam, blkaddr, pcifunc,
903 *(u64 *)&action);
904
905 /* update the action change in default rule */
906 pfvf = rvu_get_pfvf(rvu, pcifunc);
907 if (pfvf->def_ucast_rule)
908 pfvf->def_ucast_rule->rx_action = action;
909
910 index = npc_get_nixlf_mcam_index(mcam, pcifunc,
911 nixlf, NIXLF_PROMISC_ENTRY);
912
913 /* If PF's promiscuous entry is enabled,
914 * Set RSS action for that entry as well
915 */
916 if (is_mcam_entry_enabled(rvu, mcam, blkaddr, index)) {
917 bank = npc_get_bank(mcam, index);
918 index &= (mcam->banksize - 1);
919
920 rvu_write64(rvu, blkaddr,
921 NPC_AF_MCAMEX_BANKX_ACTION(index, bank),
922 *(u64 *)&action);
923 }
924 }
925
npc_enadis_default_entries(struct rvu * rvu,u16 pcifunc,int nixlf,bool enable)926 static void npc_enadis_default_entries(struct rvu *rvu, u16 pcifunc,
927 int nixlf, bool enable)
928 {
929 struct npc_mcam *mcam = &rvu->hw->mcam;
930 struct nix_rx_action action;
931 int index, bank, blkaddr;
932
933 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
934 if (blkaddr < 0)
935 return;
936
937 /* Ucast MCAM match entry of this PF/VF */
938 index = npc_get_nixlf_mcam_index(mcam, pcifunc,
939 nixlf, NIXLF_UCAST_ENTRY);
940 npc_enable_mcam_entry(rvu, mcam, blkaddr, index, enable);
941
942 /* For PF, ena/dis promisc and bcast MCAM match entries.
943 * For VFs add/delete from bcast list when RX multicast
944 * feature is present.
945 */
946 if (pcifunc & RVU_PFVF_FUNC_MASK && !rvu->hw->cap.nix_rx_multicast)
947 return;
948
949 /* For bcast, enable/disable only if it's action is not
950 * packet replication, incase if action is replication
951 * then this PF/VF's nixlf is removed from bcast replication
952 * list.
953 */
954 index = npc_get_nixlf_mcam_index(mcam, pcifunc & ~RVU_PFVF_FUNC_MASK,
955 nixlf, NIXLF_BCAST_ENTRY);
956 bank = npc_get_bank(mcam, index);
957 *(u64 *)&action = rvu_read64(rvu, blkaddr,
958 NPC_AF_MCAMEX_BANKX_ACTION(index & (mcam->banksize - 1), bank));
959
960 /* VFs will not have BCAST entry */
961 if (action.op != NIX_RX_ACTIONOP_MCAST &&
962 !(pcifunc & RVU_PFVF_FUNC_MASK)) {
963 npc_enable_mcam_entry(rvu, mcam,
964 blkaddr, index, enable);
965 } else {
966 nix_update_bcast_mce_list(rvu, pcifunc, enable);
967 /* Enable PF's BCAST entry for packet replication */
968 rvu_npc_enable_bcast_entry(rvu, pcifunc, enable);
969 }
970
971 if (enable)
972 rvu_npc_enable_promisc_entry(rvu, pcifunc, nixlf);
973 else
974 rvu_npc_disable_promisc_entry(rvu, pcifunc, nixlf);
975 }
976
rvu_npc_disable_default_entries(struct rvu * rvu,u16 pcifunc,int nixlf)977 void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf)
978 {
979 npc_enadis_default_entries(rvu, pcifunc, nixlf, false);
980 }
981
rvu_npc_enable_default_entries(struct rvu * rvu,u16 pcifunc,int nixlf)982 void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf)
983 {
984 npc_enadis_default_entries(rvu, pcifunc, nixlf, true);
985 }
986
rvu_npc_disable_mcam_entries(struct rvu * rvu,u16 pcifunc,int nixlf)987 void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf)
988 {
989 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
990 struct npc_mcam *mcam = &rvu->hw->mcam;
991 struct rvu_npc_mcam_rule *rule, *tmp;
992 int blkaddr;
993
994 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
995 if (blkaddr < 0)
996 return;
997
998 mutex_lock(&mcam->lock);
999
1000 /* Disable MCAM entries directing traffic to this 'pcifunc' */
1001 list_for_each_entry_safe(rule, tmp, &mcam->mcam_rules, list) {
1002 if (is_npc_intf_rx(rule->intf) &&
1003 rule->rx_action.pf_func == pcifunc) {
1004 npc_enable_mcam_entry(rvu, mcam, blkaddr,
1005 rule->entry, false);
1006 rule->enable = false;
1007 /* Indicate that default rule is disabled */
1008 if (rule->default_rule) {
1009 pfvf->def_ucast_rule = NULL;
1010 list_del(&rule->list);
1011 kfree(rule);
1012 }
1013 }
1014 }
1015
1016 mutex_unlock(&mcam->lock);
1017
1018 npc_mcam_disable_flows(rvu, pcifunc);
1019
1020 rvu_npc_disable_default_entries(rvu, pcifunc, nixlf);
1021 }
1022
rvu_npc_free_mcam_entries(struct rvu * rvu,u16 pcifunc,int nixlf)1023 void rvu_npc_free_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf)
1024 {
1025 struct npc_mcam *mcam = &rvu->hw->mcam;
1026 struct rvu_npc_mcam_rule *rule, *tmp;
1027 int blkaddr;
1028
1029 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1030 if (blkaddr < 0)
1031 return;
1032
1033 mutex_lock(&mcam->lock);
1034
1035 /* Free all MCAM entries owned by this 'pcifunc' */
1036 npc_mcam_free_all_entries(rvu, mcam, blkaddr, pcifunc);
1037
1038 /* Free all MCAM counters owned by this 'pcifunc' */
1039 npc_mcam_free_all_counters(rvu, mcam, pcifunc);
1040
1041 /* Delete MCAM entries owned by this 'pcifunc' */
1042 list_for_each_entry_safe(rule, tmp, &mcam->mcam_rules, list) {
1043 if (rule->owner == pcifunc && !rule->default_rule) {
1044 list_del(&rule->list);
1045 kfree(rule);
1046 }
1047 }
1048
1049 mutex_unlock(&mcam->lock);
1050
1051 rvu_npc_disable_default_entries(rvu, pcifunc, nixlf);
1052 }
1053
1054 #define SET_KEX_LD(intf, lid, ltype, ld, cfg) \
1055 rvu_write64(rvu, blkaddr, \
1056 NPC_AF_INTFX_LIDX_LTX_LDX_CFG(intf, lid, ltype, ld), cfg)
1057
1058 #define SET_KEX_LDFLAGS(intf, ld, flags, cfg) \
1059 rvu_write64(rvu, blkaddr, \
1060 NPC_AF_INTFX_LDATAX_FLAGSX_CFG(intf, ld, flags), cfg)
1061
npc_program_mkex_rx(struct rvu * rvu,int blkaddr,struct npc_mcam_kex * mkex,u8 intf)1062 static void npc_program_mkex_rx(struct rvu *rvu, int blkaddr,
1063 struct npc_mcam_kex *mkex, u8 intf)
1064 {
1065 int lid, lt, ld, fl;
1066
1067 if (is_npc_intf_tx(intf))
1068 return;
1069
1070 rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(intf),
1071 mkex->keyx_cfg[NIX_INTF_RX]);
1072
1073 /* Program LDATA */
1074 for (lid = 0; lid < NPC_MAX_LID; lid++) {
1075 for (lt = 0; lt < NPC_MAX_LT; lt++) {
1076 for (ld = 0; ld < NPC_MAX_LD; ld++)
1077 SET_KEX_LD(intf, lid, lt, ld,
1078 mkex->intf_lid_lt_ld[NIX_INTF_RX]
1079 [lid][lt][ld]);
1080 }
1081 }
1082 /* Program LFLAGS */
1083 for (ld = 0; ld < NPC_MAX_LD; ld++) {
1084 for (fl = 0; fl < NPC_MAX_LFL; fl++)
1085 SET_KEX_LDFLAGS(intf, ld, fl,
1086 mkex->intf_ld_flags[NIX_INTF_RX]
1087 [ld][fl]);
1088 }
1089 }
1090
npc_program_mkex_tx(struct rvu * rvu,int blkaddr,struct npc_mcam_kex * mkex,u8 intf)1091 static void npc_program_mkex_tx(struct rvu *rvu, int blkaddr,
1092 struct npc_mcam_kex *mkex, u8 intf)
1093 {
1094 int lid, lt, ld, fl;
1095
1096 if (is_npc_intf_rx(intf))
1097 return;
1098
1099 rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(intf),
1100 mkex->keyx_cfg[NIX_INTF_TX]);
1101
1102 /* Program LDATA */
1103 for (lid = 0; lid < NPC_MAX_LID; lid++) {
1104 for (lt = 0; lt < NPC_MAX_LT; lt++) {
1105 for (ld = 0; ld < NPC_MAX_LD; ld++)
1106 SET_KEX_LD(intf, lid, lt, ld,
1107 mkex->intf_lid_lt_ld[NIX_INTF_TX]
1108 [lid][lt][ld]);
1109 }
1110 }
1111 /* Program LFLAGS */
1112 for (ld = 0; ld < NPC_MAX_LD; ld++) {
1113 for (fl = 0; fl < NPC_MAX_LFL; fl++)
1114 SET_KEX_LDFLAGS(intf, ld, fl,
1115 mkex->intf_ld_flags[NIX_INTF_TX]
1116 [ld][fl]);
1117 }
1118 }
1119
npc_program_mkex_profile(struct rvu * rvu,int blkaddr,struct npc_mcam_kex * mkex)1120 static void npc_program_mkex_profile(struct rvu *rvu, int blkaddr,
1121 struct npc_mcam_kex *mkex)
1122 {
1123 struct rvu_hwinfo *hw = rvu->hw;
1124 u8 intf;
1125 int ld;
1126
1127 for (ld = 0; ld < NPC_MAX_LD; ld++)
1128 rvu_write64(rvu, blkaddr, NPC_AF_KEX_LDATAX_FLAGS_CFG(ld),
1129 mkex->kex_ld_flags[ld]);
1130
1131 for (intf = 0; intf < hw->npc_intfs; intf++) {
1132 npc_program_mkex_rx(rvu, blkaddr, mkex, intf);
1133 npc_program_mkex_tx(rvu, blkaddr, mkex, intf);
1134 }
1135 }
1136
1137 #define MKEX_END_SIGN 0xdeadbeef
1138
npc_load_mkex_profile(struct rvu * rvu,int blkaddr,const char * mkex_profile)1139 static void npc_load_mkex_profile(struct rvu *rvu, int blkaddr,
1140 const char *mkex_profile)
1141 {
1142 struct device *dev = &rvu->pdev->dev;
1143 struct npc_mcam_kex *mcam_kex;
1144 void *mkex_prfl_addr = NULL;
1145 u64 prfl_addr, prfl_sz;
1146
1147 /* If user not selected mkex profile */
1148 if (!strncmp(mkex_profile, def_pfl_name, MKEX_NAME_LEN))
1149 goto program_mkex;
1150
1151 if (!rvu->fwdata)
1152 goto program_mkex;
1153 prfl_addr = rvu->fwdata->mcam_addr;
1154 prfl_sz = rvu->fwdata->mcam_sz;
1155
1156 if (!prfl_addr || !prfl_sz)
1157 goto program_mkex;
1158
1159 mkex_prfl_addr = memremap(prfl_addr, prfl_sz, MEMREMAP_WC);
1160 if (!mkex_prfl_addr)
1161 goto program_mkex;
1162
1163 mcam_kex = (struct npc_mcam_kex *)mkex_prfl_addr;
1164
1165 while (((s64)prfl_sz > 0) && (mcam_kex->mkex_sign != MKEX_END_SIGN)) {
1166 /* Compare with mkex mod_param name string */
1167 if (mcam_kex->mkex_sign == MKEX_SIGN &&
1168 !strncmp(mcam_kex->name, mkex_profile, MKEX_NAME_LEN)) {
1169 /* Due to an errata (35786) in A0/B0 pass silicon,
1170 * parse nibble enable configuration has to be
1171 * identical for both Rx and Tx interfaces.
1172 */
1173 if (!is_rvu_96xx_B0(rvu) ||
1174 mcam_kex->keyx_cfg[NIX_INTF_RX] == mcam_kex->keyx_cfg[NIX_INTF_TX])
1175 rvu->kpu.mkex = mcam_kex;
1176 goto program_mkex;
1177 }
1178
1179 mcam_kex++;
1180 prfl_sz -= sizeof(struct npc_mcam_kex);
1181 }
1182 dev_warn(dev, "Failed to load requested profile: %s\n", mkex_profile);
1183
1184 program_mkex:
1185 dev_info(rvu->dev, "Using %s mkex profile\n", rvu->kpu.mkex->name);
1186 /* Program selected mkex profile */
1187 npc_program_mkex_profile(rvu, blkaddr, rvu->kpu.mkex);
1188 if (mkex_prfl_addr)
1189 memunmap(mkex_prfl_addr);
1190 }
1191
npc_config_kpuaction(struct rvu * rvu,int blkaddr,const struct npc_kpu_profile_action * kpuaction,int kpu,int entry,bool pkind)1192 static void npc_config_kpuaction(struct rvu *rvu, int blkaddr,
1193 const struct npc_kpu_profile_action *kpuaction,
1194 int kpu, int entry, bool pkind)
1195 {
1196 struct npc_kpu_action0 action0 = {0};
1197 struct npc_kpu_action1 action1 = {0};
1198 u64 reg;
1199
1200 action1.errlev = kpuaction->errlev;
1201 action1.errcode = kpuaction->errcode;
1202 action1.dp0_offset = kpuaction->dp0_offset;
1203 action1.dp1_offset = kpuaction->dp1_offset;
1204 action1.dp2_offset = kpuaction->dp2_offset;
1205
1206 if (pkind)
1207 reg = NPC_AF_PKINDX_ACTION1(entry);
1208 else
1209 reg = NPC_AF_KPUX_ENTRYX_ACTION1(kpu, entry);
1210
1211 rvu_write64(rvu, blkaddr, reg, *(u64 *)&action1);
1212
1213 action0.byp_count = kpuaction->bypass_count;
1214 action0.capture_ena = kpuaction->cap_ena;
1215 action0.parse_done = kpuaction->parse_done;
1216 action0.next_state = kpuaction->next_state;
1217 action0.capture_lid = kpuaction->lid;
1218 action0.capture_ltype = kpuaction->ltype;
1219 action0.capture_flags = kpuaction->flags;
1220 action0.ptr_advance = kpuaction->ptr_advance;
1221 action0.var_len_offset = kpuaction->offset;
1222 action0.var_len_mask = kpuaction->mask;
1223 action0.var_len_right = kpuaction->right;
1224 action0.var_len_shift = kpuaction->shift;
1225
1226 if (pkind)
1227 reg = NPC_AF_PKINDX_ACTION0(entry);
1228 else
1229 reg = NPC_AF_KPUX_ENTRYX_ACTION0(kpu, entry);
1230
1231 rvu_write64(rvu, blkaddr, reg, *(u64 *)&action0);
1232 }
1233
npc_config_kpucam(struct rvu * rvu,int blkaddr,const struct npc_kpu_profile_cam * kpucam,int kpu,int entry)1234 static void npc_config_kpucam(struct rvu *rvu, int blkaddr,
1235 const struct npc_kpu_profile_cam *kpucam,
1236 int kpu, int entry)
1237 {
1238 struct npc_kpu_cam cam0 = {0};
1239 struct npc_kpu_cam cam1 = {0};
1240
1241 cam1.state = kpucam->state & kpucam->state_mask;
1242 cam1.dp0_data = kpucam->dp0 & kpucam->dp0_mask;
1243 cam1.dp1_data = kpucam->dp1 & kpucam->dp1_mask;
1244 cam1.dp2_data = kpucam->dp2 & kpucam->dp2_mask;
1245
1246 cam0.state = ~kpucam->state & kpucam->state_mask;
1247 cam0.dp0_data = ~kpucam->dp0 & kpucam->dp0_mask;
1248 cam0.dp1_data = ~kpucam->dp1 & kpucam->dp1_mask;
1249 cam0.dp2_data = ~kpucam->dp2 & kpucam->dp2_mask;
1250
1251 rvu_write64(rvu, blkaddr,
1252 NPC_AF_KPUX_ENTRYX_CAMX(kpu, entry, 0), *(u64 *)&cam0);
1253 rvu_write64(rvu, blkaddr,
1254 NPC_AF_KPUX_ENTRYX_CAMX(kpu, entry, 1), *(u64 *)&cam1);
1255 }
1256
enable_mask(int count)1257 static inline u64 enable_mask(int count)
1258 {
1259 return (((count) < 64) ? ~(BIT_ULL(count) - 1) : (0x00ULL));
1260 }
1261
npc_program_kpu_profile(struct rvu * rvu,int blkaddr,int kpu,const struct npc_kpu_profile * profile)1262 static void npc_program_kpu_profile(struct rvu *rvu, int blkaddr, int kpu,
1263 const struct npc_kpu_profile *profile)
1264 {
1265 int entry, num_entries, max_entries;
1266
1267 if (profile->cam_entries != profile->action_entries) {
1268 dev_err(rvu->dev,
1269 "KPU%d: CAM and action entries [%d != %d] not equal\n",
1270 kpu, profile->cam_entries, profile->action_entries);
1271 }
1272
1273 max_entries = rvu->hw->npc_kpu_entries;
1274
1275 /* Program CAM match entries for previous KPU extracted data */
1276 num_entries = min_t(int, profile->cam_entries, max_entries);
1277 for (entry = 0; entry < num_entries; entry++)
1278 npc_config_kpucam(rvu, blkaddr,
1279 &profile->cam[entry], kpu, entry);
1280
1281 /* Program this KPU's actions */
1282 num_entries = min_t(int, profile->action_entries, max_entries);
1283 for (entry = 0; entry < num_entries; entry++)
1284 npc_config_kpuaction(rvu, blkaddr, &profile->action[entry],
1285 kpu, entry, false);
1286
1287 /* Enable all programmed entries */
1288 num_entries = min_t(int, profile->action_entries, profile->cam_entries);
1289 rvu_write64(rvu, blkaddr,
1290 NPC_AF_KPUX_ENTRY_DISX(kpu, 0), enable_mask(num_entries));
1291 if (num_entries > 64) {
1292 rvu_write64(rvu, blkaddr,
1293 NPC_AF_KPUX_ENTRY_DISX(kpu, 1),
1294 enable_mask(num_entries - 64));
1295 }
1296
1297 /* Enable this KPU */
1298 rvu_write64(rvu, blkaddr, NPC_AF_KPUX_CFG(kpu), 0x01);
1299 }
1300
npc_prepare_default_kpu(struct npc_kpu_profile_adapter * profile)1301 static int npc_prepare_default_kpu(struct npc_kpu_profile_adapter *profile)
1302 {
1303 profile->name = def_pfl_name;
1304 profile->version = NPC_KPU_PROFILE_VER;
1305 profile->ikpu = ikpu_action_entries;
1306 profile->pkinds = ARRAY_SIZE(ikpu_action_entries);
1307 profile->kpu = npc_kpu_profiles;
1308 profile->kpus = ARRAY_SIZE(npc_kpu_profiles);
1309 profile->lt_def = &npc_lt_defaults;
1310 profile->mkex = &npc_mkex_default;
1311
1312 return 0;
1313 }
1314
npc_load_kpu_profile(struct rvu * rvu)1315 static void npc_load_kpu_profile(struct rvu *rvu)
1316 {
1317 struct npc_kpu_profile_adapter *profile = &rvu->kpu;
1318
1319 npc_prepare_default_kpu(profile);
1320 }
1321
npc_parser_profile_init(struct rvu * rvu,int blkaddr)1322 static void npc_parser_profile_init(struct rvu *rvu, int blkaddr)
1323 {
1324 struct rvu_hwinfo *hw = rvu->hw;
1325 int num_pkinds, num_kpus, idx;
1326 struct npc_pkind *pkind;
1327
1328 /* Disable all KPUs and their entries */
1329 for (idx = 0; idx < hw->npc_kpus; idx++) {
1330 rvu_write64(rvu, blkaddr,
1331 NPC_AF_KPUX_ENTRY_DISX(idx, 0), ~0ULL);
1332 rvu_write64(rvu, blkaddr,
1333 NPC_AF_KPUX_ENTRY_DISX(idx, 1), ~0ULL);
1334 rvu_write64(rvu, blkaddr, NPC_AF_KPUX_CFG(idx), 0x00);
1335 }
1336
1337 /* Load and customize KPU profile. */
1338 npc_load_kpu_profile(rvu);
1339
1340 /* First program IKPU profile i.e PKIND configs.
1341 * Check HW max count to avoid configuring junk or
1342 * writing to unsupported CSR addresses.
1343 */
1344 pkind = &hw->pkind;
1345 num_pkinds = rvu->kpu.pkinds;
1346 num_pkinds = min_t(int, pkind->rsrc.max, num_pkinds);
1347
1348 for (idx = 0; idx < num_pkinds; idx++)
1349 npc_config_kpuaction(rvu, blkaddr, &rvu->kpu.ikpu[idx], 0, idx, true);
1350
1351 /* Program KPU CAM and Action profiles */
1352 num_kpus = rvu->kpu.kpus;
1353 num_kpus = min_t(int, hw->npc_kpus, num_kpus);
1354
1355 for (idx = 0; idx < num_kpus; idx++)
1356 npc_program_kpu_profile(rvu, blkaddr, idx, &rvu->kpu.kpu[idx]);
1357 }
1358
npc_mcam_rsrcs_init(struct rvu * rvu,int blkaddr)1359 static int npc_mcam_rsrcs_init(struct rvu *rvu, int blkaddr)
1360 {
1361 int nixlf_count = rvu_get_nixlf_count(rvu);
1362 struct npc_mcam *mcam = &rvu->hw->mcam;
1363 int rsvd, err;
1364 u64 cfg;
1365
1366 /* Actual number of MCAM entries vary by entry size */
1367 cfg = (rvu_read64(rvu, blkaddr,
1368 NPC_AF_INTFX_KEX_CFG(0)) >> 32) & 0x07;
1369 mcam->total_entries = (mcam->banks / BIT_ULL(cfg)) * mcam->banksize;
1370 mcam->keysize = cfg;
1371
1372 /* Number of banks combined per MCAM entry */
1373 if (cfg == NPC_MCAM_KEY_X4)
1374 mcam->banks_per_entry = 4;
1375 else if (cfg == NPC_MCAM_KEY_X2)
1376 mcam->banks_per_entry = 2;
1377 else
1378 mcam->banks_per_entry = 1;
1379
1380 /* Reserve one MCAM entry for each of the NIX LF to
1381 * guarantee space to install default matching DMAC rule.
1382 * Also reserve 2 MCAM entries for each PF for default
1383 * channel based matching or 'bcast & promisc' matching to
1384 * support BCAST and PROMISC modes of operation for PFs.
1385 * PF0 is excluded.
1386 */
1387 rsvd = (nixlf_count * RSVD_MCAM_ENTRIES_PER_NIXLF) +
1388 ((rvu->hw->total_pfs - 1) * RSVD_MCAM_ENTRIES_PER_PF);
1389 if (mcam->total_entries <= rsvd) {
1390 dev_warn(rvu->dev,
1391 "Insufficient NPC MCAM size %d for pkt I/O, exiting\n",
1392 mcam->total_entries);
1393 return -ENOMEM;
1394 }
1395
1396 mcam->bmap_entries = mcam->total_entries - rsvd;
1397 mcam->nixlf_offset = mcam->bmap_entries;
1398 mcam->pf_offset = mcam->nixlf_offset + nixlf_count;
1399
1400 /* Allocate bitmaps for managing MCAM entries */
1401 mcam->bmap = devm_kcalloc(rvu->dev, BITS_TO_LONGS(mcam->bmap_entries),
1402 sizeof(long), GFP_KERNEL);
1403 if (!mcam->bmap)
1404 return -ENOMEM;
1405
1406 mcam->bmap_reverse = devm_kcalloc(rvu->dev,
1407 BITS_TO_LONGS(mcam->bmap_entries),
1408 sizeof(long), GFP_KERNEL);
1409 if (!mcam->bmap_reverse)
1410 return -ENOMEM;
1411
1412 mcam->bmap_fcnt = mcam->bmap_entries;
1413
1414 /* Alloc memory for saving entry to RVU PFFUNC allocation mapping */
1415 mcam->entry2pfvf_map = devm_kcalloc(rvu->dev, mcam->bmap_entries,
1416 sizeof(u16), GFP_KERNEL);
1417 if (!mcam->entry2pfvf_map)
1418 return -ENOMEM;
1419
1420 /* Reserve 1/8th of MCAM entries at the bottom for low priority
1421 * allocations and another 1/8th at the top for high priority
1422 * allocations.
1423 */
1424 mcam->lprio_count = mcam->bmap_entries / 8;
1425 if (mcam->lprio_count > BITS_PER_LONG)
1426 mcam->lprio_count = round_down(mcam->lprio_count,
1427 BITS_PER_LONG);
1428 mcam->lprio_start = mcam->bmap_entries - mcam->lprio_count;
1429 mcam->hprio_count = mcam->lprio_count;
1430 mcam->hprio_end = mcam->hprio_count;
1431
1432
1433 /* Allocate bitmap for managing MCAM counters and memory
1434 * for saving counter to RVU PFFUNC allocation mapping.
1435 */
1436 err = rvu_alloc_bitmap(&mcam->counters);
1437 if (err)
1438 return err;
1439
1440 mcam->cntr2pfvf_map = devm_kcalloc(rvu->dev, mcam->counters.max,
1441 sizeof(u16), GFP_KERNEL);
1442 if (!mcam->cntr2pfvf_map)
1443 goto free_mem;
1444
1445 /* Alloc memory for MCAM entry to counter mapping and for tracking
1446 * counter's reference count.
1447 */
1448 mcam->entry2cntr_map = devm_kcalloc(rvu->dev, mcam->bmap_entries,
1449 sizeof(u16), GFP_KERNEL);
1450 if (!mcam->entry2cntr_map)
1451 goto free_mem;
1452
1453 mcam->cntr_refcnt = devm_kcalloc(rvu->dev, mcam->counters.max,
1454 sizeof(u16), GFP_KERNEL);
1455 if (!mcam->cntr_refcnt)
1456 goto free_mem;
1457
1458 /* Alloc memory for saving target device of mcam rule */
1459 mcam->entry2target_pffunc = devm_kcalloc(rvu->dev, mcam->total_entries,
1460 sizeof(u16), GFP_KERNEL);
1461 if (!mcam->entry2target_pffunc)
1462 goto free_mem;
1463
1464 mutex_init(&mcam->lock);
1465
1466 return 0;
1467
1468 free_mem:
1469 kfree(mcam->counters.bmap);
1470 return -ENOMEM;
1471 }
1472
rvu_npc_hw_init(struct rvu * rvu,int blkaddr)1473 static void rvu_npc_hw_init(struct rvu *rvu, int blkaddr)
1474 {
1475 struct npc_pkind *pkind = &rvu->hw->pkind;
1476 struct npc_mcam *mcam = &rvu->hw->mcam;
1477 struct rvu_hwinfo *hw = rvu->hw;
1478 u64 npc_const, npc_const1;
1479 u64 npc_const2 = 0;
1480
1481 npc_const = rvu_read64(rvu, blkaddr, NPC_AF_CONST);
1482 npc_const1 = rvu_read64(rvu, blkaddr, NPC_AF_CONST1);
1483 if (npc_const1 & BIT_ULL(63))
1484 npc_const2 = rvu_read64(rvu, blkaddr, NPC_AF_CONST2);
1485
1486 pkind->rsrc.max = (npc_const1 >> 12) & 0xFFULL;
1487 hw->npc_kpu_entries = npc_const1 & 0xFFFULL;
1488 hw->npc_kpus = (npc_const >> 8) & 0x1FULL;
1489 hw->npc_intfs = npc_const & 0xFULL;
1490 hw->npc_counters = (npc_const >> 48) & 0xFFFFULL;
1491
1492 mcam->banks = (npc_const >> 44) & 0xFULL;
1493 mcam->banksize = (npc_const >> 28) & 0xFFFFULL;
1494 /* Extended set */
1495 if (npc_const2) {
1496 hw->npc_ext_set = true;
1497 hw->npc_counters = (npc_const2 >> 16) & 0xFFFFULL;
1498 mcam->banksize = npc_const2 & 0xFFFFULL;
1499 }
1500
1501 mcam->counters.max = hw->npc_counters;
1502 }
1503
rvu_npc_setup_interfaces(struct rvu * rvu,int blkaddr)1504 static void rvu_npc_setup_interfaces(struct rvu *rvu, int blkaddr)
1505 {
1506 struct npc_mcam *mcam = &rvu->hw->mcam;
1507 struct rvu_hwinfo *hw = rvu->hw;
1508 u64 nibble_ena, rx_kex, tx_kex;
1509 u8 intf;
1510
1511 /* Reserve last counter for MCAM RX miss action which is set to
1512 * drop packet. This way we will know how many pkts didn't match
1513 * any MCAM entry.
1514 */
1515 mcam->counters.max--;
1516 mcam->rx_miss_act_cntr = mcam->counters.max;
1517
1518 rx_kex = npc_mkex_default.keyx_cfg[NIX_INTF_RX];
1519 tx_kex = npc_mkex_default.keyx_cfg[NIX_INTF_TX];
1520 nibble_ena = FIELD_GET(NPC_PARSE_NIBBLE, rx_kex);
1521
1522 nibble_ena = rvu_npc_get_tx_nibble_cfg(rvu, nibble_ena);
1523 if (nibble_ena) {
1524 tx_kex &= ~NPC_PARSE_NIBBLE;
1525 tx_kex |= FIELD_PREP(NPC_PARSE_NIBBLE, nibble_ena);
1526 npc_mkex_default.keyx_cfg[NIX_INTF_TX] = tx_kex;
1527 }
1528
1529 /* Configure RX interfaces */
1530 for (intf = 0; intf < hw->npc_intfs; intf++) {
1531 if (is_npc_intf_tx(intf))
1532 continue;
1533
1534 /* Set RX MCAM search key size. LA..LE (ltype only) + Channel */
1535 rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(intf),
1536 rx_kex);
1537
1538 /* If MCAM lookup doesn't result in a match, drop the received
1539 * packet. And map this action to a counter to count dropped
1540 * packets.
1541 */
1542 rvu_write64(rvu, blkaddr,
1543 NPC_AF_INTFX_MISS_ACT(intf), NIX_RX_ACTIONOP_DROP);
1544
1545 /* NPC_AF_INTFX_MISS_STAT_ACT[14:12] - counter[11:9]
1546 * NPC_AF_INTFX_MISS_STAT_ACT[8:0] - counter[8:0]
1547 */
1548 rvu_write64(rvu, blkaddr,
1549 NPC_AF_INTFX_MISS_STAT_ACT(intf),
1550 ((mcam->rx_miss_act_cntr >> 9) << 12) |
1551 BIT_ULL(9) | mcam->rx_miss_act_cntr);
1552 }
1553
1554 /* Configure TX interfaces */
1555 for (intf = 0; intf < hw->npc_intfs; intf++) {
1556 if (is_npc_intf_rx(intf))
1557 continue;
1558
1559 /* Extract Ltypes LID_LA to LID_LE */
1560 rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(intf),
1561 tx_kex);
1562
1563 /* Set TX miss action to UCAST_DEFAULT i.e
1564 * transmit the packet on NIX LF SQ's default channel.
1565 */
1566 rvu_write64(rvu, blkaddr,
1567 NPC_AF_INTFX_MISS_ACT(intf),
1568 NIX_TX_ACTIONOP_UCAST_DEFAULT);
1569 }
1570 }
1571
rvu_npc_init(struct rvu * rvu)1572 int rvu_npc_init(struct rvu *rvu)
1573 {
1574 struct npc_kpu_profile_adapter *kpu = &rvu->kpu;
1575 struct npc_pkind *pkind = &rvu->hw->pkind;
1576 struct npc_mcam *mcam = &rvu->hw->mcam;
1577 int blkaddr, entry, bank, err;
1578
1579 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
1580 if (blkaddr < 0) {
1581 dev_err(rvu->dev, "%s: NPC block not implemented\n", __func__);
1582 return -ENODEV;
1583 }
1584
1585 rvu_npc_hw_init(rvu, blkaddr);
1586
1587 /* First disable all MCAM entries, to stop traffic towards NIXLFs */
1588 for (bank = 0; bank < mcam->banks; bank++) {
1589 for (entry = 0; entry < mcam->banksize; entry++)
1590 rvu_write64(rvu, blkaddr,
1591 NPC_AF_MCAMEX_BANKX_CFG(entry, bank), 0);
1592 }
1593
1594 err = rvu_alloc_bitmap(&pkind->rsrc);
1595 if (err)
1596 return err;
1597
1598 /* Allocate mem for pkind to PF and channel mapping info */
1599 pkind->pfchan_map = devm_kcalloc(rvu->dev, pkind->rsrc.max,
1600 sizeof(u32), GFP_KERNEL);
1601 if (!pkind->pfchan_map)
1602 return -ENOMEM;
1603
1604 /* Configure KPU profile */
1605 npc_parser_profile_init(rvu, blkaddr);
1606
1607 /* Config Outer L2, IPv4's NPC layer info */
1608 rvu_write64(rvu, blkaddr, NPC_AF_PCK_DEF_OL2,
1609 (kpu->lt_def->pck_ol2.lid << 8) | (kpu->lt_def->pck_ol2.ltype_match << 4) |
1610 kpu->lt_def->pck_ol2.ltype_mask);
1611 rvu_write64(rvu, blkaddr, NPC_AF_PCK_DEF_OIP4,
1612 (kpu->lt_def->pck_oip4.lid << 8) | (kpu->lt_def->pck_oip4.ltype_match << 4) |
1613 kpu->lt_def->pck_oip4.ltype_mask);
1614
1615 /* Config Inner IPV4 NPC layer info */
1616 rvu_write64(rvu, blkaddr, NPC_AF_PCK_DEF_IIP4,
1617 (kpu->lt_def->pck_iip4.lid << 8) | (kpu->lt_def->pck_iip4.ltype_match << 4) |
1618 kpu->lt_def->pck_iip4.ltype_mask);
1619
1620 /* Enable below for Rx pkts.
1621 * - Outer IPv4 header checksum validation.
1622 * - Detect outer L2 broadcast address and set NPC_RESULT_S[L2M].
1623 * - Inner IPv4 header checksum validation.
1624 * - Set non zero checksum error code value
1625 */
1626 rvu_write64(rvu, blkaddr, NPC_AF_PCK_CFG,
1627 rvu_read64(rvu, blkaddr, NPC_AF_PCK_CFG) |
1628 BIT_ULL(32) | BIT_ULL(24) | BIT_ULL(6) |
1629 BIT_ULL(2) | BIT_ULL(1));
1630
1631 rvu_npc_setup_interfaces(rvu, blkaddr);
1632
1633 /* Configure MKEX profile */
1634 npc_load_mkex_profile(rvu, blkaddr, rvu->mkex_pfl_name);
1635
1636 err = npc_mcam_rsrcs_init(rvu, blkaddr);
1637 if (err)
1638 return err;
1639
1640 err = npc_flow_steering_init(rvu, blkaddr);
1641 if (err) {
1642 dev_err(rvu->dev,
1643 "Incorrect mkex profile loaded using default mkex\n");
1644 npc_load_mkex_profile(rvu, blkaddr, def_pfl_name);
1645 }
1646
1647 return 0;
1648 }
1649
rvu_npc_freemem(struct rvu * rvu)1650 void rvu_npc_freemem(struct rvu *rvu)
1651 {
1652 struct npc_pkind *pkind = &rvu->hw->pkind;
1653 struct npc_mcam *mcam = &rvu->hw->mcam;
1654
1655 kfree(pkind->rsrc.bmap);
1656 kfree(mcam->counters.bmap);
1657 mutex_destroy(&mcam->lock);
1658 }
1659
rvu_npc_get_mcam_entry_alloc_info(struct rvu * rvu,u16 pcifunc,int blkaddr,int * alloc_cnt,int * enable_cnt)1660 void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc,
1661 int blkaddr, int *alloc_cnt,
1662 int *enable_cnt)
1663 {
1664 struct npc_mcam *mcam = &rvu->hw->mcam;
1665 int entry;
1666
1667 *alloc_cnt = 0;
1668 *enable_cnt = 0;
1669
1670 for (entry = 0; entry < mcam->bmap_entries; entry++) {
1671 if (mcam->entry2pfvf_map[entry] == pcifunc) {
1672 (*alloc_cnt)++;
1673 if (is_mcam_entry_enabled(rvu, mcam, blkaddr, entry))
1674 (*enable_cnt)++;
1675 }
1676 }
1677 }
1678
rvu_npc_get_mcam_counter_alloc_info(struct rvu * rvu,u16 pcifunc,int blkaddr,int * alloc_cnt,int * enable_cnt)1679 void rvu_npc_get_mcam_counter_alloc_info(struct rvu *rvu, u16 pcifunc,
1680 int blkaddr, int *alloc_cnt,
1681 int *enable_cnt)
1682 {
1683 struct npc_mcam *mcam = &rvu->hw->mcam;
1684 int cntr;
1685
1686 *alloc_cnt = 0;
1687 *enable_cnt = 0;
1688
1689 for (cntr = 0; cntr < mcam->counters.max; cntr++) {
1690 if (mcam->cntr2pfvf_map[cntr] == pcifunc) {
1691 (*alloc_cnt)++;
1692 if (mcam->cntr_refcnt[cntr])
1693 (*enable_cnt)++;
1694 }
1695 }
1696 }
1697
npc_mcam_verify_entry(struct npc_mcam * mcam,u16 pcifunc,int entry)1698 static int npc_mcam_verify_entry(struct npc_mcam *mcam,
1699 u16 pcifunc, int entry)
1700 {
1701 /* verify AF installed entries */
1702 if (is_pffunc_af(pcifunc))
1703 return 0;
1704 /* Verify if entry is valid and if it is indeed
1705 * allocated to the requesting PFFUNC.
1706 */
1707 if (entry >= mcam->bmap_entries)
1708 return NPC_MCAM_INVALID_REQ;
1709
1710 if (pcifunc != mcam->entry2pfvf_map[entry])
1711 return NPC_MCAM_PERM_DENIED;
1712
1713 return 0;
1714 }
1715
npc_mcam_verify_counter(struct npc_mcam * mcam,u16 pcifunc,int cntr)1716 static int npc_mcam_verify_counter(struct npc_mcam *mcam,
1717 u16 pcifunc, int cntr)
1718 {
1719 /* Verify if counter is valid and if it is indeed
1720 * allocated to the requesting PFFUNC.
1721 */
1722 if (cntr >= mcam->counters.max)
1723 return NPC_MCAM_INVALID_REQ;
1724
1725 if (pcifunc != mcam->cntr2pfvf_map[cntr])
1726 return NPC_MCAM_PERM_DENIED;
1727
1728 return 0;
1729 }
1730
npc_map_mcam_entry_and_cntr(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,u16 entry,u16 cntr)1731 static void npc_map_mcam_entry_and_cntr(struct rvu *rvu, struct npc_mcam *mcam,
1732 int blkaddr, u16 entry, u16 cntr)
1733 {
1734 u16 index = entry & (mcam->banksize - 1);
1735 u16 bank = npc_get_bank(mcam, entry);
1736
1737 /* Set mapping and increment counter's refcnt */
1738 mcam->entry2cntr_map[entry] = cntr;
1739 mcam->cntr_refcnt[cntr]++;
1740 /* Enable stats
1741 * NPC_AF_MCAMEX_BANKX_STAT_ACT[14:12] - counter[11:9]
1742 * NPC_AF_MCAMEX_BANKX_STAT_ACT[8:0] - counter[8:0]
1743 */
1744 rvu_write64(rvu, blkaddr,
1745 NPC_AF_MCAMEX_BANKX_STAT_ACT(index, bank),
1746 ((cntr >> 9) << 12) | BIT_ULL(9) | cntr);
1747 }
1748
npc_unmap_mcam_entry_and_cntr(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,u16 entry,u16 cntr)1749 static void npc_unmap_mcam_entry_and_cntr(struct rvu *rvu,
1750 struct npc_mcam *mcam,
1751 int blkaddr, u16 entry, u16 cntr)
1752 {
1753 u16 index = entry & (mcam->banksize - 1);
1754 u16 bank = npc_get_bank(mcam, entry);
1755
1756 /* Remove mapping and reduce counter's refcnt */
1757 mcam->entry2cntr_map[entry] = NPC_MCAM_INVALID_MAP;
1758 mcam->cntr_refcnt[cntr]--;
1759 /* Disable stats */
1760 rvu_write64(rvu, blkaddr,
1761 NPC_AF_MCAMEX_BANKX_STAT_ACT(index, bank), 0x00);
1762 }
1763
1764 /* Sets MCAM entry in bitmap as used. Update
1765 * reverse bitmap too. Should be called with
1766 * 'mcam->lock' held.
1767 */
npc_mcam_set_bit(struct npc_mcam * mcam,u16 index)1768 static void npc_mcam_set_bit(struct npc_mcam *mcam, u16 index)
1769 {
1770 u16 entry, rentry;
1771
1772 entry = index;
1773 rentry = mcam->bmap_entries - index - 1;
1774
1775 __set_bit(entry, mcam->bmap);
1776 __set_bit(rentry, mcam->bmap_reverse);
1777 mcam->bmap_fcnt--;
1778 }
1779
1780 /* Sets MCAM entry in bitmap as free. Update
1781 * reverse bitmap too. Should be called with
1782 * 'mcam->lock' held.
1783 */
npc_mcam_clear_bit(struct npc_mcam * mcam,u16 index)1784 static void npc_mcam_clear_bit(struct npc_mcam *mcam, u16 index)
1785 {
1786 u16 entry, rentry;
1787
1788 entry = index;
1789 rentry = mcam->bmap_entries - index - 1;
1790
1791 __clear_bit(entry, mcam->bmap);
1792 __clear_bit(rentry, mcam->bmap_reverse);
1793 mcam->bmap_fcnt++;
1794 }
1795
npc_mcam_free_all_entries(struct rvu * rvu,struct npc_mcam * mcam,int blkaddr,u16 pcifunc)1796 static void npc_mcam_free_all_entries(struct rvu *rvu, struct npc_mcam *mcam,
1797 int blkaddr, u16 pcifunc)
1798 {
1799 u16 index, cntr;
1800
1801 /* Scan all MCAM entries and free the ones mapped to 'pcifunc' */
1802 for (index = 0; index < mcam->bmap_entries; index++) {
1803 if (mcam->entry2pfvf_map[index] == pcifunc) {
1804 mcam->entry2pfvf_map[index] = NPC_MCAM_INVALID_MAP;
1805 /* Free the entry in bitmap */
1806 npc_mcam_clear_bit(mcam, index);
1807 /* Disable the entry */
1808 npc_enable_mcam_entry(rvu, mcam, blkaddr, index, false);
1809
1810 /* Update entry2counter mapping */
1811 cntr = mcam->entry2cntr_map[index];
1812 if (cntr != NPC_MCAM_INVALID_MAP)
1813 npc_unmap_mcam_entry_and_cntr(rvu, mcam,
1814 blkaddr, index,
1815 cntr);
1816 mcam->entry2target_pffunc[index] = 0x0;
1817 }
1818 }
1819 }
1820
npc_mcam_free_all_counters(struct rvu * rvu,struct npc_mcam * mcam,u16 pcifunc)1821 static void npc_mcam_free_all_counters(struct rvu *rvu, struct npc_mcam *mcam,
1822 u16 pcifunc)
1823 {
1824 u16 cntr;
1825
1826 /* Scan all MCAM counters and free the ones mapped to 'pcifunc' */
1827 for (cntr = 0; cntr < mcam->counters.max; cntr++) {
1828 if (mcam->cntr2pfvf_map[cntr] == pcifunc) {
1829 mcam->cntr2pfvf_map[cntr] = NPC_MCAM_INVALID_MAP;
1830 mcam->cntr_refcnt[cntr] = 0;
1831 rvu_free_rsrc(&mcam->counters, cntr);
1832 /* This API is expected to be called after freeing
1833 * MCAM entries, which inturn will remove
1834 * 'entry to counter' mapping.
1835 * No need to do it again.
1836 */
1837 }
1838 }
1839 }
1840
1841 /* Find area of contiguous free entries of size 'nr'.
1842 * If not found return max contiguous free entries available.
1843 */
npc_mcam_find_zero_area(unsigned long * map,u16 size,u16 start,u16 nr,u16 * max_area)1844 static u16 npc_mcam_find_zero_area(unsigned long *map, u16 size, u16 start,
1845 u16 nr, u16 *max_area)
1846 {
1847 u16 max_area_start = 0;
1848 u16 index, next, end;
1849
1850 *max_area = 0;
1851
1852 again:
1853 index = find_next_zero_bit(map, size, start);
1854 if (index >= size)
1855 return max_area_start;
1856
1857 end = ((index + nr) >= size) ? size : index + nr;
1858 next = find_next_bit(map, end, index);
1859 if (*max_area < (next - index)) {
1860 *max_area = next - index;
1861 max_area_start = index;
1862 }
1863
1864 if (next < end) {
1865 start = next + 1;
1866 goto again;
1867 }
1868
1869 return max_area_start;
1870 }
1871
1872 /* Find number of free MCAM entries available
1873 * within range i.e in between 'start' and 'end'.
1874 */
npc_mcam_get_free_count(unsigned long * map,u16 start,u16 end)1875 static u16 npc_mcam_get_free_count(unsigned long *map, u16 start, u16 end)
1876 {
1877 u16 index, next;
1878 u16 fcnt = 0;
1879
1880 again:
1881 if (start >= end)
1882 return fcnt;
1883
1884 index = find_next_zero_bit(map, end, start);
1885 if (index >= end)
1886 return fcnt;
1887
1888 next = find_next_bit(map, end, index);
1889 if (next <= end) {
1890 fcnt += next - index;
1891 start = next + 1;
1892 goto again;
1893 }
1894
1895 fcnt += end - index;
1896 return fcnt;
1897 }
1898
1899 static void
npc_get_mcam_search_range_priority(struct npc_mcam * mcam,struct npc_mcam_alloc_entry_req * req,u16 * start,u16 * end,bool * reverse)1900 npc_get_mcam_search_range_priority(struct npc_mcam *mcam,
1901 struct npc_mcam_alloc_entry_req *req,
1902 u16 *start, u16 *end, bool *reverse)
1903 {
1904 u16 fcnt;
1905
1906 if (req->priority == NPC_MCAM_HIGHER_PRIO)
1907 goto hprio;
1908
1909 /* For a low priority entry allocation
1910 * - If reference entry is not in hprio zone then
1911 * search range: ref_entry to end.
1912 * - If reference entry is in hprio zone and if
1913 * request can be accomodated in non-hprio zone then
1914 * search range: 'start of middle zone' to 'end'
1915 * - else search in reverse, so that less number of hprio
1916 * zone entries are allocated.
1917 */
1918
1919 *reverse = false;
1920 *start = req->ref_entry + 1;
1921 *end = mcam->bmap_entries;
1922
1923 if (req->ref_entry >= mcam->hprio_end)
1924 return;
1925
1926 fcnt = npc_mcam_get_free_count(mcam->bmap,
1927 mcam->hprio_end, mcam->bmap_entries);
1928 if (fcnt > req->count)
1929 *start = mcam->hprio_end;
1930 else
1931 *reverse = true;
1932 return;
1933
1934 hprio:
1935 /* For a high priority entry allocation, search is always
1936 * in reverse to preserve hprio zone entries.
1937 * - If reference entry is not in lprio zone then
1938 * search range: 0 to ref_entry.
1939 * - If reference entry is in lprio zone and if
1940 * request can be accomodated in middle zone then
1941 * search range: 'hprio_end' to 'lprio_start'
1942 */
1943
1944 *reverse = true;
1945 *start = 0;
1946 *end = req->ref_entry;
1947
1948 if (req->ref_entry <= mcam->lprio_start)
1949 return;
1950
1951 fcnt = npc_mcam_get_free_count(mcam->bmap,
1952 mcam->hprio_end, mcam->lprio_start);
1953 if (fcnt < req->count)
1954 return;
1955 *start = mcam->hprio_end;
1956 *end = mcam->lprio_start;
1957 }
1958
npc_mcam_alloc_entries(struct npc_mcam * mcam,u16 pcifunc,struct npc_mcam_alloc_entry_req * req,struct npc_mcam_alloc_entry_rsp * rsp)1959 static int npc_mcam_alloc_entries(struct npc_mcam *mcam, u16 pcifunc,
1960 struct npc_mcam_alloc_entry_req *req,
1961 struct npc_mcam_alloc_entry_rsp *rsp)
1962 {
1963 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES];
1964 u16 fcnt, hp_fcnt, lp_fcnt;
1965 u16 start, end, index;
1966 int entry, next_start;
1967 bool reverse = false;
1968 unsigned long *bmap;
1969 u16 max_contig;
1970
1971 mutex_lock(&mcam->lock);
1972
1973 /* Check if there are any free entries */
1974 if (!mcam->bmap_fcnt) {
1975 mutex_unlock(&mcam->lock);
1976 return NPC_MCAM_ALLOC_FAILED;
1977 }
1978
1979 /* MCAM entries are divided into high priority, middle and
1980 * low priority zones. Idea is to not allocate top and lower
1981 * most entries as much as possible, this is to increase
1982 * probability of honouring priority allocation requests.
1983 *
1984 * Two bitmaps are used for mcam entry management,
1985 * mcam->bmap for forward search i.e '0 to mcam->bmap_entries'.
1986 * mcam->bmap_reverse for reverse search i.e 'mcam->bmap_entries to 0'.
1987 *
1988 * Reverse bitmap is used to allocate entries
1989 * - when a higher priority entry is requested
1990 * - when available free entries are less.
1991 * Lower priority ones out of avaialble free entries are always
1992 * chosen when 'high vs low' question arises.
1993 */
1994
1995 /* Get the search range for priority allocation request */
1996 if (req->priority) {
1997 npc_get_mcam_search_range_priority(mcam, req,
1998 &start, &end, &reverse);
1999 goto alloc;
2000 }
2001
2002 /* Find out the search range for non-priority allocation request
2003 *
2004 * Get MCAM free entry count in middle zone.
2005 */
2006 lp_fcnt = npc_mcam_get_free_count(mcam->bmap,
2007 mcam->lprio_start,
2008 mcam->bmap_entries);
2009 hp_fcnt = npc_mcam_get_free_count(mcam->bmap, 0, mcam->hprio_end);
2010 fcnt = mcam->bmap_fcnt - lp_fcnt - hp_fcnt;
2011
2012 /* Check if request can be accomodated in the middle zone */
2013 if (fcnt > req->count) {
2014 start = mcam->hprio_end;
2015 end = mcam->lprio_start;
2016 } else if ((fcnt + (hp_fcnt / 2) + (lp_fcnt / 2)) > req->count) {
2017 /* Expand search zone from half of hprio zone to
2018 * half of lprio zone.
2019 */
2020 start = mcam->hprio_end / 2;
2021 end = mcam->bmap_entries - (mcam->lprio_count / 2);
2022 reverse = true;
2023 } else {
2024 /* Not enough free entries, search all entries in reverse,
2025 * so that low priority ones will get used up.
2026 */
2027 reverse = true;
2028 start = 0;
2029 end = mcam->bmap_entries;
2030 }
2031
2032 alloc:
2033 if (reverse) {
2034 bmap = mcam->bmap_reverse;
2035 start = mcam->bmap_entries - start;
2036 end = mcam->bmap_entries - end;
2037 index = start;
2038 start = end;
2039 end = index;
2040 } else {
2041 bmap = mcam->bmap;
2042 }
2043
2044 if (req->contig) {
2045 /* Allocate requested number of contiguous entries, if
2046 * unsuccessful find max contiguous entries available.
2047 */
2048 index = npc_mcam_find_zero_area(bmap, end, start,
2049 req->count, &max_contig);
2050 rsp->count = max_contig;
2051 if (reverse)
2052 rsp->entry = mcam->bmap_entries - index - max_contig;
2053 else
2054 rsp->entry = index;
2055 } else {
2056 /* Allocate requested number of non-contiguous entries,
2057 * if unsuccessful allocate as many as possible.
2058 */
2059 rsp->count = 0;
2060 next_start = start;
2061 for (entry = 0; entry < req->count; entry++) {
2062 index = find_next_zero_bit(bmap, end, next_start);
2063 if (index >= end)
2064 break;
2065
2066 next_start = start + (index - start) + 1;
2067
2068 /* Save the entry's index */
2069 if (reverse)
2070 index = mcam->bmap_entries - index - 1;
2071 entry_list[entry] = index;
2072 rsp->count++;
2073 }
2074 }
2075
2076 /* If allocating requested no of entries is unsucessful,
2077 * expand the search range to full bitmap length and retry.
2078 */
2079 if (!req->priority && (rsp->count < req->count) &&
2080 ((end - start) != mcam->bmap_entries)) {
2081 reverse = true;
2082 start = 0;
2083 end = mcam->bmap_entries;
2084 goto alloc;
2085 }
2086
2087 /* For priority entry allocation requests, if allocation is
2088 * failed then expand search to max possible range and retry.
2089 */
2090 if (req->priority && rsp->count < req->count) {
2091 if (req->priority == NPC_MCAM_LOWER_PRIO &&
2092 (start != (req->ref_entry + 1))) {
2093 start = req->ref_entry + 1;
2094 end = mcam->bmap_entries;
2095 reverse = false;
2096 goto alloc;
2097 } else if ((req->priority == NPC_MCAM_HIGHER_PRIO) &&
2098 ((end - start) != req->ref_entry)) {
2099 start = 0;
2100 end = req->ref_entry;
2101 reverse = true;
2102 goto alloc;
2103 }
2104 }
2105
2106 /* Copy MCAM entry indices into mbox response entry_list.
2107 * Requester always expects indices in ascending order, so
2108 * so reverse the list if reverse bitmap is used for allocation.
2109 */
2110 if (!req->contig && rsp->count) {
2111 index = 0;
2112 for (entry = rsp->count - 1; entry >= 0; entry--) {
2113 if (reverse)
2114 rsp->entry_list[index++] = entry_list[entry];
2115 else
2116 rsp->entry_list[entry] = entry_list[entry];
2117 }
2118 }
2119
2120 /* Mark the allocated entries as used and set nixlf mapping */
2121 for (entry = 0; entry < rsp->count; entry++) {
2122 index = req->contig ?
2123 (rsp->entry + entry) : rsp->entry_list[entry];
2124 npc_mcam_set_bit(mcam, index);
2125 mcam->entry2pfvf_map[index] = pcifunc;
2126 mcam->entry2cntr_map[index] = NPC_MCAM_INVALID_MAP;
2127 }
2128
2129 /* Update available free count in mbox response */
2130 rsp->free_count = mcam->bmap_fcnt;
2131
2132 mutex_unlock(&mcam->lock);
2133 return 0;
2134 }
2135
rvu_mbox_handler_npc_mcam_alloc_entry(struct rvu * rvu,struct npc_mcam_alloc_entry_req * req,struct npc_mcam_alloc_entry_rsp * rsp)2136 int rvu_mbox_handler_npc_mcam_alloc_entry(struct rvu *rvu,
2137 struct npc_mcam_alloc_entry_req *req,
2138 struct npc_mcam_alloc_entry_rsp *rsp)
2139 {
2140 struct npc_mcam *mcam = &rvu->hw->mcam;
2141 u16 pcifunc = req->hdr.pcifunc;
2142 int blkaddr;
2143
2144 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2145 if (blkaddr < 0)
2146 return NPC_MCAM_INVALID_REQ;
2147
2148 rsp->entry = NPC_MCAM_ENTRY_INVALID;
2149 rsp->free_count = 0;
2150
2151 /* Check if ref_entry is within range */
2152 if (req->priority && req->ref_entry >= mcam->bmap_entries)
2153 return NPC_MCAM_INVALID_REQ;
2154
2155 /* ref_entry can't be '0' if requested priority is high.
2156 * Can't be last entry if requested priority is low.
2157 */
2158 if ((!req->ref_entry && req->priority == NPC_MCAM_HIGHER_PRIO) ||
2159 ((req->ref_entry == (mcam->bmap_entries - 1)) &&
2160 req->priority == NPC_MCAM_LOWER_PRIO))
2161 return NPC_MCAM_INVALID_REQ;
2162
2163 /* Since list of allocated indices needs to be sent to requester,
2164 * max number of non-contiguous entries per mbox msg is limited.
2165 */
2166 if (!req->contig && req->count > NPC_MAX_NONCONTIG_ENTRIES)
2167 return NPC_MCAM_INVALID_REQ;
2168
2169 /* Alloc request from PFFUNC with no NIXLF attached should be denied */
2170 if (!is_nixlf_attached(rvu, pcifunc))
2171 return NPC_MCAM_ALLOC_DENIED;
2172
2173 return npc_mcam_alloc_entries(mcam, pcifunc, req, rsp);
2174 }
2175
rvu_mbox_handler_npc_mcam_free_entry(struct rvu * rvu,struct npc_mcam_free_entry_req * req,struct msg_rsp * rsp)2176 int rvu_mbox_handler_npc_mcam_free_entry(struct rvu *rvu,
2177 struct npc_mcam_free_entry_req *req,
2178 struct msg_rsp *rsp)
2179 {
2180 struct npc_mcam *mcam = &rvu->hw->mcam;
2181 u16 pcifunc = req->hdr.pcifunc;
2182 int blkaddr, rc = 0;
2183 u16 cntr;
2184
2185 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2186 if (blkaddr < 0)
2187 return NPC_MCAM_INVALID_REQ;
2188
2189 /* Free request from PFFUNC with no NIXLF attached, ignore */
2190 if (!is_nixlf_attached(rvu, pcifunc))
2191 return NPC_MCAM_INVALID_REQ;
2192
2193 mutex_lock(&mcam->lock);
2194
2195 if (req->all)
2196 goto free_all;
2197
2198 rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry);
2199 if (rc)
2200 goto exit;
2201
2202 mcam->entry2pfvf_map[req->entry] = 0;
2203 mcam->entry2target_pffunc[req->entry] = 0x0;
2204 npc_mcam_clear_bit(mcam, req->entry);
2205 npc_enable_mcam_entry(rvu, mcam, blkaddr, req->entry, false);
2206
2207 /* Update entry2counter mapping */
2208 cntr = mcam->entry2cntr_map[req->entry];
2209 if (cntr != NPC_MCAM_INVALID_MAP)
2210 npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr,
2211 req->entry, cntr);
2212
2213 goto exit;
2214
2215 free_all:
2216 /* Free up all entries allocated to requesting PFFUNC */
2217 npc_mcam_free_all_entries(rvu, mcam, blkaddr, pcifunc);
2218 exit:
2219 mutex_unlock(&mcam->lock);
2220 return rc;
2221 }
2222
rvu_mbox_handler_npc_mcam_read_entry(struct rvu * rvu,struct npc_mcam_read_entry_req * req,struct npc_mcam_read_entry_rsp * rsp)2223 int rvu_mbox_handler_npc_mcam_read_entry(struct rvu *rvu,
2224 struct npc_mcam_read_entry_req *req,
2225 struct npc_mcam_read_entry_rsp *rsp)
2226 {
2227 struct npc_mcam *mcam = &rvu->hw->mcam;
2228 u16 pcifunc = req->hdr.pcifunc;
2229 int blkaddr, rc;
2230
2231 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2232 if (blkaddr < 0)
2233 return NPC_MCAM_INVALID_REQ;
2234
2235 mutex_lock(&mcam->lock);
2236 rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry);
2237 if (!rc) {
2238 npc_read_mcam_entry(rvu, mcam, blkaddr, req->entry,
2239 &rsp->entry_data,
2240 &rsp->intf, &rsp->enable);
2241 }
2242
2243 mutex_unlock(&mcam->lock);
2244 return rc;
2245 }
2246
rvu_mbox_handler_npc_mcam_write_entry(struct rvu * rvu,struct npc_mcam_write_entry_req * req,struct msg_rsp * rsp)2247 int rvu_mbox_handler_npc_mcam_write_entry(struct rvu *rvu,
2248 struct npc_mcam_write_entry_req *req,
2249 struct msg_rsp *rsp)
2250 {
2251 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, req->hdr.pcifunc);
2252 struct npc_mcam *mcam = &rvu->hw->mcam;
2253 u16 pcifunc = req->hdr.pcifunc;
2254 u16 channel, chan_mask;
2255 int blkaddr, rc;
2256 u8 nix_intf;
2257
2258 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2259 if (blkaddr < 0)
2260 return NPC_MCAM_INVALID_REQ;
2261
2262 chan_mask = req->entry_data.kw_mask[0] & NPC_KEX_CHAN_MASK;
2263 channel = req->entry_data.kw[0] & NPC_KEX_CHAN_MASK;
2264 channel &= chan_mask;
2265
2266 mutex_lock(&mcam->lock);
2267 rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry);
2268 if (rc)
2269 goto exit;
2270
2271 if (req->set_cntr &&
2272 npc_mcam_verify_counter(mcam, pcifunc, req->cntr)) {
2273 rc = NPC_MCAM_INVALID_REQ;
2274 goto exit;
2275 }
2276
2277 if (!is_npc_interface_valid(rvu, req->intf)) {
2278 rc = NPC_MCAM_INVALID_REQ;
2279 goto exit;
2280 }
2281
2282 if (is_npc_intf_tx(req->intf))
2283 nix_intf = pfvf->nix_tx_intf;
2284 else
2285 nix_intf = pfvf->nix_rx_intf;
2286
2287 if (npc_mcam_verify_channel(rvu, pcifunc, req->intf, channel)) {
2288 rc = NPC_MCAM_INVALID_REQ;
2289 goto exit;
2290 }
2291
2292 if (npc_mcam_verify_pf_func(rvu, &req->entry_data, req->intf,
2293 pcifunc)) {
2294 rc = NPC_MCAM_INVALID_REQ;
2295 goto exit;
2296 }
2297
2298 /* For AF installed rules, the nix_intf should be set to target NIX */
2299 if (is_pffunc_af(req->hdr.pcifunc))
2300 nix_intf = req->intf;
2301
2302 npc_config_mcam_entry(rvu, mcam, blkaddr, req->entry, nix_intf,
2303 &req->entry_data, req->enable_entry);
2304
2305 if (req->set_cntr)
2306 npc_map_mcam_entry_and_cntr(rvu, mcam, blkaddr,
2307 req->entry, req->cntr);
2308
2309 rc = 0;
2310 exit:
2311 mutex_unlock(&mcam->lock);
2312 return rc;
2313 }
2314
rvu_mbox_handler_npc_mcam_ena_entry(struct rvu * rvu,struct npc_mcam_ena_dis_entry_req * req,struct msg_rsp * rsp)2315 int rvu_mbox_handler_npc_mcam_ena_entry(struct rvu *rvu,
2316 struct npc_mcam_ena_dis_entry_req *req,
2317 struct msg_rsp *rsp)
2318 {
2319 struct npc_mcam *mcam = &rvu->hw->mcam;
2320 u16 pcifunc = req->hdr.pcifunc;
2321 int blkaddr, rc;
2322
2323 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2324 if (blkaddr < 0)
2325 return NPC_MCAM_INVALID_REQ;
2326
2327 mutex_lock(&mcam->lock);
2328 rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry);
2329 mutex_unlock(&mcam->lock);
2330 if (rc)
2331 return rc;
2332
2333 npc_enable_mcam_entry(rvu, mcam, blkaddr, req->entry, true);
2334
2335 return 0;
2336 }
2337
rvu_mbox_handler_npc_mcam_dis_entry(struct rvu * rvu,struct npc_mcam_ena_dis_entry_req * req,struct msg_rsp * rsp)2338 int rvu_mbox_handler_npc_mcam_dis_entry(struct rvu *rvu,
2339 struct npc_mcam_ena_dis_entry_req *req,
2340 struct msg_rsp *rsp)
2341 {
2342 struct npc_mcam *mcam = &rvu->hw->mcam;
2343 u16 pcifunc = req->hdr.pcifunc;
2344 int blkaddr, rc;
2345
2346 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2347 if (blkaddr < 0)
2348 return NPC_MCAM_INVALID_REQ;
2349
2350 mutex_lock(&mcam->lock);
2351 rc = npc_mcam_verify_entry(mcam, pcifunc, req->entry);
2352 mutex_unlock(&mcam->lock);
2353 if (rc)
2354 return rc;
2355
2356 npc_enable_mcam_entry(rvu, mcam, blkaddr, req->entry, false);
2357
2358 return 0;
2359 }
2360
rvu_mbox_handler_npc_mcam_shift_entry(struct rvu * rvu,struct npc_mcam_shift_entry_req * req,struct npc_mcam_shift_entry_rsp * rsp)2361 int rvu_mbox_handler_npc_mcam_shift_entry(struct rvu *rvu,
2362 struct npc_mcam_shift_entry_req *req,
2363 struct npc_mcam_shift_entry_rsp *rsp)
2364 {
2365 struct npc_mcam *mcam = &rvu->hw->mcam;
2366 u16 pcifunc = req->hdr.pcifunc;
2367 u16 old_entry, new_entry;
2368 u16 index, cntr;
2369 int blkaddr, rc;
2370
2371 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2372 if (blkaddr < 0)
2373 return NPC_MCAM_INVALID_REQ;
2374
2375 if (req->shift_count > NPC_MCAM_MAX_SHIFTS)
2376 return NPC_MCAM_INVALID_REQ;
2377
2378 mutex_lock(&mcam->lock);
2379 for (index = 0; index < req->shift_count; index++) {
2380 old_entry = req->curr_entry[index];
2381 new_entry = req->new_entry[index];
2382
2383 /* Check if both old and new entries are valid and
2384 * does belong to this PFFUNC or not.
2385 */
2386 rc = npc_mcam_verify_entry(mcam, pcifunc, old_entry);
2387 if (rc)
2388 break;
2389
2390 rc = npc_mcam_verify_entry(mcam, pcifunc, new_entry);
2391 if (rc)
2392 break;
2393
2394 /* new_entry should not have a counter mapped */
2395 if (mcam->entry2cntr_map[new_entry] != NPC_MCAM_INVALID_MAP) {
2396 rc = NPC_MCAM_PERM_DENIED;
2397 break;
2398 }
2399
2400 /* Disable the new_entry */
2401 npc_enable_mcam_entry(rvu, mcam, blkaddr, new_entry, false);
2402
2403 /* Copy rule from old entry to new entry */
2404 npc_copy_mcam_entry(rvu, mcam, blkaddr, old_entry, new_entry);
2405
2406 /* Copy counter mapping, if any */
2407 cntr = mcam->entry2cntr_map[old_entry];
2408 if (cntr != NPC_MCAM_INVALID_MAP) {
2409 npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr,
2410 old_entry, cntr);
2411 npc_map_mcam_entry_and_cntr(rvu, mcam, blkaddr,
2412 new_entry, cntr);
2413 }
2414
2415 /* Enable new_entry and disable old_entry */
2416 npc_enable_mcam_entry(rvu, mcam, blkaddr, new_entry, true);
2417 npc_enable_mcam_entry(rvu, mcam, blkaddr, old_entry, false);
2418 }
2419
2420 /* If shift has failed then report the failed index */
2421 if (index != req->shift_count) {
2422 rc = NPC_MCAM_PERM_DENIED;
2423 rsp->failed_entry_idx = index;
2424 }
2425
2426 mutex_unlock(&mcam->lock);
2427 return rc;
2428 }
2429
rvu_mbox_handler_npc_mcam_alloc_counter(struct rvu * rvu,struct npc_mcam_alloc_counter_req * req,struct npc_mcam_alloc_counter_rsp * rsp)2430 int rvu_mbox_handler_npc_mcam_alloc_counter(struct rvu *rvu,
2431 struct npc_mcam_alloc_counter_req *req,
2432 struct npc_mcam_alloc_counter_rsp *rsp)
2433 {
2434 struct npc_mcam *mcam = &rvu->hw->mcam;
2435 u16 pcifunc = req->hdr.pcifunc;
2436 u16 max_contig, cntr;
2437 int blkaddr, index;
2438
2439 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2440 if (blkaddr < 0)
2441 return NPC_MCAM_INVALID_REQ;
2442
2443 /* If the request is from a PFFUNC with no NIXLF attached, ignore */
2444 if (!is_nixlf_attached(rvu, pcifunc))
2445 return NPC_MCAM_INVALID_REQ;
2446
2447 /* Since list of allocated counter IDs needs to be sent to requester,
2448 * max number of non-contiguous counters per mbox msg is limited.
2449 */
2450 if (!req->contig && req->count > NPC_MAX_NONCONTIG_COUNTERS)
2451 return NPC_MCAM_INVALID_REQ;
2452
2453 mutex_lock(&mcam->lock);
2454
2455 /* Check if unused counters are available or not */
2456 if (!rvu_rsrc_free_count(&mcam->counters)) {
2457 mutex_unlock(&mcam->lock);
2458 return NPC_MCAM_ALLOC_FAILED;
2459 }
2460
2461 rsp->count = 0;
2462
2463 if (req->contig) {
2464 /* Allocate requested number of contiguous counters, if
2465 * unsuccessful find max contiguous entries available.
2466 */
2467 index = npc_mcam_find_zero_area(mcam->counters.bmap,
2468 mcam->counters.max, 0,
2469 req->count, &max_contig);
2470 rsp->count = max_contig;
2471 rsp->cntr = index;
2472 for (cntr = index; cntr < (index + max_contig); cntr++) {
2473 __set_bit(cntr, mcam->counters.bmap);
2474 mcam->cntr2pfvf_map[cntr] = pcifunc;
2475 }
2476 } else {
2477 /* Allocate requested number of non-contiguous counters,
2478 * if unsuccessful allocate as many as possible.
2479 */
2480 for (cntr = 0; cntr < req->count; cntr++) {
2481 index = rvu_alloc_rsrc(&mcam->counters);
2482 if (index < 0)
2483 break;
2484 rsp->cntr_list[cntr] = index;
2485 rsp->count++;
2486 mcam->cntr2pfvf_map[index] = pcifunc;
2487 }
2488 }
2489
2490 mutex_unlock(&mcam->lock);
2491 return 0;
2492 }
2493
rvu_mbox_handler_npc_mcam_free_counter(struct rvu * rvu,struct npc_mcam_oper_counter_req * req,struct msg_rsp * rsp)2494 int rvu_mbox_handler_npc_mcam_free_counter(struct rvu *rvu,
2495 struct npc_mcam_oper_counter_req *req, struct msg_rsp *rsp)
2496 {
2497 struct npc_mcam *mcam = &rvu->hw->mcam;
2498 u16 index, entry = 0;
2499 int blkaddr, err;
2500
2501 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2502 if (blkaddr < 0)
2503 return NPC_MCAM_INVALID_REQ;
2504
2505 mutex_lock(&mcam->lock);
2506 err = npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr);
2507 if (err) {
2508 mutex_unlock(&mcam->lock);
2509 return err;
2510 }
2511
2512 /* Mark counter as free/unused */
2513 mcam->cntr2pfvf_map[req->cntr] = NPC_MCAM_INVALID_MAP;
2514 rvu_free_rsrc(&mcam->counters, req->cntr);
2515
2516 /* Disable all MCAM entry's stats which are using this counter */
2517 while (entry < mcam->bmap_entries) {
2518 if (!mcam->cntr_refcnt[req->cntr])
2519 break;
2520
2521 index = find_next_bit(mcam->bmap, mcam->bmap_entries, entry);
2522 if (index >= mcam->bmap_entries)
2523 break;
2524 entry = index + 1;
2525 if (mcam->entry2cntr_map[index] != req->cntr)
2526 continue;
2527
2528 npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr,
2529 index, req->cntr);
2530 }
2531
2532 mutex_unlock(&mcam->lock);
2533 return 0;
2534 }
2535
rvu_mbox_handler_npc_mcam_unmap_counter(struct rvu * rvu,struct npc_mcam_unmap_counter_req * req,struct msg_rsp * rsp)2536 int rvu_mbox_handler_npc_mcam_unmap_counter(struct rvu *rvu,
2537 struct npc_mcam_unmap_counter_req *req, struct msg_rsp *rsp)
2538 {
2539 struct npc_mcam *mcam = &rvu->hw->mcam;
2540 u16 index, entry = 0;
2541 int blkaddr, rc;
2542
2543 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2544 if (blkaddr < 0)
2545 return NPC_MCAM_INVALID_REQ;
2546
2547 mutex_lock(&mcam->lock);
2548 rc = npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr);
2549 if (rc)
2550 goto exit;
2551
2552 /* Unmap the MCAM entry and counter */
2553 if (!req->all) {
2554 rc = npc_mcam_verify_entry(mcam, req->hdr.pcifunc, req->entry);
2555 if (rc)
2556 goto exit;
2557 npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr,
2558 req->entry, req->cntr);
2559 goto exit;
2560 }
2561
2562 /* Disable all MCAM entry's stats which are using this counter */
2563 while (entry < mcam->bmap_entries) {
2564 if (!mcam->cntr_refcnt[req->cntr])
2565 break;
2566
2567 index = find_next_bit(mcam->bmap, mcam->bmap_entries, entry);
2568 if (index >= mcam->bmap_entries)
2569 break;
2570 if (mcam->entry2cntr_map[index] != req->cntr)
2571 continue;
2572
2573 entry = index + 1;
2574 npc_unmap_mcam_entry_and_cntr(rvu, mcam, blkaddr,
2575 index, req->cntr);
2576 }
2577 exit:
2578 mutex_unlock(&mcam->lock);
2579 return rc;
2580 }
2581
rvu_mbox_handler_npc_mcam_clear_counter(struct rvu * rvu,struct npc_mcam_oper_counter_req * req,struct msg_rsp * rsp)2582 int rvu_mbox_handler_npc_mcam_clear_counter(struct rvu *rvu,
2583 struct npc_mcam_oper_counter_req *req, struct msg_rsp *rsp)
2584 {
2585 struct npc_mcam *mcam = &rvu->hw->mcam;
2586 int blkaddr, err;
2587
2588 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2589 if (blkaddr < 0)
2590 return NPC_MCAM_INVALID_REQ;
2591
2592 mutex_lock(&mcam->lock);
2593 err = npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr);
2594 mutex_unlock(&mcam->lock);
2595 if (err)
2596 return err;
2597
2598 rvu_write64(rvu, blkaddr, NPC_AF_MATCH_STATX(req->cntr), 0x00);
2599
2600 return 0;
2601 }
2602
rvu_mbox_handler_npc_mcam_counter_stats(struct rvu * rvu,struct npc_mcam_oper_counter_req * req,struct npc_mcam_oper_counter_rsp * rsp)2603 int rvu_mbox_handler_npc_mcam_counter_stats(struct rvu *rvu,
2604 struct npc_mcam_oper_counter_req *req,
2605 struct npc_mcam_oper_counter_rsp *rsp)
2606 {
2607 struct npc_mcam *mcam = &rvu->hw->mcam;
2608 int blkaddr, err;
2609
2610 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2611 if (blkaddr < 0)
2612 return NPC_MCAM_INVALID_REQ;
2613
2614 mutex_lock(&mcam->lock);
2615 err = npc_mcam_verify_counter(mcam, req->hdr.pcifunc, req->cntr);
2616 mutex_unlock(&mcam->lock);
2617 if (err)
2618 return err;
2619
2620 rsp->stat = rvu_read64(rvu, blkaddr, NPC_AF_MATCH_STATX(req->cntr));
2621 rsp->stat &= BIT_ULL(48) - 1;
2622
2623 return 0;
2624 }
2625
rvu_mbox_handler_npc_mcam_alloc_and_write_entry(struct rvu * rvu,struct npc_mcam_alloc_and_write_entry_req * req,struct npc_mcam_alloc_and_write_entry_rsp * rsp)2626 int rvu_mbox_handler_npc_mcam_alloc_and_write_entry(struct rvu *rvu,
2627 struct npc_mcam_alloc_and_write_entry_req *req,
2628 struct npc_mcam_alloc_and_write_entry_rsp *rsp)
2629 {
2630 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, req->hdr.pcifunc);
2631 struct npc_mcam_alloc_counter_req cntr_req;
2632 struct npc_mcam_alloc_counter_rsp cntr_rsp;
2633 struct npc_mcam_alloc_entry_req entry_req;
2634 struct npc_mcam_alloc_entry_rsp entry_rsp;
2635 struct npc_mcam *mcam = &rvu->hw->mcam;
2636 u16 entry = NPC_MCAM_ENTRY_INVALID;
2637 u16 cntr = NPC_MCAM_ENTRY_INVALID;
2638 u16 channel, chan_mask;
2639 int blkaddr, rc;
2640 u8 nix_intf;
2641
2642 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2643 if (blkaddr < 0)
2644 return NPC_MCAM_INVALID_REQ;
2645
2646 if (!is_npc_interface_valid(rvu, req->intf))
2647 return NPC_MCAM_INVALID_REQ;
2648
2649 chan_mask = req->entry_data.kw_mask[0] & NPC_KEX_CHAN_MASK;
2650 channel = req->entry_data.kw[0] & NPC_KEX_CHAN_MASK;
2651 channel &= chan_mask;
2652
2653 if (npc_mcam_verify_channel(rvu, req->hdr.pcifunc, req->intf, channel))
2654 return NPC_MCAM_INVALID_REQ;
2655
2656 if (npc_mcam_verify_pf_func(rvu, &req->entry_data, req->intf,
2657 req->hdr.pcifunc))
2658 return NPC_MCAM_INVALID_REQ;
2659
2660 /* Try to allocate a MCAM entry */
2661 entry_req.hdr.pcifunc = req->hdr.pcifunc;
2662 entry_req.contig = true;
2663 entry_req.priority = req->priority;
2664 entry_req.ref_entry = req->ref_entry;
2665 entry_req.count = 1;
2666
2667 rc = rvu_mbox_handler_npc_mcam_alloc_entry(rvu,
2668 &entry_req, &entry_rsp);
2669 if (rc)
2670 return rc;
2671
2672 if (!entry_rsp.count)
2673 return NPC_MCAM_ALLOC_FAILED;
2674
2675 entry = entry_rsp.entry;
2676
2677 if (!req->alloc_cntr)
2678 goto write_entry;
2679
2680 /* Now allocate counter */
2681 cntr_req.hdr.pcifunc = req->hdr.pcifunc;
2682 cntr_req.contig = true;
2683 cntr_req.count = 1;
2684
2685 rc = rvu_mbox_handler_npc_mcam_alloc_counter(rvu, &cntr_req, &cntr_rsp);
2686 if (rc) {
2687 /* Free allocated MCAM entry */
2688 mutex_lock(&mcam->lock);
2689 mcam->entry2pfvf_map[entry] = 0;
2690 npc_mcam_clear_bit(mcam, entry);
2691 mutex_unlock(&mcam->lock);
2692 return rc;
2693 }
2694
2695 cntr = cntr_rsp.cntr;
2696
2697 write_entry:
2698 mutex_lock(&mcam->lock);
2699
2700 if (is_npc_intf_tx(req->intf))
2701 nix_intf = pfvf->nix_tx_intf;
2702 else
2703 nix_intf = pfvf->nix_rx_intf;
2704
2705 npc_config_mcam_entry(rvu, mcam, blkaddr, entry, nix_intf,
2706 &req->entry_data, req->enable_entry);
2707
2708 if (req->alloc_cntr)
2709 npc_map_mcam_entry_and_cntr(rvu, mcam, blkaddr, entry, cntr);
2710 mutex_unlock(&mcam->lock);
2711
2712 rsp->entry = entry;
2713 rsp->cntr = cntr;
2714
2715 return 0;
2716 }
2717
2718 #define GET_KEX_CFG(intf) \
2719 rvu_read64(rvu, BLKADDR_NPC, NPC_AF_INTFX_KEX_CFG(intf))
2720
2721 #define GET_KEX_FLAGS(ld) \
2722 rvu_read64(rvu, BLKADDR_NPC, NPC_AF_KEX_LDATAX_FLAGS_CFG(ld))
2723
2724 #define GET_KEX_LD(intf, lid, lt, ld) \
2725 rvu_read64(rvu, BLKADDR_NPC, \
2726 NPC_AF_INTFX_LIDX_LTX_LDX_CFG(intf, lid, lt, ld))
2727
2728 #define GET_KEX_LDFLAGS(intf, ld, fl) \
2729 rvu_read64(rvu, BLKADDR_NPC, \
2730 NPC_AF_INTFX_LDATAX_FLAGSX_CFG(intf, ld, fl))
2731
rvu_mbox_handler_npc_get_kex_cfg(struct rvu * rvu,struct msg_req * req,struct npc_get_kex_cfg_rsp * rsp)2732 int rvu_mbox_handler_npc_get_kex_cfg(struct rvu *rvu, struct msg_req *req,
2733 struct npc_get_kex_cfg_rsp *rsp)
2734 {
2735 int lid, lt, ld, fl;
2736
2737 rsp->rx_keyx_cfg = GET_KEX_CFG(NIX_INTF_RX);
2738 rsp->tx_keyx_cfg = GET_KEX_CFG(NIX_INTF_TX);
2739 for (lid = 0; lid < NPC_MAX_LID; lid++) {
2740 for (lt = 0; lt < NPC_MAX_LT; lt++) {
2741 for (ld = 0; ld < NPC_MAX_LD; ld++) {
2742 rsp->intf_lid_lt_ld[NIX_INTF_RX][lid][lt][ld] =
2743 GET_KEX_LD(NIX_INTF_RX, lid, lt, ld);
2744 rsp->intf_lid_lt_ld[NIX_INTF_TX][lid][lt][ld] =
2745 GET_KEX_LD(NIX_INTF_TX, lid, lt, ld);
2746 }
2747 }
2748 }
2749 for (ld = 0; ld < NPC_MAX_LD; ld++)
2750 rsp->kex_ld_flags[ld] = GET_KEX_FLAGS(ld);
2751
2752 for (ld = 0; ld < NPC_MAX_LD; ld++) {
2753 for (fl = 0; fl < NPC_MAX_LFL; fl++) {
2754 rsp->intf_ld_flags[NIX_INTF_RX][ld][fl] =
2755 GET_KEX_LDFLAGS(NIX_INTF_RX, ld, fl);
2756 rsp->intf_ld_flags[NIX_INTF_TX][ld][fl] =
2757 GET_KEX_LDFLAGS(NIX_INTF_TX, ld, fl);
2758 }
2759 }
2760 memcpy(rsp->mkex_pfl_name, rvu->mkex_pfl_name, MKEX_NAME_LEN);
2761 return 0;
2762 }
2763
rvu_mbox_handler_npc_read_base_steer_rule(struct rvu * rvu,struct msg_req * req,struct npc_mcam_read_base_rule_rsp * rsp)2764 int rvu_mbox_handler_npc_read_base_steer_rule(struct rvu *rvu,
2765 struct msg_req *req,
2766 struct npc_mcam_read_base_rule_rsp *rsp)
2767 {
2768 struct npc_mcam *mcam = &rvu->hw->mcam;
2769 int index, blkaddr, nixlf, rc = 0;
2770 u16 pcifunc = req->hdr.pcifunc;
2771 struct rvu_pfvf *pfvf;
2772 u8 intf, enable;
2773
2774 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2775 if (blkaddr < 0)
2776 return NPC_MCAM_INVALID_REQ;
2777
2778 /* Return the channel number in case of PF */
2779 if (!(pcifunc & RVU_PFVF_FUNC_MASK)) {
2780 pfvf = rvu_get_pfvf(rvu, pcifunc);
2781 rsp->entry.kw[0] = pfvf->rx_chan_base;
2782 rsp->entry.kw_mask[0] = 0xFFFULL;
2783 goto out;
2784 }
2785
2786 /* Find the pkt steering rule installed by PF to this VF */
2787 mutex_lock(&mcam->lock);
2788 for (index = 0; index < mcam->bmap_entries; index++) {
2789 if (mcam->entry2target_pffunc[index] == pcifunc)
2790 goto read_entry;
2791 }
2792
2793 rc = nix_get_nixlf(rvu, pcifunc, &nixlf, NULL);
2794 if (rc < 0) {
2795 mutex_unlock(&mcam->lock);
2796 goto out;
2797 }
2798 /* Read the default ucast entry if there is no pkt steering rule */
2799 index = npc_get_nixlf_mcam_index(mcam, pcifunc, nixlf,
2800 NIXLF_UCAST_ENTRY);
2801 read_entry:
2802 /* Read the mcam entry */
2803 npc_read_mcam_entry(rvu, mcam, blkaddr, index, &rsp->entry, &intf,
2804 &enable);
2805 mutex_unlock(&mcam->lock);
2806 out:
2807 return rc;
2808 }
2809
rvu_mbox_handler_npc_mcam_entry_stats(struct rvu * rvu,struct npc_mcam_get_stats_req * req,struct npc_mcam_get_stats_rsp * rsp)2810 int rvu_mbox_handler_npc_mcam_entry_stats(struct rvu *rvu,
2811 struct npc_mcam_get_stats_req *req,
2812 struct npc_mcam_get_stats_rsp *rsp)
2813 {
2814 struct npc_mcam *mcam = &rvu->hw->mcam;
2815 u16 index, cntr;
2816 int blkaddr;
2817 u64 regval;
2818 u32 bank;
2819
2820 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
2821 if (blkaddr < 0)
2822 return NPC_MCAM_INVALID_REQ;
2823
2824 mutex_lock(&mcam->lock);
2825
2826 index = req->entry & (mcam->banksize - 1);
2827 bank = npc_get_bank(mcam, req->entry);
2828
2829 /* read MCAM entry STAT_ACT register */
2830 regval = rvu_read64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_STAT_ACT(index, bank));
2831
2832 if (!(regval & BIT_ULL(9))) {
2833 rsp->stat_ena = 0;
2834 mutex_unlock(&mcam->lock);
2835 return 0;
2836 }
2837
2838 cntr = regval & 0x1FF;
2839
2840 rsp->stat_ena = 1;
2841 rsp->stat = rvu_read64(rvu, blkaddr, NPC_AF_MATCH_STATX(cntr));
2842 rsp->stat &= BIT_ULL(48) - 1;
2843
2844 mutex_unlock(&mcam->lock);
2845
2846 return 0;
2847 }
2848