1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
2 /* Copyright (c) 2019, Mellanox Technologies */
3
4 #ifndef _DR_TYPES_
5 #define _DR_TYPES_
6
7 #include <linux/mlx5/driver.h>
8 #include <linux/refcount.h>
9 #include "fs_core.h"
10 #include "wq.h"
11 #include "lib/mlx5.h"
12 #include "mlx5_ifc_dr.h"
13 #include "mlx5dr.h"
14
15 #define DR_RULE_MAX_STES 18
16 #define DR_ACTION_MAX_STES 5
17 #define WIRE_PORT 0xFFFF
18 #define DR_STE_SVLAN 0x1
19 #define DR_STE_CVLAN 0x2
20 #define DR_SZ_MATCH_PARAM (MLX5_ST_SZ_DW_MATCH_PARAM * 4)
21 #define DR_NUM_OF_FLEX_PARSERS 8
22 #define DR_STE_MAX_FLEX_0_ID 3
23 #define DR_STE_MAX_FLEX_1_ID 7
24
25 #define mlx5dr_err(dmn, arg...) mlx5_core_err((dmn)->mdev, ##arg)
26 #define mlx5dr_info(dmn, arg...) mlx5_core_info((dmn)->mdev, ##arg)
27 #define mlx5dr_dbg(dmn, arg...) mlx5_core_dbg((dmn)->mdev, ##arg)
28
dr_is_flex_parser_0_id(u8 parser_id)29 static inline bool dr_is_flex_parser_0_id(u8 parser_id)
30 {
31 return parser_id <= DR_STE_MAX_FLEX_0_ID;
32 }
33
dr_is_flex_parser_1_id(u8 parser_id)34 static inline bool dr_is_flex_parser_1_id(u8 parser_id)
35 {
36 return parser_id > DR_STE_MAX_FLEX_0_ID;
37 }
38
39 enum mlx5dr_icm_chunk_size {
40 DR_CHUNK_SIZE_1,
41 DR_CHUNK_SIZE_MIN = DR_CHUNK_SIZE_1, /* keep updated when changing */
42 DR_CHUNK_SIZE_2,
43 DR_CHUNK_SIZE_4,
44 DR_CHUNK_SIZE_8,
45 DR_CHUNK_SIZE_16,
46 DR_CHUNK_SIZE_32,
47 DR_CHUNK_SIZE_64,
48 DR_CHUNK_SIZE_128,
49 DR_CHUNK_SIZE_256,
50 DR_CHUNK_SIZE_512,
51 DR_CHUNK_SIZE_1K,
52 DR_CHUNK_SIZE_2K,
53 DR_CHUNK_SIZE_4K,
54 DR_CHUNK_SIZE_8K,
55 DR_CHUNK_SIZE_16K,
56 DR_CHUNK_SIZE_32K,
57 DR_CHUNK_SIZE_64K,
58 DR_CHUNK_SIZE_128K,
59 DR_CHUNK_SIZE_256K,
60 DR_CHUNK_SIZE_512K,
61 DR_CHUNK_SIZE_1024K,
62 DR_CHUNK_SIZE_2048K,
63 DR_CHUNK_SIZE_MAX,
64 };
65
66 enum mlx5dr_icm_type {
67 DR_ICM_TYPE_STE,
68 DR_ICM_TYPE_MODIFY_ACTION,
69 };
70
71 static inline enum mlx5dr_icm_chunk_size
mlx5dr_icm_next_higher_chunk(enum mlx5dr_icm_chunk_size chunk)72 mlx5dr_icm_next_higher_chunk(enum mlx5dr_icm_chunk_size chunk)
73 {
74 chunk += 2;
75 if (chunk < DR_CHUNK_SIZE_MAX)
76 return chunk;
77
78 return DR_CHUNK_SIZE_MAX;
79 }
80
81 enum {
82 DR_STE_SIZE = 64,
83 DR_STE_SIZE_CTRL = 32,
84 DR_STE_SIZE_TAG = 16,
85 DR_STE_SIZE_MASK = 16,
86 };
87
88 enum {
89 DR_STE_SIZE_REDUCED = DR_STE_SIZE - DR_STE_SIZE_MASK,
90 };
91
92 enum {
93 DR_MODIFY_ACTION_SIZE = 8,
94 };
95
96 enum mlx5dr_matcher_criteria {
97 DR_MATCHER_CRITERIA_EMPTY = 0,
98 DR_MATCHER_CRITERIA_OUTER = 1 << 0,
99 DR_MATCHER_CRITERIA_MISC = 1 << 1,
100 DR_MATCHER_CRITERIA_INNER = 1 << 2,
101 DR_MATCHER_CRITERIA_MISC2 = 1 << 3,
102 DR_MATCHER_CRITERIA_MISC3 = 1 << 4,
103 DR_MATCHER_CRITERIA_MISC4 = 1 << 5,
104 DR_MATCHER_CRITERIA_MAX = 1 << 6,
105 };
106
107 enum mlx5dr_action_type {
108 DR_ACTION_TYP_TNL_L2_TO_L2,
109 DR_ACTION_TYP_L2_TO_TNL_L2,
110 DR_ACTION_TYP_TNL_L3_TO_L2,
111 DR_ACTION_TYP_L2_TO_TNL_L3,
112 DR_ACTION_TYP_DROP,
113 DR_ACTION_TYP_QP,
114 DR_ACTION_TYP_FT,
115 DR_ACTION_TYP_CTR,
116 DR_ACTION_TYP_TAG,
117 DR_ACTION_TYP_MODIFY_HDR,
118 DR_ACTION_TYP_VPORT,
119 DR_ACTION_TYP_POP_VLAN,
120 DR_ACTION_TYP_PUSH_VLAN,
121 DR_ACTION_TYP_MAX,
122 };
123
124 enum mlx5dr_ipv {
125 DR_RULE_IPV4,
126 DR_RULE_IPV6,
127 DR_RULE_IPV_MAX,
128 };
129
130 struct mlx5dr_icm_pool;
131 struct mlx5dr_icm_chunk;
132 struct mlx5dr_icm_buddy_mem;
133 struct mlx5dr_ste_htbl;
134 struct mlx5dr_match_param;
135 struct mlx5dr_cmd_caps;
136 struct mlx5dr_matcher_rx_tx;
137 struct mlx5dr_ste_ctx;
138
139 struct mlx5dr_ste {
140 u8 *hw_ste;
141 /* refcount: indicates the num of rules that using this ste */
142 u32 refcount;
143
144 /* attached to the miss_list head at each htbl entry */
145 struct list_head miss_list_node;
146
147 /* each rule member that uses this ste attached here */
148 struct list_head rule_list;
149
150 /* this ste is member of htbl */
151 struct mlx5dr_ste_htbl *htbl;
152
153 struct mlx5dr_ste_htbl *next_htbl;
154
155 /* this ste is part of a rule, located in ste's chain */
156 u8 ste_chain_location;
157 };
158
159 struct mlx5dr_ste_htbl_ctrl {
160 /* total number of valid entries belonging to this hash table. This
161 * includes the non collision and collision entries
162 */
163 unsigned int num_of_valid_entries;
164
165 /* total number of collisions entries attached to this table */
166 unsigned int num_of_collisions;
167 unsigned int increase_threshold;
168 u8 may_grow:1;
169 };
170
171 struct mlx5dr_ste_htbl {
172 u16 lu_type;
173 u16 byte_mask;
174 u32 refcount;
175 struct mlx5dr_icm_chunk *chunk;
176 struct mlx5dr_ste *ste_arr;
177 u8 *hw_ste_arr;
178
179 struct list_head *miss_list;
180
181 enum mlx5dr_icm_chunk_size chunk_size;
182 struct mlx5dr_ste *pointing_ste;
183
184 struct mlx5dr_ste_htbl_ctrl ctrl;
185 };
186
187 struct mlx5dr_ste_send_info {
188 struct mlx5dr_ste *ste;
189 struct list_head send_list;
190 u16 size;
191 u16 offset;
192 u8 data_cont[DR_STE_SIZE];
193 u8 *data;
194 };
195
196 void mlx5dr_send_fill_and_append_ste_send_info(struct mlx5dr_ste *ste, u16 size,
197 u16 offset, u8 *data,
198 struct mlx5dr_ste_send_info *ste_info,
199 struct list_head *send_list,
200 bool copy_data);
201
202 struct mlx5dr_ste_build {
203 u8 inner:1;
204 u8 rx:1;
205 u8 vhca_id_valid:1;
206 struct mlx5dr_domain *dmn;
207 struct mlx5dr_cmd_caps *caps;
208 u16 lu_type;
209 u16 byte_mask;
210 u8 bit_mask[DR_STE_SIZE_MASK];
211 int (*ste_build_tag_func)(struct mlx5dr_match_param *spec,
212 struct mlx5dr_ste_build *sb,
213 u8 *tag);
214 };
215
216 struct mlx5dr_ste_htbl *
217 mlx5dr_ste_htbl_alloc(struct mlx5dr_icm_pool *pool,
218 enum mlx5dr_icm_chunk_size chunk_size,
219 u16 lu_type, u16 byte_mask);
220
221 int mlx5dr_ste_htbl_free(struct mlx5dr_ste_htbl *htbl);
222
mlx5dr_htbl_put(struct mlx5dr_ste_htbl * htbl)223 static inline void mlx5dr_htbl_put(struct mlx5dr_ste_htbl *htbl)
224 {
225 htbl->refcount--;
226 if (!htbl->refcount)
227 mlx5dr_ste_htbl_free(htbl);
228 }
229
mlx5dr_htbl_get(struct mlx5dr_ste_htbl * htbl)230 static inline void mlx5dr_htbl_get(struct mlx5dr_ste_htbl *htbl)
231 {
232 htbl->refcount++;
233 }
234
235 /* STE utils */
236 u32 mlx5dr_ste_calc_hash_index(u8 *hw_ste_p, struct mlx5dr_ste_htbl *htbl);
237 void mlx5dr_ste_set_miss_addr(struct mlx5dr_ste_ctx *ste_ctx,
238 u8 *hw_ste, u64 miss_addr);
239 void mlx5dr_ste_set_hit_addr(struct mlx5dr_ste_ctx *ste_ctx,
240 u8 *hw_ste, u64 icm_addr, u32 ht_size);
241 void mlx5dr_ste_set_hit_addr_by_next_htbl(struct mlx5dr_ste_ctx *ste_ctx,
242 u8 *hw_ste,
243 struct mlx5dr_ste_htbl *next_htbl);
244 void mlx5dr_ste_set_bit_mask(u8 *hw_ste_p, u8 *bit_mask);
245 bool mlx5dr_ste_is_last_in_rule(struct mlx5dr_matcher_rx_tx *nic_matcher,
246 u8 ste_location);
247 u64 mlx5dr_ste_get_icm_addr(struct mlx5dr_ste *ste);
248 u64 mlx5dr_ste_get_mr_addr(struct mlx5dr_ste *ste);
249 struct list_head *mlx5dr_ste_get_miss_list(struct mlx5dr_ste *ste);
250
251 #define MLX5DR_MAX_VLANS 2
252
253 struct mlx5dr_ste_actions_attr {
254 u32 modify_index;
255 u16 modify_actions;
256 u32 decap_index;
257 u16 decap_actions;
258 u8 decap_with_vlan:1;
259 u64 final_icm_addr;
260 u32 flow_tag;
261 u32 ctr_id;
262 u16 gvmi;
263 u16 hit_gvmi;
264 u32 reformat_id;
265 u32 reformat_size;
266 struct {
267 int count;
268 u32 headers[MLX5DR_MAX_VLANS];
269 } vlans;
270 };
271
272 void mlx5dr_ste_set_actions_rx(struct mlx5dr_ste_ctx *ste_ctx,
273 struct mlx5dr_domain *dmn,
274 u8 *action_type_set,
275 u8 *last_ste,
276 struct mlx5dr_ste_actions_attr *attr,
277 u32 *added_stes);
278 void mlx5dr_ste_set_actions_tx(struct mlx5dr_ste_ctx *ste_ctx,
279 struct mlx5dr_domain *dmn,
280 u8 *action_type_set,
281 u8 *last_ste,
282 struct mlx5dr_ste_actions_attr *attr,
283 u32 *added_stes);
284
285 void mlx5dr_ste_set_action_set(struct mlx5dr_ste_ctx *ste_ctx,
286 __be64 *hw_action,
287 u8 hw_field,
288 u8 shifter,
289 u8 length,
290 u32 data);
291 void mlx5dr_ste_set_action_add(struct mlx5dr_ste_ctx *ste_ctx,
292 __be64 *hw_action,
293 u8 hw_field,
294 u8 shifter,
295 u8 length,
296 u32 data);
297 void mlx5dr_ste_set_action_copy(struct mlx5dr_ste_ctx *ste_ctx,
298 __be64 *hw_action,
299 u8 dst_hw_field,
300 u8 dst_shifter,
301 u8 dst_len,
302 u8 src_hw_field,
303 u8 src_shifter);
304 int mlx5dr_ste_set_action_decap_l3_list(struct mlx5dr_ste_ctx *ste_ctx,
305 void *data,
306 u32 data_sz,
307 u8 *hw_action,
308 u32 hw_action_sz,
309 u16 *used_hw_action_num);
310
311 const struct mlx5dr_ste_action_modify_field *
312 mlx5dr_ste_conv_modify_hdr_sw_field(struct mlx5dr_ste_ctx *ste_ctx, u16 sw_field);
313
314 struct mlx5dr_ste_ctx *mlx5dr_ste_get_ctx(u8 version);
315 void mlx5dr_ste_free(struct mlx5dr_ste *ste,
316 struct mlx5dr_matcher *matcher,
317 struct mlx5dr_matcher_rx_tx *nic_matcher);
mlx5dr_ste_put(struct mlx5dr_ste * ste,struct mlx5dr_matcher * matcher,struct mlx5dr_matcher_rx_tx * nic_matcher)318 static inline void mlx5dr_ste_put(struct mlx5dr_ste *ste,
319 struct mlx5dr_matcher *matcher,
320 struct mlx5dr_matcher_rx_tx *nic_matcher)
321 {
322 ste->refcount--;
323 if (!ste->refcount)
324 mlx5dr_ste_free(ste, matcher, nic_matcher);
325 }
326
327 /* initial as 0, increased only when ste appears in a new rule */
mlx5dr_ste_get(struct mlx5dr_ste * ste)328 static inline void mlx5dr_ste_get(struct mlx5dr_ste *ste)
329 {
330 ste->refcount++;
331 }
332
mlx5dr_ste_is_not_used(struct mlx5dr_ste * ste)333 static inline bool mlx5dr_ste_is_not_used(struct mlx5dr_ste *ste)
334 {
335 return !ste->refcount;
336 }
337
338 bool mlx5dr_ste_equal_tag(void *src, void *dst);
339 int mlx5dr_ste_create_next_htbl(struct mlx5dr_matcher *matcher,
340 struct mlx5dr_matcher_rx_tx *nic_matcher,
341 struct mlx5dr_ste *ste,
342 u8 *cur_hw_ste,
343 enum mlx5dr_icm_chunk_size log_table_size);
344
345 /* STE build functions */
346 int mlx5dr_ste_build_pre_check(struct mlx5dr_domain *dmn,
347 u8 match_criteria,
348 struct mlx5dr_match_param *mask,
349 struct mlx5dr_match_param *value);
350 int mlx5dr_ste_build_ste_arr(struct mlx5dr_matcher *matcher,
351 struct mlx5dr_matcher_rx_tx *nic_matcher,
352 struct mlx5dr_match_param *value,
353 u8 *ste_arr);
354 void mlx5dr_ste_build_eth_l2_src_dst(struct mlx5dr_ste_ctx *ste_ctx,
355 struct mlx5dr_ste_build *builder,
356 struct mlx5dr_match_param *mask,
357 bool inner, bool rx);
358 void mlx5dr_ste_build_eth_l3_ipv4_5_tuple(struct mlx5dr_ste_ctx *ste_ctx,
359 struct mlx5dr_ste_build *sb,
360 struct mlx5dr_match_param *mask,
361 bool inner, bool rx);
362 void mlx5dr_ste_build_eth_l3_ipv4_misc(struct mlx5dr_ste_ctx *ste_ctx,
363 struct mlx5dr_ste_build *sb,
364 struct mlx5dr_match_param *mask,
365 bool inner, bool rx);
366 void mlx5dr_ste_build_eth_l3_ipv6_dst(struct mlx5dr_ste_ctx *ste_ctx,
367 struct mlx5dr_ste_build *sb,
368 struct mlx5dr_match_param *mask,
369 bool inner, bool rx);
370 void mlx5dr_ste_build_eth_l3_ipv6_src(struct mlx5dr_ste_ctx *ste_ctx,
371 struct mlx5dr_ste_build *sb,
372 struct mlx5dr_match_param *mask,
373 bool inner, bool rx);
374 void mlx5dr_ste_build_eth_l2_src(struct mlx5dr_ste_ctx *ste_ctx,
375 struct mlx5dr_ste_build *sb,
376 struct mlx5dr_match_param *mask,
377 bool inner, bool rx);
378 void mlx5dr_ste_build_eth_l2_dst(struct mlx5dr_ste_ctx *ste_ctx,
379 struct mlx5dr_ste_build *sb,
380 struct mlx5dr_match_param *mask,
381 bool inner, bool rx);
382 void mlx5dr_ste_build_eth_l2_tnl(struct mlx5dr_ste_ctx *ste_ctx,
383 struct mlx5dr_ste_build *sb,
384 struct mlx5dr_match_param *mask,
385 bool inner, bool rx);
386 void mlx5dr_ste_build_eth_ipv6_l3_l4(struct mlx5dr_ste_ctx *ste_ctx,
387 struct mlx5dr_ste_build *sb,
388 struct mlx5dr_match_param *mask,
389 bool inner, bool rx);
390 void mlx5dr_ste_build_eth_l4_misc(struct mlx5dr_ste_ctx *ste_ctx,
391 struct mlx5dr_ste_build *sb,
392 struct mlx5dr_match_param *mask,
393 bool inner, bool rx);
394 void mlx5dr_ste_build_tnl_gre(struct mlx5dr_ste_ctx *ste_ctx,
395 struct mlx5dr_ste_build *sb,
396 struct mlx5dr_match_param *mask,
397 bool inner, bool rx);
398 void mlx5dr_ste_build_mpls(struct mlx5dr_ste_ctx *ste_ctx,
399 struct mlx5dr_ste_build *sb,
400 struct mlx5dr_match_param *mask,
401 bool inner, bool rx);
402 void mlx5dr_ste_build_tnl_mpls(struct mlx5dr_ste_ctx *ste_ctx,
403 struct mlx5dr_ste_build *sb,
404 struct mlx5dr_match_param *mask,
405 bool inner, bool rx);
406 void mlx5dr_ste_build_tnl_mpls_over_gre(struct mlx5dr_ste_ctx *ste_ctx,
407 struct mlx5dr_ste_build *sb,
408 struct mlx5dr_match_param *mask,
409 struct mlx5dr_cmd_caps *caps,
410 bool inner, bool rx);
411 void mlx5dr_ste_build_tnl_mpls_over_udp(struct mlx5dr_ste_ctx *ste_ctx,
412 struct mlx5dr_ste_build *sb,
413 struct mlx5dr_match_param *mask,
414 struct mlx5dr_cmd_caps *caps,
415 bool inner, bool rx);
416 void mlx5dr_ste_build_icmp(struct mlx5dr_ste_ctx *ste_ctx,
417 struct mlx5dr_ste_build *sb,
418 struct mlx5dr_match_param *mask,
419 struct mlx5dr_cmd_caps *caps,
420 bool inner, bool rx);
421 void mlx5dr_ste_build_tnl_vxlan_gpe(struct mlx5dr_ste_ctx *ste_ctx,
422 struct mlx5dr_ste_build *sb,
423 struct mlx5dr_match_param *mask,
424 bool inner, bool rx);
425 void mlx5dr_ste_build_tnl_geneve(struct mlx5dr_ste_ctx *ste_ctx,
426 struct mlx5dr_ste_build *sb,
427 struct mlx5dr_match_param *mask,
428 bool inner, bool rx);
429 void mlx5dr_ste_build_tnl_geneve_tlv_opt(struct mlx5dr_ste_ctx *ste_ctx,
430 struct mlx5dr_ste_build *sb,
431 struct mlx5dr_match_param *mask,
432 struct mlx5dr_cmd_caps *caps,
433 bool inner, bool rx);
434 void mlx5dr_ste_build_tnl_gtpu(struct mlx5dr_ste_ctx *ste_ctx,
435 struct mlx5dr_ste_build *sb,
436 struct mlx5dr_match_param *mask,
437 bool inner, bool rx);
438 void mlx5dr_ste_build_tnl_gtpu_flex_parser_0(struct mlx5dr_ste_ctx *ste_ctx,
439 struct mlx5dr_ste_build *sb,
440 struct mlx5dr_match_param *mask,
441 struct mlx5dr_cmd_caps *caps,
442 bool inner, bool rx);
443 void mlx5dr_ste_build_tnl_gtpu_flex_parser_1(struct mlx5dr_ste_ctx *ste_ctx,
444 struct mlx5dr_ste_build *sb,
445 struct mlx5dr_match_param *mask,
446 struct mlx5dr_cmd_caps *caps,
447 bool inner, bool rx);
448 void mlx5dr_ste_build_general_purpose(struct mlx5dr_ste_ctx *ste_ctx,
449 struct mlx5dr_ste_build *sb,
450 struct mlx5dr_match_param *mask,
451 bool inner, bool rx);
452 void mlx5dr_ste_build_register_0(struct mlx5dr_ste_ctx *ste_ctx,
453 struct mlx5dr_ste_build *sb,
454 struct mlx5dr_match_param *mask,
455 bool inner, bool rx);
456 void mlx5dr_ste_build_register_1(struct mlx5dr_ste_ctx *ste_ctx,
457 struct mlx5dr_ste_build *sb,
458 struct mlx5dr_match_param *mask,
459 bool inner, bool rx);
460 void mlx5dr_ste_build_src_gvmi_qpn(struct mlx5dr_ste_ctx *ste_ctx,
461 struct mlx5dr_ste_build *sb,
462 struct mlx5dr_match_param *mask,
463 struct mlx5dr_domain *dmn,
464 bool inner, bool rx);
465 void mlx5dr_ste_build_flex_parser_0(struct mlx5dr_ste_ctx *ste_ctx,
466 struct mlx5dr_ste_build *sb,
467 struct mlx5dr_match_param *mask,
468 bool inner, bool rx);
469 void mlx5dr_ste_build_flex_parser_1(struct mlx5dr_ste_ctx *ste_ctx,
470 struct mlx5dr_ste_build *sb,
471 struct mlx5dr_match_param *mask,
472 bool inner, bool rx);
473 void mlx5dr_ste_build_empty_always_hit(struct mlx5dr_ste_build *sb, bool rx);
474
475 /* Actions utils */
476 int mlx5dr_actions_build_ste_arr(struct mlx5dr_matcher *matcher,
477 struct mlx5dr_matcher_rx_tx *nic_matcher,
478 struct mlx5dr_action *actions[],
479 u32 num_actions,
480 u8 *ste_arr,
481 u32 *new_hw_ste_arr_sz);
482
483 struct mlx5dr_match_spec {
484 u32 smac_47_16; /* Source MAC address of incoming packet */
485 /* Incoming packet Ethertype - this is the Ethertype
486 * following the last VLAN tag of the packet
487 */
488 u32 ethertype:16;
489 u32 smac_15_0:16; /* Source MAC address of incoming packet */
490 u32 dmac_47_16; /* Destination MAC address of incoming packet */
491 /* VLAN ID of first VLAN tag in the incoming packet.
492 * Valid only when cvlan_tag==1 or svlan_tag==1
493 */
494 u32 first_vid:12;
495 /* CFI bit of first VLAN tag in the incoming packet.
496 * Valid only when cvlan_tag==1 or svlan_tag==1
497 */
498 u32 first_cfi:1;
499 /* Priority of first VLAN tag in the incoming packet.
500 * Valid only when cvlan_tag==1 or svlan_tag==1
501 */
502 u32 first_prio:3;
503 u32 dmac_15_0:16; /* Destination MAC address of incoming packet */
504 /* TCP flags. ;Bit 0: FIN;Bit 1: SYN;Bit 2: RST;Bit 3: PSH;Bit 4: ACK;
505 * Bit 5: URG;Bit 6: ECE;Bit 7: CWR;Bit 8: NS
506 */
507 u32 tcp_flags:9;
508 u32 ip_version:4; /* IP version */
509 u32 frag:1; /* Packet is an IP fragment */
510 /* The first vlan in the packet is s-vlan (0x8a88).
511 * cvlan_tag and svlan_tag cannot be set together
512 */
513 u32 svlan_tag:1;
514 /* The first vlan in the packet is c-vlan (0x8100).
515 * cvlan_tag and svlan_tag cannot be set together
516 */
517 u32 cvlan_tag:1;
518 /* Explicit Congestion Notification derived from
519 * Traffic Class/TOS field of IPv6/v4
520 */
521 u32 ip_ecn:2;
522 /* Differentiated Services Code Point derived from
523 * Traffic Class/TOS field of IPv6/v4
524 */
525 u32 ip_dscp:6;
526 u32 ip_protocol:8; /* IP protocol */
527 /* TCP destination port.
528 * tcp and udp sport/dport are mutually exclusive
529 */
530 u32 tcp_dport:16;
531 /* TCP source port.;tcp and udp sport/dport are mutually exclusive */
532 u32 tcp_sport:16;
533 u32 ttl_hoplimit:8;
534 u32 reserved:24;
535 /* UDP destination port.;tcp and udp sport/dport are mutually exclusive */
536 u32 udp_dport:16;
537 /* UDP source port.;tcp and udp sport/dport are mutually exclusive */
538 u32 udp_sport:16;
539 /* IPv6 source address of incoming packets
540 * For IPv4 address use bits 31:0 (rest of the bits are reserved)
541 * This field should be qualified by an appropriate ethertype
542 */
543 u32 src_ip_127_96;
544 /* IPv6 source address of incoming packets
545 * For IPv4 address use bits 31:0 (rest of the bits are reserved)
546 * This field should be qualified by an appropriate ethertype
547 */
548 u32 src_ip_95_64;
549 /* IPv6 source address of incoming packets
550 * For IPv4 address use bits 31:0 (rest of the bits are reserved)
551 * This field should be qualified by an appropriate ethertype
552 */
553 u32 src_ip_63_32;
554 /* IPv6 source address of incoming packets
555 * For IPv4 address use bits 31:0 (rest of the bits are reserved)
556 * This field should be qualified by an appropriate ethertype
557 */
558 u32 src_ip_31_0;
559 /* IPv6 destination address of incoming packets
560 * For IPv4 address use bits 31:0 (rest of the bits are reserved)
561 * This field should be qualified by an appropriate ethertype
562 */
563 u32 dst_ip_127_96;
564 /* IPv6 destination address of incoming packets
565 * For IPv4 address use bits 31:0 (rest of the bits are reserved)
566 * This field should be qualified by an appropriate ethertype
567 */
568 u32 dst_ip_95_64;
569 /* IPv6 destination address of incoming packets
570 * For IPv4 address use bits 31:0 (rest of the bits are reserved)
571 * This field should be qualified by an appropriate ethertype
572 */
573 u32 dst_ip_63_32;
574 /* IPv6 destination address of incoming packets
575 * For IPv4 address use bits 31:0 (rest of the bits are reserved)
576 * This field should be qualified by an appropriate ethertype
577 */
578 u32 dst_ip_31_0;
579 };
580
581 struct mlx5dr_match_misc {
582 u32 source_sqn:24; /* Source SQN */
583 u32 source_vhca_port:4;
584 /* used with GRE, sequence number exist when gre_s_present == 1 */
585 u32 gre_s_present:1;
586 /* used with GRE, key exist when gre_k_present == 1 */
587 u32 gre_k_present:1;
588 u32 reserved_auto1:1;
589 /* used with GRE, checksum exist when gre_c_present == 1 */
590 u32 gre_c_present:1;
591 /* Source port.;0xffff determines wire port */
592 u32 source_port:16;
593 u32 source_eswitch_owner_vhca_id:16;
594 /* VLAN ID of first VLAN tag the inner header of the incoming packet.
595 * Valid only when inner_second_cvlan_tag ==1 or inner_second_svlan_tag ==1
596 */
597 u32 inner_second_vid:12;
598 /* CFI bit of first VLAN tag in the inner header of the incoming packet.
599 * Valid only when inner_second_cvlan_tag ==1 or inner_second_svlan_tag ==1
600 */
601 u32 inner_second_cfi:1;
602 /* Priority of second VLAN tag in the inner header of the incoming packet.
603 * Valid only when inner_second_cvlan_tag ==1 or inner_second_svlan_tag ==1
604 */
605 u32 inner_second_prio:3;
606 /* VLAN ID of first VLAN tag the outer header of the incoming packet.
607 * Valid only when outer_second_cvlan_tag ==1 or outer_second_svlan_tag ==1
608 */
609 u32 outer_second_vid:12;
610 /* CFI bit of first VLAN tag in the outer header of the incoming packet.
611 * Valid only when outer_second_cvlan_tag ==1 or outer_second_svlan_tag ==1
612 */
613 u32 outer_second_cfi:1;
614 /* Priority of second VLAN tag in the outer header of the incoming packet.
615 * Valid only when outer_second_cvlan_tag ==1 or outer_second_svlan_tag ==1
616 */
617 u32 outer_second_prio:3;
618 u32 gre_protocol:16; /* GRE Protocol (outer) */
619 u32 reserved_auto3:12;
620 /* The second vlan in the inner header of the packet is s-vlan (0x8a88).
621 * inner_second_cvlan_tag and inner_second_svlan_tag cannot be set together
622 */
623 u32 inner_second_svlan_tag:1;
624 /* The second vlan in the outer header of the packet is s-vlan (0x8a88).
625 * outer_second_cvlan_tag and outer_second_svlan_tag cannot be set together
626 */
627 u32 outer_second_svlan_tag:1;
628 /* The second vlan in the inner header of the packet is c-vlan (0x8100).
629 * inner_second_cvlan_tag and inner_second_svlan_tag cannot be set together
630 */
631 u32 inner_second_cvlan_tag:1;
632 /* The second vlan in the outer header of the packet is c-vlan (0x8100).
633 * outer_second_cvlan_tag and outer_second_svlan_tag cannot be set together
634 */
635 u32 outer_second_cvlan_tag:1;
636 u32 gre_key_l:8; /* GRE Key [7:0] (outer) */
637 u32 gre_key_h:24; /* GRE Key[31:8] (outer) */
638 u32 reserved_auto4:8;
639 u32 vxlan_vni:24; /* VXLAN VNI (outer) */
640 u32 geneve_oam:1; /* GENEVE OAM field (outer) */
641 u32 reserved_auto5:7;
642 u32 geneve_vni:24; /* GENEVE VNI field (outer) */
643 u32 outer_ipv6_flow_label:20; /* Flow label of incoming IPv6 packet (outer) */
644 u32 reserved_auto6:12;
645 u32 inner_ipv6_flow_label:20; /* Flow label of incoming IPv6 packet (inner) */
646 u32 reserved_auto7:12;
647 u32 geneve_protocol_type:16; /* GENEVE protocol type (outer) */
648 u32 geneve_opt_len:6; /* GENEVE OptLen (outer) */
649 u32 reserved_auto8:10;
650 u32 bth_dst_qp:24; /* Destination QP in BTH header */
651 u32 reserved_auto9:8;
652 u8 reserved_auto10[20];
653 };
654
655 struct mlx5dr_match_misc2 {
656 u32 outer_first_mpls_ttl:8; /* First MPLS TTL (outer) */
657 u32 outer_first_mpls_s_bos:1; /* First MPLS S_BOS (outer) */
658 u32 outer_first_mpls_exp:3; /* First MPLS EXP (outer) */
659 u32 outer_first_mpls_label:20; /* First MPLS LABEL (outer) */
660 u32 inner_first_mpls_ttl:8; /* First MPLS TTL (inner) */
661 u32 inner_first_mpls_s_bos:1; /* First MPLS S_BOS (inner) */
662 u32 inner_first_mpls_exp:3; /* First MPLS EXP (inner) */
663 u32 inner_first_mpls_label:20; /* First MPLS LABEL (inner) */
664 u32 outer_first_mpls_over_gre_ttl:8; /* last MPLS TTL (outer) */
665 u32 outer_first_mpls_over_gre_s_bos:1; /* last MPLS S_BOS (outer) */
666 u32 outer_first_mpls_over_gre_exp:3; /* last MPLS EXP (outer) */
667 u32 outer_first_mpls_over_gre_label:20; /* last MPLS LABEL (outer) */
668 u32 outer_first_mpls_over_udp_ttl:8; /* last MPLS TTL (outer) */
669 u32 outer_first_mpls_over_udp_s_bos:1; /* last MPLS S_BOS (outer) */
670 u32 outer_first_mpls_over_udp_exp:3; /* last MPLS EXP (outer) */
671 u32 outer_first_mpls_over_udp_label:20; /* last MPLS LABEL (outer) */
672 u32 metadata_reg_c_7; /* metadata_reg_c_7 */
673 u32 metadata_reg_c_6; /* metadata_reg_c_6 */
674 u32 metadata_reg_c_5; /* metadata_reg_c_5 */
675 u32 metadata_reg_c_4; /* metadata_reg_c_4 */
676 u32 metadata_reg_c_3; /* metadata_reg_c_3 */
677 u32 metadata_reg_c_2; /* metadata_reg_c_2 */
678 u32 metadata_reg_c_1; /* metadata_reg_c_1 */
679 u32 metadata_reg_c_0; /* metadata_reg_c_0 */
680 u32 metadata_reg_a; /* metadata_reg_a */
681 u8 reserved_auto2[12];
682 };
683
684 struct mlx5dr_match_misc3 {
685 u32 inner_tcp_seq_num;
686 u32 outer_tcp_seq_num;
687 u32 inner_tcp_ack_num;
688 u32 outer_tcp_ack_num;
689 u32 outer_vxlan_gpe_vni:24;
690 u32 reserved_auto1:8;
691 u32 reserved_auto2:16;
692 u32 outer_vxlan_gpe_flags:8;
693 u32 outer_vxlan_gpe_next_protocol:8;
694 u32 icmpv4_header_data;
695 u32 icmpv6_header_data;
696 u8 icmpv6_code;
697 u8 icmpv6_type;
698 u8 icmpv4_code;
699 u8 icmpv4_type;
700 u32 geneve_tlv_option_0_data;
701 u8 gtpu_msg_flags;
702 u8 gtpu_msg_type;
703 u32 gtpu_teid;
704 u32 gtpu_dw_2;
705 u32 gtpu_first_ext_dw_0;
706 u32 gtpu_dw_0;
707 };
708
709 struct mlx5dr_match_misc4 {
710 u32 prog_sample_field_value_0;
711 u32 prog_sample_field_id_0;
712 u32 prog_sample_field_value_1;
713 u32 prog_sample_field_id_1;
714 u32 prog_sample_field_value_2;
715 u32 prog_sample_field_id_2;
716 u32 prog_sample_field_value_3;
717 u32 prog_sample_field_id_3;
718 };
719
720 struct mlx5dr_match_param {
721 struct mlx5dr_match_spec outer;
722 struct mlx5dr_match_misc misc;
723 struct mlx5dr_match_spec inner;
724 struct mlx5dr_match_misc2 misc2;
725 struct mlx5dr_match_misc3 misc3;
726 struct mlx5dr_match_misc4 misc4;
727 };
728
729 #define DR_MASK_IS_ICMPV4_SET(_misc3) ((_misc3)->icmpv4_type || \
730 (_misc3)->icmpv4_code || \
731 (_misc3)->icmpv4_header_data)
732
733 struct mlx5dr_esw_caps {
734 u64 drop_icm_address_rx;
735 u64 drop_icm_address_tx;
736 u64 uplink_icm_address_rx;
737 u64 uplink_icm_address_tx;
738 u8 sw_owner:1;
739 u8 sw_owner_v2:1;
740 };
741
742 struct mlx5dr_cmd_vport_cap {
743 u16 vport_gvmi;
744 u16 vhca_gvmi;
745 u64 icm_address_rx;
746 u64 icm_address_tx;
747 u32 num;
748 };
749
750 struct mlx5dr_roce_cap {
751 u8 roce_en:1;
752 u8 fl_rc_qp_when_roce_disabled:1;
753 u8 fl_rc_qp_when_roce_enabled:1;
754 };
755
756 struct mlx5dr_cmd_caps {
757 u16 gvmi;
758 u64 nic_rx_drop_address;
759 u64 nic_tx_drop_address;
760 u64 nic_tx_allow_address;
761 u64 esw_rx_drop_address;
762 u64 esw_tx_drop_address;
763 u32 log_icm_size;
764 u64 hdr_modify_icm_addr;
765 u32 flex_protocols;
766 u8 flex_parser_id_icmp_dw0;
767 u8 flex_parser_id_icmp_dw1;
768 u8 flex_parser_id_icmpv6_dw0;
769 u8 flex_parser_id_icmpv6_dw1;
770 u8 flex_parser_id_geneve_tlv_option_0;
771 u8 flex_parser_id_mpls_over_gre;
772 u8 flex_parser_id_mpls_over_udp;
773 u8 flex_parser_id_gtpu_dw_0;
774 u8 flex_parser_id_gtpu_teid;
775 u8 flex_parser_id_gtpu_dw_2;
776 u8 flex_parser_id_gtpu_first_ext_dw_0;
777 u8 max_ft_level;
778 u16 roce_min_src_udp;
779 u8 num_esw_ports;
780 u8 sw_format_ver;
781 bool eswitch_manager;
782 bool rx_sw_owner;
783 bool tx_sw_owner;
784 bool fdb_sw_owner;
785 u8 rx_sw_owner_v2:1;
786 u8 tx_sw_owner_v2:1;
787 u8 fdb_sw_owner_v2:1;
788 u32 num_vports;
789 struct mlx5dr_esw_caps esw_caps;
790 struct mlx5dr_cmd_vport_cap *vports_caps;
791 bool prio_tag_required;
792 struct mlx5dr_roce_cap roce_caps;
793 u8 isolate_vl_tc:1;
794 };
795
796 struct mlx5dr_domain_rx_tx {
797 u64 drop_icm_addr;
798 u64 default_icm_addr;
799 enum mlx5dr_ste_entry_type ste_type;
800 struct mutex mutex; /* protect rx/tx domain */
801 };
802
803 struct mlx5dr_domain_info {
804 bool supp_sw_steering;
805 u32 max_inline_size;
806 u32 max_send_wr;
807 u32 max_log_sw_icm_sz;
808 u32 max_log_action_icm_sz;
809 struct mlx5dr_domain_rx_tx rx;
810 struct mlx5dr_domain_rx_tx tx;
811 struct mlx5dr_cmd_caps caps;
812 };
813
814 struct mlx5dr_domain_cache {
815 struct mlx5dr_fw_recalc_cs_ft **recalc_cs_ft;
816 };
817
818 struct mlx5dr_domain {
819 struct mlx5dr_domain *peer_dmn;
820 struct mlx5_core_dev *mdev;
821 u32 pdn;
822 struct mlx5_uars_page *uar;
823 enum mlx5dr_domain_type type;
824 refcount_t refcount;
825 struct mlx5dr_icm_pool *ste_icm_pool;
826 struct mlx5dr_icm_pool *action_icm_pool;
827 struct mlx5dr_send_ring *send_ring;
828 struct mlx5dr_domain_info info;
829 struct mlx5dr_domain_cache cache;
830 struct mlx5dr_ste_ctx *ste_ctx;
831 };
832
833 struct mlx5dr_table_rx_tx {
834 struct mlx5dr_ste_htbl *s_anchor;
835 struct mlx5dr_domain_rx_tx *nic_dmn;
836 u64 default_icm_addr;
837 };
838
839 struct mlx5dr_table {
840 struct mlx5dr_domain *dmn;
841 struct mlx5dr_table_rx_tx rx;
842 struct mlx5dr_table_rx_tx tx;
843 u32 level;
844 u32 table_type;
845 u32 table_id;
846 u32 flags;
847 struct list_head matcher_list;
848 struct mlx5dr_action *miss_action;
849 refcount_t refcount;
850 };
851
852 struct mlx5dr_matcher_rx_tx {
853 struct mlx5dr_ste_htbl *s_htbl;
854 struct mlx5dr_ste_htbl *e_anchor;
855 struct mlx5dr_ste_build *ste_builder;
856 struct mlx5dr_ste_build ste_builder_arr[DR_RULE_IPV_MAX]
857 [DR_RULE_IPV_MAX]
858 [DR_RULE_MAX_STES];
859 u8 num_of_builders;
860 u8 num_of_builders_arr[DR_RULE_IPV_MAX][DR_RULE_IPV_MAX];
861 u64 default_icm_addr;
862 struct mlx5dr_table_rx_tx *nic_tbl;
863 };
864
865 struct mlx5dr_matcher {
866 struct mlx5dr_table *tbl;
867 struct mlx5dr_matcher_rx_tx rx;
868 struct mlx5dr_matcher_rx_tx tx;
869 struct list_head matcher_list;
870 u32 prio;
871 struct mlx5dr_match_param mask;
872 u8 match_criteria;
873 refcount_t refcount;
874 struct mlx5dv_flow_matcher *dv_matcher;
875 };
876
877 struct mlx5dr_rule_member {
878 struct mlx5dr_ste *ste;
879 /* attached to mlx5dr_rule via this */
880 struct list_head list;
881 /* attached to mlx5dr_ste via this */
882 struct list_head use_ste_list;
883 };
884
885 struct mlx5dr_ste_action_modify_field {
886 u16 hw_field;
887 u8 start;
888 u8 end;
889 u8 l3_type;
890 u8 l4_type;
891 };
892
893 struct mlx5dr_action_rewrite {
894 struct mlx5dr_domain *dmn;
895 struct mlx5dr_icm_chunk *chunk;
896 u8 *data;
897 u16 num_of_actions;
898 u32 index;
899 u8 allow_rx:1;
900 u8 allow_tx:1;
901 u8 modify_ttl:1;
902 };
903
904 struct mlx5dr_action_reformat {
905 struct mlx5dr_domain *dmn;
906 u32 reformat_id;
907 u32 reformat_size;
908 };
909
910 struct mlx5dr_action_dest_tbl {
911 u8 is_fw_tbl:1;
912 union {
913 struct mlx5dr_table *tbl;
914 struct {
915 struct mlx5dr_domain *dmn;
916 u32 id;
917 u32 group_id;
918 enum fs_flow_table_type type;
919 u64 rx_icm_addr;
920 u64 tx_icm_addr;
921 struct mlx5dr_action **ref_actions;
922 u32 num_of_ref_actions;
923 } fw_tbl;
924 };
925 };
926
927 struct mlx5dr_action_ctr {
928 u32 ctr_id;
929 u32 offeset;
930 };
931
932 struct mlx5dr_action_vport {
933 struct mlx5dr_domain *dmn;
934 struct mlx5dr_cmd_vport_cap *caps;
935 };
936
937 struct mlx5dr_action_push_vlan {
938 u32 vlan_hdr; /* tpid_pcp_dei_vid */
939 };
940
941 struct mlx5dr_action_flow_tag {
942 u32 flow_tag;
943 };
944
945 struct mlx5dr_action {
946 enum mlx5dr_action_type action_type;
947 refcount_t refcount;
948
949 union {
950 void *data;
951 struct mlx5dr_action_rewrite *rewrite;
952 struct mlx5dr_action_reformat *reformat;
953 struct mlx5dr_action_dest_tbl *dest_tbl;
954 struct mlx5dr_action_ctr *ctr;
955 struct mlx5dr_action_vport *vport;
956 struct mlx5dr_action_push_vlan *push_vlan;
957 struct mlx5dr_action_flow_tag *flow_tag;
958 };
959 };
960
961 enum mlx5dr_connect_type {
962 CONNECT_HIT = 1,
963 CONNECT_MISS = 2,
964 };
965
966 struct mlx5dr_htbl_connect_info {
967 enum mlx5dr_connect_type type;
968 union {
969 struct mlx5dr_ste_htbl *hit_next_htbl;
970 u64 miss_icm_addr;
971 };
972 };
973
974 struct mlx5dr_rule_rx_tx {
975 struct list_head rule_members_list;
976 struct mlx5dr_matcher_rx_tx *nic_matcher;
977 };
978
979 struct mlx5dr_rule {
980 struct mlx5dr_matcher *matcher;
981 struct mlx5dr_rule_rx_tx rx;
982 struct mlx5dr_rule_rx_tx tx;
983 struct list_head rule_actions_list;
984 u32 flow_source;
985 };
986
987 void mlx5dr_rule_update_rule_member(struct mlx5dr_ste *new_ste,
988 struct mlx5dr_ste *ste);
989
990 struct mlx5dr_icm_chunk {
991 struct mlx5dr_icm_buddy_mem *buddy_mem;
992 struct list_head chunk_list;
993 u32 rkey;
994 u32 num_of_entries;
995 u32 byte_size;
996 u64 icm_addr;
997 u64 mr_addr;
998
999 /* indicates the index of this chunk in the whole memory,
1000 * used for deleting the chunk from the buddy
1001 */
1002 unsigned int seg;
1003
1004 /* Memory optimisation */
1005 struct mlx5dr_ste *ste_arr;
1006 u8 *hw_ste_arr;
1007 struct list_head *miss_list;
1008 };
1009
mlx5dr_domain_nic_lock(struct mlx5dr_domain_rx_tx * nic_dmn)1010 static inline void mlx5dr_domain_nic_lock(struct mlx5dr_domain_rx_tx *nic_dmn)
1011 {
1012 mutex_lock(&nic_dmn->mutex);
1013 }
1014
mlx5dr_domain_nic_unlock(struct mlx5dr_domain_rx_tx * nic_dmn)1015 static inline void mlx5dr_domain_nic_unlock(struct mlx5dr_domain_rx_tx *nic_dmn)
1016 {
1017 mutex_unlock(&nic_dmn->mutex);
1018 }
1019
mlx5dr_domain_lock(struct mlx5dr_domain * dmn)1020 static inline void mlx5dr_domain_lock(struct mlx5dr_domain *dmn)
1021 {
1022 mlx5dr_domain_nic_lock(&dmn->info.rx);
1023 mlx5dr_domain_nic_lock(&dmn->info.tx);
1024 }
1025
mlx5dr_domain_unlock(struct mlx5dr_domain * dmn)1026 static inline void mlx5dr_domain_unlock(struct mlx5dr_domain *dmn)
1027 {
1028 mlx5dr_domain_nic_unlock(&dmn->info.tx);
1029 mlx5dr_domain_nic_unlock(&dmn->info.rx);
1030 }
1031
1032 int mlx5dr_matcher_select_builders(struct mlx5dr_matcher *matcher,
1033 struct mlx5dr_matcher_rx_tx *nic_matcher,
1034 enum mlx5dr_ipv outer_ipv,
1035 enum mlx5dr_ipv inner_ipv);
1036
1037 static inline int
mlx5dr_icm_pool_dm_type_to_entry_size(enum mlx5dr_icm_type icm_type)1038 mlx5dr_icm_pool_dm_type_to_entry_size(enum mlx5dr_icm_type icm_type)
1039 {
1040 if (icm_type == DR_ICM_TYPE_STE)
1041 return DR_STE_SIZE;
1042
1043 return DR_MODIFY_ACTION_SIZE;
1044 }
1045
1046 static inline u32
mlx5dr_icm_pool_chunk_size_to_entries(enum mlx5dr_icm_chunk_size chunk_size)1047 mlx5dr_icm_pool_chunk_size_to_entries(enum mlx5dr_icm_chunk_size chunk_size)
1048 {
1049 return 1 << chunk_size;
1050 }
1051
1052 static inline int
mlx5dr_icm_pool_chunk_size_to_byte(enum mlx5dr_icm_chunk_size chunk_size,enum mlx5dr_icm_type icm_type)1053 mlx5dr_icm_pool_chunk_size_to_byte(enum mlx5dr_icm_chunk_size chunk_size,
1054 enum mlx5dr_icm_type icm_type)
1055 {
1056 int num_of_entries;
1057 int entry_size;
1058
1059 entry_size = mlx5dr_icm_pool_dm_type_to_entry_size(icm_type);
1060 num_of_entries = mlx5dr_icm_pool_chunk_size_to_entries(chunk_size);
1061
1062 return entry_size * num_of_entries;
1063 }
1064
1065 static inline struct mlx5dr_cmd_vport_cap *
mlx5dr_get_vport_cap(struct mlx5dr_cmd_caps * caps,u32 vport)1066 mlx5dr_get_vport_cap(struct mlx5dr_cmd_caps *caps, u32 vport)
1067 {
1068 if (!caps->vports_caps ||
1069 (vport >= caps->num_vports && vport != WIRE_PORT))
1070 return NULL;
1071
1072 if (vport == WIRE_PORT)
1073 vport = caps->num_vports;
1074
1075 return &caps->vports_caps[vport];
1076 }
1077
1078 struct mlx5dr_cmd_query_flow_table_details {
1079 u8 status;
1080 u8 level;
1081 u64 sw_owner_icm_root_1;
1082 u64 sw_owner_icm_root_0;
1083 };
1084
1085 struct mlx5dr_cmd_create_flow_table_attr {
1086 u32 table_type;
1087 u64 icm_addr_rx;
1088 u64 icm_addr_tx;
1089 u8 level;
1090 bool sw_owner;
1091 bool term_tbl;
1092 bool decap_en;
1093 bool reformat_en;
1094 };
1095
1096 /* internal API functions */
1097 int mlx5dr_cmd_query_device(struct mlx5_core_dev *mdev,
1098 struct mlx5dr_cmd_caps *caps);
1099 int mlx5dr_cmd_query_esw_vport_context(struct mlx5_core_dev *mdev,
1100 bool other_vport, u16 vport_number,
1101 u64 *icm_address_rx,
1102 u64 *icm_address_tx);
1103 int mlx5dr_cmd_query_gvmi(struct mlx5_core_dev *mdev,
1104 bool other_vport, u16 vport_number, u16 *gvmi);
1105 int mlx5dr_cmd_query_esw_caps(struct mlx5_core_dev *mdev,
1106 struct mlx5dr_esw_caps *caps);
1107 int mlx5dr_cmd_sync_steering(struct mlx5_core_dev *mdev);
1108 int mlx5dr_cmd_set_fte_modify_and_vport(struct mlx5_core_dev *mdev,
1109 u32 table_type,
1110 u32 table_id,
1111 u32 group_id,
1112 u32 modify_header_id,
1113 u32 vport_id);
1114 int mlx5dr_cmd_del_flow_table_entry(struct mlx5_core_dev *mdev,
1115 u32 table_type,
1116 u32 table_id);
1117 int mlx5dr_cmd_alloc_modify_header(struct mlx5_core_dev *mdev,
1118 u32 table_type,
1119 u8 num_of_actions,
1120 u64 *actions,
1121 u32 *modify_header_id);
1122 int mlx5dr_cmd_dealloc_modify_header(struct mlx5_core_dev *mdev,
1123 u32 modify_header_id);
1124 int mlx5dr_cmd_create_empty_flow_group(struct mlx5_core_dev *mdev,
1125 u32 table_type,
1126 u32 table_id,
1127 u32 *group_id);
1128 int mlx5dr_cmd_destroy_flow_group(struct mlx5_core_dev *mdev,
1129 u32 table_type,
1130 u32 table_id,
1131 u32 group_id);
1132 int mlx5dr_cmd_create_flow_table(struct mlx5_core_dev *mdev,
1133 struct mlx5dr_cmd_create_flow_table_attr *attr,
1134 u64 *fdb_rx_icm_addr,
1135 u32 *table_id);
1136 int mlx5dr_cmd_destroy_flow_table(struct mlx5_core_dev *mdev,
1137 u32 table_id,
1138 u32 table_type);
1139 int mlx5dr_cmd_query_flow_table(struct mlx5_core_dev *dev,
1140 enum fs_flow_table_type type,
1141 u32 table_id,
1142 struct mlx5dr_cmd_query_flow_table_details *output);
1143 int mlx5dr_cmd_create_reformat_ctx(struct mlx5_core_dev *mdev,
1144 enum mlx5_reformat_ctx_type rt,
1145 size_t reformat_size,
1146 void *reformat_data,
1147 u32 *reformat_id);
1148 void mlx5dr_cmd_destroy_reformat_ctx(struct mlx5_core_dev *mdev,
1149 u32 reformat_id);
1150
1151 struct mlx5dr_cmd_gid_attr {
1152 u8 gid[16];
1153 u8 mac[6];
1154 u32 roce_ver;
1155 };
1156
1157 struct mlx5dr_cmd_qp_create_attr {
1158 u32 page_id;
1159 u32 pdn;
1160 u32 cqn;
1161 u32 pm_state;
1162 u32 service_type;
1163 u32 buff_umem_id;
1164 u32 db_umem_id;
1165 u32 sq_wqe_cnt;
1166 u32 rq_wqe_cnt;
1167 u32 rq_wqe_shift;
1168 u8 isolate_vl_tc:1;
1169 };
1170
1171 int mlx5dr_cmd_query_gid(struct mlx5_core_dev *mdev, u8 vhca_port_num,
1172 u16 index, struct mlx5dr_cmd_gid_attr *attr);
1173
1174 struct mlx5dr_icm_pool *mlx5dr_icm_pool_create(struct mlx5dr_domain *dmn,
1175 enum mlx5dr_icm_type icm_type);
1176 void mlx5dr_icm_pool_destroy(struct mlx5dr_icm_pool *pool);
1177
1178 struct mlx5dr_icm_chunk *
1179 mlx5dr_icm_alloc_chunk(struct mlx5dr_icm_pool *pool,
1180 enum mlx5dr_icm_chunk_size chunk_size);
1181 void mlx5dr_icm_free_chunk(struct mlx5dr_icm_chunk *chunk);
1182
1183 void mlx5dr_ste_prepare_for_postsend(struct mlx5dr_ste_ctx *ste_ctx,
1184 u8 *hw_ste_p, u32 ste_size);
1185 int mlx5dr_ste_htbl_init_and_postsend(struct mlx5dr_domain *dmn,
1186 struct mlx5dr_domain_rx_tx *nic_dmn,
1187 struct mlx5dr_ste_htbl *htbl,
1188 struct mlx5dr_htbl_connect_info *connect_info,
1189 bool update_hw_ste);
1190 void mlx5dr_ste_set_formatted_ste(struct mlx5dr_ste_ctx *ste_ctx,
1191 u16 gvmi,
1192 struct mlx5dr_domain_rx_tx *nic_dmn,
1193 struct mlx5dr_ste_htbl *htbl,
1194 u8 *formatted_ste,
1195 struct mlx5dr_htbl_connect_info *connect_info);
1196 void mlx5dr_ste_copy_param(u8 match_criteria,
1197 struct mlx5dr_match_param *set_param,
1198 struct mlx5dr_match_parameters *mask);
1199
1200 struct mlx5dr_qp {
1201 struct mlx5_core_dev *mdev;
1202 struct mlx5_wq_qp wq;
1203 struct mlx5_uars_page *uar;
1204 struct mlx5_wq_ctrl wq_ctrl;
1205 u32 qpn;
1206 struct {
1207 unsigned int pc;
1208 unsigned int cc;
1209 unsigned int size;
1210 unsigned int *wqe_head;
1211 unsigned int wqe_cnt;
1212 } sq;
1213 struct {
1214 unsigned int pc;
1215 unsigned int cc;
1216 unsigned int size;
1217 unsigned int wqe_cnt;
1218 } rq;
1219 int max_inline_data;
1220 };
1221
1222 struct mlx5dr_cq {
1223 struct mlx5_core_dev *mdev;
1224 struct mlx5_cqwq wq;
1225 struct mlx5_wq_ctrl wq_ctrl;
1226 struct mlx5_core_cq mcq;
1227 struct mlx5dr_qp *qp;
1228 };
1229
1230 struct mlx5dr_mr {
1231 struct mlx5_core_dev *mdev;
1232 struct mlx5_core_mkey mkey;
1233 dma_addr_t dma_addr;
1234 void *addr;
1235 size_t size;
1236 };
1237
1238 #define MAX_SEND_CQE 64
1239 #define MIN_READ_SYNC 64
1240
1241 struct mlx5dr_send_ring {
1242 struct mlx5dr_cq *cq;
1243 struct mlx5dr_qp *qp;
1244 struct mlx5dr_mr *mr;
1245 /* How much wqes are waiting for completion */
1246 u32 pending_wqe;
1247 /* Signal request per this trash hold value */
1248 u16 signal_th;
1249 /* Each post_send_size less than max_post_send_size */
1250 u32 max_post_send_size;
1251 /* manage the send queue */
1252 u32 tx_head;
1253 void *buf;
1254 u32 buf_size;
1255 struct ib_wc wc[MAX_SEND_CQE];
1256 u8 sync_buff[MIN_READ_SYNC];
1257 struct mlx5dr_mr *sync_mr;
1258 spinlock_t lock; /* Protect the data path of the send ring */
1259 };
1260
1261 int mlx5dr_send_ring_alloc(struct mlx5dr_domain *dmn);
1262 void mlx5dr_send_ring_free(struct mlx5dr_domain *dmn,
1263 struct mlx5dr_send_ring *send_ring);
1264 int mlx5dr_send_ring_force_drain(struct mlx5dr_domain *dmn);
1265 int mlx5dr_send_postsend_ste(struct mlx5dr_domain *dmn,
1266 struct mlx5dr_ste *ste,
1267 u8 *data,
1268 u16 size,
1269 u16 offset);
1270 int mlx5dr_send_postsend_htbl(struct mlx5dr_domain *dmn,
1271 struct mlx5dr_ste_htbl *htbl,
1272 u8 *formatted_ste, u8 *mask);
1273 int mlx5dr_send_postsend_formatted_htbl(struct mlx5dr_domain *dmn,
1274 struct mlx5dr_ste_htbl *htbl,
1275 u8 *ste_init_data,
1276 bool update_hw_ste);
1277 int mlx5dr_send_postsend_action(struct mlx5dr_domain *dmn,
1278 struct mlx5dr_action *action);
1279
1280 struct mlx5dr_cmd_ft_info {
1281 u32 id;
1282 u16 vport;
1283 enum fs_flow_table_type type;
1284 };
1285
1286 struct mlx5dr_cmd_flow_destination_hw_info {
1287 enum mlx5_flow_destination_type type;
1288 union {
1289 u32 tir_num;
1290 u32 ft_num;
1291 u32 ft_id;
1292 u32 counter_id;
1293 struct {
1294 u16 num;
1295 u16 vhca_id;
1296 u32 reformat_id;
1297 u8 flags;
1298 } vport;
1299 };
1300 };
1301
1302 struct mlx5dr_cmd_fte_info {
1303 u32 dests_size;
1304 u32 index;
1305 struct mlx5_flow_context flow_context;
1306 u32 *val;
1307 struct mlx5_flow_act action;
1308 struct mlx5dr_cmd_flow_destination_hw_info *dest_arr;
1309 };
1310
1311 int mlx5dr_cmd_set_fte(struct mlx5_core_dev *dev,
1312 int opmod, int modify_mask,
1313 struct mlx5dr_cmd_ft_info *ft,
1314 u32 group_id,
1315 struct mlx5dr_cmd_fte_info *fte);
1316
1317 bool mlx5dr_ste_supp_ttl_cs_recalc(struct mlx5dr_cmd_caps *caps);
1318
1319 struct mlx5dr_fw_recalc_cs_ft {
1320 u64 rx_icm_addr;
1321 u32 table_id;
1322 u32 group_id;
1323 u32 modify_hdr_id;
1324 };
1325
1326 struct mlx5dr_fw_recalc_cs_ft *
1327 mlx5dr_fw_create_recalc_cs_ft(struct mlx5dr_domain *dmn, u32 vport_num);
1328 void mlx5dr_fw_destroy_recalc_cs_ft(struct mlx5dr_domain *dmn,
1329 struct mlx5dr_fw_recalc_cs_ft *recalc_cs_ft);
1330 int mlx5dr_domain_cache_get_recalc_cs_ft_addr(struct mlx5dr_domain *dmn,
1331 u32 vport_num,
1332 u64 *rx_icm_addr);
1333 int mlx5dr_fw_create_md_tbl(struct mlx5dr_domain *dmn,
1334 struct mlx5dr_cmd_flow_destination_hw_info *dest,
1335 int num_dest,
1336 bool reformat_req,
1337 u32 *tbl_id,
1338 u32 *group_id);
1339 void mlx5dr_fw_destroy_md_tbl(struct mlx5dr_domain *dmn, u32 tbl_id,
1340 u32 group_id);
1341 #endif /* _DR_TYPES_H_ */
1342