1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* idt8a340_reg.h 3 * 4 * Originally generated by regen.tcl on Thu Feb 14 19:23:44 PST 2019 5 * https://github.com/richardcochran/regen 6 * 7 * Hand modified to include some HW registers. 8 * Based on 4.8.0, SCSR rev C commit a03c7ae5 9 */ 10 #ifndef HAVE_IDT8A340_REG 11 #define HAVE_IDT8A340_REG 12 13 #define PAGE_ADDR_BASE 0x0000 14 #define PAGE_ADDR 0x00fc 15 16 #define HW_REVISION 0x8180 17 #define REV_ID 0x007a 18 19 #define HW_DPLL_0 (0x8a00) 20 #define HW_DPLL_1 (0x8b00) 21 #define HW_DPLL_2 (0x8c00) 22 #define HW_DPLL_3 (0x8d00) 23 #define HW_DPLL_4 (0x8e00) 24 #define HW_DPLL_5 (0x8f00) 25 #define HW_DPLL_6 (0x9000) 26 #define HW_DPLL_7 (0x9100) 27 28 #define HW_DPLL_TOD_SW_TRIG_ADDR__0 (0x080) 29 #define HW_DPLL_TOD_CTRL_1 (0x089) 30 #define HW_DPLL_TOD_CTRL_2 (0x08A) 31 #define HW_DPLL_TOD_OVR__0 (0x098) 32 #define HW_DPLL_TOD_OUT_0__0 (0x0B0) 33 34 #define HW_Q0_Q1_CH_SYNC_CTRL_0 (0xa740) 35 #define HW_Q0_Q1_CH_SYNC_CTRL_1 (0xa741) 36 #define HW_Q2_Q3_CH_SYNC_CTRL_0 (0xa742) 37 #define HW_Q2_Q3_CH_SYNC_CTRL_1 (0xa743) 38 #define HW_Q4_Q5_CH_SYNC_CTRL_0 (0xa744) 39 #define HW_Q4_Q5_CH_SYNC_CTRL_1 (0xa745) 40 #define HW_Q6_Q7_CH_SYNC_CTRL_0 (0xa746) 41 #define HW_Q6_Q7_CH_SYNC_CTRL_1 (0xa747) 42 #define HW_Q8_CH_SYNC_CTRL_0 (0xa748) 43 #define HW_Q8_CH_SYNC_CTRL_1 (0xa749) 44 #define HW_Q9_CH_SYNC_CTRL_0 (0xa74a) 45 #define HW_Q9_CH_SYNC_CTRL_1 (0xa74b) 46 #define HW_Q10_CH_SYNC_CTRL_0 (0xa74c) 47 #define HW_Q10_CH_SYNC_CTRL_1 (0xa74d) 48 #define HW_Q11_CH_SYNC_CTRL_0 (0xa74e) 49 #define HW_Q11_CH_SYNC_CTRL_1 (0xa74f) 50 51 #define SYNC_SOURCE_DPLL0_TOD_PPS 0x14 52 #define SYNC_SOURCE_DPLL1_TOD_PPS 0x15 53 #define SYNC_SOURCE_DPLL2_TOD_PPS 0x16 54 #define SYNC_SOURCE_DPLL3_TOD_PPS 0x17 55 56 #define SYNCTRL1_MASTER_SYNC_RST BIT(7) 57 #define SYNCTRL1_MASTER_SYNC_TRIG BIT(5) 58 #define SYNCTRL1_TOD_SYNC_TRIG BIT(4) 59 #define SYNCTRL1_FBDIV_FRAME_SYNC_TRIG BIT(3) 60 #define SYNCTRL1_FBDIV_SYNC_TRIG BIT(2) 61 #define SYNCTRL1_Q1_DIV_SYNC_TRIG BIT(1) 62 #define SYNCTRL1_Q0_DIV_SYNC_TRIG BIT(0) 63 64 #define HW_Q8_CTRL_SPARE (0xa7d4) 65 #define HW_Q11_CTRL_SPARE (0xa7ec) 66 67 /** 68 * Select FOD5 as sync_trigger for Q8 divider. 69 * Transition from logic zero to one 70 * sets trigger to sync Q8 divider. 71 * 72 * Unused when FOD4 is driving Q8 divider (normal operation). 73 */ 74 #define Q9_TO_Q8_SYNC_TRIG BIT(1) 75 76 /** 77 * Enable FOD5 as driver for clock and sync for Q8 divider. 78 * Enable fanout buffer for FOD5. 79 * 80 * Unused when FOD4 is driving Q8 divider (normal operation). 81 */ 82 #define Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK (BIT(0) | BIT(2)) 83 84 /** 85 * Select FOD6 as sync_trigger for Q11 divider. 86 * Transition from logic zero to one 87 * sets trigger to sync Q11 divider. 88 * 89 * Unused when FOD7 is driving Q11 divider (normal operation). 90 */ 91 #define Q10_TO_Q11_SYNC_TRIG BIT(1) 92 93 /** 94 * Enable FOD6 as driver for clock and sync for Q11 divider. 95 * Enable fanout buffer for FOD6. 96 * 97 * Unused when FOD7 is driving Q11 divider (normal operation). 98 */ 99 #define Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK (BIT(0) | BIT(2)) 100 101 #define RESET_CTRL 0xc000 102 #define SM_RESET 0x0012 103 #define SM_RESET_CMD 0x5A 104 105 #define GENERAL_STATUS 0xc014 106 #define BOOT_STATUS 0x0000 107 #define HW_REV_ID 0x000A 108 #define BOND_ID 0x000B 109 #define HW_CSR_ID 0x000C 110 #define HW_IRQ_ID 0x000E 111 112 #define MAJ_REL 0x0010 113 #define MIN_REL 0x0011 114 #define HOTFIX_REL 0x0012 115 116 #define PIPELINE_ID 0x0014 117 #define BUILD_ID 0x0018 118 119 #define JTAG_DEVICE_ID 0x001c 120 #define PRODUCT_ID 0x001e 121 122 #define OTP_SCSR_CONFIG_SELECT 0x0022 123 124 #define STATUS 0xc03c 125 #define DPLL_SYS_STATUS 0x0020 126 #define DPLL_SYS_APLL_STATUS 0x0021 127 #define USER_GPIO0_TO_7_STATUS 0x008a 128 #define USER_GPIO8_TO_15_STATUS 0x008b 129 130 #define GPIO_USER_CONTROL 0xc160 131 #define GPIO0_TO_7_OUT 0x0000 132 #define GPIO8_TO_15_OUT 0x0001 133 134 #define STICKY_STATUS_CLEAR 0xc164 135 136 #define GPIO_TOD_NOTIFICATION_CLEAR 0xc16c 137 138 #define ALERT_CFG 0xc188 139 140 #define SYS_DPLL_XO 0xc194 141 142 #define SYS_APLL 0xc19c 143 144 #define INPUT_0 0xc1b0 145 146 #define INPUT_1 0xc1c0 147 148 #define INPUT_2 0xc1d0 149 150 #define INPUT_3 0xc200 151 152 #define INPUT_4 0xc210 153 154 #define INPUT_5 0xc220 155 156 #define INPUT_6 0xc230 157 158 #define INPUT_7 0xc240 159 160 #define INPUT_8 0xc250 161 162 #define INPUT_9 0xc260 163 164 #define INPUT_10 0xc280 165 166 #define INPUT_11 0xc290 167 168 #define INPUT_12 0xc2a0 169 170 #define INPUT_13 0xc2b0 171 172 #define INPUT_14 0xc2c0 173 174 #define INPUT_15 0xc2d0 175 176 #define REF_MON_0 0xc2e0 177 178 #define REF_MON_1 0xc2ec 179 180 #define REF_MON_2 0xc300 181 182 #define REF_MON_3 0xc30c 183 184 #define REF_MON_4 0xc318 185 186 #define REF_MON_5 0xc324 187 188 #define REF_MON_6 0xc330 189 190 #define REF_MON_7 0xc33c 191 192 #define REF_MON_8 0xc348 193 194 #define REF_MON_9 0xc354 195 196 #define REF_MON_10 0xc360 197 198 #define REF_MON_11 0xc36c 199 200 #define REF_MON_12 0xc380 201 202 #define REF_MON_13 0xc38c 203 204 #define REF_MON_14 0xc398 205 206 #define REF_MON_15 0xc3a4 207 208 #define DPLL_0 0xc3b0 209 #define DPLL_CTRL_REG_0 0x0002 210 #define DPLL_CTRL_REG_1 0x0003 211 #define DPLL_CTRL_REG_2 0x0004 212 #define DPLL_TOD_SYNC_CFG 0x0031 213 #define DPLL_COMBO_SLAVE_CFG_0 0x0032 214 #define DPLL_COMBO_SLAVE_CFG_1 0x0033 215 #define DPLL_SLAVE_REF_CFG 0x0034 216 #define DPLL_REF_MODE 0x0035 217 #define DPLL_PHASE_MEASUREMENT_CFG 0x0036 218 #define DPLL_MODE 0x0037 219 220 #define DPLL_1 0xc400 221 222 #define DPLL_2 0xc438 223 224 #define DPLL_3 0xc480 225 226 #define DPLL_4 0xc4b8 227 228 #define DPLL_5 0xc500 229 230 #define DPLL_6 0xc538 231 232 #define DPLL_7 0xc580 233 234 #define SYS_DPLL 0xc5b8 235 236 #define DPLL_CTRL_0 0xc600 237 #define DPLL_CTRL_DPLL_MANU_REF_CFG 0x0001 238 #define DPLL_CTRL_COMBO_MASTER_CFG 0x003a 239 240 #define DPLL_CTRL_1 0xc63c 241 242 #define DPLL_CTRL_2 0xc680 243 244 #define DPLL_CTRL_3 0xc6bc 245 246 #define DPLL_CTRL_4 0xc700 247 248 #define DPLL_CTRL_5 0xc73c 249 250 #define DPLL_CTRL_6 0xc780 251 252 #define DPLL_CTRL_7 0xc7bc 253 254 #define SYS_DPLL_CTRL 0xc800 255 256 #define DPLL_PHASE_0 0xc818 257 258 /* Signed 42-bit FFO in units of 2^(-53) */ 259 #define DPLL_WR_PHASE 0x0000 260 261 #define DPLL_PHASE_1 0xc81c 262 263 #define DPLL_PHASE_2 0xc820 264 265 #define DPLL_PHASE_3 0xc824 266 267 #define DPLL_PHASE_4 0xc828 268 269 #define DPLL_PHASE_5 0xc82c 270 271 #define DPLL_PHASE_6 0xc830 272 273 #define DPLL_PHASE_7 0xc834 274 275 #define DPLL_FREQ_0 0xc838 276 277 /* Signed 42-bit FFO in units of 2^(-53) */ 278 #define DPLL_WR_FREQ 0x0000 279 280 #define DPLL_FREQ_1 0xc840 281 282 #define DPLL_FREQ_2 0xc848 283 284 #define DPLL_FREQ_3 0xc850 285 286 #define DPLL_FREQ_4 0xc858 287 288 #define DPLL_FREQ_5 0xc860 289 290 #define DPLL_FREQ_6 0xc868 291 292 #define DPLL_FREQ_7 0xc870 293 294 #define DPLL_PHASE_PULL_IN_0 0xc880 295 #define PULL_IN_OFFSET 0x0000 /* Signed 32 bit */ 296 #define PULL_IN_SLOPE_LIMIT 0x0004 /* Unsigned 24 bit */ 297 #define PULL_IN_CTRL 0x0007 298 299 #define DPLL_PHASE_PULL_IN_1 0xc888 300 301 #define DPLL_PHASE_PULL_IN_2 0xc890 302 303 #define DPLL_PHASE_PULL_IN_3 0xc898 304 305 #define DPLL_PHASE_PULL_IN_4 0xc8a0 306 307 #define DPLL_PHASE_PULL_IN_5 0xc8a8 308 309 #define DPLL_PHASE_PULL_IN_6 0xc8b0 310 311 #define DPLL_PHASE_PULL_IN_7 0xc8b8 312 313 #define GPIO_CFG 0xc8c0 314 #define GPIO_CFG_GBL 0x0000 315 316 #define GPIO_0 0xc8c2 317 #define GPIO_DCO_INC_DEC 0x0000 318 #define GPIO_OUT_CTRL_0 0x0001 319 #define GPIO_OUT_CTRL_1 0x0002 320 #define GPIO_TOD_TRIG 0x0003 321 #define GPIO_DPLL_INDICATOR 0x0004 322 #define GPIO_LOS_INDICATOR 0x0005 323 #define GPIO_REF_INPUT_DSQ_0 0x0006 324 #define GPIO_REF_INPUT_DSQ_1 0x0007 325 #define GPIO_REF_INPUT_DSQ_2 0x0008 326 #define GPIO_REF_INPUT_DSQ_3 0x0009 327 #define GPIO_MAN_CLK_SEL_0 0x000a 328 #define GPIO_MAN_CLK_SEL_1 0x000b 329 #define GPIO_MAN_CLK_SEL_2 0x000c 330 #define GPIO_SLAVE 0x000d 331 #define GPIO_ALERT_OUT_CFG 0x000e 332 #define GPIO_TOD_NOTIFICATION_CFG 0x000f 333 #define GPIO_CTRL 0x0010 334 335 #define GPIO_1 0xc8d4 336 337 #define GPIO_2 0xc8e6 338 339 #define GPIO_3 0xc900 340 341 #define GPIO_4 0xc912 342 343 #define GPIO_5 0xc924 344 345 #define GPIO_6 0xc936 346 347 #define GPIO_7 0xc948 348 349 #define GPIO_8 0xc95a 350 351 #define GPIO_9 0xc980 352 353 #define GPIO_10 0xc992 354 355 #define GPIO_11 0xc9a4 356 357 #define GPIO_12 0xc9b6 358 359 #define GPIO_13 0xc9c8 360 361 #define GPIO_14 0xc9da 362 363 #define GPIO_15 0xca00 364 365 #define OUT_DIV_MUX 0xca12 366 367 #define OUTPUT_0 0xca14 368 /* FOD frequency output divider value */ 369 #define OUT_DIV 0x0000 370 #define OUT_DUTY_CYCLE_HIGH 0x0004 371 #define OUT_CTRL_0 0x0008 372 #define OUT_CTRL_1 0x0009 373 /* Phase adjustment in FOD cycles */ 374 #define OUT_PHASE_ADJ 0x000c 375 376 #define OUTPUT_1 0xca24 377 378 #define OUTPUT_2 0xca34 379 380 #define OUTPUT_3 0xca44 381 382 #define OUTPUT_4 0xca54 383 384 #define OUTPUT_5 0xca64 385 386 #define OUTPUT_6 0xca80 387 388 #define OUTPUT_7 0xca90 389 390 #define OUTPUT_8 0xcaa0 391 392 #define OUTPUT_9 0xcab0 393 394 #define OUTPUT_10 0xcac0 395 396 #define OUTPUT_11 0xcad0 397 398 #define SERIAL 0xcae0 399 400 #define PWM_ENCODER_0 0xcb00 401 402 #define PWM_ENCODER_1 0xcb08 403 404 #define PWM_ENCODER_2 0xcb10 405 406 #define PWM_ENCODER_3 0xcb18 407 408 #define PWM_ENCODER_4 0xcb20 409 410 #define PWM_ENCODER_5 0xcb28 411 412 #define PWM_ENCODER_6 0xcb30 413 414 #define PWM_ENCODER_7 0xcb38 415 416 #define PWM_DECODER_0 0xcb40 417 418 #define PWM_DECODER_1 0xcb48 419 420 #define PWM_DECODER_2 0xcb50 421 422 #define PWM_DECODER_3 0xcb58 423 424 #define PWM_DECODER_4 0xcb60 425 426 #define PWM_DECODER_5 0xcb68 427 428 #define PWM_DECODER_6 0xcb70 429 430 #define PWM_DECODER_7 0xcb80 431 432 #define PWM_DECODER_8 0xcb88 433 434 #define PWM_DECODER_9 0xcb90 435 436 #define PWM_DECODER_10 0xcb98 437 438 #define PWM_DECODER_11 0xcba0 439 440 #define PWM_DECODER_12 0xcba8 441 442 #define PWM_DECODER_13 0xcbb0 443 444 #define PWM_DECODER_14 0xcbb8 445 446 #define PWM_DECODER_15 0xcbc0 447 448 #define PWM_USER_DATA 0xcbc8 449 450 #define TOD_0 0xcbcc 451 452 /* Enable TOD counter, output channel sync and even-PPS mode */ 453 #define TOD_CFG 0x0000 454 455 #define TOD_1 0xcbce 456 457 #define TOD_2 0xcbd0 458 459 #define TOD_3 0xcbd2 460 461 462 #define TOD_WRITE_0 0xcc00 463 /* 8-bit subns, 32-bit ns, 48-bit seconds */ 464 #define TOD_WRITE 0x0000 465 /* Counter increments after TOD write is completed */ 466 #define TOD_WRITE_COUNTER 0x000c 467 /* TOD write trigger configuration */ 468 #define TOD_WRITE_SELECT_CFG_0 0x000d 469 /* TOD write trigger selection */ 470 #define TOD_WRITE_CMD 0x000f 471 472 #define TOD_WRITE_1 0xcc10 473 474 #define TOD_WRITE_2 0xcc20 475 476 #define TOD_WRITE_3 0xcc30 477 478 #define TOD_READ_PRIMARY_0 0xcc40 479 /* 8-bit subns, 32-bit ns, 48-bit seconds */ 480 #define TOD_READ_PRIMARY 0x0000 481 /* Counter increments after TOD write is completed */ 482 #define TOD_READ_PRIMARY_COUNTER 0x000b 483 /* Read trigger configuration */ 484 #define TOD_READ_PRIMARY_SEL_CFG_0 0x000c 485 /* Read trigger selection */ 486 #define TOD_READ_PRIMARY_CMD 0x000e 487 488 #define TOD_READ_PRIMARY_1 0xcc50 489 490 #define TOD_READ_PRIMARY_2 0xcc60 491 492 #define TOD_READ_PRIMARY_3 0xcc80 493 494 #define TOD_READ_SECONDARY_0 0xcc90 495 496 #define TOD_READ_SECONDARY_1 0xcca0 497 498 #define TOD_READ_SECONDARY_2 0xccb0 499 500 #define TOD_READ_SECONDARY_3 0xccc0 501 502 #define OUTPUT_TDC_CFG 0xccd0 503 504 #define OUTPUT_TDC_0 0xcd00 505 506 #define OUTPUT_TDC_1 0xcd08 507 508 #define OUTPUT_TDC_2 0xcd10 509 510 #define OUTPUT_TDC_3 0xcd18 511 512 #define INPUT_TDC 0xcd20 513 514 #define SCRATCH 0xcf50 515 516 #define EEPROM 0xcf68 517 518 #define OTP 0xcf70 519 520 #define BYTE 0xcf80 521 522 /* Bit definitions for the MAJ_REL register */ 523 #define MAJOR_SHIFT (1) 524 #define MAJOR_MASK (0x7f) 525 #define PR_BUILD BIT(0) 526 527 /* Bit definitions for the USER_GPIO0_TO_7_STATUS register */ 528 #define GPIO0_LEVEL BIT(0) 529 #define GPIO1_LEVEL BIT(1) 530 #define GPIO2_LEVEL BIT(2) 531 #define GPIO3_LEVEL BIT(3) 532 #define GPIO4_LEVEL BIT(4) 533 #define GPIO5_LEVEL BIT(5) 534 #define GPIO6_LEVEL BIT(6) 535 #define GPIO7_LEVEL BIT(7) 536 537 /* Bit definitions for the USER_GPIO8_TO_15_STATUS register */ 538 #define GPIO8_LEVEL BIT(0) 539 #define GPIO9_LEVEL BIT(1) 540 #define GPIO10_LEVEL BIT(2) 541 #define GPIO11_LEVEL BIT(3) 542 #define GPIO12_LEVEL BIT(4) 543 #define GPIO13_LEVEL BIT(5) 544 #define GPIO14_LEVEL BIT(6) 545 #define GPIO15_LEVEL BIT(7) 546 547 /* Bit definitions for the GPIO0_TO_7_OUT register */ 548 #define GPIO0_DRIVE_LEVEL BIT(0) 549 #define GPIO1_DRIVE_LEVEL BIT(1) 550 #define GPIO2_DRIVE_LEVEL BIT(2) 551 #define GPIO3_DRIVE_LEVEL BIT(3) 552 #define GPIO4_DRIVE_LEVEL BIT(4) 553 #define GPIO5_DRIVE_LEVEL BIT(5) 554 #define GPIO6_DRIVE_LEVEL BIT(6) 555 #define GPIO7_DRIVE_LEVEL BIT(7) 556 557 /* Bit definitions for the GPIO8_TO_15_OUT register */ 558 #define GPIO8_DRIVE_LEVEL BIT(0) 559 #define GPIO9_DRIVE_LEVEL BIT(1) 560 #define GPIO10_DRIVE_LEVEL BIT(2) 561 #define GPIO11_DRIVE_LEVEL BIT(3) 562 #define GPIO12_DRIVE_LEVEL BIT(4) 563 #define GPIO13_DRIVE_LEVEL BIT(5) 564 #define GPIO14_DRIVE_LEVEL BIT(6) 565 #define GPIO15_DRIVE_LEVEL BIT(7) 566 567 /* Bit definitions for the DPLL_TOD_SYNC_CFG register */ 568 #define TOD_SYNC_SOURCE_SHIFT (1) 569 #define TOD_SYNC_SOURCE_MASK (0x3) 570 #define TOD_SYNC_EN BIT(0) 571 572 /* Bit definitions for the DPLL_MODE register */ 573 #define WRITE_TIMER_MODE BIT(6) 574 #define PLL_MODE_SHIFT (3) 575 #define PLL_MODE_MASK (0x7) 576 #define STATE_MODE_SHIFT (0) 577 #define STATE_MODE_MASK (0x7) 578 579 /* Bit definitions for the GPIO_CFG_GBL register */ 580 #define SUPPLY_MODE_SHIFT (0) 581 #define SUPPLY_MODE_MASK (0x3) 582 583 /* Bit definitions for the GPIO_DCO_INC_DEC register */ 584 #define INCDEC_DPLL_INDEX_SHIFT (0) 585 #define INCDEC_DPLL_INDEX_MASK (0x7) 586 587 /* Bit definitions for the GPIO_OUT_CTRL_0 register */ 588 #define CTRL_OUT_0 BIT(0) 589 #define CTRL_OUT_1 BIT(1) 590 #define CTRL_OUT_2 BIT(2) 591 #define CTRL_OUT_3 BIT(3) 592 #define CTRL_OUT_4 BIT(4) 593 #define CTRL_OUT_5 BIT(5) 594 #define CTRL_OUT_6 BIT(6) 595 #define CTRL_OUT_7 BIT(7) 596 597 /* Bit definitions for the GPIO_OUT_CTRL_1 register */ 598 #define CTRL_OUT_8 BIT(0) 599 #define CTRL_OUT_9 BIT(1) 600 #define CTRL_OUT_10 BIT(2) 601 #define CTRL_OUT_11 BIT(3) 602 #define CTRL_OUT_12 BIT(4) 603 #define CTRL_OUT_13 BIT(5) 604 #define CTRL_OUT_14 BIT(6) 605 #define CTRL_OUT_15 BIT(7) 606 607 /* Bit definitions for the GPIO_TOD_TRIG register */ 608 #define TOD_TRIG_0 BIT(0) 609 #define TOD_TRIG_1 BIT(1) 610 #define TOD_TRIG_2 BIT(2) 611 #define TOD_TRIG_3 BIT(3) 612 613 /* Bit definitions for the GPIO_DPLL_INDICATOR register */ 614 #define IND_DPLL_INDEX_SHIFT (0) 615 #define IND_DPLL_INDEX_MASK (0x7) 616 617 /* Bit definitions for the GPIO_LOS_INDICATOR register */ 618 #define REFMON_INDEX_SHIFT (0) 619 #define REFMON_INDEX_MASK (0xf) 620 /* Active level of LOS indicator, 0=low 1=high */ 621 #define ACTIVE_LEVEL BIT(4) 622 623 /* Bit definitions for the GPIO_REF_INPUT_DSQ_0 register */ 624 #define DSQ_INP_0 BIT(0) 625 #define DSQ_INP_1 BIT(1) 626 #define DSQ_INP_2 BIT(2) 627 #define DSQ_INP_3 BIT(3) 628 #define DSQ_INP_4 BIT(4) 629 #define DSQ_INP_5 BIT(5) 630 #define DSQ_INP_6 BIT(6) 631 #define DSQ_INP_7 BIT(7) 632 633 /* Bit definitions for the GPIO_REF_INPUT_DSQ_1 register */ 634 #define DSQ_INP_8 BIT(0) 635 #define DSQ_INP_9 BIT(1) 636 #define DSQ_INP_10 BIT(2) 637 #define DSQ_INP_11 BIT(3) 638 #define DSQ_INP_12 BIT(4) 639 #define DSQ_INP_13 BIT(5) 640 #define DSQ_INP_14 BIT(6) 641 #define DSQ_INP_15 BIT(7) 642 643 /* Bit definitions for the GPIO_REF_INPUT_DSQ_2 register */ 644 #define DSQ_DPLL_0 BIT(0) 645 #define DSQ_DPLL_1 BIT(1) 646 #define DSQ_DPLL_2 BIT(2) 647 #define DSQ_DPLL_3 BIT(3) 648 #define DSQ_DPLL_4 BIT(4) 649 #define DSQ_DPLL_5 BIT(5) 650 #define DSQ_DPLL_6 BIT(6) 651 #define DSQ_DPLL_7 BIT(7) 652 653 /* Bit definitions for the GPIO_REF_INPUT_DSQ_3 register */ 654 #define DSQ_DPLL_SYS BIT(0) 655 #define GPIO_DSQ_LEVEL BIT(1) 656 657 /* Bit definitions for the GPIO_TOD_NOTIFICATION_CFG register */ 658 #define DPLL_TOD_SHIFT (0) 659 #define DPLL_TOD_MASK (0x3) 660 #define TOD_READ_SECONDARY BIT(2) 661 #define GPIO_ASSERT_LEVEL BIT(3) 662 663 /* Bit definitions for the GPIO_CTRL register */ 664 #define GPIO_FUNCTION_EN BIT(0) 665 #define GPIO_CMOS_OD_MODE BIT(1) 666 #define GPIO_CONTROL_DIR BIT(2) 667 #define GPIO_PU_PD_MODE BIT(3) 668 #define GPIO_FUNCTION_SHIFT (4) 669 #define GPIO_FUNCTION_MASK (0xf) 670 671 /* Bit definitions for the OUT_CTRL_1 register */ 672 #define OUT_SYNC_DISABLE BIT(7) 673 #define SQUELCH_VALUE BIT(6) 674 #define SQUELCH_DISABLE BIT(5) 675 #define PAD_VDDO_SHIFT (2) 676 #define PAD_VDDO_MASK (0x7) 677 #define PAD_CMOSDRV_SHIFT (0) 678 #define PAD_CMOSDRV_MASK (0x3) 679 680 /* Bit definitions for the TOD_CFG register */ 681 #define TOD_EVEN_PPS_MODE BIT(2) 682 #define TOD_OUT_SYNC_ENABLE BIT(1) 683 #define TOD_ENABLE BIT(0) 684 685 /* Bit definitions for the TOD_WRITE_SELECT_CFG_0 register */ 686 #define WR_PWM_DECODER_INDEX_SHIFT (4) 687 #define WR_PWM_DECODER_INDEX_MASK (0xf) 688 #define WR_REF_INDEX_SHIFT (0) 689 #define WR_REF_INDEX_MASK (0xf) 690 691 /* Bit definitions for the TOD_WRITE_CMD register */ 692 #define TOD_WRITE_SELECTION_SHIFT (0) 693 #define TOD_WRITE_SELECTION_MASK (0xf) 694 /* 4.8.7 */ 695 #define TOD_WRITE_TYPE_SHIFT (4) 696 #define TOD_WRITE_TYPE_MASK (0x3) 697 698 /* Bit definitions for the TOD_READ_PRIMARY_SEL_CFG_0 register */ 699 #define RD_PWM_DECODER_INDEX_SHIFT (4) 700 #define RD_PWM_DECODER_INDEX_MASK (0xf) 701 #define RD_REF_INDEX_SHIFT (0) 702 #define RD_REF_INDEX_MASK (0xf) 703 704 /* Bit definitions for the TOD_READ_PRIMARY_CMD register */ 705 #define TOD_READ_TRIGGER_MODE BIT(4) 706 #define TOD_READ_TRIGGER_SHIFT (0) 707 #define TOD_READ_TRIGGER_MASK (0xf) 708 709 /* Bit definitions for the DPLL_CTRL_COMBO_MASTER_CFG register */ 710 #define COMBO_MASTER_HOLD BIT(0) 711 712 /* Bit definitions for DPLL_SYS_STATUS register */ 713 #define DPLL_SYS_STATE_MASK (0xf) 714 715 /* Bit definitions for SYS_APLL_STATUS register */ 716 #define SYS_APLL_LOSS_LOCK_LIVE_MASK BIT(0) 717 #define SYS_APLL_LOSS_LOCK_LIVE_LOCKED 0 718 #define SYS_APLL_LOSS_LOCK_LIVE_UNLOCKED 1 719 720 #endif 721