1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * UFS Host Controller driver for Exynos specific extensions
4 *
5 * Copyright (C) 2014-2015 Samsung Electronics Co., Ltd.
6 * Author: Seungwon Jeon <essuuj@gmail.com>
7 * Author: Alim Akhtar <alim.akhtar@samsung.com>
8 *
9 */
10
11 #include <linux/clk.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/of_address.h>
15 #include <linux/phy/phy.h>
16 #include <linux/platform_device.h>
17
18 #include "ufshcd.h"
19 #include "ufshcd-pltfrm.h"
20 #include "ufshci.h"
21 #include "unipro.h"
22
23 #include "ufs-exynos.h"
24
25 /*
26 * Exynos's Vendor specific registers for UFSHCI
27 */
28 #define HCI_TXPRDT_ENTRY_SIZE 0x00
29 #define PRDT_PREFECT_EN BIT(31)
30 #define PRDT_SET_SIZE(x) ((x) & 0x1F)
31 #define HCI_RXPRDT_ENTRY_SIZE 0x04
32 #define HCI_1US_TO_CNT_VAL 0x0C
33 #define CNT_VAL_1US_MASK 0x3FF
34 #define HCI_UTRL_NEXUS_TYPE 0x40
35 #define HCI_UTMRL_NEXUS_TYPE 0x44
36 #define HCI_SW_RST 0x50
37 #define UFS_LINK_SW_RST BIT(0)
38 #define UFS_UNIPRO_SW_RST BIT(1)
39 #define UFS_SW_RST_MASK (UFS_UNIPRO_SW_RST | UFS_LINK_SW_RST)
40 #define HCI_DATA_REORDER 0x60
41 #define HCI_UNIPRO_APB_CLK_CTRL 0x68
42 #define UNIPRO_APB_CLK(v, x) (((v) & ~0xF) | ((x) & 0xF))
43 #define HCI_AXIDMA_RWDATA_BURST_LEN 0x6C
44 #define HCI_GPIO_OUT 0x70
45 #define HCI_ERR_EN_PA_LAYER 0x78
46 #define HCI_ERR_EN_DL_LAYER 0x7C
47 #define HCI_ERR_EN_N_LAYER 0x80
48 #define HCI_ERR_EN_T_LAYER 0x84
49 #define HCI_ERR_EN_DME_LAYER 0x88
50 #define HCI_CLKSTOP_CTRL 0xB0
51 #define REFCLK_STOP BIT(2)
52 #define UNIPRO_MCLK_STOP BIT(1)
53 #define UNIPRO_PCLK_STOP BIT(0)
54 #define CLK_STOP_MASK (REFCLK_STOP |\
55 UNIPRO_MCLK_STOP |\
56 UNIPRO_PCLK_STOP)
57 #define HCI_MISC 0xB4
58 #define REFCLK_CTRL_EN BIT(7)
59 #define UNIPRO_PCLK_CTRL_EN BIT(6)
60 #define UNIPRO_MCLK_CTRL_EN BIT(5)
61 #define HCI_CORECLK_CTRL_EN BIT(4)
62 #define CLK_CTRL_EN_MASK (REFCLK_CTRL_EN |\
63 UNIPRO_PCLK_CTRL_EN |\
64 UNIPRO_MCLK_CTRL_EN)
65 /* Device fatal error */
66 #define DFES_ERR_EN BIT(31)
67 #define DFES_DEF_L2_ERRS (UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF |\
68 UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
69 #define DFES_DEF_L3_ERRS (UIC_NETWORK_UNSUPPORTED_HEADER_TYPE |\
70 UIC_NETWORK_BAD_DEVICEID_ENC |\
71 UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING)
72 #define DFES_DEF_L4_ERRS (UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE |\
73 UIC_TRANSPORT_UNKNOWN_CPORTID |\
74 UIC_TRANSPORT_NO_CONNECTION_RX |\
75 UIC_TRANSPORT_BAD_TC)
76
77 enum {
78 UNIPRO_L1_5 = 0,/* PHY Adapter */
79 UNIPRO_L2, /* Data Link */
80 UNIPRO_L3, /* Network */
81 UNIPRO_L4, /* Transport */
82 UNIPRO_DME, /* DME */
83 };
84
85 /*
86 * UNIPRO registers
87 */
88 #define UNIPRO_COMP_VERSION 0x000
89 #define UNIPRO_DME_PWR_REQ 0x090
90 #define UNIPRO_DME_PWR_REQ_POWERMODE 0x094
91 #define UNIPRO_DME_PWR_REQ_LOCALL2TIMER0 0x098
92 #define UNIPRO_DME_PWR_REQ_LOCALL2TIMER1 0x09C
93 #define UNIPRO_DME_PWR_REQ_LOCALL2TIMER2 0x0A0
94 #define UNIPRO_DME_PWR_REQ_REMOTEL2TIMER0 0x0A4
95 #define UNIPRO_DME_PWR_REQ_REMOTEL2TIMER1 0x0A8
96 #define UNIPRO_DME_PWR_REQ_REMOTEL2TIMER2 0x0AC
97
98 /*
99 * UFS Protector registers
100 */
101 #define UFSPRSECURITY 0x010
102 #define NSSMU BIT(14)
103 #define UFSPSBEGIN0 0x200
104 #define UFSPSEND0 0x204
105 #define UFSPSLUN0 0x208
106 #define UFSPSCTRL0 0x20C
107
108 #define CNTR_DIV_VAL 40
109
110 static void exynos_ufs_auto_ctrl_hcc(struct exynos_ufs *ufs, bool en);
111 static void exynos_ufs_ctrl_clkstop(struct exynos_ufs *ufs, bool en);
112
exynos_ufs_enable_auto_ctrl_hcc(struct exynos_ufs * ufs)113 static inline void exynos_ufs_enable_auto_ctrl_hcc(struct exynos_ufs *ufs)
114 {
115 exynos_ufs_auto_ctrl_hcc(ufs, true);
116 }
117
exynos_ufs_disable_auto_ctrl_hcc(struct exynos_ufs * ufs)118 static inline void exynos_ufs_disable_auto_ctrl_hcc(struct exynos_ufs *ufs)
119 {
120 exynos_ufs_auto_ctrl_hcc(ufs, false);
121 }
122
exynos_ufs_disable_auto_ctrl_hcc_save(struct exynos_ufs * ufs,u32 * val)123 static inline void exynos_ufs_disable_auto_ctrl_hcc_save(
124 struct exynos_ufs *ufs, u32 *val)
125 {
126 *val = hci_readl(ufs, HCI_MISC);
127 exynos_ufs_auto_ctrl_hcc(ufs, false);
128 }
129
exynos_ufs_auto_ctrl_hcc_restore(struct exynos_ufs * ufs,u32 * val)130 static inline void exynos_ufs_auto_ctrl_hcc_restore(
131 struct exynos_ufs *ufs, u32 *val)
132 {
133 hci_writel(ufs, *val, HCI_MISC);
134 }
135
exynos_ufs_gate_clks(struct exynos_ufs * ufs)136 static inline void exynos_ufs_gate_clks(struct exynos_ufs *ufs)
137 {
138 exynos_ufs_ctrl_clkstop(ufs, true);
139 }
140
exynos_ufs_ungate_clks(struct exynos_ufs * ufs)141 static inline void exynos_ufs_ungate_clks(struct exynos_ufs *ufs)
142 {
143 exynos_ufs_ctrl_clkstop(ufs, false);
144 }
145
exynos7_ufs_drv_init(struct device * dev,struct exynos_ufs * ufs)146 static int exynos7_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs)
147 {
148 return 0;
149 }
150
exynos7_ufs_pre_link(struct exynos_ufs * ufs)151 static int exynos7_ufs_pre_link(struct exynos_ufs *ufs)
152 {
153 struct ufs_hba *hba = ufs->hba;
154 u32 val = ufs->drv_data->uic_attr->pa_dbg_option_suite;
155 int i;
156
157 exynos_ufs_enable_ov_tm(hba);
158 for_each_ufs_tx_lane(ufs, i)
159 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x297, i), 0x17);
160 for_each_ufs_rx_lane(ufs, i) {
161 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x362, i), 0xff);
162 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x363, i), 0x00);
163 }
164 exynos_ufs_disable_ov_tm(hba);
165
166 for_each_ufs_tx_lane(ufs, i)
167 ufshcd_dme_set(hba,
168 UIC_ARG_MIB_SEL(TX_HIBERN8_CONTROL, i), 0x0);
169 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_TXPHY_CFGUPDT), 0x1);
170 udelay(1);
171 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), val | (1 << 12));
172 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_RESET_PHY), 0x1);
173 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_LINE_RESET), 0x1);
174 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_LINE_RESET_REQ), 0x1);
175 udelay(1600);
176 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), val);
177
178 return 0;
179 }
180
exynos7_ufs_post_link(struct exynos_ufs * ufs)181 static int exynos7_ufs_post_link(struct exynos_ufs *ufs)
182 {
183 struct ufs_hba *hba = ufs->hba;
184 int i;
185
186 exynos_ufs_enable_ov_tm(hba);
187 for_each_ufs_tx_lane(ufs, i) {
188 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x28b, i), 0x83);
189 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x29a, i), 0x07);
190 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x277, i),
191 TX_LINERESET_N(exynos_ufs_calc_time_cntr(ufs, 200000)));
192 }
193 exynos_ufs_disable_ov_tm(hba);
194
195 exynos_ufs_enable_dbg_mode(hba);
196 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_SAVECONFIGTIME), 0xbb8);
197 exynos_ufs_disable_dbg_mode(hba);
198
199 return 0;
200 }
201
exynos7_ufs_pre_pwr_change(struct exynos_ufs * ufs,struct ufs_pa_layer_attr * pwr)202 static int exynos7_ufs_pre_pwr_change(struct exynos_ufs *ufs,
203 struct ufs_pa_layer_attr *pwr)
204 {
205 unipro_writel(ufs, 0x22, UNIPRO_DBG_FORCE_DME_CTRL_STATE);
206
207 return 0;
208 }
209
exynos7_ufs_post_pwr_change(struct exynos_ufs * ufs,struct ufs_pa_layer_attr * pwr)210 static int exynos7_ufs_post_pwr_change(struct exynos_ufs *ufs,
211 struct ufs_pa_layer_attr *pwr)
212 {
213 struct ufs_hba *hba = ufs->hba;
214 int lanes = max_t(u32, pwr->lane_rx, pwr->lane_tx);
215
216 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_RXPHY_CFGUPDT), 0x1);
217
218 if (lanes == 1) {
219 exynos_ufs_enable_dbg_mode(hba);
220 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 0x1);
221 exynos_ufs_disable_dbg_mode(hba);
222 }
223
224 return 0;
225 }
226
227 /*
228 * exynos_ufs_auto_ctrl_hcc - HCI core clock control by h/w
229 * Control should be disabled in the below cases
230 * - Before host controller S/W reset
231 * - Access to UFS protector's register
232 */
exynos_ufs_auto_ctrl_hcc(struct exynos_ufs * ufs,bool en)233 static void exynos_ufs_auto_ctrl_hcc(struct exynos_ufs *ufs, bool en)
234 {
235 u32 misc = hci_readl(ufs, HCI_MISC);
236
237 if (en)
238 hci_writel(ufs, misc | HCI_CORECLK_CTRL_EN, HCI_MISC);
239 else
240 hci_writel(ufs, misc & ~HCI_CORECLK_CTRL_EN, HCI_MISC);
241 }
242
exynos_ufs_ctrl_clkstop(struct exynos_ufs * ufs,bool en)243 static void exynos_ufs_ctrl_clkstop(struct exynos_ufs *ufs, bool en)
244 {
245 u32 ctrl = hci_readl(ufs, HCI_CLKSTOP_CTRL);
246 u32 misc = hci_readl(ufs, HCI_MISC);
247
248 if (en) {
249 hci_writel(ufs, misc | CLK_CTRL_EN_MASK, HCI_MISC);
250 hci_writel(ufs, ctrl | CLK_STOP_MASK, HCI_CLKSTOP_CTRL);
251 } else {
252 hci_writel(ufs, ctrl & ~CLK_STOP_MASK, HCI_CLKSTOP_CTRL);
253 hci_writel(ufs, misc & ~CLK_CTRL_EN_MASK, HCI_MISC);
254 }
255 }
256
exynos_ufs_get_clk_info(struct exynos_ufs * ufs)257 static int exynos_ufs_get_clk_info(struct exynos_ufs *ufs)
258 {
259 struct ufs_hba *hba = ufs->hba;
260 struct list_head *head = &hba->clk_list_head;
261 struct ufs_clk_info *clki;
262 u32 pclk_rate;
263 u32 f_min, f_max;
264 u8 div = 0;
265 int ret = 0;
266
267 if (list_empty(head))
268 goto out;
269
270 list_for_each_entry(clki, head, list) {
271 if (!IS_ERR(clki->clk)) {
272 if (!strcmp(clki->name, "core_clk"))
273 ufs->clk_hci_core = clki->clk;
274 else if (!strcmp(clki->name, "sclk_unipro_main"))
275 ufs->clk_unipro_main = clki->clk;
276 }
277 }
278
279 if (!ufs->clk_hci_core || !ufs->clk_unipro_main) {
280 dev_err(hba->dev, "failed to get clk info\n");
281 ret = -EINVAL;
282 goto out;
283 }
284
285 ufs->mclk_rate = clk_get_rate(ufs->clk_unipro_main);
286 pclk_rate = clk_get_rate(ufs->clk_hci_core);
287 f_min = ufs->pclk_avail_min;
288 f_max = ufs->pclk_avail_max;
289
290 if (ufs->opts & EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL) {
291 do {
292 pclk_rate /= (div + 1);
293
294 if (pclk_rate <= f_max)
295 break;
296 div++;
297 } while (pclk_rate >= f_min);
298 }
299
300 if (unlikely(pclk_rate < f_min || pclk_rate > f_max)) {
301 dev_err(hba->dev, "not available pclk range %d\n", pclk_rate);
302 ret = -EINVAL;
303 goto out;
304 }
305
306 ufs->pclk_rate = pclk_rate;
307 ufs->pclk_div = div;
308
309 out:
310 return ret;
311 }
312
exynos_ufs_set_unipro_pclk_div(struct exynos_ufs * ufs)313 static void exynos_ufs_set_unipro_pclk_div(struct exynos_ufs *ufs)
314 {
315 if (ufs->opts & EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL) {
316 u32 val;
317
318 val = hci_readl(ufs, HCI_UNIPRO_APB_CLK_CTRL);
319 hci_writel(ufs, UNIPRO_APB_CLK(val, ufs->pclk_div),
320 HCI_UNIPRO_APB_CLK_CTRL);
321 }
322 }
323
exynos_ufs_set_pwm_clk_div(struct exynos_ufs * ufs)324 static void exynos_ufs_set_pwm_clk_div(struct exynos_ufs *ufs)
325 {
326 struct ufs_hba *hba = ufs->hba;
327 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
328
329 ufshcd_dme_set(hba,
330 UIC_ARG_MIB(CMN_PWM_CLK_CTRL), attr->cmn_pwm_clk_ctrl);
331 }
332
exynos_ufs_calc_pwm_clk_div(struct exynos_ufs * ufs)333 static void exynos_ufs_calc_pwm_clk_div(struct exynos_ufs *ufs)
334 {
335 struct ufs_hba *hba = ufs->hba;
336 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
337 const unsigned int div = 30, mult = 20;
338 const unsigned long pwm_min = 3 * 1000 * 1000;
339 const unsigned long pwm_max = 9 * 1000 * 1000;
340 const int divs[] = {32, 16, 8, 4};
341 unsigned long clk = 0, _clk, clk_period;
342 int i = 0, clk_idx = -1;
343
344 clk_period = UNIPRO_PCLK_PERIOD(ufs);
345 for (i = 0; i < ARRAY_SIZE(divs); i++) {
346 _clk = NSEC_PER_SEC * mult / (clk_period * divs[i] * div);
347 if (_clk >= pwm_min && _clk <= pwm_max) {
348 if (_clk > clk) {
349 clk_idx = i;
350 clk = _clk;
351 }
352 }
353 }
354
355 if (clk_idx == -1) {
356 ufshcd_dme_get(hba, UIC_ARG_MIB(CMN_PWM_CLK_CTRL), &clk_idx);
357 dev_err(hba->dev,
358 "failed to decide pwm clock divider, will not change\n");
359 }
360
361 attr->cmn_pwm_clk_ctrl = clk_idx & PWM_CLK_CTRL_MASK;
362 }
363
exynos_ufs_calc_time_cntr(struct exynos_ufs * ufs,long period)364 long exynos_ufs_calc_time_cntr(struct exynos_ufs *ufs, long period)
365 {
366 const int precise = 10;
367 long pclk_rate = ufs->pclk_rate;
368 long clk_period, fraction;
369
370 clk_period = UNIPRO_PCLK_PERIOD(ufs);
371 fraction = ((NSEC_PER_SEC % pclk_rate) * precise) / pclk_rate;
372
373 return (period * precise) / ((clk_period * precise) + fraction);
374 }
375
exynos_ufs_specify_phy_time_attr(struct exynos_ufs * ufs)376 static void exynos_ufs_specify_phy_time_attr(struct exynos_ufs *ufs)
377 {
378 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
379 struct ufs_phy_time_cfg *t_cfg = &ufs->t_cfg;
380
381 t_cfg->tx_linereset_p =
382 exynos_ufs_calc_time_cntr(ufs, attr->tx_dif_p_nsec);
383 t_cfg->tx_linereset_n =
384 exynos_ufs_calc_time_cntr(ufs, attr->tx_dif_n_nsec);
385 t_cfg->tx_high_z_cnt =
386 exynos_ufs_calc_time_cntr(ufs, attr->tx_high_z_cnt_nsec);
387 t_cfg->tx_base_n_val =
388 exynos_ufs_calc_time_cntr(ufs, attr->tx_base_unit_nsec);
389 t_cfg->tx_gran_n_val =
390 exynos_ufs_calc_time_cntr(ufs, attr->tx_gran_unit_nsec);
391 t_cfg->tx_sleep_cnt =
392 exynos_ufs_calc_time_cntr(ufs, attr->tx_sleep_cnt);
393
394 t_cfg->rx_linereset =
395 exynos_ufs_calc_time_cntr(ufs, attr->rx_dif_p_nsec);
396 t_cfg->rx_hibern8_wait =
397 exynos_ufs_calc_time_cntr(ufs, attr->rx_hibern8_wait_nsec);
398 t_cfg->rx_base_n_val =
399 exynos_ufs_calc_time_cntr(ufs, attr->rx_base_unit_nsec);
400 t_cfg->rx_gran_n_val =
401 exynos_ufs_calc_time_cntr(ufs, attr->rx_gran_unit_nsec);
402 t_cfg->rx_sleep_cnt =
403 exynos_ufs_calc_time_cntr(ufs, attr->rx_sleep_cnt);
404 t_cfg->rx_stall_cnt =
405 exynos_ufs_calc_time_cntr(ufs, attr->rx_stall_cnt);
406 }
407
exynos_ufs_config_phy_time_attr(struct exynos_ufs * ufs)408 static void exynos_ufs_config_phy_time_attr(struct exynos_ufs *ufs)
409 {
410 struct ufs_hba *hba = ufs->hba;
411 struct ufs_phy_time_cfg *t_cfg = &ufs->t_cfg;
412 int i;
413
414 exynos_ufs_set_pwm_clk_div(ufs);
415
416 exynos_ufs_enable_ov_tm(hba);
417
418 for_each_ufs_rx_lane(ufs, i) {
419 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_FILLER_ENABLE, i),
420 ufs->drv_data->uic_attr->rx_filler_enable);
421 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_LINERESET_VAL, i),
422 RX_LINERESET(t_cfg->rx_linereset));
423 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_BASE_NVAL_07_00, i),
424 RX_BASE_NVAL_L(t_cfg->rx_base_n_val));
425 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_BASE_NVAL_15_08, i),
426 RX_BASE_NVAL_H(t_cfg->rx_base_n_val));
427 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_GRAN_NVAL_07_00, i),
428 RX_GRAN_NVAL_L(t_cfg->rx_gran_n_val));
429 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_GRAN_NVAL_10_08, i),
430 RX_GRAN_NVAL_H(t_cfg->rx_gran_n_val));
431 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_OV_SLEEP_CNT_TIMER, i),
432 RX_OV_SLEEP_CNT(t_cfg->rx_sleep_cnt));
433 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_OV_STALL_CNT_TIMER, i),
434 RX_OV_STALL_CNT(t_cfg->rx_stall_cnt));
435 }
436
437 for_each_ufs_tx_lane(ufs, i) {
438 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_LINERESET_P_VAL, i),
439 TX_LINERESET_P(t_cfg->tx_linereset_p));
440 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_HIGH_Z_CNT_07_00, i),
441 TX_HIGH_Z_CNT_L(t_cfg->tx_high_z_cnt));
442 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_HIGH_Z_CNT_11_08, i),
443 TX_HIGH_Z_CNT_H(t_cfg->tx_high_z_cnt));
444 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_BASE_NVAL_07_00, i),
445 TX_BASE_NVAL_L(t_cfg->tx_base_n_val));
446 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_BASE_NVAL_15_08, i),
447 TX_BASE_NVAL_H(t_cfg->tx_base_n_val));
448 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_GRAN_NVAL_07_00, i),
449 TX_GRAN_NVAL_L(t_cfg->tx_gran_n_val));
450 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_GRAN_NVAL_10_08, i),
451 TX_GRAN_NVAL_H(t_cfg->tx_gran_n_val));
452 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_OV_SLEEP_CNT_TIMER, i),
453 TX_OV_H8_ENTER_EN |
454 TX_OV_SLEEP_CNT(t_cfg->tx_sleep_cnt));
455 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_MIN_ACTIVATETIME, i),
456 ufs->drv_data->uic_attr->tx_min_activatetime);
457 }
458
459 exynos_ufs_disable_ov_tm(hba);
460 }
461
exynos_ufs_config_phy_cap_attr(struct exynos_ufs * ufs)462 static void exynos_ufs_config_phy_cap_attr(struct exynos_ufs *ufs)
463 {
464 struct ufs_hba *hba = ufs->hba;
465 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
466 int i;
467
468 exynos_ufs_enable_ov_tm(hba);
469
470 for_each_ufs_rx_lane(ufs, i) {
471 ufshcd_dme_set(hba,
472 UIC_ARG_MIB_SEL(RX_HS_G1_SYNC_LENGTH_CAP, i),
473 attr->rx_hs_g1_sync_len_cap);
474 ufshcd_dme_set(hba,
475 UIC_ARG_MIB_SEL(RX_HS_G2_SYNC_LENGTH_CAP, i),
476 attr->rx_hs_g2_sync_len_cap);
477 ufshcd_dme_set(hba,
478 UIC_ARG_MIB_SEL(RX_HS_G3_SYNC_LENGTH_CAP, i),
479 attr->rx_hs_g3_sync_len_cap);
480 ufshcd_dme_set(hba,
481 UIC_ARG_MIB_SEL(RX_HS_G1_PREP_LENGTH_CAP, i),
482 attr->rx_hs_g1_prep_sync_len_cap);
483 ufshcd_dme_set(hba,
484 UIC_ARG_MIB_SEL(RX_HS_G2_PREP_LENGTH_CAP, i),
485 attr->rx_hs_g2_prep_sync_len_cap);
486 ufshcd_dme_set(hba,
487 UIC_ARG_MIB_SEL(RX_HS_G3_PREP_LENGTH_CAP, i),
488 attr->rx_hs_g3_prep_sync_len_cap);
489 }
490
491 if (attr->rx_adv_fine_gran_sup_en == 0) {
492 for_each_ufs_rx_lane(ufs, i) {
493 ufshcd_dme_set(hba,
494 UIC_ARG_MIB_SEL(RX_ADV_GRANULARITY_CAP, i), 0);
495
496 if (attr->rx_min_actv_time_cap)
497 ufshcd_dme_set(hba,
498 UIC_ARG_MIB_SEL(RX_MIN_ACTIVATETIME_CAP,
499 i), attr->rx_min_actv_time_cap);
500
501 if (attr->rx_hibern8_time_cap)
502 ufshcd_dme_set(hba,
503 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAP, i),
504 attr->rx_hibern8_time_cap);
505 }
506 } else if (attr->rx_adv_fine_gran_sup_en == 1) {
507 for_each_ufs_rx_lane(ufs, i) {
508 if (attr->rx_adv_fine_gran_step)
509 ufshcd_dme_set(hba,
510 UIC_ARG_MIB_SEL(RX_ADV_GRANULARITY_CAP,
511 i), RX_ADV_FINE_GRAN_STEP(
512 attr->rx_adv_fine_gran_step));
513
514 if (attr->rx_adv_min_actv_time_cap)
515 ufshcd_dme_set(hba,
516 UIC_ARG_MIB_SEL(
517 RX_ADV_MIN_ACTIVATETIME_CAP, i),
518 attr->rx_adv_min_actv_time_cap);
519
520 if (attr->rx_adv_hibern8_time_cap)
521 ufshcd_dme_set(hba,
522 UIC_ARG_MIB_SEL(RX_ADV_HIBERN8TIME_CAP,
523 i),
524 attr->rx_adv_hibern8_time_cap);
525 }
526 }
527
528 exynos_ufs_disable_ov_tm(hba);
529 }
530
exynos_ufs_establish_connt(struct exynos_ufs * ufs)531 static void exynos_ufs_establish_connt(struct exynos_ufs *ufs)
532 {
533 struct ufs_hba *hba = ufs->hba;
534 enum {
535 DEV_ID = 0x00,
536 PEER_DEV_ID = 0x01,
537 PEER_CPORT_ID = 0x00,
538 TRAFFIC_CLASS = 0x00,
539 };
540
541 /* allow cport attributes to be set */
542 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CONNECTIONSTATE), CPORT_IDLE);
543
544 /* local unipro attributes */
545 ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID), DEV_ID);
546 ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID_VALID), TRUE);
547 ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERDEVICEID), PEER_DEV_ID);
548 ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERCPORTID), PEER_CPORT_ID);
549 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CPORTFLAGS), CPORT_DEF_FLAGS);
550 ufshcd_dme_set(hba, UIC_ARG_MIB(T_TRAFFICCLASS), TRAFFIC_CLASS);
551 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CONNECTIONSTATE), CPORT_CONNECTED);
552 }
553
exynos_ufs_config_smu(struct exynos_ufs * ufs)554 static void exynos_ufs_config_smu(struct exynos_ufs *ufs)
555 {
556 u32 reg, val;
557
558 exynos_ufs_disable_auto_ctrl_hcc_save(ufs, &val);
559
560 /* make encryption disabled by default */
561 reg = ufsp_readl(ufs, UFSPRSECURITY);
562 ufsp_writel(ufs, reg | NSSMU, UFSPRSECURITY);
563 ufsp_writel(ufs, 0x0, UFSPSBEGIN0);
564 ufsp_writel(ufs, 0xffffffff, UFSPSEND0);
565 ufsp_writel(ufs, 0xff, UFSPSLUN0);
566 ufsp_writel(ufs, 0xf1, UFSPSCTRL0);
567
568 exynos_ufs_auto_ctrl_hcc_restore(ufs, &val);
569 }
570
exynos_ufs_config_sync_pattern_mask(struct exynos_ufs * ufs,struct ufs_pa_layer_attr * pwr)571 static void exynos_ufs_config_sync_pattern_mask(struct exynos_ufs *ufs,
572 struct ufs_pa_layer_attr *pwr)
573 {
574 struct ufs_hba *hba = ufs->hba;
575 u8 g = max_t(u32, pwr->gear_rx, pwr->gear_tx);
576 u32 mask, sync_len;
577 enum {
578 SYNC_LEN_G1 = 80 * 1000, /* 80us */
579 SYNC_LEN_G2 = 40 * 1000, /* 44us */
580 SYNC_LEN_G3 = 20 * 1000, /* 20us */
581 };
582 int i;
583
584 if (g == 1)
585 sync_len = SYNC_LEN_G1;
586 else if (g == 2)
587 sync_len = SYNC_LEN_G2;
588 else if (g == 3)
589 sync_len = SYNC_LEN_G3;
590 else
591 return;
592
593 mask = exynos_ufs_calc_time_cntr(ufs, sync_len);
594 mask = (mask >> 8) & 0xff;
595
596 exynos_ufs_enable_ov_tm(hba);
597
598 for_each_ufs_rx_lane(ufs, i)
599 ufshcd_dme_set(hba,
600 UIC_ARG_MIB_SEL(RX_SYNC_MASK_LENGTH, i), mask);
601
602 exynos_ufs_disable_ov_tm(hba);
603 }
604
exynos_ufs_pre_pwr_mode(struct ufs_hba * hba,struct ufs_pa_layer_attr * dev_max_params,struct ufs_pa_layer_attr * dev_req_params)605 static int exynos_ufs_pre_pwr_mode(struct ufs_hba *hba,
606 struct ufs_pa_layer_attr *dev_max_params,
607 struct ufs_pa_layer_attr *dev_req_params)
608 {
609 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
610 struct phy *generic_phy = ufs->phy;
611 struct ufs_dev_params ufs_exynos_cap;
612 int ret;
613
614 if (!dev_req_params) {
615 pr_err("%s: incoming dev_req_params is NULL\n", __func__);
616 ret = -EINVAL;
617 goto out;
618 }
619
620 ufshcd_init_pwr_dev_param(&ufs_exynos_cap);
621
622 ret = ufshcd_get_pwr_dev_param(&ufs_exynos_cap,
623 dev_max_params, dev_req_params);
624 if (ret) {
625 pr_err("%s: failed to determine capabilities\n", __func__);
626 goto out;
627 }
628
629 if (ufs->drv_data->pre_pwr_change)
630 ufs->drv_data->pre_pwr_change(ufs, dev_req_params);
631
632 if (ufshcd_is_hs_mode(dev_req_params)) {
633 exynos_ufs_config_sync_pattern_mask(ufs, dev_req_params);
634
635 switch (dev_req_params->hs_rate) {
636 case PA_HS_MODE_A:
637 case PA_HS_MODE_B:
638 phy_calibrate(generic_phy);
639 break;
640 }
641 }
642
643 /* setting for three timeout values for traffic class #0 */
644 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 8064);
645 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 28224);
646 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 20160);
647
648 return 0;
649 out:
650 return ret;
651 }
652
653 #define PWR_MODE_STR_LEN 64
exynos_ufs_post_pwr_mode(struct ufs_hba * hba,struct ufs_pa_layer_attr * pwr_req)654 static int exynos_ufs_post_pwr_mode(struct ufs_hba *hba,
655 struct ufs_pa_layer_attr *pwr_req)
656 {
657 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
658 struct phy *generic_phy = ufs->phy;
659 int gear = max_t(u32, pwr_req->gear_rx, pwr_req->gear_tx);
660 int lanes = max_t(u32, pwr_req->lane_rx, pwr_req->lane_tx);
661 char pwr_str[PWR_MODE_STR_LEN] = "";
662
663 /* let default be PWM Gear 1, Lane 1 */
664 if (!gear)
665 gear = 1;
666
667 if (!lanes)
668 lanes = 1;
669
670 if (ufs->drv_data->post_pwr_change)
671 ufs->drv_data->post_pwr_change(ufs, pwr_req);
672
673 if ((ufshcd_is_hs_mode(pwr_req))) {
674 switch (pwr_req->hs_rate) {
675 case PA_HS_MODE_A:
676 case PA_HS_MODE_B:
677 phy_calibrate(generic_phy);
678 break;
679 }
680
681 snprintf(pwr_str, PWR_MODE_STR_LEN, "%s series_%s G_%d L_%d",
682 "FAST", pwr_req->hs_rate == PA_HS_MODE_A ? "A" : "B",
683 gear, lanes);
684 } else {
685 snprintf(pwr_str, PWR_MODE_STR_LEN, "%s G_%d L_%d",
686 "SLOW", gear, lanes);
687 }
688
689 dev_info(hba->dev, "Power mode changed to : %s\n", pwr_str);
690
691 return 0;
692 }
693
exynos_ufs_specify_nexus_t_xfer_req(struct ufs_hba * hba,int tag,bool op)694 static void exynos_ufs_specify_nexus_t_xfer_req(struct ufs_hba *hba,
695 int tag, bool op)
696 {
697 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
698 u32 type;
699
700 type = hci_readl(ufs, HCI_UTRL_NEXUS_TYPE);
701
702 if (op)
703 hci_writel(ufs, type | (1 << tag), HCI_UTRL_NEXUS_TYPE);
704 else
705 hci_writel(ufs, type & ~(1 << tag), HCI_UTRL_NEXUS_TYPE);
706 }
707
exynos_ufs_specify_nexus_t_tm_req(struct ufs_hba * hba,int tag,u8 func)708 static void exynos_ufs_specify_nexus_t_tm_req(struct ufs_hba *hba,
709 int tag, u8 func)
710 {
711 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
712 u32 type;
713
714 type = hci_readl(ufs, HCI_UTMRL_NEXUS_TYPE);
715
716 switch (func) {
717 case UFS_ABORT_TASK:
718 case UFS_QUERY_TASK:
719 hci_writel(ufs, type | (1 << tag), HCI_UTMRL_NEXUS_TYPE);
720 break;
721 case UFS_ABORT_TASK_SET:
722 case UFS_CLEAR_TASK_SET:
723 case UFS_LOGICAL_RESET:
724 case UFS_QUERY_TASK_SET:
725 hci_writel(ufs, type & ~(1 << tag), HCI_UTMRL_NEXUS_TYPE);
726 break;
727 }
728 }
729
exynos_ufs_phy_init(struct exynos_ufs * ufs)730 static int exynos_ufs_phy_init(struct exynos_ufs *ufs)
731 {
732 struct ufs_hba *hba = ufs->hba;
733 struct phy *generic_phy = ufs->phy;
734 int ret = 0;
735
736 if (ufs->avail_ln_rx == 0 || ufs->avail_ln_tx == 0) {
737 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILRXDATALANES),
738 &ufs->avail_ln_rx);
739 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILTXDATALANES),
740 &ufs->avail_ln_tx);
741 WARN(ufs->avail_ln_rx != ufs->avail_ln_tx,
742 "available data lane is not equal(rx:%d, tx:%d)\n",
743 ufs->avail_ln_rx, ufs->avail_ln_tx);
744 }
745
746 phy_set_bus_width(generic_phy, ufs->avail_ln_rx);
747 ret = phy_init(generic_phy);
748 if (ret) {
749 dev_err(hba->dev, "%s: phy init failed, ret = %d\n",
750 __func__, ret);
751 goto out_exit_phy;
752 }
753
754 return 0;
755
756 out_exit_phy:
757 phy_exit(generic_phy);
758
759 return ret;
760 }
761
exynos_ufs_config_unipro(struct exynos_ufs * ufs)762 static void exynos_ufs_config_unipro(struct exynos_ufs *ufs)
763 {
764 struct ufs_hba *hba = ufs->hba;
765
766 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_CLK_PERIOD),
767 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
768 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTRAILINGCLOCKS),
769 ufs->drv_data->uic_attr->tx_trailingclks);
770 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE),
771 ufs->drv_data->uic_attr->pa_dbg_option_suite);
772 }
773
exynos_ufs_config_intr(struct exynos_ufs * ufs,u32 errs,u8 index)774 static void exynos_ufs_config_intr(struct exynos_ufs *ufs, u32 errs, u8 index)
775 {
776 switch (index) {
777 case UNIPRO_L1_5:
778 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_PA_LAYER);
779 break;
780 case UNIPRO_L2:
781 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_DL_LAYER);
782 break;
783 case UNIPRO_L3:
784 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_N_LAYER);
785 break;
786 case UNIPRO_L4:
787 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_T_LAYER);
788 break;
789 case UNIPRO_DME:
790 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_DME_LAYER);
791 break;
792 }
793 }
794
exynos_ufs_pre_link(struct ufs_hba * hba)795 static int exynos_ufs_pre_link(struct ufs_hba *hba)
796 {
797 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
798
799 /* hci */
800 exynos_ufs_config_intr(ufs, DFES_DEF_L2_ERRS, UNIPRO_L2);
801 exynos_ufs_config_intr(ufs, DFES_DEF_L3_ERRS, UNIPRO_L3);
802 exynos_ufs_config_intr(ufs, DFES_DEF_L4_ERRS, UNIPRO_L4);
803 exynos_ufs_set_unipro_pclk_div(ufs);
804
805 /* unipro */
806 exynos_ufs_config_unipro(ufs);
807
808 /* m-phy */
809 exynos_ufs_phy_init(ufs);
810 exynos_ufs_config_phy_time_attr(ufs);
811 exynos_ufs_config_phy_cap_attr(ufs);
812
813 if (ufs->drv_data->pre_link)
814 ufs->drv_data->pre_link(ufs);
815
816 return 0;
817 }
818
exynos_ufs_fit_aggr_timeout(struct exynos_ufs * ufs)819 static void exynos_ufs_fit_aggr_timeout(struct exynos_ufs *ufs)
820 {
821 u32 val;
822
823 val = exynos_ufs_calc_time_cntr(ufs, IATOVAL_NSEC / CNTR_DIV_VAL);
824 hci_writel(ufs, val & CNT_VAL_1US_MASK, HCI_1US_TO_CNT_VAL);
825 }
826
exynos_ufs_post_link(struct ufs_hba * hba)827 static int exynos_ufs_post_link(struct ufs_hba *hba)
828 {
829 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
830 struct phy *generic_phy = ufs->phy;
831 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
832
833 exynos_ufs_establish_connt(ufs);
834 exynos_ufs_fit_aggr_timeout(ufs);
835
836 hci_writel(ufs, 0xa, HCI_DATA_REORDER);
837 hci_writel(ufs, PRDT_SET_SIZE(12), HCI_TXPRDT_ENTRY_SIZE);
838 hci_writel(ufs, PRDT_SET_SIZE(12), HCI_RXPRDT_ENTRY_SIZE);
839 hci_writel(ufs, (1 << hba->nutrs) - 1, HCI_UTRL_NEXUS_TYPE);
840 hci_writel(ufs, (1 << hba->nutmrs) - 1, HCI_UTMRL_NEXUS_TYPE);
841 hci_writel(ufs, 0xf, HCI_AXIDMA_RWDATA_BURST_LEN);
842
843 if (ufs->opts & EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB)
844 ufshcd_dme_set(hba,
845 UIC_ARG_MIB(T_DBG_SKIP_INIT_HIBERN8_EXIT), TRUE);
846
847 if (attr->pa_granularity) {
848 exynos_ufs_enable_dbg_mode(hba);
849 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_GRANULARITY),
850 attr->pa_granularity);
851 exynos_ufs_disable_dbg_mode(hba);
852
853 if (attr->pa_tactivate)
854 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
855 attr->pa_tactivate);
856 if (attr->pa_hibern8time &&
857 !(ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER))
858 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
859 attr->pa_hibern8time);
860 }
861
862 if (ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER) {
863 if (!attr->pa_granularity)
864 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
865 &attr->pa_granularity);
866 if (!attr->pa_hibern8time)
867 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
868 &attr->pa_hibern8time);
869 /*
870 * not wait for HIBERN8 time to exit hibernation
871 */
872 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), 0);
873
874 if (attr->pa_granularity < 1 || attr->pa_granularity > 6) {
875 /* Valid range for granularity: 1 ~ 6 */
876 dev_warn(hba->dev,
877 "%s: pa_granularity %d is invalid, assuming backwards compatibility\n",
878 __func__,
879 attr->pa_granularity);
880 attr->pa_granularity = 6;
881 }
882 }
883
884 phy_calibrate(generic_phy);
885
886 if (ufs->drv_data->post_link)
887 ufs->drv_data->post_link(ufs);
888
889 return 0;
890 }
891
exynos_ufs_parse_dt(struct device * dev,struct exynos_ufs * ufs)892 static int exynos_ufs_parse_dt(struct device *dev, struct exynos_ufs *ufs)
893 {
894 struct device_node *np = dev->of_node;
895 struct exynos_ufs_drv_data *drv_data = &exynos_ufs_drvs;
896 struct exynos_ufs_uic_attr *attr;
897 int ret = 0;
898
899 while (drv_data->compatible) {
900 if (of_device_is_compatible(np, drv_data->compatible)) {
901 ufs->drv_data = drv_data;
902 break;
903 }
904 drv_data++;
905 }
906
907 if (ufs->drv_data && ufs->drv_data->uic_attr) {
908 attr = ufs->drv_data->uic_attr;
909 } else {
910 dev_err(dev, "failed to get uic attributes\n");
911 ret = -EINVAL;
912 goto out;
913 }
914
915 ufs->pclk_avail_min = PCLK_AVAIL_MIN;
916 ufs->pclk_avail_max = PCLK_AVAIL_MAX;
917
918 attr->rx_adv_fine_gran_sup_en = RX_ADV_FINE_GRAN_SUP_EN;
919 attr->rx_adv_fine_gran_step = RX_ADV_FINE_GRAN_STEP_VAL;
920 attr->rx_adv_min_actv_time_cap = RX_ADV_MIN_ACTV_TIME_CAP;
921 attr->pa_granularity = PA_GRANULARITY_VAL;
922 attr->pa_tactivate = PA_TACTIVATE_VAL;
923 attr->pa_hibern8time = PA_HIBERN8TIME_VAL;
924
925 out:
926 return ret;
927 }
928
exynos_ufs_init(struct ufs_hba * hba)929 static int exynos_ufs_init(struct ufs_hba *hba)
930 {
931 struct device *dev = hba->dev;
932 struct platform_device *pdev = to_platform_device(dev);
933 struct exynos_ufs *ufs;
934 int ret;
935
936 ufs = devm_kzalloc(dev, sizeof(*ufs), GFP_KERNEL);
937 if (!ufs)
938 return -ENOMEM;
939
940 /* exynos-specific hci */
941 ufs->reg_hci = devm_platform_ioremap_resource_byname(pdev, "vs_hci");
942 if (IS_ERR(ufs->reg_hci)) {
943 dev_err(dev, "cannot ioremap for hci vendor register\n");
944 return PTR_ERR(ufs->reg_hci);
945 }
946
947 /* unipro */
948 ufs->reg_unipro = devm_platform_ioremap_resource_byname(pdev, "unipro");
949 if (IS_ERR(ufs->reg_unipro)) {
950 dev_err(dev, "cannot ioremap for unipro register\n");
951 return PTR_ERR(ufs->reg_unipro);
952 }
953
954 /* ufs protector */
955 ufs->reg_ufsp = devm_platform_ioremap_resource_byname(pdev, "ufsp");
956 if (IS_ERR(ufs->reg_ufsp)) {
957 dev_err(dev, "cannot ioremap for ufs protector register\n");
958 return PTR_ERR(ufs->reg_ufsp);
959 }
960
961 ret = exynos_ufs_parse_dt(dev, ufs);
962 if (ret) {
963 dev_err(dev, "failed to get dt info.\n");
964 goto out;
965 }
966
967 ufs->phy = devm_phy_get(dev, "ufs-phy");
968 if (IS_ERR(ufs->phy)) {
969 ret = PTR_ERR(ufs->phy);
970 dev_err(dev, "failed to get ufs-phy\n");
971 goto out;
972 }
973
974 ret = phy_power_on(ufs->phy);
975 if (ret)
976 goto phy_off;
977
978 ufs->hba = hba;
979 ufs->opts = ufs->drv_data->opts;
980 ufs->rx_sel_idx = PA_MAXDATALANES;
981 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX)
982 ufs->rx_sel_idx = 0;
983 hba->priv = (void *)ufs;
984 hba->quirks = ufs->drv_data->quirks;
985 if (ufs->drv_data->drv_init) {
986 ret = ufs->drv_data->drv_init(dev, ufs);
987 if (ret) {
988 dev_err(dev, "failed to init drv-data\n");
989 goto out;
990 }
991 }
992
993 ret = exynos_ufs_get_clk_info(ufs);
994 if (ret)
995 goto out;
996 exynos_ufs_specify_phy_time_attr(ufs);
997 exynos_ufs_config_smu(ufs);
998 return 0;
999
1000 phy_off:
1001 phy_power_off(ufs->phy);
1002 out:
1003 hba->priv = NULL;
1004 return ret;
1005 }
1006
exynos_ufs_host_reset(struct ufs_hba * hba)1007 static int exynos_ufs_host_reset(struct ufs_hba *hba)
1008 {
1009 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1010 unsigned long timeout = jiffies + msecs_to_jiffies(1);
1011 u32 val;
1012 int ret = 0;
1013
1014 exynos_ufs_disable_auto_ctrl_hcc_save(ufs, &val);
1015
1016 hci_writel(ufs, UFS_SW_RST_MASK, HCI_SW_RST);
1017
1018 do {
1019 if (!(hci_readl(ufs, HCI_SW_RST) & UFS_SW_RST_MASK))
1020 goto out;
1021 } while (time_before(jiffies, timeout));
1022
1023 dev_err(hba->dev, "timeout host sw-reset\n");
1024 ret = -ETIMEDOUT;
1025
1026 out:
1027 exynos_ufs_auto_ctrl_hcc_restore(ufs, &val);
1028 return ret;
1029 }
1030
exynos_ufs_dev_hw_reset(struct ufs_hba * hba)1031 static void exynos_ufs_dev_hw_reset(struct ufs_hba *hba)
1032 {
1033 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1034
1035 hci_writel(ufs, 0 << 0, HCI_GPIO_OUT);
1036 udelay(5);
1037 hci_writel(ufs, 1 << 0, HCI_GPIO_OUT);
1038 }
1039
exynos_ufs_pre_hibern8(struct ufs_hba * hba,u8 enter)1040 static void exynos_ufs_pre_hibern8(struct ufs_hba *hba, u8 enter)
1041 {
1042 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1043 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
1044
1045 if (!enter) {
1046 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL)
1047 exynos_ufs_disable_auto_ctrl_hcc(ufs);
1048 exynos_ufs_ungate_clks(ufs);
1049
1050 if (ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER) {
1051 const unsigned int granularity_tbl[] = {
1052 1, 4, 8, 16, 32, 100
1053 };
1054 int h8_time = attr->pa_hibern8time *
1055 granularity_tbl[attr->pa_granularity - 1];
1056 unsigned long us;
1057 s64 delta;
1058
1059 do {
1060 delta = h8_time - ktime_us_delta(ktime_get(),
1061 ufs->entry_hibern8_t);
1062 if (delta <= 0)
1063 break;
1064
1065 us = min_t(s64, delta, USEC_PER_MSEC);
1066 if (us >= 10)
1067 usleep_range(us, us + 10);
1068 } while (1);
1069 }
1070 }
1071 }
1072
exynos_ufs_post_hibern8(struct ufs_hba * hba,u8 enter)1073 static void exynos_ufs_post_hibern8(struct ufs_hba *hba, u8 enter)
1074 {
1075 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1076
1077 if (!enter) {
1078 u32 cur_mode = 0;
1079 u32 pwrmode;
1080
1081 if (ufshcd_is_hs_mode(&ufs->dev_req_params))
1082 pwrmode = FAST_MODE;
1083 else
1084 pwrmode = SLOW_MODE;
1085
1086 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &cur_mode);
1087 if (cur_mode != (pwrmode << 4 | pwrmode)) {
1088 dev_warn(hba->dev, "%s: power mode change\n", __func__);
1089 hba->pwr_info.pwr_rx = (cur_mode >> 4) & 0xf;
1090 hba->pwr_info.pwr_tx = cur_mode & 0xf;
1091 ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
1092 }
1093
1094 if (!(ufs->opts & EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB))
1095 exynos_ufs_establish_connt(ufs);
1096 } else {
1097 ufs->entry_hibern8_t = ktime_get();
1098 exynos_ufs_gate_clks(ufs);
1099 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL)
1100 exynos_ufs_enable_auto_ctrl_hcc(ufs);
1101 }
1102 }
1103
exynos_ufs_hce_enable_notify(struct ufs_hba * hba,enum ufs_notify_change_status status)1104 static int exynos_ufs_hce_enable_notify(struct ufs_hba *hba,
1105 enum ufs_notify_change_status status)
1106 {
1107 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1108 int ret = 0;
1109
1110 switch (status) {
1111 case PRE_CHANGE:
1112 ret = exynos_ufs_host_reset(hba);
1113 if (ret)
1114 return ret;
1115 exynos_ufs_dev_hw_reset(hba);
1116 break;
1117 case POST_CHANGE:
1118 exynos_ufs_calc_pwm_clk_div(ufs);
1119 if (!(ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL))
1120 exynos_ufs_enable_auto_ctrl_hcc(ufs);
1121 break;
1122 }
1123
1124 return ret;
1125 }
1126
exynos_ufs_link_startup_notify(struct ufs_hba * hba,enum ufs_notify_change_status status)1127 static int exynos_ufs_link_startup_notify(struct ufs_hba *hba,
1128 enum ufs_notify_change_status status)
1129 {
1130 int ret = 0;
1131
1132 switch (status) {
1133 case PRE_CHANGE:
1134 ret = exynos_ufs_pre_link(hba);
1135 break;
1136 case POST_CHANGE:
1137 ret = exynos_ufs_post_link(hba);
1138 break;
1139 }
1140
1141 return ret;
1142 }
1143
exynos_ufs_pwr_change_notify(struct ufs_hba * hba,enum ufs_notify_change_status status,struct ufs_pa_layer_attr * dev_max_params,struct ufs_pa_layer_attr * dev_req_params)1144 static int exynos_ufs_pwr_change_notify(struct ufs_hba *hba,
1145 enum ufs_notify_change_status status,
1146 struct ufs_pa_layer_attr *dev_max_params,
1147 struct ufs_pa_layer_attr *dev_req_params)
1148 {
1149 int ret = 0;
1150
1151 switch (status) {
1152 case PRE_CHANGE:
1153 ret = exynos_ufs_pre_pwr_mode(hba, dev_max_params,
1154 dev_req_params);
1155 break;
1156 case POST_CHANGE:
1157 ret = exynos_ufs_post_pwr_mode(hba, dev_req_params);
1158 break;
1159 }
1160
1161 return ret;
1162 }
1163
exynos_ufs_hibern8_notify(struct ufs_hba * hba,enum uic_cmd_dme enter,enum ufs_notify_change_status notify)1164 static void exynos_ufs_hibern8_notify(struct ufs_hba *hba,
1165 enum uic_cmd_dme enter,
1166 enum ufs_notify_change_status notify)
1167 {
1168 switch ((u8)notify) {
1169 case PRE_CHANGE:
1170 exynos_ufs_pre_hibern8(hba, enter);
1171 break;
1172 case POST_CHANGE:
1173 exynos_ufs_post_hibern8(hba, enter);
1174 break;
1175 }
1176 }
1177
exynos_ufs_suspend(struct ufs_hba * hba,enum ufs_pm_op pm_op)1178 static int exynos_ufs_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
1179 {
1180 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1181
1182 if (!ufshcd_is_link_active(hba))
1183 phy_power_off(ufs->phy);
1184
1185 return 0;
1186 }
1187
exynos_ufs_resume(struct ufs_hba * hba,enum ufs_pm_op pm_op)1188 static int exynos_ufs_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
1189 {
1190 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1191
1192 if (!ufshcd_is_link_active(hba))
1193 phy_power_on(ufs->phy);
1194
1195 exynos_ufs_config_smu(ufs);
1196
1197 return 0;
1198 }
1199
1200 static struct ufs_hba_variant_ops ufs_hba_exynos_ops = {
1201 .name = "exynos_ufs",
1202 .init = exynos_ufs_init,
1203 .hce_enable_notify = exynos_ufs_hce_enable_notify,
1204 .link_startup_notify = exynos_ufs_link_startup_notify,
1205 .pwr_change_notify = exynos_ufs_pwr_change_notify,
1206 .setup_xfer_req = exynos_ufs_specify_nexus_t_xfer_req,
1207 .setup_task_mgmt = exynos_ufs_specify_nexus_t_tm_req,
1208 .hibern8_notify = exynos_ufs_hibern8_notify,
1209 .suspend = exynos_ufs_suspend,
1210 .resume = exynos_ufs_resume,
1211 };
1212
exynos_ufs_probe(struct platform_device * pdev)1213 static int exynos_ufs_probe(struct platform_device *pdev)
1214 {
1215 int err;
1216 struct device *dev = &pdev->dev;
1217
1218 err = ufshcd_pltfrm_init(pdev, &ufs_hba_exynos_ops);
1219 if (err)
1220 dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", err);
1221
1222 return err;
1223 }
1224
exynos_ufs_remove(struct platform_device * pdev)1225 static int exynos_ufs_remove(struct platform_device *pdev)
1226 {
1227 struct ufs_hba *hba = platform_get_drvdata(pdev);
1228
1229 pm_runtime_get_sync(&(pdev)->dev);
1230 ufshcd_remove(hba);
1231 return 0;
1232 }
1233
1234 struct exynos_ufs_drv_data exynos_ufs_drvs = {
1235
1236 .compatible = "samsung,exynos7-ufs",
1237 .uic_attr = &exynos7_uic_attr,
1238 .quirks = UFSHCD_QUIRK_PRDT_BYTE_GRAN |
1239 UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR |
1240 UFSHCI_QUIRK_BROKEN_HCE |
1241 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR |
1242 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR |
1243 UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL |
1244 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING |
1245 UFSHCD_QUIRK_ALIGN_SG_WITH_PAGE_SIZE,
1246 .opts = EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL |
1247 EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL |
1248 EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX |
1249 EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB |
1250 EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER,
1251 .drv_init = exynos7_ufs_drv_init,
1252 .pre_link = exynos7_ufs_pre_link,
1253 .post_link = exynos7_ufs_post_link,
1254 .pre_pwr_change = exynos7_ufs_pre_pwr_change,
1255 .post_pwr_change = exynos7_ufs_post_pwr_change,
1256 };
1257
1258 static const struct of_device_id exynos_ufs_of_match[] = {
1259 { .compatible = "samsung,exynos7-ufs",
1260 .data = &exynos_ufs_drvs },
1261 {},
1262 };
1263
1264 static const struct dev_pm_ops exynos_ufs_pm_ops = {
1265 .suspend = ufshcd_pltfrm_suspend,
1266 .resume = ufshcd_pltfrm_resume,
1267 .runtime_suspend = ufshcd_pltfrm_runtime_suspend,
1268 .runtime_resume = ufshcd_pltfrm_runtime_resume,
1269 .runtime_idle = ufshcd_pltfrm_runtime_idle,
1270 };
1271
1272 static struct platform_driver exynos_ufs_pltform = {
1273 .probe = exynos_ufs_probe,
1274 .remove = exynos_ufs_remove,
1275 .shutdown = ufshcd_pltfrm_shutdown,
1276 .driver = {
1277 .name = "exynos-ufshc",
1278 .pm = &exynos_ufs_pm_ops,
1279 .of_match_table = of_match_ptr(exynos_ufs_of_match),
1280 },
1281 };
1282 module_platform_driver(exynos_ufs_pltform);
1283
1284 MODULE_AUTHOR("Alim Akhtar <alim.akhtar@samsung.com>");
1285 MODULE_AUTHOR("Seungwon Jeon <essuuj@gmail.com>");
1286 MODULE_DESCRIPTION("Exynos UFS HCI Driver");
1287 MODULE_LICENSE("GPL v2");
1288