1 // SPDX-License-Identifier: GPL-2.0
2 /******************************************************************************
3 *
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 *
6 ******************************************************************************/
7 #define _HAL_COM_PHYCFG_C_
8
9 #include <drv_types.h>
10 #include <rtw_debug.h>
11 #include <hal_data.h>
12 #include <linux/kernel.h>
13
PHY_GetTxPowerByRateBase(struct adapter * Adapter,u8 Band,u8 RfPath,u8 TxNum,enum rate_section RateSection)14 u8 PHY_GetTxPowerByRateBase(struct adapter *Adapter, u8 Band, u8 RfPath,
15 u8 TxNum, enum rate_section RateSection)
16 {
17 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
18 u8 value = 0;
19
20 if (RfPath > ODM_RF_PATH_D)
21 return 0;
22
23 if (Band == BAND_ON_2_4G) {
24 switch (RateSection) {
25 case CCK:
26 value = pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][0];
27 break;
28 case OFDM:
29 value = pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][1];
30 break;
31 case HT_MCS0_MCS7:
32 value = pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][2];
33 break;
34 case HT_MCS8_MCS15:
35 value = pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][3];
36 break;
37 case HT_MCS16_MCS23:
38 value = pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][4];
39 break;
40 case HT_MCS24_MCS31:
41 value = pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][5];
42 break;
43 case VHT_1SSMCS0_1SSMCS9:
44 value = pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][6];
45 break;
46 case VHT_2SSMCS0_2SSMCS9:
47 value = pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][7];
48 break;
49 case VHT_3SSMCS0_3SSMCS9:
50 value = pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][8];
51 break;
52 case VHT_4SSMCS0_4SSMCS9:
53 value = pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][9];
54 break;
55 default:
56 break;
57 }
58 } else if (Band == BAND_ON_5G) {
59 switch (RateSection) {
60 case OFDM:
61 value = pHalData->TxPwrByRateBase5G[RfPath][TxNum][0];
62 break;
63 case HT_MCS0_MCS7:
64 value = pHalData->TxPwrByRateBase5G[RfPath][TxNum][1];
65 break;
66 case HT_MCS8_MCS15:
67 value = pHalData->TxPwrByRateBase5G[RfPath][TxNum][2];
68 break;
69 case HT_MCS16_MCS23:
70 value = pHalData->TxPwrByRateBase5G[RfPath][TxNum][3];
71 break;
72 case HT_MCS24_MCS31:
73 value = pHalData->TxPwrByRateBase5G[RfPath][TxNum][4];
74 break;
75 case VHT_1SSMCS0_1SSMCS9:
76 value = pHalData->TxPwrByRateBase5G[RfPath][TxNum][5];
77 break;
78 case VHT_2SSMCS0_2SSMCS9:
79 value = pHalData->TxPwrByRateBase5G[RfPath][TxNum][6];
80 break;
81 case VHT_3SSMCS0_3SSMCS9:
82 value = pHalData->TxPwrByRateBase5G[RfPath][TxNum][7];
83 break;
84 case VHT_4SSMCS0_4SSMCS9:
85 value = pHalData->TxPwrByRateBase5G[RfPath][TxNum][8];
86 break;
87 default:
88 break;
89 }
90 }
91
92 return value;
93 }
94
95 static void
phy_SetTxPowerByRateBase(struct adapter * Adapter,u8 Band,u8 RfPath,enum rate_section RateSection,u8 TxNum,u8 Value)96 phy_SetTxPowerByRateBase(
97 struct adapter *Adapter,
98 u8 Band,
99 u8 RfPath,
100 enum rate_section RateSection,
101 u8 TxNum,
102 u8 Value
103 )
104 {
105 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
106
107 if (RfPath > ODM_RF_PATH_D)
108 return;
109
110 if (Band == BAND_ON_2_4G) {
111 switch (RateSection) {
112 case CCK:
113 pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][0] = Value;
114 break;
115 case OFDM:
116 pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][1] = Value;
117 break;
118 case HT_MCS0_MCS7:
119 pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][2] = Value;
120 break;
121 case HT_MCS8_MCS15:
122 pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][3] = Value;
123 break;
124 case HT_MCS16_MCS23:
125 pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][4] = Value;
126 break;
127 case HT_MCS24_MCS31:
128 pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][5] = Value;
129 break;
130 case VHT_1SSMCS0_1SSMCS9:
131 pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][6] = Value;
132 break;
133 case VHT_2SSMCS0_2SSMCS9:
134 pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][7] = Value;
135 break;
136 case VHT_3SSMCS0_3SSMCS9:
137 pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][8] = Value;
138 break;
139 case VHT_4SSMCS0_4SSMCS9:
140 pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][9] = Value;
141 break;
142 default:
143 break;
144 }
145 } else if (Band == BAND_ON_5G) {
146 switch (RateSection) {
147 case OFDM:
148 pHalData->TxPwrByRateBase5G[RfPath][TxNum][0] = Value;
149 break;
150 case HT_MCS0_MCS7:
151 pHalData->TxPwrByRateBase5G[RfPath][TxNum][1] = Value;
152 break;
153 case HT_MCS8_MCS15:
154 pHalData->TxPwrByRateBase5G[RfPath][TxNum][2] = Value;
155 break;
156 case HT_MCS16_MCS23:
157 pHalData->TxPwrByRateBase5G[RfPath][TxNum][3] = Value;
158 break;
159 case HT_MCS24_MCS31:
160 pHalData->TxPwrByRateBase5G[RfPath][TxNum][4] = Value;
161 break;
162 case VHT_1SSMCS0_1SSMCS9:
163 pHalData->TxPwrByRateBase5G[RfPath][TxNum][5] = Value;
164 break;
165 case VHT_2SSMCS0_2SSMCS9:
166 pHalData->TxPwrByRateBase5G[RfPath][TxNum][6] = Value;
167 break;
168 case VHT_3SSMCS0_3SSMCS9:
169 pHalData->TxPwrByRateBase5G[RfPath][TxNum][7] = Value;
170 break;
171 case VHT_4SSMCS0_4SSMCS9:
172 pHalData->TxPwrByRateBase5G[RfPath][TxNum][8] = Value;
173 break;
174 default:
175 break;
176 }
177 }
178 }
179
180 static void
phy_StoreTxPowerByRateBase(struct adapter * padapter)181 phy_StoreTxPowerByRateBase(
182 struct adapter *padapter
183 )
184 {
185 u8 path, base;
186
187 for (path = ODM_RF_PATH_A; path <= ODM_RF_PATH_B; ++path) {
188 base = PHY_GetTxPowerByRate(padapter, BAND_ON_2_4G, path, RF_1TX, MGN_11M);
189 phy_SetTxPowerByRateBase(padapter, BAND_ON_2_4G, path, CCK, RF_1TX, base);
190
191 base = PHY_GetTxPowerByRate(padapter, BAND_ON_2_4G, path, RF_1TX, MGN_54M);
192 phy_SetTxPowerByRateBase(padapter, BAND_ON_2_4G, path, OFDM, RF_1TX, base);
193
194 base = PHY_GetTxPowerByRate(padapter, BAND_ON_2_4G, path, RF_1TX, MGN_MCS7);
195 phy_SetTxPowerByRateBase(padapter, BAND_ON_2_4G, path, HT_MCS0_MCS7, RF_1TX, base);
196
197 base = PHY_GetTxPowerByRate(padapter, BAND_ON_2_4G, path, RF_2TX, MGN_MCS15);
198 phy_SetTxPowerByRateBase(padapter, BAND_ON_2_4G, path, HT_MCS8_MCS15, RF_2TX, base);
199
200 base = PHY_GetTxPowerByRate(padapter, BAND_ON_2_4G, path, RF_3TX, MGN_MCS23);
201 phy_SetTxPowerByRateBase(padapter, BAND_ON_2_4G, path, HT_MCS16_MCS23, RF_3TX, base);
202
203 base = PHY_GetTxPowerByRate(padapter, BAND_ON_2_4G, path, RF_1TX, MGN_VHT1SS_MCS7);
204 phy_SetTxPowerByRateBase(padapter, BAND_ON_2_4G, path, VHT_1SSMCS0_1SSMCS9, RF_1TX, base);
205
206 base = PHY_GetTxPowerByRate(padapter, BAND_ON_2_4G, path, RF_2TX, MGN_VHT2SS_MCS7);
207 phy_SetTxPowerByRateBase(padapter, BAND_ON_2_4G, path, VHT_2SSMCS0_2SSMCS9, RF_2TX, base);
208
209 base = PHY_GetTxPowerByRate(padapter, BAND_ON_2_4G, path, RF_3TX, MGN_VHT3SS_MCS7);
210 phy_SetTxPowerByRateBase(padapter, BAND_ON_2_4G, path, VHT_3SSMCS0_3SSMCS9, RF_3TX, base);
211
212 base = PHY_GetTxPowerByRate(padapter, BAND_ON_5G, path, RF_1TX, MGN_54M);
213 phy_SetTxPowerByRateBase(padapter, BAND_ON_5G, path, OFDM, RF_1TX, base);
214
215 base = PHY_GetTxPowerByRate(padapter, BAND_ON_5G, path, RF_1TX, MGN_MCS7);
216 phy_SetTxPowerByRateBase(padapter, BAND_ON_5G, path, HT_MCS0_MCS7, RF_1TX, base);
217
218 base = PHY_GetTxPowerByRate(padapter, BAND_ON_5G, path, RF_2TX, MGN_MCS15);
219 phy_SetTxPowerByRateBase(padapter, BAND_ON_5G, path, HT_MCS8_MCS15, RF_2TX, base);
220
221 base = PHY_GetTxPowerByRate(padapter, BAND_ON_5G, path, RF_3TX, MGN_MCS23);
222 phy_SetTxPowerByRateBase(padapter, BAND_ON_5G, path, HT_MCS16_MCS23, RF_3TX, base);
223
224 base = PHY_GetTxPowerByRate(padapter, BAND_ON_5G, path, RF_1TX, MGN_VHT1SS_MCS7);
225 phy_SetTxPowerByRateBase(padapter, BAND_ON_5G, path, VHT_1SSMCS0_1SSMCS9, RF_1TX, base);
226
227 base = PHY_GetTxPowerByRate(padapter, BAND_ON_5G, path, RF_2TX, MGN_VHT2SS_MCS7);
228 phy_SetTxPowerByRateBase(padapter, BAND_ON_5G, path, VHT_2SSMCS0_2SSMCS9, RF_2TX, base);
229
230 base = PHY_GetTxPowerByRate(padapter, BAND_ON_5G, path, RF_3TX, MGN_VHT2SS_MCS7);
231 phy_SetTxPowerByRateBase(padapter, BAND_ON_5G, path, VHT_3SSMCS0_3SSMCS9, RF_3TX, base);
232 }
233 }
234
PHY_GetRateSectionIndexOfTxPowerByRate(struct adapter * padapter,u32 RegAddr,u32 BitMask)235 u8 PHY_GetRateSectionIndexOfTxPowerByRate(
236 struct adapter *padapter, u32 RegAddr, u32 BitMask
237 )
238 {
239 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
240 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
241 u8 index = 0;
242
243 if (pDM_Odm->PhyRegPgVersion == 0) {
244 switch (RegAddr) {
245 case rTxAGC_A_Rate18_06:
246 index = 0;
247 break;
248 case rTxAGC_A_Rate54_24:
249 index = 1;
250 break;
251 case rTxAGC_A_CCK1_Mcs32:
252 index = 6;
253 break;
254 case rTxAGC_B_CCK11_A_CCK2_11:
255 if (BitMask == bMaskH3Bytes)
256 index = 7;
257 else if (BitMask == 0x000000ff)
258 index = 15;
259 break;
260
261 case rTxAGC_A_Mcs03_Mcs00:
262 index = 2;
263 break;
264 case rTxAGC_A_Mcs07_Mcs04:
265 index = 3;
266 break;
267 case rTxAGC_A_Mcs11_Mcs08:
268 index = 4;
269 break;
270 case rTxAGC_A_Mcs15_Mcs12:
271 index = 5;
272 break;
273 case rTxAGC_B_Rate18_06:
274 index = 8;
275 break;
276 case rTxAGC_B_Rate54_24:
277 index = 9;
278 break;
279 case rTxAGC_B_CCK1_55_Mcs32:
280 index = 14;
281 break;
282 case rTxAGC_B_Mcs03_Mcs00:
283 index = 10;
284 break;
285 case rTxAGC_B_Mcs07_Mcs04:
286 index = 11;
287 break;
288 case rTxAGC_B_Mcs11_Mcs08:
289 index = 12;
290 break;
291 case rTxAGC_B_Mcs15_Mcs12:
292 index = 13;
293 break;
294 default:
295 break;
296 }
297 }
298
299 return index;
300 }
301
302 void
PHY_GetRateValuesOfTxPowerByRate(struct adapter * padapter,u32 RegAddr,u32 BitMask,u32 Value,u8 * RateIndex,s8 * PwrByRateVal,u8 * RateNum)303 PHY_GetRateValuesOfTxPowerByRate(
304 struct adapter *padapter,
305 u32 RegAddr,
306 u32 BitMask,
307 u32 Value,
308 u8 *RateIndex,
309 s8 *PwrByRateVal,
310 u8 *RateNum
311 )
312 {
313 u8 i = 0;
314
315 switch (RegAddr) {
316 case rTxAGC_A_Rate18_06:
317 case rTxAGC_B_Rate18_06:
318 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_6M);
319 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_9M);
320 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_12M);
321 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_18M);
322 for (i = 0; i < 4; ++i) {
323 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
324 ((Value >> (i * 8)) & 0xF));
325 }
326 *RateNum = 4;
327 break;
328
329 case rTxAGC_A_Rate54_24:
330 case rTxAGC_B_Rate54_24:
331 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_24M);
332 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_36M);
333 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_48M);
334 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_54M);
335 for (i = 0; i < 4; ++i) {
336 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
337 ((Value >> (i * 8)) & 0xF));
338 }
339 *RateNum = 4;
340 break;
341
342 case rTxAGC_A_CCK1_Mcs32:
343 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_1M);
344 PwrByRateVal[0] = (s8) ((((Value >> (8 + 4)) & 0xF)) * 10 +
345 ((Value >> 8) & 0xF));
346 *RateNum = 1;
347 break;
348
349 case rTxAGC_B_CCK11_A_CCK2_11:
350 if (BitMask == 0xffffff00) {
351 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_2M);
352 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_5_5M);
353 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_11M);
354 for (i = 1; i < 4; ++i) {
355 PwrByRateVal[i - 1] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
356 ((Value >> (i * 8)) & 0xF));
357 }
358 *RateNum = 3;
359 } else if (BitMask == 0x000000ff) {
360 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_11M);
361 PwrByRateVal[0] = (s8) ((((Value >> 4) & 0xF)) * 10 + (Value & 0xF));
362 *RateNum = 1;
363 }
364 break;
365
366 case rTxAGC_A_Mcs03_Mcs00:
367 case rTxAGC_B_Mcs03_Mcs00:
368 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS0);
369 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS1);
370 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS2);
371 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS3);
372 for (i = 0; i < 4; ++i) {
373 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
374 ((Value >> (i * 8)) & 0xF));
375 }
376 *RateNum = 4;
377 break;
378
379 case rTxAGC_A_Mcs07_Mcs04:
380 case rTxAGC_B_Mcs07_Mcs04:
381 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS4);
382 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS5);
383 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS6);
384 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS7);
385 for (i = 0; i < 4; ++i) {
386 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
387 ((Value >> (i * 8)) & 0xF));
388 }
389 *RateNum = 4;
390 break;
391
392 case rTxAGC_A_Mcs11_Mcs08:
393 case rTxAGC_B_Mcs11_Mcs08:
394 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS8);
395 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS9);
396 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS10);
397 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS11);
398 for (i = 0; i < 4; ++i) {
399 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
400 ((Value >> (i * 8)) & 0xF));
401 }
402 *RateNum = 4;
403 break;
404
405 case rTxAGC_A_Mcs15_Mcs12:
406 case rTxAGC_B_Mcs15_Mcs12:
407 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS12);
408 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS13);
409 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS14);
410 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS15);
411 for (i = 0; i < 4; ++i) {
412 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
413 ((Value >> (i * 8)) & 0xF));
414 }
415 *RateNum = 4;
416
417 break;
418
419 case rTxAGC_B_CCK1_55_Mcs32:
420 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_1M);
421 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_2M);
422 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_5_5M);
423 for (i = 1; i < 4; ++i) {
424 PwrByRateVal[i - 1] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
425 ((Value >> (i * 8)) & 0xF));
426 }
427 *RateNum = 3;
428 break;
429
430 case 0xC20:
431 case 0xE20:
432 case 0x1820:
433 case 0x1a20:
434 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_1M);
435 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_2M);
436 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_5_5M);
437 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_11M);
438 for (i = 0; i < 4; ++i) {
439 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
440 ((Value >> (i * 8)) & 0xF));
441 }
442 *RateNum = 4;
443 break;
444
445 case 0xC24:
446 case 0xE24:
447 case 0x1824:
448 case 0x1a24:
449 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_6M);
450 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_9M);
451 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_12M);
452 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_18M);
453 for (i = 0; i < 4; ++i) {
454 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
455 ((Value >> (i * 8)) & 0xF));
456 }
457 *RateNum = 4;
458 break;
459
460 case 0xC28:
461 case 0xE28:
462 case 0x1828:
463 case 0x1a28:
464 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_24M);
465 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_36M);
466 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_48M);
467 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_54M);
468 for (i = 0; i < 4; ++i) {
469 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
470 ((Value >> (i * 8)) & 0xF));
471 }
472 *RateNum = 4;
473 break;
474
475 case 0xC2C:
476 case 0xE2C:
477 case 0x182C:
478 case 0x1a2C:
479 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS0);
480 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS1);
481 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS2);
482 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS3);
483 for (i = 0; i < 4; ++i) {
484 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
485 ((Value >> (i * 8)) & 0xF));
486 }
487 *RateNum = 4;
488 break;
489
490 case 0xC30:
491 case 0xE30:
492 case 0x1830:
493 case 0x1a30:
494 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS4);
495 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS5);
496 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS6);
497 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS7);
498 for (i = 0; i < 4; ++i) {
499 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
500 ((Value >> (i * 8)) & 0xF));
501 }
502 *RateNum = 4;
503 break;
504
505 case 0xC34:
506 case 0xE34:
507 case 0x1834:
508 case 0x1a34:
509 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS8);
510 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS9);
511 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS10);
512 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS11);
513 for (i = 0; i < 4; ++i) {
514 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
515 ((Value >> (i * 8)) & 0xF));
516 }
517 *RateNum = 4;
518 break;
519
520 case 0xC38:
521 case 0xE38:
522 case 0x1838:
523 case 0x1a38:
524 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS12);
525 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS13);
526 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS14);
527 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS15);
528 for (i = 0; i < 4; ++i) {
529 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
530 ((Value >> (i * 8)) & 0xF));
531 }
532 *RateNum = 4;
533 break;
534
535 case 0xC3C:
536 case 0xE3C:
537 case 0x183C:
538 case 0x1a3C:
539 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_VHT1SS_MCS0);
540 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_VHT1SS_MCS1);
541 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_VHT1SS_MCS2);
542 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_VHT1SS_MCS3);
543 for (i = 0; i < 4; ++i) {
544 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
545 ((Value >> (i * 8)) & 0xF));
546 }
547 *RateNum = 4;
548 break;
549
550 case 0xC40:
551 case 0xE40:
552 case 0x1840:
553 case 0x1a40:
554 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_VHT1SS_MCS4);
555 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_VHT1SS_MCS5);
556 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_VHT1SS_MCS6);
557 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_VHT1SS_MCS7);
558 for (i = 0; i < 4; ++i) {
559 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
560 ((Value >> (i * 8)) & 0xF));
561 }
562 *RateNum = 4;
563 break;
564
565 case 0xC44:
566 case 0xE44:
567 case 0x1844:
568 case 0x1a44:
569 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_VHT1SS_MCS8);
570 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_VHT1SS_MCS9);
571 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_VHT2SS_MCS0);
572 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_VHT2SS_MCS1);
573 for (i = 0; i < 4; ++i) {
574 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
575 ((Value >> (i * 8)) & 0xF));
576 }
577 *RateNum = 4;
578 break;
579
580 case 0xC48:
581 case 0xE48:
582 case 0x1848:
583 case 0x1a48:
584 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_VHT2SS_MCS2);
585 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_VHT2SS_MCS3);
586 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_VHT2SS_MCS4);
587 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_VHT2SS_MCS5);
588 for (i = 0; i < 4; ++i) {
589 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
590 ((Value >> (i * 8)) & 0xF));
591 }
592 *RateNum = 4;
593 break;
594
595 case 0xC4C:
596 case 0xE4C:
597 case 0x184C:
598 case 0x1a4C:
599 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_VHT2SS_MCS6);
600 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_VHT2SS_MCS7);
601 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_VHT2SS_MCS8);
602 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_VHT2SS_MCS9);
603 for (i = 0; i < 4; ++i) {
604 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
605 ((Value >> (i * 8)) & 0xF));
606 }
607 *RateNum = 4;
608 break;
609
610 case 0xCD8:
611 case 0xED8:
612 case 0x18D8:
613 case 0x1aD8:
614 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS16);
615 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS17);
616 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS18);
617 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS19);
618 for (i = 0; i < 4; ++i) {
619 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
620 ((Value >> (i * 8)) & 0xF));
621 }
622 *RateNum = 4;
623 break;
624
625 case 0xCDC:
626 case 0xEDC:
627 case 0x18DC:
628 case 0x1aDC:
629 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS20);
630 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS21);
631 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS22);
632 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS23);
633 for (i = 0; i < 4; ++i) {
634 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
635 ((Value >> (i * 8)) & 0xF));
636 }
637 *RateNum = 4;
638 break;
639
640 case 0xCE0:
641 case 0xEE0:
642 case 0x18E0:
643 case 0x1aE0:
644 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_VHT3SS_MCS0);
645 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_VHT3SS_MCS1);
646 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_VHT3SS_MCS2);
647 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_VHT3SS_MCS3);
648 for (i = 0; i < 4; ++i) {
649 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
650 ((Value >> (i * 8)) & 0xF));
651 }
652 *RateNum = 4;
653 break;
654
655 case 0xCE4:
656 case 0xEE4:
657 case 0x18E4:
658 case 0x1aE4:
659 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_VHT3SS_MCS4);
660 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_VHT3SS_MCS5);
661 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_VHT3SS_MCS6);
662 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_VHT3SS_MCS7);
663 for (i = 0; i < 4; ++i) {
664 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
665 ((Value >> (i * 8)) & 0xF));
666 }
667 *RateNum = 4;
668 break;
669
670 case 0xCE8:
671 case 0xEE8:
672 case 0x18E8:
673 case 0x1aE8:
674 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_VHT3SS_MCS8);
675 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_VHT3SS_MCS9);
676 for (i = 0; i < 2; ++i) {
677 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 +
678 ((Value >> (i * 8)) & 0xF));
679 }
680 *RateNum = 4;
681 break;
682
683 default:
684 break;
685 }
686 }
687
PHY_StoreTxPowerByRateNew(struct adapter * padapter,u32 Band,u32 RfPath,u32 TxNum,u32 RegAddr,u32 BitMask,u32 Data)688 static void PHY_StoreTxPowerByRateNew(
689 struct adapter *padapter,
690 u32 Band,
691 u32 RfPath,
692 u32 TxNum,
693 u32 RegAddr,
694 u32 BitMask,
695 u32 Data
696 )
697 {
698 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
699 u8 i = 0, rateIndex[4] = {0}, rateNum = 0;
700 s8 PwrByRateVal[4] = {0};
701
702 PHY_GetRateValuesOfTxPowerByRate(padapter, RegAddr, BitMask, Data, rateIndex, PwrByRateVal, &rateNum);
703
704 if (Band != BAND_ON_2_4G && Band != BAND_ON_5G)
705 return;
706
707 if (RfPath > ODM_RF_PATH_D)
708 return;
709
710 if (TxNum > ODM_RF_PATH_D)
711 return;
712
713 for (i = 0; i < rateNum; ++i) {
714 if (rateIndex[i] == PHY_GetRateIndexOfTxPowerByRate(MGN_VHT2SS_MCS0) ||
715 rateIndex[i] == PHY_GetRateIndexOfTxPowerByRate(MGN_VHT2SS_MCS1))
716 TxNum = RF_2TX;
717
718 pHalData->TxPwrByRateOffset[Band][RfPath][TxNum][rateIndex[i]] = PwrByRateVal[i];
719 }
720 }
721
PHY_StoreTxPowerByRateOld(struct adapter * padapter,u32 RegAddr,u32 BitMask,u32 Data)722 static void PHY_StoreTxPowerByRateOld(
723 struct adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data
724 )
725 {
726 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
727 u8 index = PHY_GetRateSectionIndexOfTxPowerByRate(padapter, RegAddr, BitMask);
728
729 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][index] = Data;
730 }
731
PHY_InitTxPowerByRate(struct adapter * padapter)732 void PHY_InitTxPowerByRate(struct adapter *padapter)
733 {
734 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
735 u8 band, rfPath, TxNum, rate;
736
737 for (band = BAND_ON_2_4G; band <= BAND_ON_5G; ++band)
738 for (rfPath = 0; rfPath < TX_PWR_BY_RATE_NUM_RF; ++rfPath)
739 for (TxNum = 0; TxNum < TX_PWR_BY_RATE_NUM_RF; ++TxNum)
740 for (rate = 0; rate < TX_PWR_BY_RATE_NUM_RATE; ++rate)
741 pHalData->TxPwrByRateOffset[band][rfPath][TxNum][rate] = 0;
742 }
743
PHY_StoreTxPowerByRate(struct adapter * padapter,u32 Band,u32 RfPath,u32 TxNum,u32 RegAddr,u32 BitMask,u32 Data)744 void PHY_StoreTxPowerByRate(
745 struct adapter *padapter,
746 u32 Band,
747 u32 RfPath,
748 u32 TxNum,
749 u32 RegAddr,
750 u32 BitMask,
751 u32 Data
752 )
753 {
754 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
755 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
756
757 if (pDM_Odm->PhyRegPgVersion > 0)
758 PHY_StoreTxPowerByRateNew(padapter, Band, RfPath, TxNum, RegAddr, BitMask, Data);
759 else if (pDM_Odm->PhyRegPgVersion == 0) {
760 PHY_StoreTxPowerByRateOld(padapter, RegAddr, BitMask, Data);
761
762 if (RegAddr == rTxAGC_A_Mcs15_Mcs12 && pHalData->rf_type == RF_1T1R)
763 pHalData->pwrGroupCnt++;
764 else if (RegAddr == rTxAGC_B_Mcs15_Mcs12 && pHalData->rf_type != RF_1T1R)
765 pHalData->pwrGroupCnt++;
766 }
767 }
768
769 static void
phy_ConvertTxPowerByRateInDbmToRelativeValues(struct adapter * padapter)770 phy_ConvertTxPowerByRateInDbmToRelativeValues(
771 struct adapter *padapter
772 )
773 {
774 u8 base = 0, i = 0, value = 0, band = 0, path = 0, txNum = 0;
775 u8 cckRates[4] = {
776 MGN_1M, MGN_2M, MGN_5_5M, MGN_11M
777 };
778 u8 ofdmRates[8] = {
779 MGN_6M, MGN_9M, MGN_12M, MGN_18M, MGN_24M, MGN_36M, MGN_48M, MGN_54M
780 };
781 u8 mcs0_7Rates[8] = {
782 MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7
783 };
784 u8 mcs8_15Rates[8] = {
785 MGN_MCS8, MGN_MCS9, MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14, MGN_MCS15
786 };
787 u8 mcs16_23Rates[8] = {
788 MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19, MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23
789 };
790 u8 vht1ssRates[10] = {
791 MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3, MGN_VHT1SS_MCS4,
792 MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7, MGN_VHT1SS_MCS8, MGN_VHT1SS_MCS9
793 };
794 u8 vht2ssRates[10] = {
795 MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1, MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4,
796 MGN_VHT2SS_MCS5, MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9
797 };
798 u8 vht3ssRates[10] = {
799 MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3, MGN_VHT3SS_MCS4,
800 MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7, MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9
801 };
802
803 for (band = BAND_ON_2_4G; band <= BAND_ON_5G; ++band) {
804 for (path = ODM_RF_PATH_A; path <= ODM_RF_PATH_D; ++path) {
805 for (txNum = RF_1TX; txNum < RF_MAX_TX_NUM; ++txNum) {
806 /* CCK */
807 base = PHY_GetTxPowerByRate(padapter, band, path, txNum, MGN_11M);
808 for (i = 0; i < ARRAY_SIZE(cckRates); ++i) {
809 value = PHY_GetTxPowerByRate(padapter, band, path, txNum, cckRates[i]);
810 PHY_SetTxPowerByRate(padapter, band, path, txNum, cckRates[i], value - base);
811 }
812
813 /* OFDM */
814 base = PHY_GetTxPowerByRate(padapter, band, path, txNum, MGN_54M);
815 for (i = 0; i < sizeof(ofdmRates); ++i) {
816 value = PHY_GetTxPowerByRate(padapter, band, path, txNum, ofdmRates[i]);
817 PHY_SetTxPowerByRate(padapter, band, path, txNum, ofdmRates[i], value - base);
818 }
819
820 /* HT MCS0~7 */
821 base = PHY_GetTxPowerByRate(padapter, band, path, txNum, MGN_MCS7);
822 for (i = 0; i < sizeof(mcs0_7Rates); ++i) {
823 value = PHY_GetTxPowerByRate(padapter, band, path, txNum, mcs0_7Rates[i]);
824 PHY_SetTxPowerByRate(padapter, band, path, txNum, mcs0_7Rates[i], value - base);
825 }
826
827 /* HT MCS8~15 */
828 base = PHY_GetTxPowerByRate(padapter, band, path, txNum, MGN_MCS15);
829 for (i = 0; i < sizeof(mcs8_15Rates); ++i) {
830 value = PHY_GetTxPowerByRate(padapter, band, path, txNum, mcs8_15Rates[i]);
831 PHY_SetTxPowerByRate(padapter, band, path, txNum, mcs8_15Rates[i], value - base);
832 }
833
834 /* HT MCS16~23 */
835 base = PHY_GetTxPowerByRate(padapter, band, path, txNum, MGN_MCS23);
836 for (i = 0; i < sizeof(mcs16_23Rates); ++i) {
837 value = PHY_GetTxPowerByRate(padapter, band, path, txNum, mcs16_23Rates[i]);
838 PHY_SetTxPowerByRate(padapter, band, path, txNum, mcs16_23Rates[i], value - base);
839 }
840
841 /* VHT 1SS */
842 base = PHY_GetTxPowerByRate(padapter, band, path, txNum, MGN_VHT1SS_MCS7);
843 for (i = 0; i < sizeof(vht1ssRates); ++i) {
844 value = PHY_GetTxPowerByRate(padapter, band, path, txNum, vht1ssRates[i]);
845 PHY_SetTxPowerByRate(padapter, band, path, txNum, vht1ssRates[i], value - base);
846 }
847
848 /* VHT 2SS */
849 base = PHY_GetTxPowerByRate(padapter, band, path, txNum, MGN_VHT2SS_MCS7);
850 for (i = 0; i < sizeof(vht2ssRates); ++i) {
851 value = PHY_GetTxPowerByRate(padapter, band, path, txNum, vht2ssRates[i]);
852 PHY_SetTxPowerByRate(padapter, band, path, txNum, vht2ssRates[i], value - base);
853 }
854
855 /* VHT 3SS */
856 base = PHY_GetTxPowerByRate(padapter, band, path, txNum, MGN_VHT3SS_MCS7);
857 for (i = 0; i < sizeof(vht3ssRates); ++i) {
858 value = PHY_GetTxPowerByRate(padapter, band, path, txNum, vht3ssRates[i]);
859 PHY_SetTxPowerByRate(padapter, band, path, txNum, vht3ssRates[i], value - base);
860 }
861 }
862 }
863 }
864 }
865
866 /*
867 * This function must be called if the value in the PHY_REG_PG.txt(or header)
868 * is exact dBm values
869 */
PHY_TxPowerByRateConfiguration(struct adapter * padapter)870 void PHY_TxPowerByRateConfiguration(struct adapter *padapter)
871 {
872 phy_StoreTxPowerByRateBase(padapter);
873 phy_ConvertTxPowerByRateInDbmToRelativeValues(padapter);
874 }
875
PHY_SetTxPowerIndexByRateSection(struct adapter * padapter,u8 RFPath,u8 Channel,u8 RateSection)876 void PHY_SetTxPowerIndexByRateSection(
877 struct adapter *padapter, u8 RFPath, u8 Channel, u8 RateSection
878 )
879 {
880 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
881
882 if (RateSection == CCK) {
883 u8 cckRates[] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M};
884 if (pHalData->CurrentBandType == BAND_ON_2_4G)
885 PHY_SetTxPowerIndexByRateArray(padapter, RFPath,
886 pHalData->CurrentChannelBW,
887 Channel, cckRates,
888 ARRAY_SIZE(cckRates));
889
890 } else if (RateSection == OFDM) {
891 u8 ofdmRates[] = {MGN_6M, MGN_9M, MGN_12M, MGN_18M, MGN_24M, MGN_36M, MGN_48M, MGN_54M};
892 PHY_SetTxPowerIndexByRateArray(padapter, RFPath,
893 pHalData->CurrentChannelBW,
894 Channel, ofdmRates,
895 ARRAY_SIZE(ofdmRates));
896
897 } else if (RateSection == HT_MCS0_MCS7) {
898 u8 htRates1T[] = {MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7};
899 PHY_SetTxPowerIndexByRateArray(padapter, RFPath,
900 pHalData->CurrentChannelBW,
901 Channel, htRates1T,
902 ARRAY_SIZE(htRates1T));
903
904 } else if (RateSection == HT_MCS8_MCS15) {
905 u8 htRates2T[] = {MGN_MCS8, MGN_MCS9, MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14, MGN_MCS15};
906 PHY_SetTxPowerIndexByRateArray(padapter, RFPath,
907 pHalData->CurrentChannelBW,
908 Channel, htRates2T,
909 ARRAY_SIZE(htRates2T));
910
911 } else if (RateSection == HT_MCS16_MCS23) {
912 u8 htRates3T[] = {MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19, MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23};
913 PHY_SetTxPowerIndexByRateArray(padapter, RFPath,
914 pHalData->CurrentChannelBW,
915 Channel, htRates3T,
916 ARRAY_SIZE(htRates3T));
917
918 } else if (RateSection == HT_MCS24_MCS31) {
919 u8 htRates4T[] = {MGN_MCS24, MGN_MCS25, MGN_MCS26, MGN_MCS27, MGN_MCS28, MGN_MCS29, MGN_MCS30, MGN_MCS31};
920 PHY_SetTxPowerIndexByRateArray(padapter, RFPath,
921 pHalData->CurrentChannelBW,
922 Channel, htRates4T,
923 ARRAY_SIZE(htRates4T));
924
925 } else if (RateSection == VHT_1SSMCS0_1SSMCS9) {
926 u8 vhtRates1T[] = {MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3, MGN_VHT1SS_MCS4,
927 MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7, MGN_VHT1SS_MCS8, MGN_VHT1SS_MCS9};
928 PHY_SetTxPowerIndexByRateArray(padapter, RFPath,
929 pHalData->CurrentChannelBW,
930 Channel, vhtRates1T,
931 ARRAY_SIZE(vhtRates1T));
932
933 } else if (RateSection == VHT_2SSMCS0_2SSMCS9) {
934 u8 vhtRates2T[] = {MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1, MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4,
935 MGN_VHT2SS_MCS5, MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9};
936
937 PHY_SetTxPowerIndexByRateArray(padapter, RFPath,
938 pHalData->CurrentChannelBW,
939 Channel, vhtRates2T,
940 ARRAY_SIZE(vhtRates2T));
941 } else if (RateSection == VHT_3SSMCS0_3SSMCS9) {
942 u8 vhtRates3T[] = {MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3, MGN_VHT3SS_MCS4,
943 MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7, MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9};
944
945 PHY_SetTxPowerIndexByRateArray(padapter, RFPath,
946 pHalData->CurrentChannelBW,
947 Channel, vhtRates3T,
948 ARRAY_SIZE(vhtRates3T));
949 } else if (RateSection == VHT_4SSMCS0_4SSMCS9) {
950 u8 vhtRates4T[] = {MGN_VHT4SS_MCS0, MGN_VHT4SS_MCS1, MGN_VHT4SS_MCS2, MGN_VHT4SS_MCS3, MGN_VHT4SS_MCS4,
951 MGN_VHT4SS_MCS5, MGN_VHT4SS_MCS6, MGN_VHT4SS_MCS7, MGN_VHT4SS_MCS8, MGN_VHT4SS_MCS9};
952
953 PHY_SetTxPowerIndexByRateArray(padapter, RFPath,
954 pHalData->CurrentChannelBW,
955 Channel, vhtRates4T,
956 ARRAY_SIZE(vhtRates4T));
957 }
958 }
959
phy_GetChnlIndex(u8 Channel,u8 * ChannelIdx)960 static bool phy_GetChnlIndex(u8 Channel, u8 *ChannelIdx)
961 {
962 u8 channel5G[CHANNEL_MAX_NUMBER_5G] = {
963 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 100, 102,
964 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130,
965 132, 134, 136, 138, 140, 142, 144, 149, 151, 153, 155, 157, 159, 161,
966 163, 165, 167, 168, 169, 171, 173, 175, 177
967 };
968 u8 i = 0;
969 bool bIn24G = true;
970
971 if (Channel <= 14) {
972 bIn24G = true;
973 *ChannelIdx = Channel-1;
974 } else {
975 bIn24G = false;
976
977 for (i = 0; i < ARRAY_SIZE(channel5G); ++i) {
978 if (channel5G[i] == Channel) {
979 *ChannelIdx = i;
980 return bIn24G;
981 }
982 }
983 }
984
985 return bIn24G;
986 }
987
PHY_GetTxPowerIndexBase(struct adapter * padapter,u8 RFPath,u8 Rate,enum channel_width BandWidth,u8 Channel,bool * bIn24G)988 u8 PHY_GetTxPowerIndexBase(
989 struct adapter *padapter,
990 u8 RFPath,
991 u8 Rate,
992 enum channel_width BandWidth,
993 u8 Channel,
994 bool *bIn24G
995 )
996 {
997 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
998 u8 i = 0; /* default set to 1S */
999 u8 txPower = 0;
1000 u8 chnlIdx = (Channel-1);
1001
1002 if (HAL_IsLegalChannel(padapter, Channel) == false)
1003 chnlIdx = 0;
1004
1005 *bIn24G = phy_GetChnlIndex(Channel, &chnlIdx);
1006
1007 if (*bIn24G) { /* 3 ============================== 2.4 G ============================== */
1008 if (IS_CCK_RATE(Rate))
1009 txPower = pHalData->Index24G_CCK_Base[RFPath][chnlIdx];
1010 else if (MGN_6M <= Rate)
1011 txPower = pHalData->Index24G_BW40_Base[RFPath][chnlIdx];
1012
1013 /* OFDM-1T */
1014 if ((MGN_6M <= Rate && Rate <= MGN_54M) && !IS_CCK_RATE(Rate))
1015 txPower += pHalData->OFDM_24G_Diff[RFPath][TX_1S];
1016
1017 if (BandWidth == CHANNEL_WIDTH_20) { /* BW20-1S, BW20-2S */
1018 if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
1019 txPower += pHalData->BW20_24G_Diff[RFPath][TX_1S];
1020 if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
1021 txPower += pHalData->BW20_24G_Diff[RFPath][TX_2S];
1022 if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
1023 txPower += pHalData->BW20_24G_Diff[RFPath][TX_3S];
1024 if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
1025 txPower += pHalData->BW20_24G_Diff[RFPath][TX_4S];
1026
1027 } else if (BandWidth == CHANNEL_WIDTH_40) { /* BW40-1S, BW40-2S */
1028 if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
1029 txPower += pHalData->BW40_24G_Diff[RFPath][TX_1S];
1030 if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
1031 txPower += pHalData->BW40_24G_Diff[RFPath][TX_2S];
1032 if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
1033 txPower += pHalData->BW40_24G_Diff[RFPath][TX_3S];
1034 if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
1035 txPower += pHalData->BW40_24G_Diff[RFPath][TX_4S];
1036
1037 }
1038 /* Willis suggest adopt BW 40M power index while in BW 80 mode */
1039 else if (BandWidth == CHANNEL_WIDTH_80) {
1040 if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
1041 txPower += pHalData->BW40_24G_Diff[RFPath][TX_1S];
1042 if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
1043 txPower += pHalData->BW40_24G_Diff[RFPath][TX_2S];
1044 if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
1045 txPower += pHalData->BW40_24G_Diff[RFPath][TX_3S];
1046 if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
1047 txPower += pHalData->BW40_24G_Diff[RFPath][TX_4S];
1048
1049 }
1050 } else {/* 3 ============================== 5 G ============================== */
1051 if (MGN_6M <= Rate)
1052 txPower = pHalData->Index5G_BW40_Base[RFPath][chnlIdx];
1053
1054 /* OFDM-1T */
1055 if ((MGN_6M <= Rate && Rate <= MGN_54M) && !IS_CCK_RATE(Rate))
1056 txPower += pHalData->OFDM_5G_Diff[RFPath][TX_1S];
1057
1058 /* BW20-1S, BW20-2S */
1059 if (BandWidth == CHANNEL_WIDTH_20) {
1060 if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
1061 txPower += pHalData->BW20_5G_Diff[RFPath][TX_1S];
1062 if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
1063 txPower += pHalData->BW20_5G_Diff[RFPath][TX_2S];
1064 if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
1065 txPower += pHalData->BW20_5G_Diff[RFPath][TX_3S];
1066 if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
1067 txPower += pHalData->BW20_5G_Diff[RFPath][TX_4S];
1068
1069 } else if (BandWidth == CHANNEL_WIDTH_40) { /* BW40-1S, BW40-2S */
1070 if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
1071 txPower += pHalData->BW40_5G_Diff[RFPath][TX_1S];
1072 if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
1073 txPower += pHalData->BW40_5G_Diff[RFPath][TX_2S];
1074 if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
1075 txPower += pHalData->BW40_5G_Diff[RFPath][TX_3S];
1076 if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
1077 txPower += pHalData->BW40_5G_Diff[RFPath][TX_4S];
1078
1079 } else if (BandWidth == CHANNEL_WIDTH_80) { /* BW80-1S, BW80-2S */
1080 /* <20121220, Kordan> Get the index of array "Index5G_BW80_Base". */
1081 u8 channel5G_80M[CHANNEL_MAX_NUMBER_5G_80M] = {42, 58, 106, 122, 138, 155, 171};
1082 for (i = 0; i < ARRAY_SIZE(channel5G_80M); ++i)
1083 if (channel5G_80M[i] == Channel)
1084 chnlIdx = i;
1085
1086 txPower = pHalData->Index5G_BW80_Base[RFPath][chnlIdx];
1087
1088 if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
1089 txPower += + pHalData->BW80_5G_Diff[RFPath][TX_1S];
1090 if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
1091 txPower += pHalData->BW80_5G_Diff[RFPath][TX_2S];
1092 if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
1093 txPower += pHalData->BW80_5G_Diff[RFPath][TX_3S];
1094 if ((MGN_MCS23 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9))
1095 txPower += pHalData->BW80_5G_Diff[RFPath][TX_4S];
1096 }
1097 }
1098
1099 return txPower;
1100 }
1101
PHY_GetTxPowerTrackingOffset(struct adapter * padapter,u8 RFPath,u8 Rate)1102 s8 PHY_GetTxPowerTrackingOffset(struct adapter *padapter, u8 RFPath, u8 Rate)
1103 {
1104 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1105 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
1106 s8 offset = 0;
1107
1108 if (pDM_Odm->RFCalibrateInfo.TxPowerTrackControl == false)
1109 return offset;
1110
1111 if ((Rate == MGN_1M) || (Rate == MGN_2M) || (Rate == MGN_5_5M) || (Rate == MGN_11M))
1112 offset = pDM_Odm->Remnant_CCKSwingIdx;
1113 else
1114 offset = pDM_Odm->Remnant_OFDMSwingIdx[RFPath];
1115
1116 return offset;
1117 }
1118
PHY_GetRateIndexOfTxPowerByRate(u8 Rate)1119 u8 PHY_GetRateIndexOfTxPowerByRate(u8 Rate)
1120 {
1121 u8 index = 0;
1122 switch (Rate) {
1123 case MGN_1M:
1124 index = 0;
1125 break;
1126 case MGN_2M:
1127 index = 1;
1128 break;
1129 case MGN_5_5M:
1130 index = 2;
1131 break;
1132 case MGN_11M:
1133 index = 3;
1134 break;
1135 case MGN_6M:
1136 index = 4;
1137 break;
1138 case MGN_9M:
1139 index = 5;
1140 break;
1141 case MGN_12M:
1142 index = 6;
1143 break;
1144 case MGN_18M:
1145 index = 7;
1146 break;
1147 case MGN_24M:
1148 index = 8;
1149 break;
1150 case MGN_36M:
1151 index = 9;
1152 break;
1153 case MGN_48M:
1154 index = 10;
1155 break;
1156 case MGN_54M:
1157 index = 11;
1158 break;
1159 case MGN_MCS0:
1160 index = 12;
1161 break;
1162 case MGN_MCS1:
1163 index = 13;
1164 break;
1165 case MGN_MCS2:
1166 index = 14;
1167 break;
1168 case MGN_MCS3:
1169 index = 15;
1170 break;
1171 case MGN_MCS4:
1172 index = 16;
1173 break;
1174 case MGN_MCS5:
1175 index = 17;
1176 break;
1177 case MGN_MCS6:
1178 index = 18;
1179 break;
1180 case MGN_MCS7:
1181 index = 19;
1182 break;
1183 case MGN_MCS8:
1184 index = 20;
1185 break;
1186 case MGN_MCS9:
1187 index = 21;
1188 break;
1189 case MGN_MCS10:
1190 index = 22;
1191 break;
1192 case MGN_MCS11:
1193 index = 23;
1194 break;
1195 case MGN_MCS12:
1196 index = 24;
1197 break;
1198 case MGN_MCS13:
1199 index = 25;
1200 break;
1201 case MGN_MCS14:
1202 index = 26;
1203 break;
1204 case MGN_MCS15:
1205 index = 27;
1206 break;
1207 case MGN_MCS16:
1208 index = 28;
1209 break;
1210 case MGN_MCS17:
1211 index = 29;
1212 break;
1213 case MGN_MCS18:
1214 index = 30;
1215 break;
1216 case MGN_MCS19:
1217 index = 31;
1218 break;
1219 case MGN_MCS20:
1220 index = 32;
1221 break;
1222 case MGN_MCS21:
1223 index = 33;
1224 break;
1225 case MGN_MCS22:
1226 index = 34;
1227 break;
1228 case MGN_MCS23:
1229 index = 35;
1230 break;
1231 case MGN_MCS24:
1232 index = 36;
1233 break;
1234 case MGN_MCS25:
1235 index = 37;
1236 break;
1237 case MGN_MCS26:
1238 index = 38;
1239 break;
1240 case MGN_MCS27:
1241 index = 39;
1242 break;
1243 case MGN_MCS28:
1244 index = 40;
1245 break;
1246 case MGN_MCS29:
1247 index = 41;
1248 break;
1249 case MGN_MCS30:
1250 index = 42;
1251 break;
1252 case MGN_MCS31:
1253 index = 43;
1254 break;
1255 case MGN_VHT1SS_MCS0:
1256 index = 44;
1257 break;
1258 case MGN_VHT1SS_MCS1:
1259 index = 45;
1260 break;
1261 case MGN_VHT1SS_MCS2:
1262 index = 46;
1263 break;
1264 case MGN_VHT1SS_MCS3:
1265 index = 47;
1266 break;
1267 case MGN_VHT1SS_MCS4:
1268 index = 48;
1269 break;
1270 case MGN_VHT1SS_MCS5:
1271 index = 49;
1272 break;
1273 case MGN_VHT1SS_MCS6:
1274 index = 50;
1275 break;
1276 case MGN_VHT1SS_MCS7:
1277 index = 51;
1278 break;
1279 case MGN_VHT1SS_MCS8:
1280 index = 52;
1281 break;
1282 case MGN_VHT1SS_MCS9:
1283 index = 53;
1284 break;
1285 case MGN_VHT2SS_MCS0:
1286 index = 54;
1287 break;
1288 case MGN_VHT2SS_MCS1:
1289 index = 55;
1290 break;
1291 case MGN_VHT2SS_MCS2:
1292 index = 56;
1293 break;
1294 case MGN_VHT2SS_MCS3:
1295 index = 57;
1296 break;
1297 case MGN_VHT2SS_MCS4:
1298 index = 58;
1299 break;
1300 case MGN_VHT2SS_MCS5:
1301 index = 59;
1302 break;
1303 case MGN_VHT2SS_MCS6:
1304 index = 60;
1305 break;
1306 case MGN_VHT2SS_MCS7:
1307 index = 61;
1308 break;
1309 case MGN_VHT2SS_MCS8:
1310 index = 62;
1311 break;
1312 case MGN_VHT2SS_MCS9:
1313 index = 63;
1314 break;
1315 case MGN_VHT3SS_MCS0:
1316 index = 64;
1317 break;
1318 case MGN_VHT3SS_MCS1:
1319 index = 65;
1320 break;
1321 case MGN_VHT3SS_MCS2:
1322 index = 66;
1323 break;
1324 case MGN_VHT3SS_MCS3:
1325 index = 67;
1326 break;
1327 case MGN_VHT3SS_MCS4:
1328 index = 68;
1329 break;
1330 case MGN_VHT3SS_MCS5:
1331 index = 69;
1332 break;
1333 case MGN_VHT3SS_MCS6:
1334 index = 70;
1335 break;
1336 case MGN_VHT3SS_MCS7:
1337 index = 71;
1338 break;
1339 case MGN_VHT3SS_MCS8:
1340 index = 72;
1341 break;
1342 case MGN_VHT3SS_MCS9:
1343 index = 73;
1344 break;
1345 case MGN_VHT4SS_MCS0:
1346 index = 74;
1347 break;
1348 case MGN_VHT4SS_MCS1:
1349 index = 75;
1350 break;
1351 case MGN_VHT4SS_MCS2:
1352 index = 76;
1353 break;
1354 case MGN_VHT4SS_MCS3:
1355 index = 77;
1356 break;
1357 case MGN_VHT4SS_MCS4:
1358 index = 78;
1359 break;
1360 case MGN_VHT4SS_MCS5:
1361 index = 79;
1362 break;
1363 case MGN_VHT4SS_MCS6:
1364 index = 80;
1365 break;
1366 case MGN_VHT4SS_MCS7:
1367 index = 81;
1368 break;
1369 case MGN_VHT4SS_MCS8:
1370 index = 82;
1371 break;
1372 case MGN_VHT4SS_MCS9:
1373 index = 83;
1374 break;
1375 default:
1376 break;
1377 }
1378 return index;
1379 }
1380
PHY_GetTxPowerByRate(struct adapter * padapter,u8 Band,u8 RFPath,u8 TxNum,u8 Rate)1381 s8 PHY_GetTxPowerByRate(
1382 struct adapter *padapter, u8 Band, u8 RFPath, u8 TxNum, u8 Rate
1383 )
1384 {
1385 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1386 s8 value = 0;
1387 u8 rateIndex = PHY_GetRateIndexOfTxPowerByRate(Rate);
1388
1389 if ((padapter->registrypriv.RegEnableTxPowerByRate == 2 && pHalData->EEPROMRegulatory == 2) ||
1390 padapter->registrypriv.RegEnableTxPowerByRate == 0)
1391 return 0;
1392
1393 if (Band != BAND_ON_2_4G && Band != BAND_ON_5G)
1394 return value;
1395
1396 if (RFPath > ODM_RF_PATH_D)
1397 return value;
1398
1399 if (TxNum >= RF_MAX_TX_NUM)
1400 return value;
1401
1402 if (rateIndex >= TX_PWR_BY_RATE_NUM_RATE)
1403 return value;
1404
1405 return pHalData->TxPwrByRateOffset[Band][RFPath][TxNum][rateIndex];
1406
1407 }
1408
PHY_SetTxPowerByRate(struct adapter * padapter,u8 Band,u8 RFPath,u8 TxNum,u8 Rate,s8 Value)1409 void PHY_SetTxPowerByRate(
1410 struct adapter *padapter,
1411 u8 Band,
1412 u8 RFPath,
1413 u8 TxNum,
1414 u8 Rate,
1415 s8 Value
1416 )
1417 {
1418 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1419 u8 rateIndex = PHY_GetRateIndexOfTxPowerByRate(Rate);
1420
1421 if (Band != BAND_ON_2_4G && Band != BAND_ON_5G)
1422 return;
1423
1424 if (RFPath > ODM_RF_PATH_D)
1425 return;
1426
1427 if (TxNum >= RF_MAX_TX_NUM)
1428 return;
1429
1430 if (rateIndex >= TX_PWR_BY_RATE_NUM_RATE)
1431 return;
1432
1433 pHalData->TxPwrByRateOffset[Band][RFPath][TxNum][rateIndex] = Value;
1434 }
1435
PHY_SetTxPowerLevelByPath(struct adapter * Adapter,u8 channel,u8 path)1436 void PHY_SetTxPowerLevelByPath(struct adapter *Adapter, u8 channel, u8 path)
1437 {
1438 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
1439 bool bIsIn24G = (pHalData->CurrentBandType == BAND_ON_2_4G);
1440
1441 /* if (pMgntInfo->RegNByteAccess == 0) */
1442 {
1443 if (bIsIn24G)
1444 PHY_SetTxPowerIndexByRateSection(Adapter, path, channel, CCK);
1445
1446 PHY_SetTxPowerIndexByRateSection(Adapter, path, channel, OFDM);
1447 PHY_SetTxPowerIndexByRateSection(Adapter, path, channel, HT_MCS0_MCS7);
1448
1449 if (pHalData->NumTotalRFPath >= 2)
1450 PHY_SetTxPowerIndexByRateSection(Adapter, path, channel, HT_MCS8_MCS15);
1451
1452 }
1453 }
1454
PHY_SetTxPowerIndexByRateArray(struct adapter * padapter,u8 RFPath,enum channel_width BandWidth,u8 Channel,u8 * Rates,u8 RateArraySize)1455 void PHY_SetTxPowerIndexByRateArray(
1456 struct adapter *padapter,
1457 u8 RFPath,
1458 enum channel_width BandWidth,
1459 u8 Channel,
1460 u8 *Rates,
1461 u8 RateArraySize
1462 )
1463 {
1464 u32 powerIndex = 0;
1465 int i = 0;
1466
1467 for (i = 0; i < RateArraySize; ++i) {
1468 powerIndex = PHY_GetTxPowerIndex(padapter, RFPath, Rates[i], BandWidth, Channel);
1469 PHY_SetTxPowerIndex(padapter, powerIndex, RFPath, Rates[i]);
1470 }
1471 }
1472
phy_GetWorldWideLimit(s8 * LimitTable)1473 static s8 phy_GetWorldWideLimit(s8 *LimitTable)
1474 {
1475 s8 min = LimitTable[0];
1476 u8 i = 0;
1477
1478 for (i = 0; i < MAX_REGULATION_NUM; ++i) {
1479 if (LimitTable[i] < min)
1480 min = LimitTable[i];
1481 }
1482
1483 return min;
1484 }
1485
phy_GetChannelIndexOfTxPowerLimit(u8 Band,u8 Channel)1486 static s8 phy_GetChannelIndexOfTxPowerLimit(u8 Band, u8 Channel)
1487 {
1488 s8 channelIndex = -1;
1489 u8 channel5G[CHANNEL_MAX_NUMBER_5G] = {
1490 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 100, 102,
1491 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130,
1492 132, 134, 136, 138, 140, 142, 144, 149, 151, 153, 155, 157, 159, 161,
1493 163, 165, 167, 168, 169, 171, 173, 175, 177
1494 };
1495 u8 i = 0;
1496 if (Band == BAND_ON_2_4G)
1497 channelIndex = Channel - 1;
1498 else if (Band == BAND_ON_5G) {
1499 for (i = 0; i < ARRAY_SIZE(channel5G); ++i) {
1500 if (channel5G[i] == Channel)
1501 channelIndex = i;
1502 }
1503 }
1504
1505 return channelIndex;
1506 }
1507
get_bandwidth_idx(const enum channel_width bandwidth)1508 static s16 get_bandwidth_idx(const enum channel_width bandwidth)
1509 {
1510 switch (bandwidth) {
1511 case CHANNEL_WIDTH_20:
1512 return 0;
1513 case CHANNEL_WIDTH_40:
1514 return 1;
1515 case CHANNEL_WIDTH_80:
1516 return 2;
1517 case CHANNEL_WIDTH_160:
1518 return 3;
1519 default:
1520 return -1;
1521 }
1522 }
1523
get_rate_sctn_idx(const u8 rate)1524 static s16 get_rate_sctn_idx(const u8 rate)
1525 {
1526 switch (rate) {
1527 case MGN_1M: case MGN_2M: case MGN_5_5M: case MGN_11M:
1528 return 0;
1529 case MGN_6M: case MGN_9M: case MGN_12M: case MGN_18M:
1530 case MGN_24M: case MGN_36M: case MGN_48M: case MGN_54M:
1531 return 1;
1532 case MGN_MCS0: case MGN_MCS1: case MGN_MCS2: case MGN_MCS3:
1533 case MGN_MCS4: case MGN_MCS5: case MGN_MCS6: case MGN_MCS7:
1534 return 2;
1535 case MGN_MCS8: case MGN_MCS9: case MGN_MCS10: case MGN_MCS11:
1536 case MGN_MCS12: case MGN_MCS13: case MGN_MCS14: case MGN_MCS15:
1537 return 3;
1538 case MGN_MCS16: case MGN_MCS17: case MGN_MCS18: case MGN_MCS19:
1539 case MGN_MCS20: case MGN_MCS21: case MGN_MCS22: case MGN_MCS23:
1540 return 4;
1541 case MGN_MCS24: case MGN_MCS25: case MGN_MCS26: case MGN_MCS27:
1542 case MGN_MCS28: case MGN_MCS29: case MGN_MCS30: case MGN_MCS31:
1543 return 5;
1544 case MGN_VHT1SS_MCS0: case MGN_VHT1SS_MCS1: case MGN_VHT1SS_MCS2:
1545 case MGN_VHT1SS_MCS3: case MGN_VHT1SS_MCS4: case MGN_VHT1SS_MCS5:
1546 case MGN_VHT1SS_MCS6: case MGN_VHT1SS_MCS7: case MGN_VHT1SS_MCS8:
1547 case MGN_VHT1SS_MCS9:
1548 return 6;
1549 case MGN_VHT2SS_MCS0: case MGN_VHT2SS_MCS1: case MGN_VHT2SS_MCS2:
1550 case MGN_VHT2SS_MCS3: case MGN_VHT2SS_MCS4: case MGN_VHT2SS_MCS5:
1551 case MGN_VHT2SS_MCS6: case MGN_VHT2SS_MCS7: case MGN_VHT2SS_MCS8:
1552 case MGN_VHT2SS_MCS9:
1553 return 7;
1554 case MGN_VHT3SS_MCS0: case MGN_VHT3SS_MCS1: case MGN_VHT3SS_MCS2:
1555 case MGN_VHT3SS_MCS3: case MGN_VHT3SS_MCS4: case MGN_VHT3SS_MCS5:
1556 case MGN_VHT3SS_MCS6: case MGN_VHT3SS_MCS7: case MGN_VHT3SS_MCS8:
1557 case MGN_VHT3SS_MCS9:
1558 return 8;
1559 case MGN_VHT4SS_MCS0: case MGN_VHT4SS_MCS1: case MGN_VHT4SS_MCS2:
1560 case MGN_VHT4SS_MCS3: case MGN_VHT4SS_MCS4: case MGN_VHT4SS_MCS5:
1561 case MGN_VHT4SS_MCS6: case MGN_VHT4SS_MCS7: case MGN_VHT4SS_MCS8:
1562 case MGN_VHT4SS_MCS9:
1563 return 9;
1564 default:
1565 return -1;
1566 }
1567 }
1568
phy_get_tx_pwr_lmt(struct adapter * adapter,u32 reg_pwr_tbl_sel,enum band_type band_type,enum channel_width bandwidth,u8 rf_path,u8 data_rate,u8 channel)1569 s8 phy_get_tx_pwr_lmt(struct adapter *adapter, u32 reg_pwr_tbl_sel,
1570 enum band_type band_type, enum channel_width bandwidth,
1571 u8 rf_path, u8 data_rate, u8 channel)
1572 {
1573 s16 idx_band = -1;
1574 s16 idx_regulation = -1;
1575 s16 idx_bandwidth = -1;
1576 s16 idx_rate_sctn = -1;
1577 s16 idx_channel = -1;
1578 s8 pwr_lmt = MAX_POWER_INDEX;
1579 struct hal_com_data *hal_data = GET_HAL_DATA(adapter);
1580
1581 if (((adapter->registrypriv.RegEnableTxPowerLimit == 2) &&
1582 (hal_data->EEPROMRegulatory != 1)) ||
1583 (adapter->registrypriv.RegEnableTxPowerLimit == 0))
1584 return MAX_POWER_INDEX;
1585
1586 switch (adapter->registrypriv.RegPwrTblSel) {
1587 case 1:
1588 idx_regulation = TXPWR_LMT_ETSI;
1589 break;
1590 case 2:
1591 idx_regulation = TXPWR_LMT_MKK;
1592 break;
1593 case 3:
1594 idx_regulation = TXPWR_LMT_FCC;
1595 break;
1596 case 4:
1597 idx_regulation = TXPWR_LMT_WW;
1598 break;
1599 default:
1600 idx_regulation = (band_type == BAND_ON_2_4G) ?
1601 hal_data->Regulation2_4G :
1602 hal_data->Regulation5G;
1603 break;
1604 }
1605
1606 if (band_type == BAND_ON_2_4G)
1607 idx_band = 0;
1608 else if (band_type == BAND_ON_5G)
1609 idx_band = 1;
1610
1611 idx_bandwidth = get_bandwidth_idx(bandwidth);
1612 idx_rate_sctn = get_rate_sctn_idx(data_rate);
1613
1614 /* workaround for wrong index combination to obtain tx power limit, */
1615 /* OFDM only exists in BW 20M */
1616 /* CCK table will only be given in BW 20M */
1617 /* HT on 80M will reference to HT on 40M */
1618 if (idx_rate_sctn == 0 || idx_rate_sctn == 1)
1619 idx_bandwidth = 0;
1620 else if ((idx_rate_sctn == 2 || idx_rate_sctn == 3) &&
1621 (band_type == BAND_ON_5G) && (idx_bandwidth == 2))
1622 idx_bandwidth = 1;
1623
1624 if (band_type == BAND_ON_2_4G || band_type == BAND_ON_5G)
1625 channel = phy_GetChannelIndexOfTxPowerLimit(band_type, channel);
1626
1627 if (idx_band == -1 || idx_regulation == -1 || idx_bandwidth == -1 ||
1628 idx_rate_sctn == -1 || idx_channel == -1)
1629 return MAX_POWER_INDEX;
1630
1631 if (band_type == BAND_ON_2_4G) {
1632 s8 limits[10] = {0}; u8 i = 0;
1633
1634 for (i = 0; i < MAX_REGULATION_NUM; i++)
1635 limits[i] = hal_data->TxPwrLimit_2_4G[i]
1636 [idx_bandwidth]
1637 [idx_rate_sctn]
1638 [idx_channel]
1639 [rf_path];
1640
1641 pwr_lmt = (idx_regulation == TXPWR_LMT_WW) ?
1642 phy_GetWorldWideLimit(limits) :
1643 hal_data->TxPwrLimit_2_4G[idx_regulation]
1644 [idx_bandwidth]
1645 [idx_rate_sctn]
1646 [idx_channel]
1647 [rf_path];
1648
1649 } else if (band_type == BAND_ON_5G) {
1650 s8 limits[10] = {0}; u8 i = 0;
1651
1652 for (i = 0; i < MAX_REGULATION_NUM; ++i)
1653 limits[i] = hal_data->TxPwrLimit_5G[i]
1654 [idx_bandwidth]
1655 [idx_rate_sctn]
1656 [idx_channel]
1657 [rf_path];
1658
1659 pwr_lmt = (idx_regulation == TXPWR_LMT_WW) ?
1660 phy_GetWorldWideLimit(limits) :
1661 hal_data->TxPwrLimit_5G[idx_regulation]
1662 [idx_bandwidth]
1663 [idx_rate_sctn]
1664 [idx_channel]
1665 [rf_path];
1666 }
1667
1668 return pwr_lmt;
1669 }
1670
phy_CrossReferenceHTAndVHTTxPowerLimit(struct adapter * padapter)1671 static void phy_CrossReferenceHTAndVHTTxPowerLimit(struct adapter *padapter)
1672 {
1673 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1674 u8 regulation, bw, channel, rateSection;
1675 s8 tempPwrLmt = 0;
1676
1677 for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) {
1678 for (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; ++bw) {
1679 for (channel = 0; channel < CHANNEL_MAX_NUMBER_5G; ++channel) {
1680 for (rateSection = 0; rateSection < MAX_RATE_SECTION_NUM; ++rateSection) {
1681 tempPwrLmt = pHalData->TxPwrLimit_5G[regulation][bw][rateSection][channel][ODM_RF_PATH_A];
1682 if (tempPwrLmt == MAX_POWER_INDEX) {
1683 u8 baseSection = 2, refSection = 6;
1684 if (bw == 0 || bw == 1) { /* 5G 20M 40M VHT and HT can cross reference */
1685 /* 1, bw, rateSection, channel, ODM_RF_PATH_A); */
1686 if (rateSection >= 2 && rateSection <= 9) {
1687 if (rateSection == 2) {
1688 baseSection = 2;
1689 refSection = 6;
1690 } else if (rateSection == 3) {
1691 baseSection = 3;
1692 refSection = 7;
1693 } else if (rateSection == 4) {
1694 baseSection = 4;
1695 refSection = 8;
1696 } else if (rateSection == 5) {
1697 baseSection = 5;
1698 refSection = 9;
1699 } else if (rateSection == 6) {
1700 baseSection = 6;
1701 refSection = 2;
1702 } else if (rateSection == 7) {
1703 baseSection = 7;
1704 refSection = 3;
1705 } else if (rateSection == 8) {
1706 baseSection = 8;
1707 refSection = 4;
1708 } else if (rateSection == 9) {
1709 baseSection = 9;
1710 refSection = 5;
1711 }
1712 pHalData->TxPwrLimit_5G[regulation][bw][baseSection][channel][ODM_RF_PATH_A] =
1713 pHalData->TxPwrLimit_5G[regulation][bw][refSection][channel][ODM_RF_PATH_A];
1714 }
1715 }
1716 }
1717 }
1718 }
1719 }
1720 }
1721 }
1722
PHY_ConvertTxPowerLimitToPowerIndex(struct adapter * Adapter)1723 void PHY_ConvertTxPowerLimitToPowerIndex(struct adapter *Adapter)
1724 {
1725 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
1726 u8 BW40PwrBasedBm2_4G = 0x2E;
1727 u8 regulation, bw, channel, rateSection;
1728 s8 tempValue = 0, tempPwrLmt = 0;
1729 u8 rfPath = 0;
1730
1731 phy_CrossReferenceHTAndVHTTxPowerLimit(Adapter);
1732
1733 for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) {
1734 for (bw = 0; bw < MAX_2_4G_BANDWIDTH_NUM; ++bw) {
1735 for (channel = 0; channel < CHANNEL_MAX_NUMBER_2G; ++channel) {
1736 for (rateSection = 0; rateSection < MAX_RATE_SECTION_NUM; ++rateSection) {
1737 tempPwrLmt = pHalData->TxPwrLimit_2_4G[regulation][bw][rateSection][channel][ODM_RF_PATH_A];
1738
1739 for (rfPath = ODM_RF_PATH_A; rfPath < MAX_RF_PATH_NUM; ++rfPath) {
1740 if (pHalData->odmpriv.PhyRegPgValueType == PHY_REG_PG_EXACT_VALUE) {
1741 if (rateSection == 5) /* HT 4T */
1742 BW40PwrBasedBm2_4G = PHY_GetTxPowerByRateBase(Adapter, BAND_ON_2_4G, rfPath, RF_4TX, HT_MCS24_MCS31);
1743 else if (rateSection == 4) /* HT 3T */
1744 BW40PwrBasedBm2_4G = PHY_GetTxPowerByRateBase(Adapter, BAND_ON_2_4G, rfPath, RF_3TX, HT_MCS16_MCS23);
1745 else if (rateSection == 3) /* HT 2T */
1746 BW40PwrBasedBm2_4G = PHY_GetTxPowerByRateBase(Adapter, BAND_ON_2_4G, rfPath, RF_2TX, HT_MCS8_MCS15);
1747 else if (rateSection == 2) /* HT 1T */
1748 BW40PwrBasedBm2_4G = PHY_GetTxPowerByRateBase(Adapter, BAND_ON_2_4G, rfPath, RF_1TX, HT_MCS0_MCS7);
1749 else if (rateSection == 1) /* OFDM */
1750 BW40PwrBasedBm2_4G = PHY_GetTxPowerByRateBase(Adapter, BAND_ON_2_4G, rfPath, RF_1TX, OFDM);
1751 else if (rateSection == 0) /* CCK */
1752 BW40PwrBasedBm2_4G = PHY_GetTxPowerByRateBase(Adapter, BAND_ON_2_4G, rfPath, RF_1TX, CCK);
1753 } else
1754 BW40PwrBasedBm2_4G = Adapter->registrypriv.RegPowerBase * 2;
1755
1756 if (tempPwrLmt != MAX_POWER_INDEX) {
1757 tempValue = tempPwrLmt - BW40PwrBasedBm2_4G;
1758 pHalData->TxPwrLimit_2_4G[regulation][bw][rateSection][channel][rfPath] = tempValue;
1759 }
1760 }
1761 }
1762 }
1763 }
1764 }
1765 }
1766
PHY_InitTxPowerLimit(struct adapter * Adapter)1767 void PHY_InitTxPowerLimit(struct adapter *Adapter)
1768 {
1769 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
1770 u8 i, j, k, l, m;
1771
1772 for (i = 0; i < MAX_REGULATION_NUM; ++i) {
1773 for (j = 0; j < MAX_2_4G_BANDWIDTH_NUM; ++j)
1774 for (k = 0; k < MAX_RATE_SECTION_NUM; ++k)
1775 for (m = 0; m < CHANNEL_MAX_NUMBER_2G; ++m)
1776 for (l = 0; l < MAX_RF_PATH_NUM; ++l)
1777 pHalData->TxPwrLimit_2_4G[i][j][k][m][l] = MAX_POWER_INDEX;
1778 }
1779
1780 for (i = 0; i < MAX_REGULATION_NUM; ++i) {
1781 for (j = 0; j < MAX_5G_BANDWIDTH_NUM; ++j)
1782 for (k = 0; k < MAX_RATE_SECTION_NUM; ++k)
1783 for (m = 0; m < CHANNEL_MAX_NUMBER_5G; ++m)
1784 for (l = 0; l < MAX_RF_PATH_NUM; ++l)
1785 pHalData->TxPwrLimit_5G[i][j][k][m][l] = MAX_POWER_INDEX;
1786 }
1787 }
1788
PHY_SetTxPowerLimit(struct adapter * Adapter,u8 * Regulation,u8 * Band,u8 * Bandwidth,u8 * RateSection,u8 * RfPath,u8 * Channel,u8 * PowerLimit)1789 void PHY_SetTxPowerLimit(
1790 struct adapter *Adapter,
1791 u8 *Regulation,
1792 u8 *Band,
1793 u8 *Bandwidth,
1794 u8 *RateSection,
1795 u8 *RfPath,
1796 u8 *Channel,
1797 u8 *PowerLimit
1798 )
1799 {
1800 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
1801 u8 regulation = 0, bandwidth = 0, rateSection = 0, channel;
1802 s8 powerLimit = 0, prevPowerLimit, channelIndex;
1803
1804 GetU1ByteIntegerFromStringInDecimal((s8 *)Channel, &channel);
1805 GetU1ByteIntegerFromStringInDecimal((s8 *)PowerLimit, &powerLimit);
1806
1807 powerLimit = powerLimit > MAX_POWER_INDEX ? MAX_POWER_INDEX : powerLimit;
1808
1809 if (eqNByte(Regulation, (u8 *)("FCC"), 3))
1810 regulation = 0;
1811 else if (eqNByte(Regulation, (u8 *)("MKK"), 3))
1812 regulation = 1;
1813 else if (eqNByte(Regulation, (u8 *)("ETSI"), 4))
1814 regulation = 2;
1815 else if (eqNByte(Regulation, (u8 *)("WW13"), 4))
1816 regulation = 3;
1817
1818 if (eqNByte(RateSection, (u8 *)("CCK"), 3) && eqNByte(RfPath, (u8 *)("1T"), 2))
1819 rateSection = 0;
1820 else if (eqNByte(RateSection, (u8 *)("OFDM"), 4) && eqNByte(RfPath, (u8 *)("1T"), 2))
1821 rateSection = 1;
1822 else if (eqNByte(RateSection, (u8 *)("HT"), 2) && eqNByte(RfPath, (u8 *)("1T"), 2))
1823 rateSection = 2;
1824 else if (eqNByte(RateSection, (u8 *)("HT"), 2) && eqNByte(RfPath, (u8 *)("2T"), 2))
1825 rateSection = 3;
1826 else if (eqNByte(RateSection, (u8 *)("HT"), 2) && eqNByte(RfPath, (u8 *)("3T"), 2))
1827 rateSection = 4;
1828 else if (eqNByte(RateSection, (u8 *)("HT"), 2) && eqNByte(RfPath, (u8 *)("4T"), 2))
1829 rateSection = 5;
1830 else if (eqNByte(RateSection, (u8 *)("VHT"), 3) && eqNByte(RfPath, (u8 *)("1T"), 2))
1831 rateSection = 6;
1832 else if (eqNByte(RateSection, (u8 *)("VHT"), 3) && eqNByte(RfPath, (u8 *)("2T"), 2))
1833 rateSection = 7;
1834 else if (eqNByte(RateSection, (u8 *)("VHT"), 3) && eqNByte(RfPath, (u8 *)("3T"), 2))
1835 rateSection = 8;
1836 else if (eqNByte(RateSection, (u8 *)("VHT"), 3) && eqNByte(RfPath, (u8 *)("4T"), 2))
1837 rateSection = 9;
1838 else
1839 return;
1840
1841 if (eqNByte(Bandwidth, (u8 *)("20M"), 3))
1842 bandwidth = 0;
1843 else if (eqNByte(Bandwidth, (u8 *)("40M"), 3))
1844 bandwidth = 1;
1845 else if (eqNByte(Bandwidth, (u8 *)("80M"), 3))
1846 bandwidth = 2;
1847 else if (eqNByte(Bandwidth, (u8 *)("160M"), 4))
1848 bandwidth = 3;
1849
1850 if (eqNByte(Band, (u8 *)("2.4G"), 4)) {
1851 channelIndex = phy_GetChannelIndexOfTxPowerLimit(BAND_ON_2_4G, channel);
1852
1853 if (channelIndex == -1)
1854 return;
1855
1856 prevPowerLimit = pHalData->TxPwrLimit_2_4G[regulation][bandwidth][rateSection][channelIndex][ODM_RF_PATH_A];
1857
1858 if (powerLimit < prevPowerLimit)
1859 pHalData->TxPwrLimit_2_4G[regulation][bandwidth][rateSection][channelIndex][ODM_RF_PATH_A] = powerLimit;
1860
1861 } else if (eqNByte(Band, (u8 *)("5G"), 2)) {
1862 channelIndex = phy_GetChannelIndexOfTxPowerLimit(BAND_ON_5G, channel);
1863
1864 if (channelIndex == -1)
1865 return;
1866
1867 prevPowerLimit = pHalData->TxPwrLimit_5G[regulation][bandwidth][rateSection][channelIndex][ODM_RF_PATH_A];
1868
1869 if (powerLimit < prevPowerLimit)
1870 pHalData->TxPwrLimit_5G[regulation][bandwidth][rateSection][channelIndex][ODM_RF_PATH_A] = powerLimit;
1871
1872 } else {
1873 return;
1874 }
1875 }
1876
Hal_ChannelPlanToRegulation(struct adapter * Adapter,u16 ChannelPlan)1877 void Hal_ChannelPlanToRegulation(struct adapter *Adapter, u16 ChannelPlan)
1878 {
1879 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
1880 pHalData->Regulation2_4G = TXPWR_LMT_WW;
1881 pHalData->Regulation5G = TXPWR_LMT_WW;
1882
1883 switch (ChannelPlan) {
1884 case RT_CHANNEL_DOMAIN_WORLD_NULL:
1885 pHalData->Regulation2_4G = TXPWR_LMT_WW;
1886 break;
1887 case RT_CHANNEL_DOMAIN_ETSI1_NULL:
1888 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
1889 break;
1890 case RT_CHANNEL_DOMAIN_FCC1_NULL:
1891 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
1892 break;
1893 case RT_CHANNEL_DOMAIN_MKK1_NULL:
1894 pHalData->Regulation2_4G = TXPWR_LMT_MKK;
1895 break;
1896 case RT_CHANNEL_DOMAIN_ETSI2_NULL:
1897 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
1898 break;
1899 case RT_CHANNEL_DOMAIN_FCC1_FCC1:
1900 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
1901 pHalData->Regulation5G = TXPWR_LMT_FCC;
1902 break;
1903 case RT_CHANNEL_DOMAIN_WORLD_ETSI1:
1904 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
1905 pHalData->Regulation5G = TXPWR_LMT_ETSI;
1906 break;
1907 case RT_CHANNEL_DOMAIN_MKK1_MKK1:
1908 pHalData->Regulation2_4G = TXPWR_LMT_MKK;
1909 pHalData->Regulation5G = TXPWR_LMT_MKK;
1910 break;
1911 case RT_CHANNEL_DOMAIN_WORLD_KCC1:
1912 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
1913 pHalData->Regulation5G = TXPWR_LMT_MKK;
1914 break;
1915 case RT_CHANNEL_DOMAIN_WORLD_FCC2:
1916 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
1917 pHalData->Regulation5G = TXPWR_LMT_FCC;
1918 break;
1919 case RT_CHANNEL_DOMAIN_WORLD_FCC3:
1920 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
1921 pHalData->Regulation5G = TXPWR_LMT_FCC;
1922 break;
1923 case RT_CHANNEL_DOMAIN_WORLD_FCC4:
1924 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
1925 pHalData->Regulation5G = TXPWR_LMT_FCC;
1926 break;
1927 case RT_CHANNEL_DOMAIN_WORLD_FCC5:
1928 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
1929 pHalData->Regulation5G = TXPWR_LMT_FCC;
1930 break;
1931 case RT_CHANNEL_DOMAIN_WORLD_FCC6:
1932 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
1933 pHalData->Regulation5G = TXPWR_LMT_FCC;
1934 break;
1935 case RT_CHANNEL_DOMAIN_FCC1_FCC7:
1936 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
1937 pHalData->Regulation5G = TXPWR_LMT_FCC;
1938 break;
1939 case RT_CHANNEL_DOMAIN_WORLD_ETSI2:
1940 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
1941 pHalData->Regulation5G = TXPWR_LMT_FCC;
1942 break;
1943 case RT_CHANNEL_DOMAIN_WORLD_ETSI3:
1944 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
1945 pHalData->Regulation5G = TXPWR_LMT_FCC;
1946 break;
1947 case RT_CHANNEL_DOMAIN_MKK1_MKK2:
1948 pHalData->Regulation2_4G = TXPWR_LMT_MKK;
1949 pHalData->Regulation5G = TXPWR_LMT_FCC;
1950 break;
1951 case RT_CHANNEL_DOMAIN_MKK1_MKK3:
1952 pHalData->Regulation2_4G = TXPWR_LMT_MKK;
1953 pHalData->Regulation5G = TXPWR_LMT_FCC;
1954 break;
1955 case RT_CHANNEL_DOMAIN_FCC1_NCC1:
1956 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
1957 pHalData->Regulation5G = TXPWR_LMT_FCC;
1958 break;
1959 case RT_CHANNEL_DOMAIN_FCC1_NCC2:
1960 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
1961 pHalData->Regulation5G = TXPWR_LMT_FCC;
1962 break;
1963 case RT_CHANNEL_DOMAIN_GLOBAL_NULL:
1964 pHalData->Regulation2_4G = TXPWR_LMT_WW;
1965 pHalData->Regulation5G = TXPWR_LMT_WW;
1966 break;
1967 case RT_CHANNEL_DOMAIN_ETSI1_ETSI4:
1968 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
1969 pHalData->Regulation5G = TXPWR_LMT_ETSI;
1970 break;
1971 case RT_CHANNEL_DOMAIN_FCC1_FCC2:
1972 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
1973 pHalData->Regulation5G = TXPWR_LMT_FCC;
1974 break;
1975 case RT_CHANNEL_DOMAIN_FCC1_NCC3:
1976 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
1977 pHalData->Regulation5G = TXPWR_LMT_FCC;
1978 break;
1979 case RT_CHANNEL_DOMAIN_WORLD_ETSI5:
1980 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
1981 pHalData->Regulation5G = TXPWR_LMT_ETSI;
1982 break;
1983 case RT_CHANNEL_DOMAIN_FCC1_FCC8:
1984 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
1985 pHalData->Regulation5G = TXPWR_LMT_FCC;
1986 break;
1987 case RT_CHANNEL_DOMAIN_WORLD_ETSI6:
1988 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
1989 pHalData->Regulation5G = TXPWR_LMT_ETSI;
1990 break;
1991 case RT_CHANNEL_DOMAIN_WORLD_ETSI7:
1992 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
1993 pHalData->Regulation5G = TXPWR_LMT_ETSI;
1994 break;
1995 case RT_CHANNEL_DOMAIN_WORLD_ETSI8:
1996 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
1997 pHalData->Regulation5G = TXPWR_LMT_ETSI;
1998 break;
1999 case RT_CHANNEL_DOMAIN_WORLD_ETSI9:
2000 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
2001 pHalData->Regulation5G = TXPWR_LMT_ETSI;
2002 break;
2003 case RT_CHANNEL_DOMAIN_WORLD_ETSI10:
2004 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
2005 pHalData->Regulation5G = TXPWR_LMT_ETSI;
2006 break;
2007 case RT_CHANNEL_DOMAIN_WORLD_ETSI11:
2008 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
2009 pHalData->Regulation5G = TXPWR_LMT_ETSI;
2010 break;
2011 case RT_CHANNEL_DOMAIN_FCC1_NCC4:
2012 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
2013 pHalData->Regulation5G = TXPWR_LMT_FCC;
2014 break;
2015 case RT_CHANNEL_DOMAIN_WORLD_ETSI12:
2016 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
2017 pHalData->Regulation5G = TXPWR_LMT_ETSI;
2018 break;
2019 case RT_CHANNEL_DOMAIN_FCC1_FCC9:
2020 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
2021 pHalData->Regulation5G = TXPWR_LMT_FCC;
2022 break;
2023 case RT_CHANNEL_DOMAIN_WORLD_ETSI13:
2024 pHalData->Regulation2_4G = TXPWR_LMT_ETSI;
2025 pHalData->Regulation5G = TXPWR_LMT_ETSI;
2026 break;
2027 case RT_CHANNEL_DOMAIN_FCC1_FCC10:
2028 pHalData->Regulation2_4G = TXPWR_LMT_FCC;
2029 pHalData->Regulation5G = TXPWR_LMT_FCC;
2030 break;
2031 case RT_CHANNEL_DOMAIN_REALTEK_DEFINE: /* Realtek Reserve */
2032 pHalData->Regulation2_4G = TXPWR_LMT_WW;
2033 pHalData->Regulation5G = TXPWR_LMT_WW;
2034 break;
2035 default:
2036 break;
2037 }
2038 }
2039