1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * tools/testing/selftests/kvm/include/x86_64/processor.h
4 *
5 * Copyright (C) 2018, Google LLC.
6 */
7
8 #ifndef SELFTEST_KVM_PROCESSOR_H
9 #define SELFTEST_KVM_PROCESSOR_H
10
11 #include <assert.h>
12 #include <stdint.h>
13
14 #include <asm/msr-index.h>
15
16 #define X86_EFLAGS_FIXED (1u << 1)
17
18 #define X86_CR4_VME (1ul << 0)
19 #define X86_CR4_PVI (1ul << 1)
20 #define X86_CR4_TSD (1ul << 2)
21 #define X86_CR4_DE (1ul << 3)
22 #define X86_CR4_PSE (1ul << 4)
23 #define X86_CR4_PAE (1ul << 5)
24 #define X86_CR4_MCE (1ul << 6)
25 #define X86_CR4_PGE (1ul << 7)
26 #define X86_CR4_PCE (1ul << 8)
27 #define X86_CR4_OSFXSR (1ul << 9)
28 #define X86_CR4_OSXMMEXCPT (1ul << 10)
29 #define X86_CR4_UMIP (1ul << 11)
30 #define X86_CR4_LA57 (1ul << 12)
31 #define X86_CR4_VMXE (1ul << 13)
32 #define X86_CR4_SMXE (1ul << 14)
33 #define X86_CR4_FSGSBASE (1ul << 16)
34 #define X86_CR4_PCIDE (1ul << 17)
35 #define X86_CR4_OSXSAVE (1ul << 18)
36 #define X86_CR4_SMEP (1ul << 20)
37 #define X86_CR4_SMAP (1ul << 21)
38 #define X86_CR4_PKE (1ul << 22)
39
40 /* CPUID.1.ECX */
41 #define CPUID_VMX (1ul << 5)
42 #define CPUID_SMX (1ul << 6)
43 #define CPUID_PCID (1ul << 17)
44 #define CPUID_XSAVE (1ul << 26)
45
46 /* CPUID.7.EBX */
47 #define CPUID_FSGSBASE (1ul << 0)
48 #define CPUID_SMEP (1ul << 7)
49 #define CPUID_SMAP (1ul << 20)
50
51 /* CPUID.7.ECX */
52 #define CPUID_UMIP (1ul << 2)
53 #define CPUID_PKU (1ul << 3)
54 #define CPUID_LA57 (1ul << 16)
55
56 #define UNEXPECTED_VECTOR_PORT 0xfff0u
57
58 /* General Registers in 64-Bit Mode */
59 struct gpr64_regs {
60 u64 rax;
61 u64 rcx;
62 u64 rdx;
63 u64 rbx;
64 u64 rsp;
65 u64 rbp;
66 u64 rsi;
67 u64 rdi;
68 u64 r8;
69 u64 r9;
70 u64 r10;
71 u64 r11;
72 u64 r12;
73 u64 r13;
74 u64 r14;
75 u64 r15;
76 };
77
78 struct desc64 {
79 uint16_t limit0;
80 uint16_t base0;
81 unsigned base1:8, type:4, s:1, dpl:2, p:1;
82 unsigned limit1:4, avl:1, l:1, db:1, g:1, base2:8;
83 uint32_t base3;
84 uint32_t zero1;
85 } __attribute__((packed));
86
87 struct desc_ptr {
88 uint16_t size;
89 uint64_t address;
90 } __attribute__((packed));
91
get_desc64_base(const struct desc64 * desc)92 static inline uint64_t get_desc64_base(const struct desc64 *desc)
93 {
94 return ((uint64_t)desc->base3 << 32) |
95 (desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24));
96 }
97
rdtsc(void)98 static inline uint64_t rdtsc(void)
99 {
100 uint32_t eax, edx;
101 uint64_t tsc_val;
102 /*
103 * The lfence is to wait (on Intel CPUs) until all previous
104 * instructions have been executed. If software requires RDTSC to be
105 * executed prior to execution of any subsequent instruction, it can
106 * execute LFENCE immediately after RDTSC
107 */
108 __asm__ __volatile__("lfence; rdtsc; lfence" : "=a"(eax), "=d"(edx));
109 tsc_val = ((uint64_t)edx) << 32 | eax;
110 return tsc_val;
111 }
112
rdtscp(uint32_t * aux)113 static inline uint64_t rdtscp(uint32_t *aux)
114 {
115 uint32_t eax, edx;
116
117 __asm__ __volatile__("rdtscp" : "=a"(eax), "=d"(edx), "=c"(*aux));
118 return ((uint64_t)edx) << 32 | eax;
119 }
120
rdmsr(uint32_t msr)121 static inline uint64_t rdmsr(uint32_t msr)
122 {
123 uint32_t a, d;
124
125 __asm__ __volatile__("rdmsr" : "=a"(a), "=d"(d) : "c"(msr) : "memory");
126
127 return a | ((uint64_t) d << 32);
128 }
129
wrmsr(uint32_t msr,uint64_t value)130 static inline void wrmsr(uint32_t msr, uint64_t value)
131 {
132 uint32_t a = value;
133 uint32_t d = value >> 32;
134
135 __asm__ __volatile__("wrmsr" :: "a"(a), "d"(d), "c"(msr) : "memory");
136 }
137
138
inw(uint16_t port)139 static inline uint16_t inw(uint16_t port)
140 {
141 uint16_t tmp;
142
143 __asm__ __volatile__("in %%dx, %%ax"
144 : /* output */ "=a" (tmp)
145 : /* input */ "d" (port));
146
147 return tmp;
148 }
149
get_es(void)150 static inline uint16_t get_es(void)
151 {
152 uint16_t es;
153
154 __asm__ __volatile__("mov %%es, %[es]"
155 : /* output */ [es]"=rm"(es));
156 return es;
157 }
158
get_cs(void)159 static inline uint16_t get_cs(void)
160 {
161 uint16_t cs;
162
163 __asm__ __volatile__("mov %%cs, %[cs]"
164 : /* output */ [cs]"=rm"(cs));
165 return cs;
166 }
167
get_ss(void)168 static inline uint16_t get_ss(void)
169 {
170 uint16_t ss;
171
172 __asm__ __volatile__("mov %%ss, %[ss]"
173 : /* output */ [ss]"=rm"(ss));
174 return ss;
175 }
176
get_ds(void)177 static inline uint16_t get_ds(void)
178 {
179 uint16_t ds;
180
181 __asm__ __volatile__("mov %%ds, %[ds]"
182 : /* output */ [ds]"=rm"(ds));
183 return ds;
184 }
185
get_fs(void)186 static inline uint16_t get_fs(void)
187 {
188 uint16_t fs;
189
190 __asm__ __volatile__("mov %%fs, %[fs]"
191 : /* output */ [fs]"=rm"(fs));
192 return fs;
193 }
194
get_gs(void)195 static inline uint16_t get_gs(void)
196 {
197 uint16_t gs;
198
199 __asm__ __volatile__("mov %%gs, %[gs]"
200 : /* output */ [gs]"=rm"(gs));
201 return gs;
202 }
203
get_tr(void)204 static inline uint16_t get_tr(void)
205 {
206 uint16_t tr;
207
208 __asm__ __volatile__("str %[tr]"
209 : /* output */ [tr]"=rm"(tr));
210 return tr;
211 }
212
get_cr0(void)213 static inline uint64_t get_cr0(void)
214 {
215 uint64_t cr0;
216
217 __asm__ __volatile__("mov %%cr0, %[cr0]"
218 : /* output */ [cr0]"=r"(cr0));
219 return cr0;
220 }
221
get_cr3(void)222 static inline uint64_t get_cr3(void)
223 {
224 uint64_t cr3;
225
226 __asm__ __volatile__("mov %%cr3, %[cr3]"
227 : /* output */ [cr3]"=r"(cr3));
228 return cr3;
229 }
230
get_cr4(void)231 static inline uint64_t get_cr4(void)
232 {
233 uint64_t cr4;
234
235 __asm__ __volatile__("mov %%cr4, %[cr4]"
236 : /* output */ [cr4]"=r"(cr4));
237 return cr4;
238 }
239
set_cr4(uint64_t val)240 static inline void set_cr4(uint64_t val)
241 {
242 __asm__ __volatile__("mov %0, %%cr4" : : "r" (val) : "memory");
243 }
244
get_gdt(void)245 static inline struct desc_ptr get_gdt(void)
246 {
247 struct desc_ptr gdt;
248 __asm__ __volatile__("sgdt %[gdt]"
249 : /* output */ [gdt]"=m"(gdt));
250 return gdt;
251 }
252
get_idt(void)253 static inline struct desc_ptr get_idt(void)
254 {
255 struct desc_ptr idt;
256 __asm__ __volatile__("sidt %[idt]"
257 : /* output */ [idt]"=m"(idt));
258 return idt;
259 }
260
outl(uint16_t port,uint32_t value)261 static inline void outl(uint16_t port, uint32_t value)
262 {
263 __asm__ __volatile__("outl %%eax, %%dx" : : "d"(port), "a"(value));
264 }
265
cpuid(uint32_t * eax,uint32_t * ebx,uint32_t * ecx,uint32_t * edx)266 static inline void cpuid(uint32_t *eax, uint32_t *ebx,
267 uint32_t *ecx, uint32_t *edx)
268 {
269 /* ecx is often an input as well as an output. */
270 asm volatile("cpuid"
271 : "=a" (*eax),
272 "=b" (*ebx),
273 "=c" (*ecx),
274 "=d" (*edx)
275 : "0" (*eax), "2" (*ecx)
276 : "memory");
277 }
278
279 #define SET_XMM(__var, __xmm) \
280 asm volatile("movq %0, %%"#__xmm : : "r"(__var) : #__xmm)
281
set_xmm(int n,unsigned long val)282 static inline void set_xmm(int n, unsigned long val)
283 {
284 switch (n) {
285 case 0:
286 SET_XMM(val, xmm0);
287 break;
288 case 1:
289 SET_XMM(val, xmm1);
290 break;
291 case 2:
292 SET_XMM(val, xmm2);
293 break;
294 case 3:
295 SET_XMM(val, xmm3);
296 break;
297 case 4:
298 SET_XMM(val, xmm4);
299 break;
300 case 5:
301 SET_XMM(val, xmm5);
302 break;
303 case 6:
304 SET_XMM(val, xmm6);
305 break;
306 case 7:
307 SET_XMM(val, xmm7);
308 break;
309 }
310 }
311
312 typedef unsigned long v1di __attribute__ ((vector_size (8)));
get_xmm(int n)313 static inline unsigned long get_xmm(int n)
314 {
315 assert(n >= 0 && n <= 7);
316
317 register v1di xmm0 __asm__("%xmm0");
318 register v1di xmm1 __asm__("%xmm1");
319 register v1di xmm2 __asm__("%xmm2");
320 register v1di xmm3 __asm__("%xmm3");
321 register v1di xmm4 __asm__("%xmm4");
322 register v1di xmm5 __asm__("%xmm5");
323 register v1di xmm6 __asm__("%xmm6");
324 register v1di xmm7 __asm__("%xmm7");
325 switch (n) {
326 case 0:
327 return (unsigned long)xmm0;
328 case 1:
329 return (unsigned long)xmm1;
330 case 2:
331 return (unsigned long)xmm2;
332 case 3:
333 return (unsigned long)xmm3;
334 case 4:
335 return (unsigned long)xmm4;
336 case 5:
337 return (unsigned long)xmm5;
338 case 6:
339 return (unsigned long)xmm6;
340 case 7:
341 return (unsigned long)xmm7;
342 }
343 return 0;
344 }
345
346 bool is_intel_cpu(void);
347
348 struct kvm_x86_state;
349 struct kvm_x86_state *vcpu_save_state(struct kvm_vm *vm, uint32_t vcpuid);
350 void vcpu_load_state(struct kvm_vm *vm, uint32_t vcpuid,
351 struct kvm_x86_state *state);
352
353 struct kvm_msr_list *kvm_get_msr_index_list(void);
354 uint64_t kvm_get_feature_msr(uint64_t msr_index);
355 struct kvm_cpuid2 *kvm_get_supported_cpuid(void);
356
357 struct kvm_cpuid2 *vcpu_get_cpuid(struct kvm_vm *vm, uint32_t vcpuid);
358 void vcpu_set_cpuid(struct kvm_vm *vm, uint32_t vcpuid,
359 struct kvm_cpuid2 *cpuid);
360
361 struct kvm_cpuid_entry2 *
362 kvm_get_supported_cpuid_index(uint32_t function, uint32_t index);
363
364 static inline struct kvm_cpuid_entry2 *
kvm_get_supported_cpuid_entry(uint32_t function)365 kvm_get_supported_cpuid_entry(uint32_t function)
366 {
367 return kvm_get_supported_cpuid_index(function, 0);
368 }
369
370 uint64_t vcpu_get_msr(struct kvm_vm *vm, uint32_t vcpuid, uint64_t msr_index);
371 int _vcpu_set_msr(struct kvm_vm *vm, uint32_t vcpuid, uint64_t msr_index,
372 uint64_t msr_value);
373 void vcpu_set_msr(struct kvm_vm *vm, uint32_t vcpuid, uint64_t msr_index,
374 uint64_t msr_value);
375
376 uint32_t kvm_get_cpuid_max_basic(void);
377 uint32_t kvm_get_cpuid_max_extended(void);
378 void kvm_get_cpu_address_width(unsigned int *pa_bits, unsigned int *va_bits);
379
380 struct ex_regs {
381 uint64_t rax, rcx, rdx, rbx;
382 uint64_t rbp, rsi, rdi;
383 uint64_t r8, r9, r10, r11;
384 uint64_t r12, r13, r14, r15;
385 uint64_t vector;
386 uint64_t error_code;
387 uint64_t rip;
388 uint64_t cs;
389 uint64_t rflags;
390 };
391
392 void vm_init_descriptor_tables(struct kvm_vm *vm);
393 void vcpu_init_descriptor_tables(struct kvm_vm *vm, uint32_t vcpuid);
394 void vm_handle_exception(struct kvm_vm *vm, int vector,
395 void (*handler)(struct ex_regs *));
396
397 /*
398 * set_cpuid() - overwrites a matching cpuid entry with the provided value.
399 * matches based on ent->function && ent->index. returns true
400 * if a match was found and successfully overwritten.
401 * @cpuid: the kvm cpuid list to modify.
402 * @ent: cpuid entry to insert
403 */
404 bool set_cpuid(struct kvm_cpuid2 *cpuid, struct kvm_cpuid_entry2 *ent);
405
406 uint64_t kvm_hypercall(uint64_t nr, uint64_t a0, uint64_t a1, uint64_t a2,
407 uint64_t a3);
408
409 struct kvm_cpuid2 *kvm_get_supported_hv_cpuid(void);
410 void vcpu_set_hv_cpuid(struct kvm_vm *vm, uint32_t vcpuid);
411 struct kvm_cpuid2 *vcpu_get_supported_hv_cpuid(struct kvm_vm *vm, uint32_t vcpuid);
412
413 /*
414 * Basic CPU control in CR0
415 */
416 #define X86_CR0_PE (1UL<<0) /* Protection Enable */
417 #define X86_CR0_MP (1UL<<1) /* Monitor Coprocessor */
418 #define X86_CR0_EM (1UL<<2) /* Emulation */
419 #define X86_CR0_TS (1UL<<3) /* Task Switched */
420 #define X86_CR0_ET (1UL<<4) /* Extension Type */
421 #define X86_CR0_NE (1UL<<5) /* Numeric Error */
422 #define X86_CR0_WP (1UL<<16) /* Write Protect */
423 #define X86_CR0_AM (1UL<<18) /* Alignment Mask */
424 #define X86_CR0_NW (1UL<<29) /* Not Write-through */
425 #define X86_CR0_CD (1UL<<30) /* Cache Disable */
426 #define X86_CR0_PG (1UL<<31) /* Paging */
427
428 #define APIC_DEFAULT_GPA 0xfee00000ULL
429
430 /* APIC base address MSR and fields */
431 #define MSR_IA32_APICBASE 0x0000001b
432 #define MSR_IA32_APICBASE_BSP (1<<8)
433 #define MSR_IA32_APICBASE_EXTD (1<<10)
434 #define MSR_IA32_APICBASE_ENABLE (1<<11)
435 #define MSR_IA32_APICBASE_BASE (0xfffff<<12)
436 #define GET_APIC_BASE(x) (((x) >> 12) << 12)
437
438 #define APIC_BASE_MSR 0x800
439 #define X2APIC_ENABLE (1UL << 10)
440 #define APIC_ID 0x20
441 #define APIC_LVR 0x30
442 #define GET_APIC_ID_FIELD(x) (((x) >> 24) & 0xFF)
443 #define APIC_TASKPRI 0x80
444 #define APIC_PROCPRI 0xA0
445 #define APIC_EOI 0xB0
446 #define APIC_SPIV 0xF0
447 #define APIC_SPIV_FOCUS_DISABLED (1 << 9)
448 #define APIC_SPIV_APIC_ENABLED (1 << 8)
449 #define APIC_ICR 0x300
450 #define APIC_DEST_SELF 0x40000
451 #define APIC_DEST_ALLINC 0x80000
452 #define APIC_DEST_ALLBUT 0xC0000
453 #define APIC_ICR_RR_MASK 0x30000
454 #define APIC_ICR_RR_INVALID 0x00000
455 #define APIC_ICR_RR_INPROG 0x10000
456 #define APIC_ICR_RR_VALID 0x20000
457 #define APIC_INT_LEVELTRIG 0x08000
458 #define APIC_INT_ASSERT 0x04000
459 #define APIC_ICR_BUSY 0x01000
460 #define APIC_DEST_LOGICAL 0x00800
461 #define APIC_DEST_PHYSICAL 0x00000
462 #define APIC_DM_FIXED 0x00000
463 #define APIC_DM_FIXED_MASK 0x00700
464 #define APIC_DM_LOWEST 0x00100
465 #define APIC_DM_SMI 0x00200
466 #define APIC_DM_REMRD 0x00300
467 #define APIC_DM_NMI 0x00400
468 #define APIC_DM_INIT 0x00500
469 #define APIC_DM_STARTUP 0x00600
470 #define APIC_DM_EXTINT 0x00700
471 #define APIC_VECTOR_MASK 0x000FF
472 #define APIC_ICR2 0x310
473 #define SET_APIC_DEST_FIELD(x) ((x) << 24)
474
475 /* VMX_EPT_VPID_CAP bits */
476 #define VMX_EPT_VPID_CAP_AD_BITS (1ULL << 21)
477
478 #endif /* SELFTEST_KVM_PROCESSOR_H */
479