1/* 2 * Copyright © <2010>, Intel Corporation. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25// Modual name: ME_header.inc for Gen8 26// 27// Global symbols define 28// 29 30/* 31 * Constant 32 */ 33define(`VME_MESSAGE_TYPE_INTER', `1') 34define(`VME_MESSAGE_TYPE_INTRA', `2') 35define(`VME_MESSAGE_TYPE_MIXED', `3') 36 37define(`VME_SIC_MESSAGE_TYPE', `1') 38define(`VME_IME_MESSAGE_TYPE', `2') 39define(`VME_FBR_MESSAGE_TYPE', `3') 40 41define(`BLOCK_32X1', `0x0000001F') 42define(`BLOCK_4X16', `0x000F0003') 43define(`BLOCK_8X4', `0x00070003') 44 45define(`LUMA_INTRA_16x16_DISABLE', `0x1') 46define(`LUMA_INTRA_8x8_DISABLE', `0x2') 47define(`LUMA_INTRA_4x4_DISABLE', `0x4') 48 49define(`SUB_PART_8x4_DISABLE', `0x10') 50define(`SUB_PART_4x8_DISABLE', `0x20') 51 52define(`INTRA_PRED_AVAIL_FLAG_AE', `0x60') 53define(`INTRA_PRED_AVAIL_FLAG_B', `0x10') 54define(`INTRA_PRED_AVAIL_FLAG_C', `0x8') 55define(`INTRA_PRED_AVAIL_FLAG_D', `0x4') 56 57define(`BIND_IDX_VME', `0') 58define(`BIND_IDX_VME_REF0', `1') 59define(`BIND_IDX_VME_REF1', `2') 60define(`BIND_IDX_OUTPUT', `3') 61define(`BIND_IDX_INEP', `4') 62 63define(`SUB_PEL_MODE_INTEGER', `0x00000000') 64define(`SUB_PEL_MODE_HALF', `0x00001000') 65define(`SUB_PEL_MODE_QUARTER', `0x00003000') 66 67define(`INTER_SAD_NONE', `0x00000000') 68define(`INTER_SAD_HAAR', `0x00200000') 69 70define(`INTRA_SAD_NONE', `0x00000000') 71define(`INTRA_SAD_HAAR', `0x00800000') 72 73define(`INTER_PART_MASK', `0x00000000') 74define(`VP8_INTER_PART_MASK', `0x7e000000') 75 76define(`SEARCH_CTRL_SINGLE', `0x00000000') 77define(`SEARCH_CTRL_DUAL_START', `0x00000100') 78define(`SEARCH_CTRL_DUAL_RECORD', `0x00000300') 79define(`SEARCH_CTRL_DUAL_REFERENCE', `0x00000700') 80 81define(`REF_REGION_SIZE', `0x2830:UW') 82define(`MIN_REF_REGION_SIZE', `0x2020:UW') 83define(`DREF_REGION_SIZE', `0x2020:UW') 84 85define(`BI_SUB_MB_PART_MASK', `0x0c000000') 86define(`MAX_NUM_MV', `0x00000020') 87define(`FB_PRUNING_ENABLE', `0x40000000') 88 89define(`SEARCH_PATH_LEN', `0x00003030') 90define(`START_CENTER', `0x30000000') 91 92define(`ADAPTIVE_SEARCH_ENABLE', `0x00000002') 93define(`INTRA_PREDICTORE_MODE', `0x11111111:UD') 94 95define(`INTRA_PLANAR_MODE_MASK', `0x10001000:UD') 96 97define(`INTER_VME_OUTPUT_IN_OWS', `10') 98define(`INTER_VME_OUTPUT_MV_IN_OWS', `8') 99 100define(`INTRAMBFLAG_MASK', `0x00002000') 101define(`MVSIZE_UW_BASE', `0x0040') 102define(`MFC_MV32_BIT_SHIFT', `5') 103define(`CBP_DC_YUV_UW', `0x000E') 104 105define(`DC_HARR_ENABLE', `0x0000') 106define(`DC_HARR_DISABLE', `0x0020') 107 108define(`MV32_BIT_MASK', `0x0020') 109define(`MV32_BIT_SHIFT', `5') 110 111define(`OBW_CACHE_TYPE', `10') 112 113 114define(`OBW_MESSAGE_TYPE', `8') 115 116define(`OBW_BIND_IDX', `BIND_IDX_OUTPUT') 117 118define(`OBW_CONTROL_0', `0') /* 1 OWord, low 128 bits */ 119define(`OBW_CONTROL_1', `1') /* 1 OWord, high 128 bits */ 120define(`OBW_CONTROL_2', `2') /* 2 OWords */ 121define(`OBW_CONTROL_3', `3') /* 4 OWords */ 122define(`OBW_CONTROL_8', `4') /* 8 OWords */ 123 124define(`FBR_BME_ENABLE', `0x00000000') 125define(`FBR_BME_DISABLE', `0x00040000') 126 127define(`OBW_WRITE_COMMIT_CATEGORY', `0') /* category on Ivybridge */ 128 129 130define(`OBW_HEADER_PRESENT', `1') 131 132define(`W0_INTRA_MB_TYPE_MASK', `0x1F0000:UD') 133define(`W0_INTRA_MB_MODE_MASK', `0x30:UD') 134define(`W0_INTRA_8x8', `0x10:UD') 135define(`W0_TRANSFORM_8x8_FLAG', `0x8000:UD') 136 137/* GRF registers 138 * r0 header 139 * r1~r4 constant buffer (reserved) 140 * r5 inline data 141 * r6~r11 reserved 142 * r12 write back of VME message 143 * r13 write back of Oword Block Write 144 */ 145/* 146 * GRF 0 -- header 147 */ 148define(`thread_id_ub', `r0.20<0,1,0>:UB') /* thread id in payload */ 149 150/* 151 * GRF 1~4 -- Constant Buffer (reserved) 152 */ 153 154/* 155 * GRF 5 -- inline data 156 */ 157define(`inline_reg0', `r5') 158define(`w_in_mb_uw', `inline_reg0.2') 159define(`orig_xy_ub', `inline_reg0.0') 160define(`orig_x_ub', `inline_reg0.0') /* in macroblock */ 161define(`orig_y_ub', `inline_reg0.1') 162define(`transform_8x8_ub', `inline_reg0.4') 163define(`input_mb_intra_ub', `inline_reg0.5') 164define(`num_macroblocks', `inline_reg0.6') 165define(`quality_level_ub', `inline_reg0.7') 166 167/* 168 * GRF 6~11 -- reserved 169 */ 170 171/* 172 * GRF 12~15 -- write back for VME message 173 */ 174define(`vme_wb', `r12') 175define(`vme_wb0', `r12') 176define(`vme_wb1', `r13') 177define(`vme_wb2', `r14') 178define(`vme_wb3', `r15') 179define(`vme_wb4', `r16') 180define(`vme_wb5', `r17') 181define(`vme_wb6', `r18') 182define(`vme_ime_wb7', `r19') 183define(`vme_ime_wb8', `r20') 184define(`vme_ime_wb9', `r21') 185define(`vme_ime_wb10', `r22') 186 187 188/* 189 * GRF 24 -- write for VME output message 190 */ 191define(`obw_wb', `null<1>:W') 192define(`obw_wb_length', `0') 193 194 195/* 196 * GRF 28~30 -- Intra Neighbor Edge Pixels 197 */ 198define(`INEP_ROW', `r28') 199define(`INEP_COL0', `r29') 200define(`INEP_COL1', `r30') 201 202/* 203 * GRF 48~50 -- Chroma Neighbor Edge Pixels 204 */ 205define(`CHROMA_ROW', `r48') 206define(`CHROMA_COL', `r49') 207 208/* 209 * temporary registers 210 */ 211define(`tmp_reg0', `r32') 212define(`read0_header', `tmp_reg0') 213define(`tmp_reg1', `r33') 214define(`read1_header', `tmp_reg1') 215define(`tmp_reg2', `r34') 216define(`vme_m0', `tmp_reg2') 217define(`tmp_reg3', `r35') 218define(`vme_m1', `tmp_reg3') 219define(`intra_flag', `vme_m1.28') 220define(`intra_part_mask_ub', `vme_m1.28') 221define(`mb_intra_struct_ub', `vme_m1.29') 222define(`tmp_reg4', `r36') 223define(`obw_m0', `tmp_reg4') 224define(`tmp_reg5', `r37') 225define(`obw_m1', `tmp_reg5') 226define(`tmp_reg6', `r38') 227define(`obw_m2', `tmp_reg6') 228define(`tmp_reg7', `r39') 229define(`obw_m3', `tmp_reg7') 230define(`tmp_reg8', `r40') 231define(`obw_m4', `tmp_reg8') 232define(`tmp_reg9', `r41') 233define(`tmp_x_w', `tmp_reg9.0') 234define(`tmp_rega', `r42') 235define(`tmp_ud0', `tmp_rega.0') 236define(`tmp_ud1', `tmp_rega.4') 237define(`tmp_ud2', `tmp_rega.8') 238define(`tmp_ud3', `tmp_rega.12') 239define(`tmp_uw0', `tmp_rega.0') 240define(`tmp_uw1', `tmp_rega.2') 241define(`tmp_uw2', `tmp_rega.4') 242define(`tmp_uw3', `tmp_rega.6') 243define(`tmp_uw4', `tmp_rega.8') 244define(`tmp_uw5', `tmp_rega.10') 245define(`tmp_uw6', `tmp_rega.12') 246define(`tmp_uw7', `tmp_rega.14') 247 248define(`vme_m2', `r43') 249define(`vme_m3', `r44') 250/* 251 * MRF registers 252 */ 253 254define(`msg_ind', `64') 255define(`msg_reg0', `r64') 256define(`msg_reg1', `r65') 257define(`msg_reg2', `r66') 258define(`msg_reg3', `r67') 259define(`msg_reg4', `r68') 260define(`msg_reg5', `r69') 261define(`msg_reg6', `r70') 262define(`msg_reg7', `r71') 263define(`msg_reg8', `r72') 264define(`msg_reg9', `r73') 265 266define(`ts_msg_ind', `112') 267define(`ts_msg_reg0', `r112') 268/* 269 * VME message payload 270 */ 271 272define(`vme_intra_wb_length', `1') 273define(`vme_wb_length', `7') 274define(`sic_vme_msg_length', `8') 275define(`fbr_vme_msg_length', `8') 276define(`ime_vme_msg_length', `6') 277 278define(`vme_msg_ind', `msg_ind') 279define(`vme_msg_0', `msg_reg0') 280define(`vme_msg_1', `msg_reg1') 281define(`vme_msg_2', `msg_reg2') 282 283define(`vme_msg_3', `msg_reg3') 284define(`vme_msg_4', `msg_reg4') 285 286 287define(`vme_msg_5', `msg_reg5') 288define(`vme_msg_6', `msg_reg6') 289define(`vme_msg_7', `msg_reg7') 290define(`vme_msg_8', `msg_reg8') 291define(`vme_msg_9', `msg_reg9') 292 293define(`BIND_IDX_CBCR', `6') 294 295 296define(`LUMA_CHROMA_MODE', `0x0') 297define(`LUMA_INTRA_MODE', `0x1') 298define(`LUMA_INTRA_DISABLE', `0x2') 299 300define(`RETURN_REG', `r127.0') 301define(`RET_ARG', `r127.4') 302 303/* Now at most two registers are used for input parameter */ 304define(`INPUT_ARG0', `r125') 305define(`INPUT_ARG1', `r126') 306 307/* Two temporal registers are used in the function */ 308define(`TEMP_VAR0', `r123') 309define(`TEMP_VAR1', `r124') 310 311 312define(`OBR_MESSAGE_TYPE', `0') 313define(`OBR_CACHE_TYPE', `10') 314define(`OBR_BIND_IDX', `BIND_IDX_OUTPUT') 315 316define(`OBR_CONTROL_0', `0') /* 1 OWord, low 128 bits */ 317define(`OBR_CONTROL_1', `1') /* 1 OWord, high 128 bits */ 318define(`OBR_CONTROL_2', `2') /* 2 OWords */ 319define(`OBR_CONTROL_4', `3') /* 4 OWords */ 320define(`OBR_CONTROL_8', `4') /* 8 OWords */ 321define(`OBR_WRITE_COMMIT_CATEGORY', `0') /* category on SNB+ for Data port */ 322define(`OBR_HEADER_PRESENT', `1') 323 324define(`mb_hwdep', `r5.6') 325define(`MB_AVAIL', `1:d') 326define(`MB_PRED_FLAG', `1:w') 327 328define(`mb_pred_mode', `r85') 329define(`mb_mvp_ref', `r86') 330define(`mba_result', `r87') 331define(`mbb_result', `r88') 332define(`mbc_result', `r89') 333define(`mb_ind', `90') 334define(`mb_msg0', `r90') 335define(`mb_wb', `r91') 336define(`mb_intra_wb', `r91') 337define(`mb_inter_wb', `r92') 338define(`mb_mv0', `r93') 339define(`mb_mv1', `r94') 340define(`mb_mv2', `r95') 341define(`mb_mv3', `r96') 342define(`mb_ref', `r97') 343define(`mb_ref_win', `r84') 344 345define(`PRED_L0', `0x0':uw) 346define(`PRED_L1', `0x1':uw) 347define(`PRED_BI', `0x2':uw) 348define(`PRED_DIRECT', `0x3':uw) 349define(`PRED_MASK', `0x3':uw) 350 351/* The MAX search len per reference is 16 */ 352define(`DSEARCH_PATH_LEN', `0x00001212') 353define(`BI_WEIGHT', `0x20':uw) 354define(`DSTART_CENTER', `0x00000000') 355define(`INTER_MASK', `0x03') 356define(`INTER_16X16MODE', `0x0') 357define(`INTER_16X8MODE', `0x01') 358define(`INTER_8X16MODE', `0x02') 359define(`INTER_8X8MODE', `0x03') 360define(`INTER_BLOCK0', `0x0') 361define(`INTER_BLOCK1', `0x1') 362define(`INTER_BLOCK2', `0x2') 363define(`INTER_BLOCK3', `0x3') 364define(`INTER_16X8MODE', `0x01') 365define(`INTER_8X16MODE', `0x02') 366 367 368define(`OBR_MESSAGE_FENCE', `7') 369define(`OBR_MF_NOCOMMIT', `0') 370define(`OBR_MF_COMMIT', `0x20') 371 372define(`DEFAULT_QUALITY_LEVEL', `0x01') 373define(`HIGH_QUALITY_LEVEL', `DEFAULT_QUALITY_LEVEL') 374define(`LOW_QUALITY_LEVEL', `0x02') 375