1 /* 2 * Copyright (c) 2017-2021, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 //! \file mhw_vdbox_huc_generic.h 24 //! \brief MHW interface for constructing HUC commands for the Vdbox engine 25 //! \details Impelements shared Vdbox HUC command construction functions across all platforms as templates 26 //! 27 28 #ifndef _MHW_VDBOX_HUC_GENERIC_H_ 29 #define _MHW_VDBOX_HUC_GENERIC_H_ 30 31 #include "mhw_vdbox_huc_interface.h" 32 33 //! MHW Vdbox Huc generic interface 34 /*! 35 This class defines the shared Huc command construction functions across all platforms as templates 36 */ 37 template <class THucCmds, class TMiCmds> 38 class MhwVdboxHucInterfaceGeneric : public MhwVdboxHucInterface 39 { 40 protected: 41 //! 42 //! \brief Constructor 43 //! MhwVdboxHucInterfaceGeneric(PMOS_INTERFACE osInterface,MhwMiInterface * miInterface,MhwCpInterface * cpInterface)44 MhwVdboxHucInterfaceGeneric( 45 PMOS_INTERFACE osInterface, 46 MhwMiInterface *miInterface, 47 MhwCpInterface *cpInterface) : 48 MhwVdboxHucInterface(osInterface, miInterface, cpInterface) 49 { 50 MHW_FUNCTION_ENTER; 51 } 52 53 //! 54 //! \brief Destructor 55 //! ~MhwVdboxHucInterfaceGeneric()56 virtual ~MhwVdboxHucInterfaceGeneric() {} 57 58 protected: GetHucStateCommandSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize,PMHW_VDBOX_STATE_CMDSIZE_PARAMS params)59 MOS_STATUS GetHucStateCommandSize( 60 uint32_t mode, 61 uint32_t *commandsSize, 62 uint32_t *patchListSize, 63 PMHW_VDBOX_STATE_CMDSIZE_PARAMS params) 64 { 65 MHW_FUNCTION_ENTER; 66 67 uint32_t maxSize = 0; 68 uint32_t patchListMaxSize = 0; 69 uint32_t standard = CodecHal_GetStandardFromMode(mode); 70 uint32_t numSlices = 1; 71 uint32_t numStoreDataImm = 1; 72 uint32_t numStoreReg = 1; 73 74 MHW_MI_CHK_NULL(commandsSize); 75 MHW_MI_CHK_NULL(patchListSize); 76 MHW_MI_CHK_NULL(params); 77 78 if(params->uNumStoreDataImm) 79 { 80 numStoreDataImm = params->uNumStoreDataImm; 81 } 82 if(params->uNumStoreReg) 83 { 84 numStoreReg = params->uNumStoreReg; 85 } 86 87 if (mode == CODECHAL_DECODE_MODE_HEVCVLD && params->bShortFormat) 88 { 89 numSlices = CODECHAL_HEVC_MAX_NUM_SLICES_LVL_6; 90 numStoreDataImm = 2; 91 numStoreReg = 2; 92 93 maxSize += 94 2 * TMiCmds::MI_CONDITIONAL_BATCH_BUFFER_END_CMD::byteSize; 95 96 patchListMaxSize += 97 2 * PATCH_LIST_COMMAND(MI_CONDITIONAL_BATCH_BUFFER_END_CMD); 98 } 99 else if (standard == CODECHAL_CENC) 100 { 101 numStoreDataImm = 3; 102 numStoreReg = 3; 103 104 maxSize += 105 TMiCmds::MI_FLUSH_DW_CMD::byteSize * 2 + 106 TMiCmds::MI_BATCH_BUFFER_END_CMD::byteSize; 107 108 patchListMaxSize += 109 PATCH_LIST_COMMAND(MI_FLUSH_DW_CMD) * 2; 110 111 } 112 else if (mode == CODECHAL_ENCODE_MODE_VP9) 113 { 114 // for huc status 2 register and semaphore signal and reset 115 numStoreDataImm = 3; 116 117 maxSize += 118 TMiCmds::MI_BATCH_BUFFER_END_CMD::byteSize + 119 TMiCmds::MI_FLUSH_DW_CMD::byteSize; 120 121 patchListMaxSize += 122 PATCH_LIST_COMMAND(MI_FLUSH_DW_CMD); 123 } 124 else if (mode == CODECHAL_ENCODE_MODE_AVC) 125 { 126 numStoreDataImm = 2; 127 numStoreReg = 2; 128 129 maxSize += 130 2 * TMiCmds::MI_CONDITIONAL_BATCH_BUFFER_END_CMD::byteSize; 131 132 patchListMaxSize += 133 2 * PATCH_LIST_COMMAND(MI_CONDITIONAL_BATCH_BUFFER_END_CMD); 134 } 135 136 maxSize += 137 THucCmds::HUC_PIPE_MODE_SELECT_CMD::byteSize + 138 THucCmds::HUC_IMEM_STATE_CMD::byteSize + 139 THucCmds::HUC_DMEM_STATE_CMD::byteSize + 140 THucCmds::HUC_VIRTUAL_ADDR_STATE_CMD::byteSize + 141 THucCmds::HUC_IND_OBJ_BASE_ADDR_STATE_CMD::byteSize + 142 numSlices * THucCmds::HUC_STREAM_OBJECT_CMD::byteSize + 143 numSlices * THucCmds::HUC_START_CMD::byteSize + 144 numStoreDataImm * TMiCmds::MI_STORE_DATA_IMM_CMD::byteSize + 145 numStoreReg * TMiCmds::MI_STORE_REGISTER_MEM_CMD::byteSize; 146 147 if(params->uNumMfxWait) 148 { 149 maxSize += 150 params->uNumMfxWait * TMiCmds::MFX_WAIT_CMD::byteSize; 151 } 152 153 patchListMaxSize += 154 PATCH_LIST_COMMAND(HUC_PIPE_MODE_SELECT_CMD) + 155 PATCH_LIST_COMMAND(HUC_IMEM_STATE_CMD) + 156 PATCH_LIST_COMMAND(HUC_DMEM_STATE_CMD) + 157 PATCH_LIST_COMMAND(HUC_VIRTUAL_ADDR_STATE_CMD) + 158 PATCH_LIST_COMMAND(HUC_IND_OBJ_BASE_ADDR_STATE_CMD) + 159 numSlices * PATCH_LIST_COMMAND(HUC_STREAM_OBJECT_CMD) + 160 numSlices * PATCH_LIST_COMMAND(HUC_START_CMD) + 161 numStoreDataImm * PATCH_LIST_COMMAND(MI_STORE_DATA_IMM_CMD) + 162 numStoreReg * PATCH_LIST_COMMAND(MI_STORE_REGISTER_MEM_CMD); 163 164 if(params->uNumAddConBBEnd) 165 { 166 maxSize += 167 params->uNumAddConBBEnd * TMiCmds::MI_CONDITIONAL_BATCH_BUFFER_END_CMD::byteSize; 168 169 patchListMaxSize += 170 params->uNumAddConBBEnd * PATCH_LIST_COMMAND(MI_CONDITIONAL_BATCH_BUFFER_END_CMD); 171 } 172 if(params->uNumMiCopy) 173 { 174 maxSize += 175 params->uNumMiCopy * TMiCmds::MI_COPY_MEM_MEM_CMD::byteSize; 176 177 patchListMaxSize += 178 params->uNumMiCopy * PATCH_LIST_COMMAND(MI_COPY_MEM_MEM_CMD); 179 } 180 if(params->uNumMiFlush) 181 { 182 maxSize += 183 params->uNumMiFlush * TMiCmds::MI_FLUSH_DW_CMD::byteSize; 184 185 patchListMaxSize += 186 params->uNumMiFlush * PATCH_LIST_COMMAND(MI_FLUSH_DW_CMD); 187 } 188 189 if (params->bHucDummyStream || params->bPerformHucStreamOut) 190 { 191 uint32_t dummyTimes = params->bPerformHucStreamOut ? 2: 1; 192 for (uint32_t i = 0; i < dummyTimes; i++) 193 { 194 maxSize += 195 THucCmds::HUC_PIPE_MODE_SELECT_CMD::byteSize + 196 THucCmds::HUC_IMEM_STATE_CMD::byteSize + 197 THucCmds::HUC_DMEM_STATE_CMD::byteSize + 198 THucCmds::HUC_VIRTUAL_ADDR_STATE_CMD::byteSize + 199 THucCmds::HUC_IND_OBJ_BASE_ADDR_STATE_CMD::byteSize + 200 THucCmds::HUC_STREAM_OBJECT_CMD::byteSize + 201 THucCmds::HUC_START_CMD::byteSize + 202 TMiCmds::MI_FLUSH_DW_CMD::byteSize; 203 204 patchListMaxSize += 205 PATCH_LIST_COMMAND(HUC_PIPE_MODE_SELECT_CMD) + 206 PATCH_LIST_COMMAND(HUC_IMEM_STATE_CMD) + 207 PATCH_LIST_COMMAND(HUC_DMEM_STATE_CMD) + 208 PATCH_LIST_COMMAND(HUC_VIRTUAL_ADDR_STATE_CMD) + 209 PATCH_LIST_COMMAND(HUC_IND_OBJ_BASE_ADDR_STATE_CMD) + 210 PATCH_LIST_COMMAND(HUC_STREAM_OBJECT_CMD) + 211 PATCH_LIST_COMMAND(HUC_START_CMD) + 212 PATCH_LIST_COMMAND(MI_FLUSH_DW_CMD); 213 } 214 if (params->bPerformHucStreamOut) 215 { 216 maxSize += 217 THucCmds::HUC_PIPE_MODE_SELECT_CMD::byteSize + 218 THucCmds::HUC_IND_OBJ_BASE_ADDR_STATE_CMD::byteSize + 219 THucCmds::HUC_STREAM_OBJECT_CMD::byteSize + 220 4 * TMiCmds::MI_FLUSH_DW_CMD::byteSize; 221 222 patchListMaxSize += 223 PATCH_LIST_COMMAND(HUC_PIPE_MODE_SELECT_CMD) + 224 PATCH_LIST_COMMAND(HUC_IND_OBJ_BASE_ADDR_STATE_CMD) + 225 PATCH_LIST_COMMAND(HUC_STREAM_OBJECT_CMD) + 226 4 * PATCH_LIST_COMMAND(MI_FLUSH_DW_CMD); 227 } 228 } 229 230 *commandsSize = maxSize; 231 *patchListSize = patchListMaxSize; 232 233 return MOS_STATUS_SUCCESS; 234 } 235 GetHucPrimitiveCommandSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize)236 MOS_STATUS GetHucPrimitiveCommandSize( 237 uint32_t mode, 238 uint32_t *commandsSize, 239 uint32_t *patchListSize) 240 { 241 MOS_STATUS eStatus = MOS_STATUS_SUCCESS; 242 243 MHW_FUNCTION_ENTER; 244 245 uint32_t maxSize = 0; 246 uint32_t patchListMaxSize = 0; 247 248 // Hal will handling the multiplication of cmd size instead of MHW 249 250 *commandsSize = maxSize; 251 *patchListSize = patchListMaxSize; 252 253 return eStatus; 254 } 255 AddHucPipeModeSelectCmd(MOS_COMMAND_BUFFER * cmdBuffer,MHW_VDBOX_PIPE_MODE_SELECT_PARAMS * params)256 MOS_STATUS AddHucPipeModeSelectCmd( 257 MOS_COMMAND_BUFFER *cmdBuffer, 258 MHW_VDBOX_PIPE_MODE_SELECT_PARAMS *params) 259 { 260 MHW_MI_CHK_NULL(cmdBuffer); 261 MHW_MI_CHK_NULL(params); 262 263 typename THucCmds::HUC_PIPE_MODE_SELECT_CMD cmd; 264 265 if (!params->disableProtectionSetting) 266 { 267 MHW_MI_CHK_STATUS(m_cpInterface->SetProtectionSettingsForHucPipeModeSelect((uint32_t*)&cmd)); 268 } 269 270 cmd.DW1.IndirectStreamOutEnable = params->bStreamOutEnabled; 271 cmd.DW2.MediaSoftResetCounterPer1000Clocks = params->dwMediaSoftResetCounterValue; 272 273 MHW_MI_CHK_STATUS(Mos_AddCommand(cmdBuffer, &cmd, cmd.byteSize)); 274 275 return MOS_STATUS_SUCCESS; 276 } 277 AddHucImemStateCmd(MOS_COMMAND_BUFFER * cmdBuffer,MHW_VDBOX_HUC_IMEM_STATE_PARAMS * params)278 MOS_STATUS AddHucImemStateCmd( 279 MOS_COMMAND_BUFFER *cmdBuffer, 280 MHW_VDBOX_HUC_IMEM_STATE_PARAMS *params) 281 { 282 MHW_MI_CHK_NULL(cmdBuffer); 283 MHW_MI_CHK_NULL(params); 284 285 typename THucCmds::HUC_IMEM_STATE_CMD cmd; 286 287 cmd.DW4.HucFirmwareDescriptor = params->dwKernelDescriptor; 288 289 MHW_MI_CHK_STATUS(Mos_AddCommand(cmdBuffer, &cmd, cmd.byteSize)); 290 291 return MOS_STATUS_SUCCESS; 292 } 293 AddHucDmemStateCmd(MOS_COMMAND_BUFFER * cmdBuffer,MHW_VDBOX_HUC_DMEM_STATE_PARAMS * params)294 MOS_STATUS AddHucDmemStateCmd( 295 MOS_COMMAND_BUFFER *cmdBuffer, 296 MHW_VDBOX_HUC_DMEM_STATE_PARAMS *params) 297 { 298 299 MHW_MI_CHK_NULL(cmdBuffer); 300 MHW_MI_CHK_NULL(params); 301 302 MHW_RESOURCE_PARAMS resourceParams; 303 MOS_ZeroMemory(&resourceParams, sizeof(resourceParams)); 304 resourceParams.dwLsbNum = MHW_VDBOX_HUC_GENERAL_STATE_SHIFT; 305 resourceParams.HwCommandType = MOS_HUC_DMEM; 306 307 typename THucCmds::HUC_DMEM_STATE_CMD cmd; 308 309 if (params->presHucDataSource) 310 { 311 cmd.HucDataSourceAttributes.DW0.Value |= m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_SURFACE_UNCACHED].Value; 312 resourceParams.presResource = params->presHucDataSource; 313 resourceParams.dwOffset = 0; 314 resourceParams.pdwCmd = (cmd.HucDataSourceBaseAddress.DW0_1.Value); 315 resourceParams.dwLocationInCmd = 1; 316 resourceParams.bIsWritable = false; 317 318 MHW_MI_CHK_STATUS(AddResourceToCmd( 319 m_osInterface, 320 cmdBuffer, 321 &resourceParams)); 322 323 // set HuC data destination address 324 cmd.DW4.HucDataDestinationBaseAddress = params->dwDmemOffset >> MHW_VDBOX_HUC_GENERAL_STATE_SHIFT; 325 326 // set data length 327 cmd.DW5.HucDataLength = params->dwDataLength >> MHW_VDBOX_HUC_GENERAL_STATE_SHIFT; 328 } 329 330 MHW_MI_CHK_STATUS(Mos_AddCommand(cmdBuffer, &cmd, cmd.byteSize)); 331 332 return MOS_STATUS_SUCCESS; 333 } 334 AddHucVirtualAddrStateCmd(MOS_COMMAND_BUFFER * cmdBuffer,MHW_VDBOX_HUC_VIRTUAL_ADDR_PARAMS * params)335 MOS_STATUS AddHucVirtualAddrStateCmd( 336 MOS_COMMAND_BUFFER *cmdBuffer, 337 MHW_VDBOX_HUC_VIRTUAL_ADDR_PARAMS *params) 338 { 339 MHW_MI_CHK_NULL(cmdBuffer); 340 MHW_MI_CHK_NULL(params); 341 342 MHW_RESOURCE_PARAMS resourceParams; 343 344 // set up surface 0~15 345 MOS_ZeroMemory(&resourceParams, sizeof(resourceParams)); 346 resourceParams.dwLsbNum = MHW_VDBOX_HUC_UPPER_BOUND_STATE_SHIFT; 347 resourceParams.HwCommandType = MOS_HUC_VIRTUAL_ADDR; 348 349 typename THucCmds::HUC_VIRTUAL_ADDR_STATE_CMD cmd; 350 351 for (int i = 0; i < 16; i++) 352 { 353 if (params->regionParams[i].presRegion) 354 { 355 cmd.HucVirtualAddressRegion[i].HucSurfaceVirtualaddrregion015.DW0.Value |= 356 m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_HUC_VIRTUAL_ADDR_REGION_BUFFER_CODEC].Value; 357 resourceParams.presResource = params->regionParams[i].presRegion; 358 resourceParams.dwOffset = params->regionParams[i].dwOffset; 359 resourceParams.bIsWritable = params->regionParams[i].isWritable; 360 resourceParams.pdwCmd = cmd.HucVirtualAddressRegion[i].HucSurfaceBaseAddressVirtualaddrregion015.DW0_1.Value; 361 resourceParams.dwLocationInCmd = 1 + (i * 3); 362 363 MHW_MI_CHK_STATUS(AddResourceToCmd( 364 m_osInterface, 365 cmdBuffer, 366 &resourceParams)); 367 } 368 } 369 370 MHW_MI_CHK_STATUS(Mos_AddCommand(cmdBuffer, &cmd, cmd.byteSize)); 371 372 return MOS_STATUS_SUCCESS; 373 } 374 AddHucIndObjBaseAddrStateCmd(MOS_COMMAND_BUFFER * cmdBuffer,MHW_VDBOX_IND_OBJ_BASE_ADDR_PARAMS * params)375 MOS_STATUS AddHucIndObjBaseAddrStateCmd( 376 MOS_COMMAND_BUFFER *cmdBuffer, 377 MHW_VDBOX_IND_OBJ_BASE_ADDR_PARAMS *params) 378 { 379 MHW_MI_CHK_NULL(cmdBuffer); 380 MHW_MI_CHK_NULL(params); 381 382 MHW_RESOURCE_PARAMS resourceParams; 383 384 // base address of the bit-stream buffer 385 MOS_ZeroMemory(&resourceParams, sizeof(resourceParams)); 386 resourceParams.dwLsbNum = MHW_VDBOX_HUC_UPPER_BOUND_STATE_SHIFT; 387 resourceParams.dwUpperBoundLocationOffsetFromCmd = 3; 388 resourceParams.HwCommandType = MOS_HUC_IND_OBJ_BASE_ADDR; 389 390 typename THucCmds::HUC_IND_OBJ_BASE_ADDR_STATE_CMD cmd; 391 392 if (params->presDataBuffer) 393 { 394 cmd.HucIndirectStreamInObjectbaseAttributes.DW0.Value |= m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_SURFACE_UNCACHED].Value; 395 resourceParams.presResource = params->presDataBuffer; 396 resourceParams.dwOffset = params->dwDataOffset; 397 resourceParams.pdwCmd = cmd.HucIndirectStreamInObjectbaseAddress.DW0_1.Value; 398 resourceParams.dwLocationInCmd = 1; 399 resourceParams.bIsWritable = false; 400 resourceParams.dwSize = params->dwDataSize; 401 402 MHW_MI_CHK_STATUS(AddResourceToCmd( 403 m_osInterface, 404 cmdBuffer, 405 &resourceParams)); 406 } 407 408 if (params->presStreamOutObjectBuffer) 409 { 410 // base address of the stream out buffer 411 cmd.HucIndirectStreamOutObjectbaseAttributes.DW0.Value |= m_cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_SURFACE_UNCACHED].Value; 412 resourceParams.presResource = params->presStreamOutObjectBuffer; 413 resourceParams.dwOffset = params->dwStreamOutObjectOffset; 414 resourceParams.pdwCmd = cmd.HucIndirectStreamOutObjectbaseAddress.DW0_1.Value; 415 resourceParams.dwLocationInCmd = 6; 416 resourceParams.bIsWritable = true; 417 resourceParams.dwSize = params->dwStreamOutObjectSize; 418 419 MHW_MI_CHK_STATUS(AddResourceToCmd( 420 m_osInterface, 421 cmdBuffer, 422 &resourceParams)); 423 } 424 425 MHW_MI_CHK_STATUS(Mos_AddCommand(cmdBuffer, &cmd, cmd.byteSize)); 426 427 return MOS_STATUS_SUCCESS; 428 } 429 AddHucStreamObjectCmd(MOS_COMMAND_BUFFER * cmdBuffer,MHW_VDBOX_HUC_STREAM_OBJ_PARAMS * params)430 MOS_STATUS AddHucStreamObjectCmd( 431 MOS_COMMAND_BUFFER *cmdBuffer, 432 MHW_VDBOX_HUC_STREAM_OBJ_PARAMS *params) 433 { 434 MHW_MI_CHK_NULL(cmdBuffer); 435 MHW_MI_CHK_NULL(params); 436 437 typename THucCmds::HUC_STREAM_OBJECT_CMD cmd; 438 439 cmd.DW1.IndirectStreamInDataLength = params->dwIndStreamInLength; 440 cmd.DW2.IndirectStreamInStartAddress = params->dwIndStreamInStartAddrOffset; 441 cmd.DW2.HucProcessing = params->bHucProcessing; 442 cmd.DW3.IndirectStreamOutStartAddress = params->dwIndStreamOutStartAddrOffset; 443 cmd.DW4.HucBitstreamEnable = params->bStreamInEnable; 444 cmd.DW4.StreamOut = params->bStreamOutEnable; 445 cmd.DW4.EmulationPreventionByteRemoval = params->bEmulPreventionByteRemoval; 446 cmd.DW4.StartCodeSearchEngine = params->bStartCodeSearchEngine; 447 cmd.DW4.Drmlengthmode = params->bLengthModeEnabled; 448 cmd.DW4.StartCodeByte2 = params->ucStartCodeByte2; 449 cmd.DW4.StartCodeByte1 = params->ucStartCodeByte1; 450 cmd.DW4.StartCodeByte0 = params->ucStartCodeByte0; 451 452 MHW_MI_CHK_STATUS(Mos_AddCommand(cmdBuffer, &cmd, cmd.byteSize)); 453 454 return MOS_STATUS_SUCCESS; 455 } 456 AddHucStartCmd(MOS_COMMAND_BUFFER * cmdBuffer,bool lastStreamObject)457 MOS_STATUS AddHucStartCmd( 458 MOS_COMMAND_BUFFER *cmdBuffer, 459 bool lastStreamObject) 460 { 461 MHW_MI_CHK_NULL(cmdBuffer); 462 463 typename THucCmds::HUC_START_CMD cmd; 464 465 // set last stream object or not 466 cmd.DW1.Laststreamobject = (lastStreamObject != 0); 467 468 MHW_MI_CHK_STATUS(Mos_AddCommand(cmdBuffer, &cmd, cmd.byteSize)); 469 470 return MOS_STATUS_SUCCESS; 471 } 472 }; 473 474 #endif 475