1 /*===================== begin_copyright_notice ================================== 2 3 Copyright (c) 2018-2019, Intel Corporation 4 5 Permission is hereby granted, free of charge, to any person obtaining a 6 copy of this software and associated documentation files (the "Software"), 7 to deal in the Software without restriction, including without limitation 8 the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 and/or sell copies of the Software, and to permit persons to whom the 10 Software is furnished to do so, subject to the following conditions: 11 12 The above copyright notice and this permission notice shall be included 13 in all copies or substantial portions of the Software. 14 15 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 16 OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 OTHER DEALINGS IN THE SOFTWARE. 22 23 ======================= end_copyright_notice ==================================*/ 24 //! 25 //! \file mhw_vdbox_hcp_hwcmd_g12_X.h 26 //! \brief Auto-generated constructors for MHW and states. 27 //! \details This file may not be included outside of g12_X as other components 28 //! should use MHW interface to interact with MHW commands and states. 29 //! 30 31 // DO NOT EDIT 32 33 #ifndef __MHW_VDBOX_HCP_HWCMD_G12_X_H__ 34 #define __MHW_VDBOX_HCP_HWCMD_G12_X_H__ 35 36 #pragma once 37 #pragma pack(1) 38 39 #include <cstdint> 40 #include <cstddef> 41 42 class mhw_vdbox_hcp_g12_X 43 { 44 public: 45 // Internal Macros 46 #define __CODEGEN_MAX(_a, _b) (((_a) > (_b)) ? (_a) : (_b)) 47 #define __CODEGEN_BITFIELD(l, h) (h) - (l) + 1 48 #define __CODEGEN_OP_LENGTH_BIAS 2 49 #define __CODEGEN_OP_LENGTH(x) (uint32_t)((__CODEGEN_MAX(x, __CODEGEN_OP_LENGTH_BIAS)) - __CODEGEN_OP_LENGTH_BIAS) 50 GetOpLength(uint32_t uiLength)51 static uint32_t GetOpLength(uint32_t uiLength) { return __CODEGEN_OP_LENGTH(uiLength); } 52 53 //! 54 //! \brief MEMORYADDRESSATTRIBUTES 55 //! \details 56 //! This field controls the priority of arbitration used in the GAC/GAM 57 //! pipeline for this surface. It defines the attributes for VDBOX addresses 58 //! on BDW+. 59 //! 60 struct MEMORYADDRESSATTRIBUTES_CMD 61 { 62 union 63 { 64 struct 65 { 66 uint32_t Reserved0 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 67 uint32_t BaseAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< Base Address - Index to Memory Object Control State (MOCS) Tables 68 uint32_t BaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< Base Address - Arbitration Priority Control 69 uint32_t BaseAddressMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< Base Address - Memory Compression Enable 70 uint32_t CompressionType : __CODEGEN_BITFIELD(10, 10) ; //!< COMPRESSION_TYPE 71 uint32_t Reserved11 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 72 uint32_t BaseAddressRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 73 uint32_t BaseAddressTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< BASE_ADDRESS_TILED_RESOURCE_MODE 74 uint32_t Reserved15 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 75 }; 76 uint32_t Value; 77 } DW0; 78 79 //! \name Local enumerations 80 81 //! \brief COMPRESSION_TYPE 82 //! \details 83 //! Indicates if buffer is render/media compressed. 84 enum COMPRESSION_TYPE 85 { 86 COMPRESSION_TYPE_MEDIACOMPRESSIONENABLE = 0, //!< No additional details 87 COMPRESSION_TYPE_RENDERCOMPRESSIONENABLE = 1, //!< No additional details 88 }; 89 90 //! \brief BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 91 //! \details 92 //! This field controls if the Row Store is going to store inside Media 93 //! Cache (rowstore cache) or to LLC. 94 enum BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 95 { 96 BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED0 = 0, //!< Buffer going to LLC. 97 BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED1 = 1, //!< Buffer going to Internal Media Storage. 98 }; 99 100 //! \brief BASE_ADDRESS_TILED_RESOURCE_MODE 101 //! \details 102 //! <b>For Media Surfaces:</b> This field specifies the tiled resource mode. 103 enum BASE_ADDRESS_TILED_RESOURCE_MODE 104 { 105 BASE_ADDRESS_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< TileY resources 106 BASE_ADDRESS_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 107 BASE_ADDRESS_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 108 }; 109 110 //! \name Initializations 111 112 //! \brief Explicit member initialization function 113 MEMORYADDRESSATTRIBUTES_CMD(); 114 115 static const size_t dwSize = 1; 116 static const size_t byteSize = 4; 117 }; 118 119 //! 120 //! \brief SPLITBASEADDRESS64BYTEALIGNED 121 //! \details 122 //! Specifies a 64-bit (48-bit canonical) 64-byte aligned memory base 123 //! address. 124 //! 125 struct SPLITBASEADDRESS64BYTEALIGNED_CMD 126 { 127 union 128 { 129 struct 130 { 131 uint64_t Reserved0 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 132 uint64_t Graphicsaddress476 : __CODEGEN_BITFIELD( 6, 47) ; //!< GraphicsAddress47-6 133 uint64_t Reserved48 : __CODEGEN_BITFIELD(48, 63) ; //!< Reserved 134 }; 135 uint32_t Value[2]; 136 } DW0_1; 137 138 //! \name Local enumerations 139 140 //! \name Initializations 141 142 //! \brief Explicit member initialization function 143 SPLITBASEADDRESS64BYTEALIGNED_CMD(); 144 145 static const size_t dwSize = 2; 146 static const size_t byteSize = 8; 147 }; 148 149 //! 150 //! \brief SPLITBASEADDRESS4KBYTEALIGNED 151 //! \details 152 //! Specifies a 64-bit (48-bit canonical) 4K-byte aligned memory base 153 //! address. GraphicsAddress is a 64-bit value [63:0], but only a portion of 154 //! it is used by hardware. The upper reserved bits are ignored and MBZ. 155 //! 156 struct SPLITBASEADDRESS4KBYTEALIGNED_CMD 157 { 158 union 159 { 160 struct 161 { 162 uint64_t Reserved0 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 163 uint64_t Graphicsaddress4712 : __CODEGEN_BITFIELD(12, 47) ; //!< GraphicsAddress47-12 164 uint64_t Reserved48 : __CODEGEN_BITFIELD(48, 63) ; //!< Reserved 165 }; 166 uint32_t Value[2]; 167 } DW0_1; 168 169 //! \name Local enumerations 170 171 //! \name Initializations 172 173 //! \brief Explicit member initialization function 174 SPLITBASEADDRESS4KBYTEALIGNED_CMD(); 175 176 static const size_t dwSize = 2; 177 static const size_t byteSize = 8; 178 }; 179 180 //! 181 //! \brief HCP_PIPE_MODE_SELECT 182 //! \details 183 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 184 //! Commands. Each HCP command has assigned a media instruction command as 185 //! defined in DWord 0, BitField 22:16. 186 //! 187 //! The workload for the HCP is based upon a single frame decode. There are 188 //! no states saved between frame decodes in the HCP. Once the bit stream 189 //! DMA is configured with the HCP_BSD_OBJECT command, and the bit stream is 190 //! presented to the HCP, the frame decode will begin. The 191 //! HCP_PIPE_MODE_SELECT command is responsible for general pipeline level 192 //! configuration that would normally be set once for a single stream encode 193 //! or decode and would not be modified on a frame workload basis. This is a 194 //! picture level state command and is shared by both encoding and decoding 195 //! processes. 196 //! 197 struct HCP_PIPE_MODE_SELECT_CMD 198 { 199 union 200 { 201 struct 202 { 203 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 204 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 205 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 206 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 207 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 208 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 209 }; 210 uint32_t Value; 211 } DW0; 212 union 213 { 214 struct 215 { 216 uint32_t CodecSelect : __CODEGEN_BITFIELD( 0, 0) ; //!< CODEC_SELECT 217 uint32_t DeblockerStreamoutEnable : __CODEGEN_BITFIELD( 1, 1) ; //!< DEBLOCKER_STREAMOUT_ENABLE 218 uint32_t PakPipelineStreamoutEnable : __CODEGEN_BITFIELD( 2, 2) ; //!< PAK_PIPELINE_STREAMOUT_ENABLE 219 uint32_t PicStatusErrorReportEnable : __CODEGEN_BITFIELD( 3, 3) ; //!< PIC_STATUSERROR_REPORT_ENABLE 220 uint32_t Reserved36 : __CODEGEN_BITFIELD( 4, 4) ; //!< Reserved 221 uint32_t CodecStandardSelect : __CODEGEN_BITFIELD( 5, 7) ; //!< CODEC_STANDARD_SELECT 222 uint32_t Reserved40 : __CODEGEN_BITFIELD( 8, 8) ; //!< Reserved 223 uint32_t AdvancedRateControlEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< Advanced Rate Control Enable 224 uint32_t VdencMode : __CODEGEN_BITFIELD(10, 10) ; //!< VDEnc_Mode 225 uint32_t RdoqEnabledFlag : __CODEGEN_BITFIELD(11, 11) ; //!< RDOQ_ENABLED_FLAG 226 uint32_t PakFrameLevelStreamoutEnable : __CODEGEN_BITFIELD(12, 12) ; //!< PAK Frame Level StreamOut enable 227 uint32_t MultiEngineMode : __CODEGEN_BITFIELD(13, 14) ; //!< MULTI_ENGINE_MODE 228 uint32_t PipeWorkingMode : __CODEGEN_BITFIELD(15, 16) ; //!< PIPE_WORKING_MODE 229 uint32_t TileBasedEngine : __CODEGEN_BITFIELD(17, 17) ; //!< Tile Based Engine 230 uint32_t PrefetchDisable : __CODEGEN_BITFIELD(18, 18) ; //!< Prefetch Disable 231 uint32_t Vp9DynamicScalingEnable : __CODEGEN_BITFIELD(19, 19) ; //!< VP9 Dynamic scaling enable 232 uint32_t Reserved52 : __CODEGEN_BITFIELD(20, 22) ; //!< Reserved 233 uint32_t MotionCompMemoryTrackerCounterEnable : __CODEGEN_BITFIELD(23, 23) ; //!< Motion Comp Memory Tracker Counter Enable 234 uint32_t Reserved56 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 235 }; 236 uint32_t Value; 237 } DW1; 238 union 239 { 240 struct 241 { 242 uint32_t MediaSoftResetCounterPer1000Clocks ; //!< MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS 243 }; 244 uint32_t Value; 245 } DW2; 246 union 247 { 248 struct 249 { 250 uint32_t PicStatusErrorReportId ; //!< PIC_STATUSERROR_REPORT_ID 251 }; 252 uint32_t Value; 253 } DW3; 254 union 255 { 256 struct 257 { 258 uint32_t Reserved128 ; //!< Reserved 259 }; 260 uint32_t Value; 261 } DW4; 262 union 263 { 264 struct 265 { 266 uint32_t Reserved160 ; //!< Reserved 267 }; 268 uint32_t Value; 269 } DW5; 270 union 271 { 272 struct 273 { 274 uint32_t PhaseIndicator : __CODEGEN_BITFIELD( 0, 1) ; //!< PHASE_INDICATOR 275 uint32_t HevcSeparateTileProgramming : __CODEGEN_BITFIELD( 2, 2) ; //!< HEVC Separate Tile Programming 276 uint32_t FrameReconstructionDisable : __CODEGEN_BITFIELD( 3, 3) ; //!< Frame reconstruction disable 277 uint32_t Reserved196 : __CODEGEN_BITFIELD( 4, 31) ; //!< Reserved 278 }; 279 uint32_t Value; 280 } DW6; 281 282 //! \name Local enumerations 283 284 enum MEDIA_INSTRUCTION_COMMAND 285 { 286 MEDIA_INSTRUCTION_COMMAND_HCPPIPEMODESELECT = 0, //!< No additional details 287 }; 288 289 //! \brief MEDIA_INSTRUCTION_OPCODE 290 //! \details 291 //! Codec/Engine Name = HCP = 7h 292 enum MEDIA_INSTRUCTION_OPCODE 293 { 294 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 295 }; 296 297 enum PIPELINE_TYPE 298 { 299 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 300 }; 301 302 enum COMMAND_TYPE 303 { 304 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 305 }; 306 307 enum CODEC_SELECT 308 { 309 CODEC_SELECT_DECODE = 0, //!< No additional details 310 CODEC_SELECT_ENCODE = 1, //!< No additional details 311 }; 312 313 //! \brief DEBLOCKER_STREAMOUT_ENABLE 314 //! \details 315 //! Deblocker Streamout Enable not currently supported for Encode or Decode 316 enum DEBLOCKER_STREAMOUT_ENABLE 317 { 318 DEBLOCKER_STREAMOUT_ENABLE_DISABLE = 0, //!< Disable deblocker-only parameter streamout 319 DEBLOCKER_STREAMOUT_ENABLE_ENABLE = 1, //!< Enable deblocker-only parameter streamout 320 }; 321 322 //! \brief PAK_PIPELINE_STREAMOUT_ENABLE 323 //! \details 324 //! Pipeline Streamout Enable is only defined for encode. It is ignored for 325 //! decode. 326 enum PAK_PIPELINE_STREAMOUT_ENABLE 327 { 328 PAK_PIPELINE_STREAMOUT_ENABLE_DISABLEPIPELINESTATESANDPARAMETERSSTREAMOUT = 0, //!< No additional details 329 PAK_PIPELINE_STREAMOUT_ENABLE_ENABLEPIPELINESTATESANDPARAMETERSSTREAMOUT = 1, //!< No additional details 330 }; 331 332 enum PIC_STATUSERROR_REPORT_ENABLE 333 { 334 PIC_STATUSERROR_REPORT_ENABLE_DISABLE = 0, //!< Disable status/error reporting 335 PIC_STATUSERROR_REPORT_ENABLE_ENABLE = 1, //!< Status/Error reporting is written out once per picture. The Pic Status/Error Report ID in DWord3along with the status/error status bits are packed into one cache line and written to theStatus/Error Buffer address in the HCP_PIPE_BUF_ADDR_STATE command. Must be zero for encoder mode. 336 }; 337 338 enum CODEC_STANDARD_SELECT 339 { 340 CODEC_STANDARD_SELECT_HEVC = 0, //!< No additional details 341 CODEC_STANDARD_SELECT_VP9 = 1, //!< No additional details 342 }; 343 344 enum RDOQ_ENABLED_FLAG 345 { 346 RDOQ_ENABLED_FLAG_DISABLED = 0, //!< No additional details 347 RDOQ_ENABLED_FLAG_ENABLED = 1, //!< No additional details 348 }; 349 350 //! \brief MULTI_ENGINE_MODE 351 //! \details 352 //! <p>This indicates the current pipe is in single pipe mode or if in 353 //! scalable mode is in left/right/middle pipe in multi-engine mode.</p> 354 enum MULTI_ENGINE_MODE 355 { 356 MULTI_ENGINE_MODE_SINGLEENGINEMODEORCABACFEONLYDECODEMODE = 0, //!< This is for single engine mode (legacy) OR CABAC FE only decode mode During HEVC Decoder Scalability Real Tile Mode, for the last phase, it is possible to have single tile column left. In this case, it should be programmed with pipe as a single engine mode (using this value).For example, for 9 tile column running on 4 pipes. The first two phases will use all 4 pipes and finish 8 tile column. The remaining one column will be processed as last third phase as single tile column. 357 MULTI_ENGINE_MODE_PIPEISTHELEFTENGINEINAMULTI_ENGINEMODE = 1, //!< Current pipe is the most left engine while running in scalable multi-engine mode 358 MULTI_ENGINE_MODE_PIPEISTHERIGHTENGINEINAMULTI_ENGINEMODE = 2, //!< Current pipe is the most right engine while running in scalable multi-engine mode 359 MULTI_ENGINE_MODE_PIPEISONEOFTHEMIDDLEENGINEINAMULTI_ENGINEMODE = 3, //!< Current pipe is in one of the middle engine while running in scalable multi-engine mode 360 }; 361 362 //! \brief PIPE_WORKING_MODE 363 //! \details 364 //! <p>This programs the working mode for HCP pipe.</p> 365 enum PIPE_WORKING_MODE 366 { 367 PIPE_WORKING_MODE_LEGACYDECODERENCODERMODE_SINGLEPIPE = 0, //!< This is for single pipe mode non-scalable mode. It is used by both decoder and encoder. 368 PIPE_WORKING_MODE_CABACFEONLYDECODEMODE_SINGLECABACPIPE = 1, //!< This is for the single CABAC FE only in decoder mode. This will be only run CABAC and streamout syntax element. 369 PIPE_WORKING_MODE_DECODERBEONLYORENCODERMODE_SCALABLEMULTI_PIPE = 2, //!< This is for multiple-pipe scalable mode. In decoder, it is only on BE reconstruction. In ecoder, it is for PAK. 370 PIPE_WORKING_MODE_DECODERSCALABLEMODEWITHCABACINREALTILES_SCALABLEMULTI_PIPE = 3, //!< This is for multiple-pipe scalable mode decoder mode in real tiles. CABAC and reconstruction will run together. Each pipes will run in real tiles vertically. 371 }; 372 373 //! \brief MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS 374 //! \details 375 //! In decoder modes, this counter value specifies the number of clocks (per 376 //! 1000) of GAC inactivity 377 //! before a media soft-reset is applied to the HCP and HuC. If counter 378 //! value is set to 0, the media 379 //! soft-reset feature is disabled and no reset will occur. 380 //! <p>In encoder modes, this counter must be set to 0 to disable media 381 //! soft reset. This feature is not 382 //! supported for the encoder.</p> 383 enum MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS 384 { 385 MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS_DISABLE = 0, //!< No additional details 386 }; 387 388 //! \brief PIC_STATUSERROR_REPORT_ID 389 //! \details 390 //! The Pic Status/Error Report ID is a unique 32-bit unsigned integer 391 //! assigned to each picture 392 //! status/error output. Must be zero for encoder mode. 393 enum PIC_STATUSERROR_REPORT_ID 394 { 395 PIC_STATUSERROR_REPORT_ID_32_BITUNSIGNED = 0, //!< Unique ID Number 396 }; 397 398 //! \brief PHASE_INDICATOR 399 //! \details 400 //! <p>This is used to indicate whether this is first, middle or last phase 401 //! of programming during Real-Tile Decoder Mode. Since HEVC can have upto 402 //! 20 tile columns, maximum 10 phases are possible during 2 VDbox scalable 403 //! mode. This is used by hardware to know if the current programming is 404 //! first or last phases.</p> 405 //! <p>This field is ignored (programmed to 0) for other modes other than 406 //! HEVC Real-Tile Decoder Mode.</p> 407 enum PHASE_INDICATOR 408 { 409 PHASE_INDICATOR_FIRSTPHASE = 0, //!< No additional details 410 PHASE_INDICATOR_MIDDLEPHASE = 1, //!< No additional details 411 PHASE_INDICATOR_LASTPHASE = 2, //!< No additional details 412 }; 413 414 //! \name Initializations 415 416 //! \brief Explicit member initialization function 417 HCP_PIPE_MODE_SELECT_CMD(); 418 419 static const size_t dwSize = 7; 420 static const size_t byteSize = 28; 421 }; 422 423 //! 424 //! \brief HCP_SURFACE_STATE 425 //! \details 426 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 427 //! Commands. Each HCP command has assigned a media instruction command as 428 //! defined in DWord 0, BitField 22:16. 429 //! 430 //! The HCP_SURFACE_STATE command is responsible for defining the frame 431 //! buffer pitch and the offset of the chroma component. This is a picture 432 //! level state command and is shared by both encoding and decoding 433 //! processes. Note : Only NV12 and Tile Y are being supported for HEVC. 434 //! Hence full pitch and interleaved UV is always in use. U and V Xoffset 435 //! must be set to 0; U and V Yoffset must be 16-pixel aligned. This Surface 436 //! State is not the same as that of the 3D engine and of the MFX pipeline. 437 //! 438 struct HCP_SURFACE_STATE_CMD 439 { 440 union 441 { 442 struct 443 { 444 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 445 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 446 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 447 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 448 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 449 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 450 }; 451 uint32_t Value; 452 } DW0; 453 union 454 { 455 struct 456 { 457 uint32_t SurfacePitchMinus1 : __CODEGEN_BITFIELD( 0, 16) ; //!< Surface Pitch Minus1 458 uint32_t Reserved49 : __CODEGEN_BITFIELD(17, 27) ; //!< Reserved 459 uint32_t SurfaceId : __CODEGEN_BITFIELD(28, 31) ; //!< SURFACE_ID 460 }; 461 uint32_t Value; 462 } DW1; 463 union 464 { 465 struct 466 { 467 uint32_t YOffsetForUCbInPixel : __CODEGEN_BITFIELD( 0, 14) ; //!< Y Offset for U(Cb) in pixel 468 uint32_t Reserved79 : __CODEGEN_BITFIELD(15, 26) ; //!< Reserved 469 uint32_t SurfaceFormat : __CODEGEN_BITFIELD(27, 31) ; //!< SURFACE_FORMAT 470 }; 471 uint32_t Value; 472 } DW2; 473 union 474 { 475 struct 476 { 477 uint32_t DefaultAlphaValue : __CODEGEN_BITFIELD( 0, 15) ; //!< Default Alpha Value 478 uint32_t YOffsetForVCr : __CODEGEN_BITFIELD(16, 31) ; //!< Y Offset for V(Cr) 479 }; 480 uint32_t Value; 481 } DW3; 482 union 483 { 484 struct 485 { 486 uint32_t MemoryCompressionEnable : __CODEGEN_BITFIELD( 0, 7) ; //!< MEMORY_COMPRESSION_ENABLE 487 uint32_t CompressionType : __CODEGEN_BITFIELD( 8, 15) ; //!< COMPRESSION_TYPE 488 uint32_t Reserved144 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 489 }; 490 uint32_t Value; 491 } DW4; 492 493 //! \name Local enumerations 494 495 enum MEDIA_INSTRUCTION_COMMAND 496 { 497 MEDIA_INSTRUCTION_COMMAND_HCPSURFACESTATE = 1, //!< No additional details 498 }; 499 500 //! \brief MEDIA_INSTRUCTION_OPCODE 501 //! \details 502 //! Codec/Engine Name = HCP = 7h 503 enum MEDIA_INSTRUCTION_OPCODE 504 { 505 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 506 }; 507 508 enum PIPELINE_TYPE 509 { 510 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 511 }; 512 513 enum COMMAND_TYPE 514 { 515 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 516 }; 517 518 enum SURFACE_ID 519 { 520 SURFACE_ID_HEVCFORCURRENTDECODEDPICTURE = 0, //!< 8-bit uncompressed data 521 SURFACE_ID_SOURCEINPUTPICTURE_ENCODER = 1, //!< 8-bit uncompressed data 522 SURFACE_ID_PREVREFERENCEPICTURE = 2, //!< (VP9 only) Previous Reference 523 SURFACE_ID_GOLDENREFERENCEPICTURE = 3, //!< (VP9 only) Golden Reference 524 SURFACE_ID_ALTREFREFERENCEPICTURE = 4, //!< (VP9 only) AltRef Reference 525 SURFACE_ID_HEVCREFERENCEPICTURES = 5, //!< (HEVC only) Reference. Also, this will have separate compressible bits per reference surfaces for HEVC 526 }; 527 528 //! \brief SURFACE_FORMAT 529 //! \details 530 //! <p>Specifies the format of the surface.</p> 531 enum SURFACE_FORMAT 532 { 533 SURFACE_FORMAT_YUY2FORMAT = 0, //!< No additional details 534 SURFACE_FORMAT_RGB8FORMAT = 1, //!< No additional details 535 SURFACE_FORMAT_AYUV4444FORMAT = 2, //!< No additional details 536 SURFACE_FORMAT_P010VARIANT = 3, //!< No additional details 537 SURFACE_FORMAT_PLANAR4208 = 4, //!< No additional details 538 SURFACE_FORMAT_YCRCBSWAPYFORMAT = 5, //!< No additional details 539 SURFACE_FORMAT_YCRCBSWAPUVFORMAT = 6, //!< No additional details 540 SURFACE_FORMAT_YCRCBSWAPUVYFORMAT = 7, //!< No additional details 541 SURFACE_FORMAT_Y216Y210FORMAT = 8, //!< Same value is used to represent Y216 and Y210 542 SURFACE_FORMAT_RGB10FORMAT = 9, //!< No additional details 543 SURFACE_FORMAT_Y410FORMAT = 10, //!< No additional details 544 SURFACE_FORMAT_NV21PLANAR4208FORMAT = 11, //!< No additional details 545 SURFACE_FORMAT_Y416FORMAT = 12, //!< No additional details 546 SURFACE_FORMAT_P010 = 13, //!< No additional details 547 SURFACE_FORMAT_P016 = 14, //!< No additional details 548 SURFACE_FORMAT_Y8FORMAT = 15, //!< No additional details 549 SURFACE_FORMAT_Y16FORMAT = 16, //!< No additional details 550 SURFACE_FORMAT_Y216VARIANT = 17, //!< Y216Variant is the modifed Y210/Y216 format, 8 bit planar 422 with MSB bytes packed together and LSB bytes at an offset in the X-direction where the x-offset is 32-bit aligned. The chroma is UV interleaved with identical MSB and LSB split as luma and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma. 551 SURFACE_FORMAT_Y416VARIANT = 18, //!< Y416Variant is the modifed Y410/Y412/Y416 format,8 bit planar 444 with MSB bytes packed together and LSB bytes at an offset in the X-direction where the x-offset is 32-bit aligned. The U channel is below the luma, has identical MSB and LSB split as luma and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma The V channel is below the U, has identical MSB and LSB split as luma and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma. 552 SURFACE_FORMAT_YUY2VARIANT = 19, //!< YUY2Variant is the modifed YUY2 format, 8 bit planar 422. The chroma is UV interleaved and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma. 553 SURFACE_FORMAT_AYUV4444VARIANT = 20, //!< AYUV4444Variant is the modifed AYUV4444 format, 8 bit planar 444 format. The U channel is below the luma and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma. The V channel is below the and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma. 554 }; 555 556 //! \brief MEMORY_COMPRESSION_ENABLE 557 //! \details 558 //! <p>In HEVC mode, each bit is used for 1 reference starting with Bit 0 559 //! for Ref 0 in the ref list and Bit 1 for Ref 1 and so on.</p> 560 //! <p>In VP9 mode, Bit 0 is for Previous Reference; Bit 1 is for Golden 561 //! Reference and Bit 2 is for Alterante Reference; Bits 3-7 are unused and 562 //! should be programmed to 0.</p> 563 enum MEMORY_COMPRESSION_ENABLE 564 { 565 MEMORY_COMPRESSION_ENABLE_MEMORYCOMPRESSIONDISABLE = 0, //!< No additional details 566 MEMORY_COMPRESSION_ENABLE_MEMORYCOMPRESSIONENABLE = 1, //!< No additional details 567 }; 568 569 //! \brief COMPRESSION_TYPE 570 //! \details 571 //! <p>This field indicates if the compression type for the reference 572 //! surface is media or render compressed.</p> 573 //! <p>In HEVC mode, each bit is used for 1 reference starting with Bit 8for 574 //! Ref 0 in the ref list and Bit 9for Ref 1 and so on.</p> 575 //! <p>In VP9 mode, Bit 8is for Previous Reference; Bit 9is for Golden 576 //! Reference and Bit 10is for Alterante Reference; Bits11-15are unused and 577 //! should be programmed to 0</p> 578 enum COMPRESSION_TYPE 579 { 580 COMPRESSION_TYPE_MEDIACOMPRESSIONENABLED = 0, //!< No additional details 581 COMPRESSION_TYPE_RENDERCOMPRESSIONENABLED = 1, //!< No additional details 582 }; 583 584 //! \name Initializations 585 586 //! \brief Explicit member initialization function 587 HCP_SURFACE_STATE_CMD(); 588 589 static const size_t dwSize = 5; 590 static const size_t byteSize = 20; 591 }; 592 593 //! 594 //! \brief HCP_PIPE_BUF_ADDR_STATE 595 //! \details 596 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 597 //! Commands. Each HCP command has assigned a media instruction command as 598 //! defined in DWord 0, BitField 22:16. 599 //! 600 //! This state command provides the memory base addresses for the row store 601 //! buffer and reconstructed picture output buffers required by the HCP. 602 //! This is a picture level state command and is shared by both encoding and 603 //! decoding processes. 604 //! 605 //! All pixel surface addresses must be 4K byte aligned. There is a max of 8 606 //! Reference Picture Buffer Addresses, and all share the same third address 607 //! DW in specifying 48-bit address. 608 //! 609 struct HCP_PIPE_BUF_ADDR_STATE_CMD 610 { 611 union 612 { 613 struct 614 { 615 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 616 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 617 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 618 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 619 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 620 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 621 }; 622 uint32_t Value; 623 } DW0; 624 SPLITBASEADDRESS4KBYTEALIGNED_CMD DecodedPicture; //!< DW1..2, Decoded Picture 625 MEMORYADDRESSATTRIBUTES_CMD DecodedPictureMemoryAddressAttributes; //!< DW3, Decoded Picture Memory Address Attributes 626 SPLITBASEADDRESS64BYTEALIGNED_CMD DeblockingFilterLineBuffer; //!< DW4..5, Deblocking Filter Line Buffer 627 MEMORYADDRESSATTRIBUTES_CMD DeblockingFilterLineBufferMemoryAddressAttributes; //!< DW6, Deblocking Filter Line Buffer Memory Address Attributes 628 SPLITBASEADDRESS64BYTEALIGNED_CMD DeblockingFilterTileLineBuffer; //!< DW7..8, Deblocking Filter Tile Line Buffer 629 MEMORYADDRESSATTRIBUTES_CMD DeblockingFilterTileLineBufferMemoryAddressAttributes; //!< DW9, Deblocking Filter Tile Line Buffer Memory Address Attributes 630 SPLITBASEADDRESS64BYTEALIGNED_CMD DeblockingFilterTileColumnBuffer; //!< DW10..11, Deblocking Filter Tile Column Buffer 631 MEMORYADDRESSATTRIBUTES_CMD DeblockingFilterTileColumnBufferMemoryAddressAttributes; //!< DW12, Deblocking Filter Tile Column Buffer Memory Address Attributes 632 SPLITBASEADDRESS64BYTEALIGNED_CMD MetadataLineBuffer; //!< DW13..14, Metadata Line Buffer 633 MEMORYADDRESSATTRIBUTES_CMD MetadataLineBufferMemoryAddressAttributes; //!< DW15, Metadata Line Buffer Memory Address Attributes 634 SPLITBASEADDRESS64BYTEALIGNED_CMD MetadataTileLineBuffer; //!< DW16..17, Metadata Tile Line Buffer 635 MEMORYADDRESSATTRIBUTES_CMD MetadataTileLineBufferMemoryAddressAttributes; //!< DW18, Metadata Tile Line Buffer Memory Address Attributes 636 SPLITBASEADDRESS64BYTEALIGNED_CMD MetadataTileColumnBuffer; //!< DW19..20, Metadata Tile Column Buffer 637 MEMORYADDRESSATTRIBUTES_CMD MetadataTileColumnBufferMemoryAddressAttributes; //!< DW21, Metadata Tile Column Buffer Memory Address Attributes 638 SPLITBASEADDRESS64BYTEALIGNED_CMD SaoLineBuffer; //!< DW22..23, SAO Line Buffer 639 MEMORYADDRESSATTRIBUTES_CMD SaoLineBufferMemoryAddressAttributes; //!< DW24, SAO Line Buffer Memory Address Attributes 640 SPLITBASEADDRESS64BYTEALIGNED_CMD SaoTileLineBuffer; //!< DW25..26, SAO Tile Line Buffer 641 MEMORYADDRESSATTRIBUTES_CMD SaoTileLineBufferMemoryAddressAttributes; //!< DW27, SAO Tile Line Buffer Memory Address Attributes 642 SPLITBASEADDRESS64BYTEALIGNED_CMD SaoTileColumnBuffer; //!< DW28..29, SAO Tile Column Buffer 643 MEMORYADDRESSATTRIBUTES_CMD SaoTileColumnBufferMemoryAddressAttributes; //!< DW30, SAO Tile Column Buffer Memory Address Attributes 644 SPLITBASEADDRESS64BYTEALIGNED_CMD CurrentMotionVectorTemporalBuffer; //!< DW31..32, Current Motion Vector Temporal Buffer 645 MEMORYADDRESSATTRIBUTES_CMD CurrentMotionVectorTemporalBufferMemoryAddressAttributes; //!< DW33, Current Motion Vector Temporal Buffer Memory Address Attributes 646 union 647 { 648 struct 649 { 650 uint64_t Reserved1088 ; //!< Reserved 651 }; 652 uint32_t Value[2]; 653 } DW34_35; 654 union 655 { 656 struct 657 { 658 uint32_t Reserved1152 ; //!< Reserved 659 }; 660 uint32_t Value; 661 } DW36; 662 SPLITBASEADDRESS64BYTEALIGNED_CMD ReferencePictureBaseAddressRefaddr07[8]; //!< DW37..52, Reference Picture Base Address (RefAddr[0-7]) 663 MEMORYADDRESSATTRIBUTES_CMD ReferencePictureBaseAddressMemoryAddressAttributes; //!< DW53, Reference Picture Base Address Memory Address Attributes 664 SPLITBASEADDRESS64BYTEALIGNED_CMD OriginalUncompressedPictureSource; //!< DW54..55, Original Uncompressed Picture Source 665 MEMORYADDRESSATTRIBUTES_CMD OriginalUncompressedPictureSourceMemoryAddressAttributes; //!< DW56, Original Uncompressed Picture Source Memory Address Attributes 666 SPLITBASEADDRESS64BYTEALIGNED_CMD StreamoutDataDestination; //!< DW57..58, Streamout Data Destination 667 MEMORYADDRESSATTRIBUTES_CMD StreamoutDataDestinationMemoryAddressAttributes; //!< DW59, Streamout Data Destination Memory Address Attributes, Decoder Only 668 SPLITBASEADDRESS64BYTEALIGNED_CMD DecodedPictureStatusErrorBufferBaseAddressOrEncodedSliceSizeStreamoutBaseAddress;//!< DW60..61, Decoded Picture Status/Error Buffer Base Address or Encoded slice size streamout Base Address 669 MEMORYADDRESSATTRIBUTES_CMD DecodedPictureStatusErrorBufferBaseAddressMemoryAddressAttributes; //!< DW62, Decoded Picture Status/Error Buffer Base Address Memory Address Attributes 670 SPLITBASEADDRESS64BYTEALIGNED_CMD LcuIldbStreamoutBuffer; //!< DW63..64, LCU ILDB Streamout Buffer 671 MEMORYADDRESSATTRIBUTES_CMD LcuIldbStreamoutBufferMemoryAddressAttributes; //!< DW65, LCU ILDB Streamout Buffer Memory Address Attributes 672 SPLITBASEADDRESS64BYTEALIGNED_CMD CollocatedMotionVectorTemporalBuffer07[8]; //!< DW66..81, Collocated Motion Vector Temporal Buffer[0-7] 673 MEMORYADDRESSATTRIBUTES_CMD CollocatedMotionVectorTemporalBuffer07MemoryAddressAttributes; //!< DW82, Collocated Motion Vector Temporal Buffer[0-7] Memory Address Attributes 674 SPLITBASEADDRESS64BYTEALIGNED_CMD Vp9ProbabilityBufferReadWrite; //!< DW83..84, VP9 Probability Buffer Read/Write 675 MEMORYADDRESSATTRIBUTES_CMD Vp9ProbabilityBufferReadWriteMemoryAddressAttributes; //!< DW85, VP9 Probability Buffer Read/Write Memory Address Attributes 676 union 677 { 678 struct 679 { 680 uint64_t Vp9SegmentIdBufferReadWrite ; //!< VP9 Segment ID Buffer Read/Write 681 }; 682 uint32_t Value[2]; 683 } DW86_87; 684 MEMORYADDRESSATTRIBUTES_CMD Vp9SegmentIdBufferReadWriteMemoryAddressAttributes; //!< DW88, VP9 Segment ID buffer Read/Write Memory Address Attributes 685 SPLITBASEADDRESS64BYTEALIGNED_CMD Vp9HvdLineRowstoreBufferReadWrite; //!< DW89..90, VP9 HVD Line Rowstore Buffer Read/Write 686 MEMORYADDRESSATTRIBUTES_CMD Vp9HvdLineRowstoreBufferReadWriteMemoryAddressAttributes; //!< DW91, VP9 HVD Line Rowstore buffer Read/Write Memory Address Attributes 687 SPLITBASEADDRESS64BYTEALIGNED_CMD Vp9HvdTileRowstoreBufferReadWrite; //!< DW92..93, VP9 HVD Tile Rowstore Buffer Read/Write 688 MEMORYADDRESSATTRIBUTES_CMD Vp9HvdTileRowstoreBufferReadWriteMemoryAddressAttributes; //!< DW94, VP9 HVD Tile Rowstore buffer Read/Write Memory Address Attributes 689 union 690 { 691 struct 692 { 693 uint64_t SaoRowstoreBufferBaseAddress ; //!< SAO Rowstore Buffer Base Address 694 }; 695 uint32_t Value[2]; 696 } DW95_96; 697 MEMORYADDRESSATTRIBUTES_CMD SaoRowstoreBufferReadWriteMemoryAddressAttributes; //!< DW97, SAO Rowstore Buffer Read/Write Memory Address Attributes 698 SPLITBASEADDRESS64BYTEALIGNED_CMD FrameStatisticsStreamoutDataDestinationBufferBaseAddress; //!< DW98..99, Frame Statistics Streamout Data Destination Buffer Base Address 699 MEMORYADDRESSATTRIBUTES_CMD FrameStatisticsStreamoutDataDestinationBufferAttributesReadWrite; //!< DW100, Frame Statistics Streamout Data Destination buffer (attributes) Read/Write 700 SPLITBASEADDRESS64BYTEALIGNED_CMD SseSourcePixelRowstoreBufferBaseAddress; //!< DW101..102, SSE Source Pixel RowStore Buffer Base Address 701 MEMORYADDRESSATTRIBUTES_CMD SseSourcePixelRowstoreBufferAttributesReadWrite; //!< DW103, SSE Source Pixel RowStore buffer (attributes) Read/Write 702 SPLITBASEADDRESS64BYTEALIGNED_CMD HcpScalabilitySliceStateBufferBaseAddress; //!< DW104..105, HCP Scalability Slice State Buffer Base Address 703 MEMORYADDRESSATTRIBUTES_CMD HcpScalabilitySliceStateBufferAttributesReadWrite; //!< DW106, HCP Scalability Slice State Buffer (attributes) Read/Write 704 SPLITBASEADDRESS64BYTEALIGNED_CMD HcpScalabilityCabacDecodedSyntaxElementsBufferBaseAddress; //!< DW107..108, HCP Scalability CABAC Decoded Syntax Elements Buffer Base Address 705 MEMORYADDRESSATTRIBUTES_CMD HcpScalabilityCabacDecodedSyntaxElementsBufferAttributesReadWrite; //!< DW109, HCP Scalability CABAC Decoded Syntax Elements Buffer (attributes) Read/Write 706 SPLITBASEADDRESS64BYTEALIGNED_CMD MotionVectorUpperRightColumnStoreBufferBaseAddress; //!< DW110..111, Motion Vector Upper Right Column Store Buffer Base Address 707 MEMORYADDRESSATTRIBUTES_CMD MotionVectorUpperRightColumnStoreBufferAttributesReadWrite; //!< DW112, Motion Vector Upper Right Column Store Buffer (attributes) Read/Write 708 SPLITBASEADDRESS64BYTEALIGNED_CMD IntraPredictionUpperRightColumnStoreBufferBaseAddress; //!< DW113..114, Intra Prediction Upper Right Column Store Buffer Base Address 709 MEMORYADDRESSATTRIBUTES_CMD IntraPredictionUpperRightColumnStoreBufferAttributesReadWrite; //!< DW115, Intra Prediction Upper Right Column Store Buffer (attributes) Read/Write 710 SPLITBASEADDRESS64BYTEALIGNED_CMD IntraPredictionLeftReconColumnStoreBufferBaseAddress; //!< DW116..117, Intra Prediction Left Recon Column Store Buffer Base Address 711 MEMORYADDRESSATTRIBUTES_CMD IntraPredictionLeftReconColumnStoreBufferAttributesReadWrite; //!< DW118, Intra Prediction Left Recon Column Store Buffer (attributes) Read/Write 712 SPLITBASEADDRESS64BYTEALIGNED_CMD HcpScalabilityCabacDecodedSyntaxElementsBufferMaxAddress; //!< DW119..120, HCP Scalability CABAC Decoded Syntax Elements Buffer Max Address 713 714 //! \name Local enumerations 715 716 enum MEDIA_INSTRUCTION_COMMAND 717 { 718 MEDIA_INSTRUCTION_COMMAND_HCPPIPEBUFADDRSTATE = 2, //!< No additional details 719 }; 720 721 //! \brief MEDIA_INSTRUCTION_OPCODE 722 //! \details 723 //! Codec/Engine Name = HCP = 7h 724 enum MEDIA_INSTRUCTION_OPCODE 725 { 726 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 727 }; 728 729 enum PIPELINE_TYPE 730 { 731 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 732 }; 733 734 enum COMMAND_TYPE 735 { 736 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 737 }; 738 739 //! \name Initializations 740 741 //! \brief Explicit member initialization function 742 HCP_PIPE_BUF_ADDR_STATE_CMD(); 743 744 static const size_t dwSize = 121; 745 static const size_t byteSize = 484; 746 }; 747 748 //! 749 //! \brief HCP_IND_OBJ_BASE_ADDR_STATE 750 //! \details 751 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 752 //! Commands. Each HCP command has assigned a media instruction command as 753 //! defined in DWord 0, BitField 22:16. 754 //! 755 //! The HCP_IND_OBJ_BASE_ADDR_STATE command is used to define the indirect 756 //! object base address of the stream in graphics memory. This is a frame 757 //! level command. (Is it frame or picture level?) 758 //! This is a picture level state command and is issued in both encoding and 759 //! decoding processes. 760 //! 761 //! Compressed Header Format 762 //! 763 //! 764 //! 765 struct HCP_IND_OBJ_BASE_ADDR_STATE_CMD 766 { 767 union 768 { 769 struct 770 { 771 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 772 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 773 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 774 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 775 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 776 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 777 }; 778 uint32_t Value; 779 } DW0; 780 SPLITBASEADDRESS4KBYTEALIGNED_CMD HcpIndirectBitstreamObjectBaseAddress; //!< DW1..2, HCP Indirect Bitstream Object Base Address 781 MEMORYADDRESSATTRIBUTES_CMD HcpIndirectBitstreamObjectMemoryAddressAttributes; //!< DW3, HCP Indirect Bitstream Object Memory Address Attributes 782 SPLITBASEADDRESS4KBYTEALIGNED_CMD HcpIndirectBitstreamObjectAccessUpperBound; //!< DW4..5, HCP Indirect Bitstream Object Access Upper Bound 783 union 784 { 785 struct 786 { 787 uint64_t HcpIndirectCuObjectBaseAddress ; //!< HCP Indirect CU Object Base Address 788 }; 789 uint32_t Value[2]; 790 } DW6_7; 791 MEMORYADDRESSATTRIBUTES_CMD HcpIndirectCuObjectObjectMemoryAddressAttributes; //!< DW8, HCP Indirect CU Object Object Memory Address Attributes 792 union 793 { 794 struct 795 { 796 uint64_t HcpPakBseObjectBaseAddress ; //!< HCP PAK-BSE Object Base Address 797 }; 798 uint32_t Value[2]; 799 } DW9_10; 800 MEMORYADDRESSATTRIBUTES_CMD HcpPakBseObjectAddressMemoryAddressAttributes; //!< DW11, HCP PAK-BSE Object Address Memory Address Attributes 801 SPLITBASEADDRESS4KBYTEALIGNED_CMD HcpPakBseObjectAccessUpperBound; //!< DW12..13, HCP PAK-BSE Object Access Upper Bound 802 union 803 { 804 struct 805 { 806 uint64_t HcpVp9PakCompressedHeaderSyntaxStreaminBaseAddress ; //!< HCP VP9 PAK Compressed Header Syntax Streamin- Base Address 807 }; 808 uint32_t Value[2]; 809 } DW14_15; 810 MEMORYADDRESSATTRIBUTES_CMD HcpVp9PakCompressedHeaderSyntaxStreaminMemoryAddressAttributes; //!< DW16, HCP VP9 PAK Compressed Header Syntax StreamIn Memory Address Attributes 811 union 812 { 813 struct 814 { 815 uint64_t HcpVp9PakProbabilityCounterStreamoutBaseAddress ; //!< HCP VP9 PAK Probability Counter StreamOut- Base Address 816 }; 817 uint32_t Value[2]; 818 } DW17_18; 819 MEMORYADDRESSATTRIBUTES_CMD HcpVp9PakProbabilityCounterStreamoutMemoryAddressAttributes; //!< DW19, HCP VP9 PAK Probability Counter StreamOut Memory Address Attributes 820 union 821 { 822 struct 823 { 824 uint64_t HcpVp9PakProbabilityDeltasStreaminBaseAddress ; //!< HCP VP9 PAK Probability Deltas StreamIn- Base Address 825 }; 826 uint32_t Value[2]; 827 } DW20_21; 828 MEMORYADDRESSATTRIBUTES_CMD HcpVp9PakProbabilityDeltasStreaminMemoryAddressAttributes; //!< DW22, HCP VP9 PAK Probability Deltas StreamIn Memory Address Attributes 829 union 830 { 831 struct 832 { 833 uint64_t HcpVp9PakTileRecordStreamoutBaseAddress ; //!< HCP VP9 PAK Tile Record StreamOut- Base Address 834 }; 835 uint32_t Value[2]; 836 } DW23_24; 837 MEMORYADDRESSATTRIBUTES_CMD HcpVp9PakTileRecordStreamoutMemoryAddressAttributes; //!< DW25, HCP VP9 PAK Tile Record StreamOut Memory Address Attributes 838 union 839 { 840 struct 841 { 842 uint64_t HcpVp9PakCuLevelStatisticStreamoutBaseAddress ; //!< HCP VP9 PAK CU Level Statistic StreamOut- Base Address 843 }; 844 uint32_t Value[2]; 845 } DW26_27; 846 MEMORYADDRESSATTRIBUTES_CMD HcpVp9PakCuLevelStatisticStreamoutMemoryAddressAttributes; //!< DW28, HCP VP9 PAK CU Level Statistic StreamOut Memory Address Attributes 847 848 //! \name Local enumerations 849 850 enum MEDIA_INSTRUCTION_COMMAND 851 { 852 MEDIA_INSTRUCTION_COMMAND_HCPINDOBJBASEADDRSTATE = 3, //!< No additional details 853 }; 854 855 //! \brief MEDIA_INSTRUCTION_OPCODE 856 //! \details 857 //! Codec/Engine Name = HCP = 7h 858 enum MEDIA_INSTRUCTION_OPCODE 859 { 860 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 861 }; 862 863 enum PIPELINE_TYPE 864 { 865 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 866 }; 867 868 enum COMMAND_TYPE 869 { 870 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 871 }; 872 873 //! \name Initializations 874 875 //! \brief Explicit member initialization function 876 HCP_IND_OBJ_BASE_ADDR_STATE_CMD(); 877 878 static const size_t dwSize = 29; 879 static const size_t byteSize = 116; 880 }; 881 882 //! 883 //! \brief HCP_QM_STATE 884 //! \details 885 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 886 //! Commands. Each HCP command has assigned a media instruction command as 887 //! defined in DWord 0, BitField 22:16. 888 //! 889 //! The HCP_QM_STATE command loads the custom HEVC quantization tables into 890 //! local RAM and may be issued up to 20 times: 3x Colour Component plus 2x 891 //! intra/inter plus 4x SizeID minus 4 for the 32x32 chroma components. When 892 //! the scaling_list_enable_flag is set to disable, the scaling matrix is 893 //! still sent to the decoder, and with all entries programmed to the same 894 //! value = 16. This is a picture level state command and is issued in both 895 //! encoding and decoding processes. 896 //! 897 //! Dwords 2-17 form a table for the DCT coefficients, 4 8-bit 898 //! coefficients/DWord. Size 4x4 for SizeID0, DWords 2-5. 899 //! Size 8x8 for SizeID1/2/3, DWords 2-17. 900 //! 901 //! 902 //! SizeID 0 (Table 4-10) 903 //! 904 struct HCP_QM_STATE_CMD 905 { 906 union 907 { 908 struct 909 { 910 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 911 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 912 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 913 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 914 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 915 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 916 }; 917 uint32_t Value; 918 } DW0; 919 union 920 { 921 struct 922 { 923 uint32_t PredictionType : __CODEGEN_BITFIELD( 0, 0) ; //!< PREDICTION_TYPE 924 uint32_t Sizeid : __CODEGEN_BITFIELD( 1, 2) ; //!< SIZEID 925 uint32_t ColorComponent : __CODEGEN_BITFIELD( 3, 4) ; //!< COLOR_COMPONENT 926 uint32_t DcCoefficient : __CODEGEN_BITFIELD( 5, 12) ; //!< DC Coefficient 927 uint32_t Reserved45 : __CODEGEN_BITFIELD(13, 31) ; //!< Reserved 928 }; 929 uint32_t Value; 930 } DW1; 931 uint32_t Quantizermatrix[16]; //!< QuantizerMatrix 932 933 //! \name Local enumerations 934 935 enum MEDIA_INSTRUCTION_COMMAND 936 { 937 MEDIA_INSTRUCTION_COMMAND_HCPQMSTATE = 4, //!< No additional details 938 }; 939 940 //! \brief MEDIA_INSTRUCTION_OPCODE 941 //! \details 942 //! Codec/Engine Name = HCP = 7h 943 enum MEDIA_INSTRUCTION_OPCODE 944 { 945 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 946 }; 947 948 enum PIPELINE_TYPE 949 { 950 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 951 }; 952 953 enum COMMAND_TYPE 954 { 955 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 956 }; 957 958 enum PREDICTION_TYPE 959 { 960 PREDICTION_TYPE_INTRA = 0, //!< No additional details 961 PREDICTION_TYPE_INTER = 1, //!< No additional details 962 }; 963 964 enum SIZEID 965 { 966 SIZEID_4X4 = 0, //!< No additional details 967 SIZEID_8X8 = 1, //!< No additional details 968 SIZEID_16X16 = 2, //!< No additional details 969 SIZEID_32X32 = 3, //!< (Illegal Value for Colour Component Chroma Cr and Cb.) 970 }; 971 972 //! \brief COLOR_COMPONENT 973 //! \details 974 //! Encoder: When RDOQ is enabled, scaling list for all 3 color components 975 //! must be same. So this field is set to always 0. 976 enum COLOR_COMPONENT 977 { 978 COLOR_COMPONENT_LUMA = 0, //!< No additional details 979 COLOR_COMPONENT_CHROMACB = 1, //!< No additional details 980 COLOR_COMPONENT_CHROMACR = 2, //!< No additional details 981 }; 982 983 //! \name Initializations 984 985 //! \brief Explicit member initialization function 986 HCP_QM_STATE_CMD(); 987 988 static const size_t dwSize = 18; 989 static const size_t byteSize = 72; 990 }; 991 992 //! 993 //! \brief HCP_PIC_STATE 994 //! \details 995 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 996 //! Commands. Each HCP command has assigned a media instruction command as 997 //! defined in DWord 0, BitField 22:16. 998 //! 999 //! This is a picture level command and is issued only once per workload for 1000 //! both encoding and decoding processes. 1001 //! 1002 struct HCP_PIC_STATE_CMD 1003 { 1004 union 1005 { 1006 struct 1007 { 1008 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1009 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1010 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 1011 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 1012 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 1013 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1014 }; 1015 uint32_t Value; 1016 } DW0; 1017 union 1018 { 1019 struct 1020 { 1021 uint32_t Framewidthinmincbminus1 : __CODEGEN_BITFIELD( 0, 10) ; //!< FrameWidthInMinCbMinus1 1022 uint32_t Reserved43 : __CODEGEN_BITFIELD(11, 14) ; //!< Reserved 1023 uint32_t PakTransformSkipEnable : __CODEGEN_BITFIELD(15, 15) ; //!< PAK Transform Skip Enable 1024 uint32_t Frameheightinmincbminus1 : __CODEGEN_BITFIELD(16, 26) ; //!< FrameHeightInMinCbMinus1 1025 uint32_t Reserved59 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 1026 }; 1027 uint32_t Value; 1028 } DW1; 1029 union 1030 { 1031 struct 1032 { 1033 uint32_t Mincusize : __CODEGEN_BITFIELD( 0, 1) ; //!< MINCUSIZE 1034 uint32_t CtbsizeLcusize : __CODEGEN_BITFIELD( 2, 3) ; //!< CTBSIZE_LCUSIZE 1035 uint32_t Mintusize : __CODEGEN_BITFIELD( 4, 5) ; //!< MINTUSIZE 1036 uint32_t Maxtusize : __CODEGEN_BITFIELD( 6, 7) ; //!< MAXTUSIZE 1037 uint32_t Minpcmsize : __CODEGEN_BITFIELD( 8, 9) ; //!< MINPCMSIZE 1038 uint32_t Maxpcmsize : __CODEGEN_BITFIELD(10, 11) ; //!< MAXPCMSIZE 1039 uint32_t Log2SaoOffsetScaleLuma : __CODEGEN_BITFIELD(12, 14) ; //!< LOG2_SAO_OFFSET_SCALE_LUMA 1040 uint32_t Reserved79 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 1041 uint32_t Log2SaoOffsetScaleChroma : __CODEGEN_BITFIELD(16, 18) ; //!< LOG2_SAO_OFFSET_SCALE_CHROMA 1042 uint32_t Reserved83 : __CODEGEN_BITFIELD(19, 19) ; //!< Reserved 1043 uint32_t ChromaQpOffsetListLenMinus1 : __CODEGEN_BITFIELD(20, 22) ; //!< chroma_qp_offset_list_len_minus1 1044 uint32_t Reserved87 : __CODEGEN_BITFIELD(23, 23) ; //!< Reserved 1045 uint32_t DiffCuChromaQpOffsetDepth : __CODEGEN_BITFIELD(24, 27) ; //!< diff_cu_chroma_qp_offset_depth 1046 uint32_t ChromaQpOffsetListEnabledFlag : __CODEGEN_BITFIELD(28, 28) ; //!< chroma_qp_offset_list_enabled_flag 1047 uint32_t ChromaSubsampling : __CODEGEN_BITFIELD(29, 31) ; //!< CHROMA_SUBSAMPLING 1048 }; 1049 uint32_t Value; 1050 } DW2; 1051 union 1052 { 1053 struct 1054 { 1055 uint32_t Colpicisi : __CODEGEN_BITFIELD( 0, 0) ; //!< COLPICISI 1056 uint32_t Curpicisi : __CODEGEN_BITFIELD( 1, 1) ; //!< CURPICISI 1057 uint32_t Inserttestflag : __CODEGEN_BITFIELD( 2, 2) ; //!< INSERTTESTFLAG 1058 uint32_t Reserved99 : __CODEGEN_BITFIELD( 3, 7) ; //!< Reserved 1059 uint32_t TileNumber : __CODEGEN_BITFIELD( 8, 13) ; //!< Tile number 1060 uint32_t FrameNumber : __CODEGEN_BITFIELD(14, 17) ; //!< Frame number 1061 uint32_t Reserved114 : __CODEGEN_BITFIELD(18, 18) ; //!< Reserved 1062 uint32_t HighPrecisionOffsetsEnableFlag : __CODEGEN_BITFIELD(19, 19) ; //!< High Precision Offsets Enable Flag 1063 uint32_t Log2Maxtransformskipsize : __CODEGEN_BITFIELD(20, 22) ; //!< Log2MaxTransformSkipSize 1064 uint32_t CrossComponentPredictionEnabledFlag : __CODEGEN_BITFIELD(23, 23) ; //!< cross_component_prediction_enabled_flag 1065 uint32_t CabacBypassAlignmentEnabledFlag : __CODEGEN_BITFIELD(24, 24) ; //!< cabac_bypass_alignment_enabled_flag 1066 uint32_t PersistentRiceAdaptationEnabledFlag : __CODEGEN_BITFIELD(25, 25) ; //!< persistent_rice_adaptation_enabled_flag 1067 uint32_t IntraSmoothingDisabledFlag : __CODEGEN_BITFIELD(26, 26) ; //!< intra_smoothing_disabled_flag 1068 uint32_t ExplicitRdpcmEnabledFlag : __CODEGEN_BITFIELD(27, 27) ; //!< explicit_rdpcm_enabled_flag 1069 uint32_t ImplicitRdpcmEnabledFlag : __CODEGEN_BITFIELD(28, 28) ; //!< implicit_rdpcm_enabled_flag 1070 uint32_t TransformSkipContextEnabledFlag : __CODEGEN_BITFIELD(29, 29) ; //!< transform_skip_context_enabled_flag 1071 uint32_t TransformSkipRotationEnabledFlag : __CODEGEN_BITFIELD(30, 30) ; //!< transform_skip_rotation_enabled_flag 1072 uint32_t SpsRangeExtensionEnableFlag : __CODEGEN_BITFIELD(31, 31) ; //!< sps_range_extension_enable_flag 1073 }; 1074 uint32_t Value; 1075 } DW3; 1076 union 1077 { 1078 struct 1079 { 1080 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 2) ; //!< Reserved 1081 uint32_t SampleAdaptiveOffsetEnabledFlag : __CODEGEN_BITFIELD( 3, 3) ; //!< sample_adaptive_offset_enabled_flag 1082 uint32_t PcmEnabledFlag : __CODEGEN_BITFIELD( 4, 4) ; //!< pcm_enabled_flag 1083 uint32_t CuQpDeltaEnabledFlag : __CODEGEN_BITFIELD( 5, 5) ; //!< CU_QP_DELTA_ENABLED_FLAG 1084 uint32_t DiffCuQpDeltaDepthOrNamedAsMaxDqpDepth : __CODEGEN_BITFIELD( 6, 7) ; //!< diff_cu_qp_delta_depth (or named as max_dqp_depth) 1085 uint32_t PcmLoopFilterDisableFlag : __CODEGEN_BITFIELD( 8, 8) ; //!< pcm_loop_filter_disable_flag 1086 uint32_t ConstrainedIntraPredFlag : __CODEGEN_BITFIELD( 9, 9) ; //!< constrained_intra_pred_flag 1087 uint32_t Log2ParallelMergeLevelMinus2 : __CODEGEN_BITFIELD(10, 12) ; //!< log2_parallel_merge_level_minus2 1088 uint32_t SignDataHidingFlag : __CODEGEN_BITFIELD(13, 13) ; //!< SIGN_DATA_HIDING_FLAG 1089 uint32_t Reserved142 : __CODEGEN_BITFIELD(14, 14) ; //!< Reserved 1090 uint32_t LoopFilterAcrossTilesEnabledFlag : __CODEGEN_BITFIELD(15, 15) ; //!< loop_filter_across_tiles_enabled_flag 1091 uint32_t EntropyCodingSyncEnabledFlag : __CODEGEN_BITFIELD(16, 16) ; //!< entropy_coding_sync_enabled_flag 1092 uint32_t TilesEnabledFlag : __CODEGEN_BITFIELD(17, 17) ; //!< tiles_enabled_flag 1093 uint32_t WeightedBipredFlag : __CODEGEN_BITFIELD(18, 18) ; //!< weighted_bipred_flag 1094 uint32_t WeightedPredFlag : __CODEGEN_BITFIELD(19, 19) ; //!< weighted_pred_flag 1095 uint32_t Fieldpic : __CODEGEN_BITFIELD(20, 20) ; //!< FIELDPIC 1096 uint32_t Bottomfield : __CODEGEN_BITFIELD(21, 21) ; //!< BOTTOMFIELD 1097 uint32_t TransformSkipEnabledFlag : __CODEGEN_BITFIELD(22, 22) ; //!< TRANSFORM_SKIP_ENABLED_FLAG 1098 uint32_t AmpEnabledFlag : __CODEGEN_BITFIELD(23, 23) ; //!< AMP_ENABLED_FLAG 1099 uint32_t Reserved152 : __CODEGEN_BITFIELD(24, 24) ; //!< Reserved 1100 uint32_t TransquantBypassEnableFlag : __CODEGEN_BITFIELD(25, 25) ; //!< TRANSQUANT_BYPASS_ENABLE_FLAG 1101 uint32_t StrongIntraSmoothingEnableFlag : __CODEGEN_BITFIELD(26, 26) ; //!< strong_intra_smoothing_enable_flag 1102 uint32_t CuPacketStructure : __CODEGEN_BITFIELD(27, 27) ; //!< CU packet structure 1103 uint32_t Reserved156 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1104 }; 1105 uint32_t Value; 1106 } DW4; 1107 union 1108 { 1109 struct 1110 { 1111 uint32_t PicCbQpOffset : __CODEGEN_BITFIELD( 0, 4) ; //!< pic_cb_qp_offset 1112 uint32_t PicCrQpOffset : __CODEGEN_BITFIELD( 5, 9) ; //!< pic_cr_qp_offset 1113 uint32_t MaxTransformHierarchyDepthIntraOrNamedAsTuMaxDepthIntra : __CODEGEN_BITFIELD(10, 12) ; //!< max_transform_hierarchy_depth_intra (or named as tu_max_depth_intra) 1114 uint32_t MaxTransformHierarchyDepthInterOrNamedAsTuMaxDepthInter : __CODEGEN_BITFIELD(13, 15) ; //!< max_transform_hierarchy_depth_inter(or named as tu_max_depth_inter) 1115 uint32_t PcmSampleBitDepthChromaMinus1 : __CODEGEN_BITFIELD(16, 19) ; //!< pcm_sample_bit_depth_chroma_minus1 1116 uint32_t PcmSampleBitDepthLumaMinus1 : __CODEGEN_BITFIELD(20, 23) ; //!< pcm_sample_bit_depth_luma_minus1 1117 uint32_t BitDepthChromaMinus8 : __CODEGEN_BITFIELD(24, 26) ; //!< BIT_DEPTH_CHROMA_MINUS8 1118 uint32_t BitDepthLumaMinus8 : __CODEGEN_BITFIELD(27, 29) ; //!< BIT_DEPTH_LUMA_MINUS8 1119 uint32_t Reserved190 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1120 }; 1121 uint32_t Value; 1122 } DW5; 1123 union 1124 { 1125 struct 1126 { 1127 uint32_t LcuMaxBitsizeAllowed : __CODEGEN_BITFIELD( 0, 15) ; //!< LCU Max BitSize Allowed 1128 uint32_t Nonfirstpassflag : __CODEGEN_BITFIELD(16, 16) ; //!< NonFirstPassFlag 1129 uint32_t Reserved209 : __CODEGEN_BITFIELD(17, 23) ; //!< Reserved 1130 uint32_t LcumaxbitstatusenLcumaxsizereportmask : __CODEGEN_BITFIELD(24, 24) ; //!< LCUMAXBITSTATUSEN_LCUMAXSIZEREPORTMASK 1131 uint32_t FrameszoverstatusenFramebitratemaxreportmask : __CODEGEN_BITFIELD(25, 25) ; //!< FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK 1132 uint32_t FrameszunderstatusenFramebitrateminreportmask : __CODEGEN_BITFIELD(26, 26) ; //!< FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK 1133 uint32_t Reserved219 : __CODEGEN_BITFIELD(27, 28) ; //!< Reserved 1134 uint32_t LoadSlicePointerFlag : __CODEGEN_BITFIELD(29, 29) ; //!< LOAD_SLICE_POINTER_FLAG 1135 uint32_t Reserved222 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1136 }; 1137 uint32_t Value; 1138 } DW6; 1139 union 1140 { 1141 struct 1142 { 1143 uint32_t Framebitratemax : __CODEGEN_BITFIELD( 0, 13) ; //!< FrameBitRateMax 1144 uint32_t Reserved238 : __CODEGEN_BITFIELD(14, 30) ; //!< Reserved 1145 uint32_t Framebitratemaxunit : __CODEGEN_BITFIELD(31, 31) ; //!< FRAMEBITRATEMAXUNIT 1146 }; 1147 uint32_t Value; 1148 } DW7; 1149 union 1150 { 1151 struct 1152 { 1153 uint32_t Framebitratemin : __CODEGEN_BITFIELD( 0, 13) ; //!< FrameBitRateMin 1154 uint32_t Reserved270 : __CODEGEN_BITFIELD(14, 30) ; //!< Reserved 1155 uint32_t Framebitrateminunit : __CODEGEN_BITFIELD(31, 31) ; //!< FRAMEBITRATEMINUNIT 1156 }; 1157 uint32_t Value; 1158 } DW8; 1159 union 1160 { 1161 struct 1162 { 1163 uint32_t Framebitratemindelta : __CODEGEN_BITFIELD( 0, 14) ; //!< FRAMEBITRATEMINDELTA 1164 uint32_t Reserved303 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 1165 uint32_t Framebitratemaxdelta : __CODEGEN_BITFIELD(16, 30) ; //!< FRAMEBITRATEMAXDELTA 1166 uint32_t Reserved319 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 1167 }; 1168 uint32_t Value; 1169 } DW9; 1170 union 1171 { 1172 struct 1173 { 1174 uint64_t Framedeltaqpmax ; //!< FrameDeltaQpMax 1175 }; 1176 uint32_t Value[2]; 1177 } DW10_11; 1178 union 1179 { 1180 struct 1181 { 1182 uint64_t Framedeltaqpmin ; //!< FrameDeltaQpMin 1183 }; 1184 uint32_t Value[2]; 1185 } DW12_13; 1186 union 1187 { 1188 struct 1189 { 1190 uint64_t Framedeltaqpmaxrange ; //!< FrameDeltaQpMaxRange 1191 }; 1192 uint32_t Value[2]; 1193 } DW14_15; 1194 union 1195 { 1196 struct 1197 { 1198 uint64_t Framedeltaqpminrange ; //!< FrameDeltaQpMinRange 1199 }; 1200 uint32_t Value[2]; 1201 } DW16_17; 1202 union 1203 { 1204 struct 1205 { 1206 uint32_t Minframesize : __CODEGEN_BITFIELD( 0, 15) ; //!< MINFRAMESIZE 1207 uint32_t Reserved592 : __CODEGEN_BITFIELD(16, 29) ; //!< Reserved 1208 uint32_t Minframesizeunits : __CODEGEN_BITFIELD(30, 31) ; //!< MINFRAMESIZEUNITS 1209 }; 1210 uint32_t Value; 1211 } DW18; 1212 union 1213 { 1214 struct 1215 { 1216 uint32_t FractionalQpInput : __CODEGEN_BITFIELD( 0, 2) ; //!< Fractional QP Input 1217 uint32_t FractionalQpOffset : __CODEGEN_BITFIELD( 3, 5) ; //!< Fractional QP Offset 1218 uint32_t RhodomainRateControlEnable : __CODEGEN_BITFIELD( 6, 6) ; //!< RhoDomain Rate Control Enable 1219 uint32_t FractionalQpAdjustmentEnable : __CODEGEN_BITFIELD( 7, 7) ; //!< Fractional QP adjustment enable 1220 uint32_t Rhodomainframelevelqp : __CODEGEN_BITFIELD( 8, 13) ; //!< RhoDomainFrameLevelQP 1221 uint32_t PakDynamicSliceModeEnable : __CODEGEN_BITFIELD(14, 14) ; //!< PAK Dynamic Slice Mode Enable 1222 uint32_t NoOutputOfPriorPicsFlag : __CODEGEN_BITFIELD(15, 15) ; //!< no_output_of_prior_pics_flag 1223 uint32_t FirstSliceSegmentInPicFlag : __CODEGEN_BITFIELD(16, 16) ; //!< first_slice_segment_in_pic_flag 1224 uint32_t Nalunittypeflag : __CODEGEN_BITFIELD(17, 17) ; //!< NalUnitTypeFlag 1225 uint32_t SlicePicParameterSetId : __CODEGEN_BITFIELD(18, 23) ; //!< slice_pic_parameter_set_id 1226 uint32_t SseEnable : __CODEGEN_BITFIELD(24, 24) ; //!< SSE Enable 1227 uint32_t RdoqEnable : __CODEGEN_BITFIELD(25, 25) ; //!< RDOQ Enable 1228 uint32_t NumberoflcusinnormalSliceSizeConformanceMode : __CODEGEN_BITFIELD(26, 27) ; //!< NumberOfLCUsInNormal Slice size conformance Mode 1229 uint32_t Reserved636 : __CODEGEN_BITFIELD(28, 29) ; //!< Reserved 1230 uint32_t PartialFrameUpdateMode : __CODEGEN_BITFIELD(30, 30) ; //!< Partial Frame Update Mode 1231 uint32_t TemporalMvPredDisable : __CODEGEN_BITFIELD(31, 31) ; //!< Temporal MV pred disable 1232 }; 1233 uint32_t Value; 1234 } DW19; 1235 union 1236 { 1237 struct 1238 { 1239 uint32_t Reserved640 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 1240 uint32_t Intratucountbasedrdoqdisable : __CODEGEN_BITFIELD( 6, 6) ; //!< IntraTuCountBasedRDOQdisable 1241 uint32_t Reserved647 : __CODEGEN_BITFIELD( 7, 31) ; //!< Reserved 1242 }; 1243 uint32_t Value; 1244 } DW20; 1245 union 1246 { 1247 struct 1248 { 1249 uint32_t SliceSizeThresholdInBytes ; //!< Slice Size Threshold in Bytes 1250 }; 1251 uint32_t Value; 1252 } DW21; 1253 union 1254 { 1255 struct 1256 { 1257 uint32_t TargetSliceSizeInBytes ; //!< Target Slice Size in Bytes 1258 }; 1259 uint32_t Value; 1260 } DW22; 1261 union 1262 { 1263 struct 1264 { 1265 uint32_t Class0SseThreshold0 : __CODEGEN_BITFIELD( 0, 15) ; //!< Class0_SSE_Threshold0 1266 uint32_t Class0SseThreshold1 : __CODEGEN_BITFIELD(16, 31) ; //!< Class0_SSE_Threshold1 1267 }; 1268 uint32_t Value; 1269 } DW23; 1270 uint32_t SseThresholdsForClass18[8]; //!< SSE thresholds for Class1-8 1271 union 1272 { 1273 struct 1274 { 1275 uint32_t CbQpOffsetList0 : __CODEGEN_BITFIELD( 0, 4) ; //!< cb_qp_offset_list[0] 1276 uint32_t CbQpOffsetList1 : __CODEGEN_BITFIELD( 5, 9) ; //!< cb_qp_offset_list[1] 1277 uint32_t CbQpOffsetList2 : __CODEGEN_BITFIELD(10, 14) ; //!< cb_qp_offset_list[2] 1278 uint32_t CbQpOffsetList3 : __CODEGEN_BITFIELD(15, 19) ; //!< cb_qp_offset_list[3] 1279 uint32_t CbQpOffsetList4 : __CODEGEN_BITFIELD(20, 24) ; //!< cb_qp_offset_list[4] 1280 uint32_t CbQpOffsetList5 : __CODEGEN_BITFIELD(25, 29) ; //!< cb_qp_offset_list[5] 1281 uint32_t Reserved1054 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1282 }; 1283 uint32_t Value; 1284 } DW32; 1285 union 1286 { 1287 struct 1288 { 1289 uint32_t CrQpOffsetList0 : __CODEGEN_BITFIELD( 0, 4) ; //!< cr_qp_offset_list[0] 1290 uint32_t CrQpOffsetList1 : __CODEGEN_BITFIELD( 5, 9) ; //!< cr_qp_offset_list[1] 1291 uint32_t CrQpOffsetList2 : __CODEGEN_BITFIELD(10, 14) ; //!< cr_qp_offset_list[2] 1292 uint32_t CrQpOffsetList3 : __CODEGEN_BITFIELD(15, 19) ; //!< cr_qp_offset_list[3] 1293 uint32_t CrQpOffsetList4 : __CODEGEN_BITFIELD(20, 24) ; //!< cr_qp_offset_list[4] 1294 uint32_t CrQpOffsetList5 : __CODEGEN_BITFIELD(25, 29) ; //!< cr_qp_offset_list[5] 1295 uint32_t Reserved1086 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1296 }; 1297 uint32_t Value; 1298 } DW33; 1299 union 1300 { 1301 struct 1302 { 1303 uint32_t IbcMotionCompensationBufferReferenceIdc : __CODEGEN_BITFIELD( 0, 2) ; //!< IBC Motion Compensation Buffer Reference IDC 1304 uint32_t Reserved1091 : __CODEGEN_BITFIELD( 3, 5) ; //!< Reserved 1305 uint32_t DeblockingFilterOverrideEnabledFlag : __CODEGEN_BITFIELD( 6, 6) ; //!< deblocking_filter_override_enabled_flag 1306 uint32_t PpsDeblockingFilterDisabledFlag : __CODEGEN_BITFIELD( 7, 7) ; //!< pps_deblocking_filter_disabled_flag 1307 uint32_t PpsActCrQpOffsetPlus3 : __CODEGEN_BITFIELD( 8, 13) ; //!< pps_act_cr_qp_offset_plus3 1308 uint32_t PpsActCbQpOffsetPlus5 : __CODEGEN_BITFIELD(14, 19) ; //!< pps_act_cb_qp_offset_plus5 1309 uint32_t PpsActYOffsetPlus5 : __CODEGEN_BITFIELD(20, 25) ; //!< pps_act_y_offset_plus5 1310 uint32_t PpsSliceActQpOffsetsPresentFlag : __CODEGEN_BITFIELD(26, 26) ; //!< pps_slice_act_qp_offsets_present_flag 1311 uint32_t ResidualAdaptiveColourTransformEnabledFlag : __CODEGEN_BITFIELD(27, 27) ; //!< residual_adaptive_colour_transform_enabled_flag 1312 uint32_t PpsCurrPicRefEnabledFlag : __CODEGEN_BITFIELD(28, 28) ; //!< pps_curr_pic_ref_enabled_flag 1313 uint32_t MotionVectorResolutionControlIdc : __CODEGEN_BITFIELD(29, 30) ; //!< MOTION_VECTOR_RESOLUTION_CONTROL_IDC 1314 uint32_t IntraBoundaryFilteringDisabledFlag : __CODEGEN_BITFIELD(31, 31) ; //!< intra_boundary_filtering_disabled_flag 1315 }; 1316 uint32_t Value; 1317 } DW34; 1318 union 1319 { 1320 struct 1321 { 1322 uint32_t PaletteMaxSize : __CODEGEN_BITFIELD( 0, 6) ; //!< palette_max_size 1323 uint32_t Reserved1127 : __CODEGEN_BITFIELD( 7, 9) ; //!< Reserved 1324 uint32_t DeltaPaletteMaxPredictorSize : __CODEGEN_BITFIELD(10, 16) ; //!< delta_palette_max_predictor_size 1325 uint32_t Reserved1137 : __CODEGEN_BITFIELD(17, 18) ; //!< Reserved 1326 uint32_t IbcMotionVectorErrorHandlingDisable : __CODEGEN_BITFIELD(19, 19) ; //!< IBC Motion Vector Error Handling Disable 1327 uint32_t ChromaBitDepthEntryMinus8 : __CODEGEN_BITFIELD(20, 23) ; //!< chroma_bit_depth_entry_minus8 1328 uint32_t LumaBitDepthEntryMinus8 : __CODEGEN_BITFIELD(24, 27) ; //!< luma_bit_depth_entry_minus8 1329 uint32_t IbcConfiguration : __CODEGEN_BITFIELD(28, 29) ; //!< IBC_CONFIGURATION 1330 uint32_t MonochromePaletteFlag : __CODEGEN_BITFIELD(30, 30) ; //!< monochrome_palette_flag 1331 uint32_t PaletteModeEnabledFlag : __CODEGEN_BITFIELD(31, 31) ; //!< palette_mode_enabled_flag 1332 }; 1333 uint32_t Value; 1334 } DW35; 1335 union 1336 { 1337 struct 1338 { 1339 uint32_t EnableFpakMessaging : __CODEGEN_BITFIELD( 0, 0) ; //!< Enable FPAK Messaging 1340 uint32_t Reserved1153 : __CODEGEN_BITFIELD( 1, 29) ; //!< Reserved 1341 uint32_t FrameCrcType : __CODEGEN_BITFIELD(30, 30) ; //!< FRAME_CRC_TYPE 1342 uint32_t FrameCrcEnable : __CODEGEN_BITFIELD(31, 31) ; //!< Frame CRC Enable 1343 }; 1344 uint32_t Value; 1345 } DW36; 1346 union 1347 { 1348 struct 1349 { 1350 uint32_t Rdoqintratuthreshold : __CODEGEN_BITFIELD( 0, 15) ; //!< RDOQIntraTUThreshold 1351 uint32_t Reserved1200 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1352 }; 1353 uint32_t Value; 1354 } DW37; 1355 union 1356 { 1357 struct 1358 { 1359 uint32_t Rdoqintra16X16Tuthreshold : __CODEGEN_BITFIELD( 0, 15) ; //!< RDOQIntra16x16TUThreshold 1360 uint32_t Rdoqintra32X32Tuthreshold : __CODEGEN_BITFIELD(16, 31) ; //!< RDOQIntra32x32TUThreshold 1361 }; 1362 uint32_t Value; 1363 } DW38; 1364 union 1365 { 1366 struct 1367 { 1368 uint64_t SsethresholdsForClass910 ; //!< SSEThresholds for Class9 ..10 1369 }; 1370 uint32_t Value[2]; 1371 } DW39_40; 1372 1373 //! \name Local enumerations 1374 1375 enum MEDIA_INSTRUCTION_COMMAND 1376 { 1377 MEDIA_INSTRUCTION_COMMAND_HCPPICSTATE = 16, //!< No additional details 1378 }; 1379 1380 //! \brief MEDIA_INSTRUCTION_OPCODE 1381 //! \details 1382 //! Codec/Engine Name = HCP = 7h 1383 enum MEDIA_INSTRUCTION_OPCODE 1384 { 1385 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 1386 }; 1387 1388 enum PIPELINE_TYPE 1389 { 1390 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 1391 }; 1392 1393 enum COMMAND_TYPE 1394 { 1395 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1396 }; 1397 1398 //! \brief MINCUSIZE 1399 //! \details 1400 //! Specifies the smallest coding block size. 1401 enum MINCUSIZE 1402 { 1403 MINCUSIZE_8X8 = 0, //!< No additional details 1404 MINCUSIZE_16X16 = 1, //!< No additional details 1405 MINCUSIZE_32X32 = 2, //!< No additional details 1406 MINCUSIZE_64X64 = 3, //!< No additional details 1407 }; 1408 1409 //! \brief CTBSIZE_LCUSIZE 1410 //! \details 1411 //! Specifies the coding tree block size. 1412 enum CTBSIZE_LCUSIZE 1413 { 1414 CTBSIZE_LCUSIZE_ILLEGALRESERVED = 0, //!< No additional details 1415 CTBSIZE_LCUSIZE_16X16 = 1, //!< No additional details 1416 CTBSIZE_LCUSIZE_32X32 = 2, //!< No additional details 1417 CTBSIZE_LCUSIZE_64X64 = 3, //!< No additional details 1418 }; 1419 1420 //! \brief MINTUSIZE 1421 //! \details 1422 //! Specifies the smallest allowed transform block size. 1423 enum MINTUSIZE 1424 { 1425 MINTUSIZE_4X4 = 0, //!< No additional details 1426 MINTUSIZE_8X8 = 1, //!< No additional details 1427 MINTUSIZE_16X16 = 2, //!< No additional details 1428 MINTUSIZE_32X32 = 3, //!< No additional details 1429 }; 1430 1431 //! \brief MAXTUSIZE 1432 //! \details 1433 //! Specifies the largest allowed transform block size. 1434 enum MAXTUSIZE 1435 { 1436 MAXTUSIZE_4X4 = 0, //!< No additional details 1437 MAXTUSIZE_8X8 = 1, //!< No additional details 1438 MAXTUSIZE_16X16 = 2, //!< No additional details 1439 MAXTUSIZE_32X32 = 3, //!< No additional details 1440 }; 1441 1442 //! \brief MINPCMSIZE 1443 //! \details 1444 //! Specifies the smallest allowed PCM coding block size. 1445 enum MINPCMSIZE 1446 { 1447 MINPCMSIZE_8X8 = 0, //!< No additional details 1448 MINPCMSIZE_16X16 = 1, //!< No additional details 1449 MINPCMSIZE_32X32 = 2, //!< No additional details 1450 }; 1451 1452 //! \brief MAXPCMSIZE 1453 //! \details 1454 //! Specifies the largest allowed PCM coding block size. 1455 enum MAXPCMSIZE 1456 { 1457 MAXPCMSIZE_8X8 = 0, //!< No additional details 1458 MAXPCMSIZE_16X16 = 1, //!< No additional details 1459 MAXPCMSIZE_32X32 = 2, //!< No additional details 1460 }; 1461 1462 //! \brief LOG2_SAO_OFFSET_SCALE_LUMA 1463 //! \details 1464 //! <p>To scale SAO offset values for luma samples</p> 1465 //! <p>0 to Max(0,BitDepth<sub><font size="2">C</font></sub>−10)</p> 1466 //! <p>Default = 0</p> 1467 enum LOG2_SAO_OFFSET_SCALE_LUMA 1468 { 1469 LOG2_SAO_OFFSET_SCALE_LUMA_0 = 0, //!< No additional details 1470 LOG2_SAO_OFFSET_SCALE_LUMA_1 = 1, //!< No additional details 1471 LOG2_SAO_OFFSET_SCALE_LUMA_2 = 2, //!< No additional details 1472 }; 1473 1474 //! \brief LOG2_SAO_OFFSET_SCALE_CHROMA 1475 //! \details 1476 //! <p>To scale SAO offset values for chroma samples.</p> 1477 //! <p>0 to Max(0,BitDepth<sub>C</sub>−10)</p> 1478 //! <p>default = 0</p> 1479 //! <p>Decoder Only</p> 1480 enum LOG2_SAO_OFFSET_SCALE_CHROMA 1481 { 1482 LOG2_SAO_OFFSET_SCALE_CHROMA_0 = 0, //!< No additional details 1483 LOG2_SAO_OFFSET_SCALE_CHROMA_1 = 1, //!< No additional details 1484 LOG2_SAO_OFFSET_SCALE_CHROMA_2 = 2, //!< No additional details 1485 }; 1486 1487 //! \brief CHROMA_SUBSAMPLING 1488 //! \details 1489 //! <p>Specify the chroma subsampling of the current bitstream to be decoded 1490 //! or encoded.</p> 1491 //! <p>000 (0h) - Reserved (This setting is reserved for Monochrome 1492 //! setting--currently not suppported)</p> 1493 //! <p>001 (1h) - 4:2:0</p> 1494 //! <p>010 (2h) - 4:2:2</p> 1495 //! <p>011 (3h) - 4:4:4</p> 1496 //! <p>All other values are invalid for both encoder and decoder.</p> 1497 enum CHROMA_SUBSAMPLING 1498 { 1499 CHROMA_SUBSAMPLING_420 = 1, //!< No additional details 1500 CHROMA_SUBSAMPLING_422 = 2, //!< No additional details 1501 CHROMA_SUBSAMPLING_444 = 3, //!< No additional details 1502 }; 1503 1504 //! \brief COLPICISI 1505 //! \details 1506 //! Specifies that the collocated picture is comprised solely of I slices 1507 //! and that there are no P or B slices in the picture. 1508 enum COLPICISI 1509 { 1510 COLPICISI_COLLOCATEDPICTUREHASATLEASTONEPORBSLICE = 0, //!< No additional details 1511 }; 1512 1513 //! \brief CURPICISI 1514 //! \details 1515 //! Specifies that the current picture is comprised solely of I slices and 1516 //! that there are no P or B slices in the picture. 1517 enum CURPICISI 1518 { 1519 CURPICISI_CURRENTPICTUREHASATLEASTONEPORBSLICE = 0, //!< No additional details 1520 }; 1521 1522 //! \brief INSERTTESTFLAG 1523 //! \details 1524 //! <p>CABAC 0 Word Insertion Test Enable (Encoder Only)This bit will modify 1525 //! CABAC K equation so that a positive K value can be generated easily. 1526 //! This is done for validation purpose only. In normal usage this bit 1527 //! should be set to 0.</p> 1528 //! <p>Regular equation for generating 'K' value when CABAC 0 Word Insertion 1529 //! Test Enable is set to 0.</p> 1530 //! <pre>K = {[((96 * pic_bin_count()) - (RawMinCUBits * PicSizeInMinCUs *3) 1531 //! + 1023) / 1024] - bytes_in_picture} / 3</pre> 1532 //! 1533 //! <p>Modified equation when CABAC 0 Word Insertion Test Enable bit set to 1534 //! 1.</p> 1535 //! 1536 //! <pre>K = {[((1536 * pic_bin_count()) - (RawMinCUBits * PicSizeInMinCUs 1537 //! *3) + 1023) / 1024] - bytes_in_picture} / 3</pre> 1538 //! 1539 //! <p>Encoder only feature.</p> 1540 enum INSERTTESTFLAG 1541 { 1542 INSERTTESTFLAG_UNNAMED0 = 0, //!< No additional details 1543 INSERTTESTFLAG_UNNAMED1 = 1, //!< No additional details 1544 }; 1545 1546 //! \brief CU_QP_DELTA_ENABLED_FLAG 1547 //! \details 1548 //! <p>cu_qp_delta_enabled_flag = 1 and Max_DQP_Level = 0 or 3 is supported 1549 //! for PAK standalone andVDEnc modes.</p> 1550 enum CU_QP_DELTA_ENABLED_FLAG 1551 { 1552 CU_QP_DELTA_ENABLED_FLAG_DISABLE = 0, //!< Does not allow QP change at CU or LCU level, the same QP is used for the entire slice. Max_DQP_Level = 0 (i.e. diff_cu_qp_delta_depath = 0). 1553 CU_QP_DELTA_ENABLED_FLAG_ENABLE = 1, //!< Allow QP change at CU level. MAX_DQP_level can be >0. 1554 }; 1555 1556 //! \brief SIGN_DATA_HIDING_FLAG 1557 //! \details 1558 //! Currently not supported in encoder, so must be set to 0 for encoding 1559 //! session. 1560 enum SIGN_DATA_HIDING_FLAG 1561 { 1562 SIGN_DATA_HIDING_FLAG_DISABLE = 0, //!< Specifies that sign bit hiding is disabled. 1563 SIGN_DATA_HIDING_FLAG_ENABLE = 1, //!< Specifies that sign bit hiding is enabled. 1564 }; 1565 1566 //! \brief FIELDPIC 1567 //! \details 1568 //! <p>Must be zero for encoder only.</p> 1569 enum FIELDPIC 1570 { 1571 FIELDPIC_VIDEOFRAME = 0, //!< No additional details 1572 FIELDPIC_VIDEOFIELD = 1, //!< No additional details 1573 }; 1574 1575 //! \brief BOTTOMFIELD 1576 //! \details 1577 //! <p>Must be zero for encoder only</p> 1578 enum BOTTOMFIELD 1579 { 1580 BOTTOMFIELD_BOTTOMFIELD = 0, //!< No additional details 1581 BOTTOMFIELD_TOPFIELD = 1, //!< No additional details 1582 }; 1583 1584 enum TRANSFORM_SKIP_ENABLED_FLAG 1585 { 1586 TRANSFORM_SKIP_ENABLED_FLAG_DISABLE = 0, //!< transform_skip_flag is not supported in the residual coding 1587 TRANSFORM_SKIP_ENABLED_FLAG_ENABLE = 1, //!< transform_skip_flag is supported 1588 }; 1589 1590 //! \brief AMP_ENABLED_FLAG 1591 //! \details 1592 //! In VDENC mode, this bit should be set to 1. 1593 enum AMP_ENABLED_FLAG 1594 { 1595 AMP_ENABLED_FLAG_DISABLE = 0, //!< Asymmetric motion partitions cannot be used in coding tree blocks. 1596 AMP_ENABLED_FLAG_ENABLE = 1, //!< Support asymmetric motion partitions, i.e. PartMode equal to PART_2NxnU, PART_2NxnD, PART_nLx2N, or PART_nRx2N. 1597 }; 1598 1599 enum TRANSQUANT_BYPASS_ENABLE_FLAG 1600 { 1601 TRANSQUANT_BYPASS_ENABLE_FLAG_DISABLE = 0, //!< cu_transquant_bypass is not supported 1602 TRANSQUANT_BYPASS_ENABLE_FLAG_ENABLE = 1, //!< cu_transquant_bypass is supported 1603 }; 1604 1605 //! \brief BIT_DEPTH_CHROMA_MINUS8 1606 //! \details 1607 //! This specifies the number of bit allow for Chroma pixels. In 8 bit mode, 1608 //! this must be set to 0. Encoder: Supports bit depths 8, 10 and 12 only. 1609 //! And also it must be same as Luma. Encoder: Does not support 10 or 12 bit 1610 //! Source Pixels and 8bit PAK. i.e. The source pixel depth should be less 1611 //! than or equal to the PAK bit depth. 1612 enum BIT_DEPTH_CHROMA_MINUS8 1613 { 1614 BIT_DEPTH_CHROMA_MINUS8_CHROMA8BIT = 0, //!< No additional details 1615 BIT_DEPTH_CHROMA_MINUS8_CHROMA9BIT = 1, //!< Only HEVC decoder supports 9 bits chroma.HEVC encoder does not supports 9 bits chroma. 1616 BIT_DEPTH_CHROMA_MINUS8_CHROMA10BIT = 2, //!< No additional details 1617 BIT_DEPTH_CHROMA_MINUS8_CHROMA11BIT = 3, //!< HEVC SCC does not support 11 bits chromaAlso only HEVC decoder (non-SCC) support 11 bits chromaHEVC encoder (non-SCC) does not support 11 bits chroma 1618 BIT_DEPTH_CHROMA_MINUS8_CHROMA12BIT = 4, //!< HEVC SCC does not support 12bits Luma 1619 }; 1620 1621 //! \brief BIT_DEPTH_LUMA_MINUS8 1622 //! \details 1623 //! This specifies the number of bit allow for Luma pixels. In 8 bit mode, 1624 //! this must be set to 0. Encoder: Suports bit depths 8, 10 and 12 only. 1625 //! Encoder: Does not support 10 or 12 bit Source Pixels and 8bit PAK i.e. 1626 //! the source pixel depth should be less than or equal to PAK bit depth. 1627 enum BIT_DEPTH_LUMA_MINUS8 1628 { 1629 BIT_DEPTH_LUMA_MINUS8_LUMA8BIT = 0, //!< No additional details 1630 BIT_DEPTH_LUMA_MINUS8_LUMA9BIT = 1, //!< Only HEVC decoder supports 9 bits luma.HEVC encoder does not supports 9 bits luma. 1631 BIT_DEPTH_LUMA_MINUS8_LUMA10BIT = 2, //!< No additional details 1632 BIT_DEPTH_LUMA_MINUS8_LUMA11BIT = 3, //!< HEVC SCC does not support 11 bits LumaAlso only HEVC decoder (non-SCC) support 11 bits LumaHEVC encoder (non-SCC) does not support 11 bits Luma 1633 BIT_DEPTH_LUMA_MINUS8_LUMA12BIT = 4, //!< HEVC SCC does not support 12bits Luma 1634 }; 1635 1636 //! \brief NONFIRSTPASSFLAG 1637 //! \details 1638 //! This signals the current pass is not the first pass. It will imply 1639 //! designate HW behavior. 1640 enum NONFIRSTPASSFLAG 1641 { 1642 NONFIRSTPASSFLAG_DISABLE = 0, //!< If it is initial-Pass, this bit is set to 0. 1643 NONFIRSTPASSFLAG_ENABLE = 1, //!< For subsequent passes, this bit is set to 1. 1644 }; 1645 1646 //! \brief LCUMAXBITSTATUSEN_LCUMAXSIZEREPORTMASK 1647 //! \details 1648 //! This is a mask bit controlling if the condition of any LCU in the frame 1649 //! exceeds LCUMaxSize. 1650 enum LCUMAXBITSTATUSEN_LCUMAXSIZEREPORTMASK 1651 { 1652 LCUMAXBITSTATUSEN_LCUMAXSIZEREPORTMASK_DISABLE = 0, //!< Do not update bit 0 of HCP_IMAGE_STATUS control register. 1653 LCUMAXBITSTATUSEN_LCUMAXSIZEREPORTMASK_ENABLE = 1, //!< HW does not use this bit to set the bit in HCP_IMAGE_STATUS_CONTROL register. 1654 }; 1655 1656 //! \brief FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK 1657 //! \details 1658 //! This is a mask bit controlling if the condition of frame level bit count 1659 //! exceeds FrameBitRateMax. 1660 enum FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK 1661 { 1662 FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK_DISABLE = 0, //!< Do not update bit 1 of HCP_IMAGE_STATUS control register. 1663 FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK_ENABLE = 1, //!< HW does not use this bit to set the bit in HCP_IMAGE_STATUS_CONTROL register. It's used pass the bit inHCP_IMAGE_STATUS_MASK register 1664 }; 1665 1666 //! \brief FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK 1667 //! \details 1668 //! This is a mask bit controlling if the condition of frame level bit count 1669 //! is less than FrameBitRateMin. 1670 enum FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK 1671 { 1672 FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK_DISABLE = 0, //!< Do not update bit 2 (Frame Bit Count Violate -- under run) of HCP_IMAGE_STATUS control register. 1673 FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK_ENABLE = 1, //!< Set bit 2 (Frame Bit Count Violate -- under run) of HCP_IMAGE_STATUS control register if the total frame level bit counter is less than or equal to Frame Bit Rate Minimum limit. HW does not use this bit to set the bit in HCP_IMAGE_STATUS_CONTROL register. It's used pass the bit in HCP_IMAGE_STATUS_MASK register 1674 }; 1675 1676 //! \brief LOAD_SLICE_POINTER_FLAG 1677 //! \details 1678 //! <p>LoadBitStreamPointerPerSlice (Encoder-only)</p> 1679 //! <p>To support multiple slice picture and additional header/data 1680 //! insertion before and after an encoded slice. When this field is set to 1681 //! 0, bitstream pointer is only loaded once for the first slice of a frame. 1682 //! For subsequent slices in the frame, bitstream data are stitched together 1683 //! to form a single output data stream. When this field is set to 1, 1684 //! bitstream pointer is loaded for each slice of a frame. Basically 1685 //! bitstream data for different slices of a frame will be written to 1686 //! different memory locations.</p> 1687 enum LOAD_SLICE_POINTER_FLAG 1688 { 1689 LOAD_SLICE_POINTER_FLAG_DISABLE = 0, //!< Load BitStream Pointer only once for the first slice of a frame. 1690 LOAD_SLICE_POINTER_FLAG_ENABLE = 1, //!< Load/reload BitStream Pointer only once for the each slice, reload the start location of thebitstream buffer from the Indirect PAK-BSE Object Data Start Address field. 1691 }; 1692 1693 //! \brief FRAMEBITRATEMAXUNIT 1694 //! \details 1695 //! This field is the Frame Bitrate Maximum Limit Units. 1696 enum FRAMEBITRATEMAXUNIT 1697 { 1698 FRAMEBITRATEMAXUNIT_BYTE = 0, //!< 32byte unit 1699 FRAMEBITRATEMAXUNIT_KILOBYTE = 1, //!< 4kbyte unit 1700 }; 1701 1702 //! \brief FRAMEBITRATEMINUNIT 1703 //! \details 1704 //! This field is the Frame Bitrate Minimum Limit Units. 1705 enum FRAMEBITRATEMINUNIT 1706 { 1707 FRAMEBITRATEMINUNIT_BYTE = 0, //!< 32byte unit 1708 FRAMEBITRATEMINUNIT_KILOBYTE = 1, //!< 4kbyte unit 1709 }; 1710 1711 //! \brief FRAMEBITRATEMINDELTA 1712 //! \details 1713 //! This field is used to select the slice delta QP when FrameBitRateMin Is 1714 //! exceeded. It shares the same 1715 //! FrameBitrateMinUnit. 1716 enum FRAMEBITRATEMINDELTA 1717 { 1718 FRAMEBITRATEMINDELTA_UNNAMED0 = 0, //!< No additional details 1719 }; 1720 1721 //! \brief FRAMEBITRATEMAXDELTA 1722 //! \details 1723 //! This field is used to select the slice delta QP when FrameBitRateMax Is 1724 //! exceeded. It shares the same 1725 //! FrameBitrateMaxUnit. 1726 enum FRAMEBITRATEMAXDELTA 1727 { 1728 FRAMEBITRATEMAXDELTA_UNNAMED0 = 0, //!< No additional details 1729 }; 1730 1731 //! \brief MINFRAMESIZE 1732 //! \details 1733 //! <p>Minimum Frame Size [15:0] (in Word, 16-bit)(Encoder Only)</p> 1734 //! <p>Mininum Frame Size is specified to compensate for intel Rate Control 1735 //! Currently zero fill (no need to perform emulation byte insertion) is 1736 //! done only to the end of the CABAC_ZERO_WORD insertion (if any) at the 1737 //! last slice of a picture. It is needed for CBR. Intel encoder parameter. 1738 //! The caller should always make sure that the value, represented by 1739 //! Mininum Frame Size, is always less than maximum frame size 1740 //! FrameBitRateMax. This field is reserved in Decode mode.</p> 1741 enum MINFRAMESIZE 1742 { 1743 MINFRAMESIZE_UNNAMED0 = 0, //!< No additional details 1744 }; 1745 1746 //! \brief MINFRAMESIZEUNITS 1747 //! \details 1748 //! This field is the Minimum Frame Size Units 1749 enum MINFRAMESIZEUNITS 1750 { 1751 MINFRAMESIZEUNITS_4KB = 0, //!< Minimum Frame Size is in 4Kbytes. 1752 MINFRAMESIZEUNITS_16KB = 1, //!< Minimum Frame Size is in 16Kbytes. 1753 MINFRAMESIZEUNITS_COMPATIBILITYMODE = 2, //!< Minimum Frame Size is in 4bytes 1754 MINFRAMESIZEUNITS_16BYTES = 3, //!< Minimum Frame Size is 16 bytes. 1755 }; 1756 1757 //! \brief MOTION_VECTOR_RESOLUTION_CONTROL_IDC 1758 //! \details 1759 //! <p>This controls the presense and inference of the use_integer_mv_flag 1760 //! that specifies the resolution of motion vectors for inter 1761 //! prediction.</p> 1762 //! <p>Decoder only (Encoder default to "00")</p> 1763 enum MOTION_VECTOR_RESOLUTION_CONTROL_IDC 1764 { 1765 MOTION_VECTOR_RESOLUTION_CONTROL_IDC_NOINTEGERMVFORTHEFRAME = 0, //!< No additional details 1766 MOTION_VECTOR_RESOLUTION_CONTROL_IDC_ONLYINTEGERMVFORTHEFRAME = 1, //!< No additional details 1767 MOTION_VECTOR_RESOLUTION_CONTROL_IDC_ADAPTIVEINTEGERMVFORTHEFRAME = 2, //!< Slice signal use_inter_mv_flag will indicate if the slice will use interger MV or not 1768 }; 1769 1770 //! \brief IBC_CONFIGURATION 1771 //! \details 1772 //! <p>IBC configuration is used configure Intra block copy.</p> 1773 //! <p>- Disable Intra block copy.</p> 1774 //! <p>- Limit Intra block copy from Left blocks only.</p> 1775 //! <p>- Allow full range of Intra block copy as specified in spec.</p> 1776 //! <p></p> 1777 enum IBC_CONFIGURATION 1778 { 1779 IBC_CONFIGURATION_UNNAMED0 = 0, //!< When IBC configuration is 0, intra block copy is disabled and it applies for both Fixed function encoder and decoder. 1780 IBC_CONFIGURATION_UNNAMED1 = 1, //!< When IBC configuration in fixed function encoder (VDENC) mode is set to 1, Intra block search includes only left region. 1781 IBC_CONFIGURATION_UNNAMED2 = 2, //!< No additional details 1782 IBC_CONFIGURATION_UNNAMED3 = 3, //!< When IBC configuration in VDENC mode is set to 3, Intra block search includes top and left regions.In decoder mode, When SCC is enabled this field should be set to 3. 1783 }; 1784 1785 //! \brief FRAME_CRC_TYPE 1786 //! \details 1787 //! <p>This indicates how CRC is generated. This bit is ignored and must be 1788 //! programmed to 0 if Frame CRC Enable is "0"</p> 1789 enum FRAME_CRC_TYPE 1790 { 1791 FRAME_CRC_TYPE_CRCWITHYUVVALUE = 0, //!< No additional details 1792 FRAME_CRC_TYPE_CRCWITHYVALUEONLY = 1, //!< No additional details 1793 }; 1794 1795 //! \name Initializations 1796 1797 //! \brief Explicit member initialization function 1798 HCP_PIC_STATE_CMD(); 1799 1800 static const size_t dwSize = 41; 1801 static const size_t byteSize = 164; 1802 }; 1803 1804 //! 1805 //! \brief HCP_TILE_POSITION_IN_CTB 1806 //! \details 1807 //! 1808 //! 1809 struct HCP_TILE_POSITION_IN_CTB_CMD 1810 { 1811 union 1812 { 1813 struct 1814 { 1815 uint32_t Ctbpos0I : __CODEGEN_BITFIELD( 0, 7) ; //!< CtbPos0+i 1816 uint32_t Ctbpos1I : __CODEGEN_BITFIELD( 8, 15) ; //!< CtbPos1+i 1817 uint32_t Ctbpos2I : __CODEGEN_BITFIELD(16, 23) ; //!< CtbPos2+i 1818 uint32_t Ctbpos3I : __CODEGEN_BITFIELD(24, 31) ; //!< CtbPos3+i 1819 }; 1820 uint32_t Value; 1821 } DW0; 1822 1823 //! \name Local enumerations 1824 1825 //! \name Initializations 1826 1827 //! \brief Explicit member initialization function 1828 HCP_TILE_POSITION_IN_CTB_CMD(); 1829 1830 static const size_t dwSize = 1; 1831 static const size_t byteSize = 4; 1832 }; 1833 1834 //! 1835 //! \brief HCP_TILE_POSITION_IN_CTB_MSB 1836 //! \details 1837 //! Added to support 16k picture size. 1838 //! 1839 struct HCP_TILE_POSITION_IN_CTB_MSB_CMD 1840 { 1841 union 1842 { 1843 struct 1844 { 1845 uint32_t CtbRowPositionOfTileColumn098 : __CODEGEN_BITFIELD( 0, 1) ; //!< Ctb row position of tile column 0 [9:8] 1846 uint32_t CtbRowPositionOfTileColumn198 : __CODEGEN_BITFIELD( 2, 3) ; //!< Ctb row position of tile column 1 [9:8] 1847 uint32_t CtbRowPositionOfTileColumn298 : __CODEGEN_BITFIELD( 4, 5) ; //!< Ctb row position of tile column 2 [9:8] 1848 uint32_t CtbRowPositionOfTileColumn398 : __CODEGEN_BITFIELD( 6, 7) ; //!< Ctb row position of tile column 3 [9:8] 1849 uint32_t CtbRowPositionOfTileColumn498 : __CODEGEN_BITFIELD( 8, 9) ; //!< Ctb row position of tile column 4 [9:8] 1850 uint32_t CtbRowPositionOfTileColumn598 : __CODEGEN_BITFIELD(10, 11) ; //!< Ctb row position of tile column 5 [9:8] 1851 uint32_t CtbRowPositionOfTileColumn698 : __CODEGEN_BITFIELD(12, 13) ; //!< Ctb row position of tile column 6 [9:8] 1852 uint32_t CtbRowPositionOfTileColumn798 : __CODEGEN_BITFIELD(14, 15) ; //!< Ctb row position of tile column 7 [9:8] 1853 uint32_t CtbRowPositionOfTileColumn898 : __CODEGEN_BITFIELD(16, 17) ; //!< Ctb row position of tile column 8 [9:8] 1854 uint32_t CtbRowPositionOfTileColumn998 : __CODEGEN_BITFIELD(18, 19) ; //!< Ctb row position of tile column 9 [9:8] 1855 uint32_t CtbRowPositionOfTileColumn1098 : __CODEGEN_BITFIELD(20, 21) ; //!< Ctb row position of tile column 10 [9:8] 1856 uint32_t CtbRowPositionOfTileColumn1198 : __CODEGEN_BITFIELD(22, 23) ; //!< Ctb row position of tile column 11 [9:8] 1857 uint32_t CtbRowPositionOfTileColumn1298 : __CODEGEN_BITFIELD(24, 25) ; //!< Ctb row position of tile column 12 [9:8] 1858 uint32_t CtbRowPositionOfTileColumn1398 : __CODEGEN_BITFIELD(26, 27) ; //!< Ctb row position of tile column 13 [9:8] 1859 uint32_t CtbRowPositionOfTileColumn1498 : __CODEGEN_BITFIELD(28, 29) ; //!< Ctb row position of tile column 14 [9:8] 1860 uint32_t CtbRowPositionOfTileColumn1598 : __CODEGEN_BITFIELD(30, 31) ; //!< Ctb row position of tile column 15 [9:8] 1861 }; 1862 uint32_t Value; 1863 } DW0; 1864 union 1865 { 1866 struct 1867 { 1868 uint32_t CtbRowPositionOfTileColumn1698 : __CODEGEN_BITFIELD( 0, 1) ; //!< Ctb row position of tile column 16 [9:8] 1869 uint32_t CtbRowPositionOfTileColumn1798 : __CODEGEN_BITFIELD( 2, 3) ; //!< Ctb row position of tile column 17 [9:8] 1870 uint32_t CtbRowPositionOfTileColumn1898 : __CODEGEN_BITFIELD( 4, 5) ; //!< Ctb row position of tile column 18 [9:8] 1871 uint32_t CtbRowPositionOfTileColumn1998 : __CODEGEN_BITFIELD( 6, 7) ; //!< Ctb row position of tile column 19 [9:8] 1872 uint32_t CtbRowPositionOfTileColumn2098 : __CODEGEN_BITFIELD( 8, 9) ; //!< Ctb row position of tile column 20 [9:8] 1873 uint32_t CtbPositionOfTile2198 : __CODEGEN_BITFIELD(10, 11) ; //!< Ctb position of tile 21 [9:8] 1874 uint32_t Reserved44 : __CODEGEN_BITFIELD(12, 31) ; //!< Reserved 1875 }; 1876 uint32_t Value; 1877 } DW1; 1878 1879 //! \name Local enumerations 1880 1881 //! \name Initializations 1882 1883 //! \brief Explicit member initialization function 1884 HCP_TILE_POSITION_IN_CTB_MSB_CMD(); 1885 1886 static const size_t dwSize = 2; 1887 static const size_t byteSize = 8; 1888 }; 1889 1890 //! 1891 //! \brief HCP_TILE_STATE 1892 //! \details 1893 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 1894 //! Commands. Each HCP command has assigned a media instruction command as 1895 //! defined in DWord 0, BitField 22:16. 1896 //! 1897 //! This command is valid for decoder only. 1898 //! 1899 struct HCP_TILE_STATE_CMD 1900 { 1901 union 1902 { 1903 struct 1904 { 1905 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1906 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1907 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 1908 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 1909 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 1910 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1911 }; 1912 uint32_t Value; 1913 } DW0; 1914 union 1915 { 1916 struct 1917 { 1918 uint32_t Numtilerowsminus1 : __CODEGEN_BITFIELD( 0, 4) ; //!< NumTileRowsMinus1 1919 uint32_t Numtilecolumnsminus1 : __CODEGEN_BITFIELD( 5, 9) ; //!< NumTileColumnsMinus1 1920 uint32_t Reserved42 : __CODEGEN_BITFIELD(10, 31) ; //!< Reserved 1921 }; 1922 uint32_t Value; 1923 } DW1; 1924 HCP_TILE_POSITION_IN_CTB_CMD CtbColumnPositionOfTileColumn[5]; //!< DW2..6, Ctb column position of tile column 1925 HCP_TILE_POSITION_IN_CTB_CMD CtbRowPositionOfTileRow[6]; //!< DW7..12, Ctb row position of tile row 1926 HCP_TILE_POSITION_IN_CTB_MSB_CMD CtbColumnPositionMsb; //!< DW13..14, Ctb column position MSB 1927 HCP_TILE_POSITION_IN_CTB_MSB_CMD CtbRowPositionMsb; //!< DW15..16, Ctb row position MSB 1928 1929 //! \name Local enumerations 1930 1931 enum MEDIA_INSTRUCTION_COMMAND 1932 { 1933 MEDIA_INSTRUCTION_COMMAND_HCPTILESTATE = 17, //!< No additional details 1934 }; 1935 1936 //! \brief MEDIA_INSTRUCTION_OPCODE 1937 //! \details 1938 //! Codec/Engine Name = HCP = 7h 1939 enum MEDIA_INSTRUCTION_OPCODE 1940 { 1941 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 1942 }; 1943 1944 enum PIPELINE_TYPE 1945 { 1946 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 1947 }; 1948 1949 enum COMMAND_TYPE 1950 { 1951 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1952 }; 1953 1954 //! \name Initializations 1955 1956 //! \brief Explicit member initialization function 1957 HCP_TILE_STATE_CMD(); 1958 1959 static const size_t dwSize = 17; 1960 static const size_t byteSize = 68; 1961 }; 1962 1963 //! 1964 //! \brief HCP_REF_LIST_ENTRY 1965 //! \details 1966 //! 1967 //! 1968 struct HCP_REF_LIST_ENTRY_CMD 1969 { 1970 union 1971 { 1972 struct 1973 { 1974 uint32_t ReferencePictureTbValue : __CODEGEN_BITFIELD( 0, 7) ; //!< Reference Picture tb Value 1975 uint32_t ListEntryLxReferencePictureFrameIdRefaddr07 : __CODEGEN_BITFIELD( 8, 10) ; //!< list_entry_lX: Reference Picture Frame ID (RefAddr[0-7]) 1976 uint32_t ChromaWeightLxFlag : __CODEGEN_BITFIELD(11, 11) ; //!< CHROMA_WEIGHT_LX_FLAG 1977 uint32_t LumaWeightLxFlag : __CODEGEN_BITFIELD(12, 12) ; //!< LUMA_WEIGHT_LX_FLAG 1978 uint32_t Longtermreference : __CODEGEN_BITFIELD(13, 13) ; //!< LONGTERMREFERENCE 1979 uint32_t FieldPicFlag : __CODEGEN_BITFIELD(14, 14) ; //!< FIELD_PIC_FLAG 1980 uint32_t BottomFieldFlag : __CODEGEN_BITFIELD(15, 15) ; //!< BOTTOM_FIELD_FLAG 1981 uint32_t Reserved16 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1982 }; 1983 uint32_t Value; 1984 } DW0; 1985 1986 //! \name Local enumerations 1987 1988 //! \brief CHROMA_WEIGHT_LX_FLAG 1989 //! \details 1990 //! Where X is the RefPicListNum and i is the list entry number 0 through 1991 //! 15. DW2 corresponds to i=0, 1992 //! DW17 corresponds to i=15. 1993 enum CHROMA_WEIGHT_LX_FLAG 1994 { 1995 CHROMA_WEIGHT_LX_FLAG_DEFAULTWEIGHTEDPREDICTIONFORCHROMA = 0, //!< No additional details 1996 CHROMA_WEIGHT_LX_FLAG_EXPLICITWEIGHTEDPREDICTIONFORCHROMA = 1, //!< No additional details 1997 }; 1998 1999 //! \brief LUMA_WEIGHT_LX_FLAG 2000 //! \details 2001 //! Where X is the RefPicListNum and i is the list entry number 0 through 2002 //! 15. DW2 corresponds to i=0, 2003 //! DW17 corresponds to i=15. 2004 enum LUMA_WEIGHT_LX_FLAG 2005 { 2006 LUMA_WEIGHT_LX_FLAG_DEFAULTWEIGHTEDPREDICTIONFORLUMA = 0, //!< No additional details 2007 LUMA_WEIGHT_LX_FLAG_EXPLICITWEIGHTEDPREDICTIONFORLUMA = 1, //!< No additional details 2008 }; 2009 2010 //! \brief LONGTERMREFERENCE 2011 //! \details 2012 //! Where X is the RefPicListNum and i is the list entry number 0 through 2013 //! 15. DW2 corresponds to i=0, 2014 //! DW17 corresponds to i=15. 2015 enum LONGTERMREFERENCE 2016 { 2017 LONGTERMREFERENCE_SHORTTERMREFERENCE = 0, //!< No additional details 2018 LONGTERMREFERENCE_LONGTERMREFERENCE = 1, //!< No additional details 2019 }; 2020 2021 //! \brief FIELD_PIC_FLAG 2022 //! \details 2023 //! Where X is the RefPicListNum and i is the list entry number 0 through 2024 //! 15. DW2 corresponds to i=0, 2025 //! DW17 corresponds to i=15. 2026 enum FIELD_PIC_FLAG 2027 { 2028 FIELD_PIC_FLAG_VIDEOFRAME = 0, //!< No additional details 2029 FIELD_PIC_FLAG_VIDEOFIELD = 1, //!< No additional details 2030 }; 2031 2032 //! \brief BOTTOM_FIELD_FLAG 2033 //! \details 2034 //! Where X is the RefPicListNum and i is the list entry number 0 through 2035 //! 15. DW2 corresponds to i=0, 2036 //! DW17 corresponds to i=15. 2037 enum BOTTOM_FIELD_FLAG 2038 { 2039 BOTTOM_FIELD_FLAG_BOTTOMFIELD = 0, //!< No additional details 2040 BOTTOM_FIELD_FLAG_TOPFIELD = 1, //!< No additional details 2041 }; 2042 2043 //! \name Initializations 2044 2045 //! \brief Explicit member initialization function 2046 HCP_REF_LIST_ENTRY_CMD(); 2047 2048 static const size_t dwSize = 1; 2049 static const size_t byteSize = 4; 2050 }; 2051 2052 //! 2053 //! \brief HCP_REF_IDX_STATE 2054 //! \details 2055 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 2056 //! Commands. Each HCP command has assigned a media instruction command as 2057 //! defined in DWord 0, BitField 22:16. 2058 //! 2059 //! This is a slice level command used in both encoding and decoding 2060 //! processes. For decoder, it is issued with the HCP_BSD_OBJECT command. 2061 //! 2062 //! Unlike AVC, HEVC allows 16 reference idx entries in each of the L0 and 2063 //! L1 list for a progressive picture. Hence, a max total 32 reference idx 2064 //! in both lists together. The same when the picture is a field picture. 2065 //! Regardless the number of reference idx entries, there are only max 8 2066 //! reference pictures exist at any one time. Multiple reference idx can 2067 //! point to the same reference picture and can optionally pic a top or 2068 //! bottom field, or frame. 2069 //! 2070 //! For P-Slice, this command is issued only once, representing L0 list. For 2071 //! B-Slice, this command can be issued up to two times, one for L0 list and 2072 //! one for L1 list. 2073 //! 2074 struct HCP_REF_IDX_STATE_CMD 2075 { 2076 union 2077 { 2078 struct 2079 { 2080 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2081 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2082 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 2083 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 2084 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 2085 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2086 }; 2087 uint32_t Value; 2088 } DW0; 2089 union 2090 { 2091 struct 2092 { 2093 uint32_t Refpiclistnum : __CODEGEN_BITFIELD( 0, 0) ; //!< REFPICLISTNUM 2094 uint32_t NumRefIdxLRefpiclistnumActiveMinus1 : __CODEGEN_BITFIELD( 1, 4) ; //!< num_ref_idx_l[RefPicListNum]_active_minus1 2095 uint32_t Reserved37 : __CODEGEN_BITFIELD( 5, 31) ; //!< Reserved 2096 }; 2097 uint32_t Value; 2098 } DW1; 2099 HCP_REF_LIST_ENTRY_CMD Entries[16]; //!< DW2..17, Entries 2100 2101 //! \name Local enumerations 2102 2103 enum MEDIA_INSTRUCTION_COMMAND 2104 { 2105 MEDIA_INSTRUCTION_COMMAND_HCPREFIDXSTATE = 18, //!< No additional details 2106 }; 2107 2108 //! \brief MEDIA_INSTRUCTION_OPCODE 2109 //! \details 2110 //! Codec/Engine Name = HCP = 7h 2111 enum MEDIA_INSTRUCTION_OPCODE 2112 { 2113 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 2114 }; 2115 2116 enum PIPELINE_TYPE 2117 { 2118 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 2119 }; 2120 2121 enum COMMAND_TYPE 2122 { 2123 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2124 }; 2125 2126 enum REFPICLISTNUM 2127 { 2128 REFPICLISTNUM_REFERENCEPICTURELIST0 = 0, //!< No additional details 2129 REFPICLISTNUM_REFERENCEPICTURELIST1 = 1, //!< No additional details 2130 }; 2131 2132 //! \name Initializations 2133 2134 //! \brief Explicit member initialization function 2135 HCP_REF_IDX_STATE_CMD(); 2136 2137 static const size_t dwSize = 18; 2138 static const size_t byteSize = 72; 2139 }; 2140 2141 //! 2142 //! \brief HCP_WEIGHTOFFSET_LUMA_ENTRY 2143 //! \details 2144 //! 2145 //! 2146 struct HCP_WEIGHTOFFSET_LUMA_ENTRY_CMD 2147 { 2148 union 2149 { 2150 struct 2151 { 2152 uint32_t DeltaLumaWeightLxI : __CODEGEN_BITFIELD( 0, 7) ; //!< delta_luma_weight_lX[i] 2153 uint32_t LumaOffsetLxI : __CODEGEN_BITFIELD( 8, 15) ; //!< luma_offset_lX[i] 2154 uint32_t Reserved16 : __CODEGEN_BITFIELD(16, 23) ; //!< Reserved 2155 uint32_t LumaOffsetLxIMsbyte : __CODEGEN_BITFIELD(24, 31) ; //!< luma_offset_lX[i] MSByte 2156 }; 2157 uint32_t Value; 2158 } DW0; 2159 2160 //! \name Local enumerations 2161 2162 //! \name Initializations 2163 2164 //! \brief Explicit member initialization function 2165 HCP_WEIGHTOFFSET_LUMA_ENTRY_CMD(); 2166 2167 static const size_t dwSize = 1; 2168 static const size_t byteSize = 4; 2169 }; 2170 2171 //! 2172 //! \brief HCP_WEIGHTOFFSET_CHROMA_ENTRY 2173 //! \details 2174 //! 2175 //! 2176 struct HCP_WEIGHTOFFSET_CHROMA_ENTRY_CMD 2177 { 2178 union 2179 { 2180 struct 2181 { 2182 uint32_t DeltaChromaWeightLxI0 : __CODEGEN_BITFIELD( 0, 7) ; //!< delta_chroma_weight_lX[i][0] 2183 uint32_t ChromaoffsetlxI0 : __CODEGEN_BITFIELD( 8, 15) ; //!< ChromaOffsetLX[i][0] 2184 uint32_t DeltaChromaWeightLxI1 : __CODEGEN_BITFIELD(16, 23) ; //!< delta_chroma_weight_lX[i][1] 2185 uint32_t ChromaoffsetlxI1 : __CODEGEN_BITFIELD(24, 31) ; //!< ChromaOffsetLX [i][1] 2186 }; 2187 uint32_t Value; 2188 } DW0; 2189 2190 //! \name Local enumerations 2191 2192 //! \name Initializations 2193 2194 //! \brief Explicit member initialization function 2195 HCP_WEIGHTOFFSET_CHROMA_ENTRY_CMD(); 2196 2197 static const size_t dwSize = 1; 2198 static const size_t byteSize = 4; 2199 }; 2200 2201 //! 2202 //! \brief HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY 2203 //! \details 2204 //! 2205 //! 2206 struct HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_CMD 2207 { 2208 union 2209 { 2210 struct 2211 { 2212 uint32_t ChromaoffsetlxI0Msbyte : __CODEGEN_BITFIELD( 0, 7) ; //!< ChromaOffsetLX[i][0] MSByte 2213 uint32_t ChromaoffsetlxI10Msbyte : __CODEGEN_BITFIELD( 8, 15) ; //!< ChromaOffsetLX[i+1][0] MSByte 2214 uint32_t ChromaoffsetlxI1Msbyte : __CODEGEN_BITFIELD(16, 23) ; //!< ChromaOffsetLX[i][1] MSByte 2215 uint32_t ChromaoffsetlxI11Msbyte : __CODEGEN_BITFIELD(24, 31) ; //!< ChromaOffsetLX[i+1][1] MSByte 2216 }; 2217 uint32_t Value; 2218 } DW0; 2219 2220 //! \name Local enumerations 2221 2222 //! \name Initializations 2223 2224 //! \brief Explicit member initialization function 2225 HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_CMD(); 2226 2227 static const size_t dwSize = 1; 2228 static const size_t byteSize = 4; 2229 }; 2230 2231 //! 2232 //! \brief HCP_WEIGHTOFFSET_STATE 2233 //! \details 2234 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 2235 //! Commands. Each HCP command has assigned a media instruction command as 2236 //! defined in DWord 0, BitField 22:16. 2237 //! 2238 //! This slice level command is issued in both the encoding and decoding 2239 //! processes, if the weighted_pred_flag or weighted_bipred_flag equals one. 2240 //! If zero, then this command is not issued. Weight Prediction Values are 2241 //! provided in this command. Only Explicit Weight Prediction is supported 2242 //! in encoder. For P-Slice, this command is issued only once together with 2243 //! HCP_REF_IDX_STATE Command for L0 list. For B-Slice, this command can be 2244 //! issued up to two times together with HCP_REF_IDX_STATE Command, one for 2245 //! L0 list and one for L1 list. 2246 //! 2247 struct HCP_WEIGHTOFFSET_STATE_CMD 2248 { 2249 union 2250 { 2251 struct 2252 { 2253 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2254 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2255 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 2256 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 2257 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 2258 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2259 }; 2260 uint32_t Value; 2261 } DW0; 2262 union 2263 { 2264 struct 2265 { 2266 uint32_t Refpiclistnum : __CODEGEN_BITFIELD( 0, 0) ; //!< REFPICLISTNUM 2267 uint32_t Reserved33 : __CODEGEN_BITFIELD( 1, 31) ; //!< Reserved 2268 }; 2269 uint32_t Value; 2270 } DW1; 2271 HCP_WEIGHTOFFSET_LUMA_ENTRY_CMD Lumaoffsets[16]; //!< DW2..17, LumaOffsets 2272 HCP_WEIGHTOFFSET_CHROMA_ENTRY_CMD Chromaoffsets[16]; //!< DW18..33, ChromaOffsets 2273 HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_CMD Chromaoffsetsext[8]; //!< DW34..41, ChromaOffsetsExt 2274 2275 //! \name Local enumerations 2276 2277 enum MEDIA_INSTRUCTION_COMMAND 2278 { 2279 MEDIA_INSTRUCTION_COMMAND_HCPWEIGHTOFFSETSTATE = 19, //!< No additional details 2280 }; 2281 2282 //! \brief MEDIA_INSTRUCTION_OPCODE 2283 //! \details 2284 //! Codec/Engine Name = HCP = 7h 2285 enum MEDIA_INSTRUCTION_OPCODE 2286 { 2287 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 2288 }; 2289 2290 enum PIPELINE_TYPE 2291 { 2292 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 2293 }; 2294 2295 enum COMMAND_TYPE 2296 { 2297 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2298 }; 2299 2300 enum REFPICLISTNUM 2301 { 2302 REFPICLISTNUM_REFERENCEPICTURELIST0 = 0, //!< No additional details 2303 REFPICLISTNUM_REFERENCEPICTURELIST1 = 1, //!< No additional details 2304 }; 2305 2306 //! \name Initializations 2307 2308 //! \brief Explicit member initialization function 2309 HCP_WEIGHTOFFSET_STATE_CMD(); 2310 2311 static const size_t dwSize = 42; 2312 static const size_t byteSize = 168; 2313 }; 2314 2315 //! 2316 //! \brief HCP_SLICE_STATE 2317 //! \details 2318 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 2319 //! Commands. Each HCP command has assigned a media instruction command as 2320 //! defined in DWord 0, BitField 22:16. 2321 //! 2322 //! This is a slice level command used in both encoding and decoding 2323 //! processes. For decoder, it is issued with the HCP_BSD_OBJECT command. 2324 //! 2325 struct HCP_SLICE_STATE_CMD 2326 { 2327 union 2328 { 2329 struct 2330 { 2331 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2332 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2333 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 2334 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 2335 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 2336 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2337 }; 2338 uint32_t Value; 2339 } DW0; 2340 union 2341 { 2342 struct 2343 { 2344 uint32_t SlicestartctbxOrSliceStartLcuXEncoder : __CODEGEN_BITFIELD( 0, 9) ; //!< SliceStartCtbX or (slice_start_lcu_x encoder) 2345 uint32_t Reserved42 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 2346 uint32_t SlicestartctbyOrSliceStartLcuYEncoder : __CODEGEN_BITFIELD(16, 25) ; //!< SliceStartCtbY or (slice_start_lcu_y encoder) 2347 uint32_t Reserved58 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 2348 }; 2349 uint32_t Value; 2350 } DW1; 2351 union 2352 { 2353 struct 2354 { 2355 uint32_t NextslicestartctbxOrNextSliceStartLcuXEncoder : __CODEGEN_BITFIELD( 0, 9) ; //!< NextSliceStartCtbX or (next_slice_start_lcu_x encoder) 2356 uint32_t Reserved74 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 2357 uint32_t NextslicestartctbyOrNextSliceStartLcuYEncoder : __CODEGEN_BITFIELD(16, 26) ; //!< NextSliceStartCtbY or (next_slice_start_lcu_y encoder) 2358 uint32_t Reserved91 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 2359 }; 2360 uint32_t Value; 2361 } DW2; 2362 union 2363 { 2364 struct 2365 { 2366 uint32_t SliceType : __CODEGEN_BITFIELD( 0, 1) ; //!< SLICE_TYPE 2367 uint32_t Lastsliceofpic : __CODEGEN_BITFIELD( 2, 2) ; //!< LASTSLICEOFPIC 2368 uint32_t SliceqpSignFlag : __CODEGEN_BITFIELD( 3, 3) ; //!< SliceQp Sign Flag 2369 uint32_t DependentSliceFlag : __CODEGEN_BITFIELD( 4, 4) ; //!< dependent_slice_flag 2370 uint32_t SliceTemporalMvpEnableFlag : __CODEGEN_BITFIELD( 5, 5) ; //!< slice_temporal_mvp_enable_flag 2371 uint32_t Sliceqp : __CODEGEN_BITFIELD( 6, 11) ; //!< SliceQp 2372 uint32_t SliceCbQpOffset : __CODEGEN_BITFIELD(12, 16) ; //!< SLICE_CB_QP_OFFSET 2373 uint32_t SliceCrQpOffset : __CODEGEN_BITFIELD(17, 21) ; //!< SLICE_CR_QP_OFFSET 2374 uint32_t Intrareffetchdisable : __CODEGEN_BITFIELD(22, 22) ; //!< IntraRefFetchDisable 2375 uint32_t CuChromaQpOffsetEnabledFlag : __CODEGEN_BITFIELD(23, 23) ; //!< cu_chroma_qp_offset_enabled_flag 2376 uint32_t Lastsliceoftile : __CODEGEN_BITFIELD(24, 24) ; //!< LastSliceOfTile 2377 uint32_t Lastsliceoftilecolumn : __CODEGEN_BITFIELD(25, 25) ; //!< LastSliceOfTileColumn 2378 uint32_t Reserved122 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 2379 }; 2380 uint32_t Value; 2381 } DW3; 2382 union 2383 { 2384 struct 2385 { 2386 uint32_t SliceHeaderDisableDeblockingFilterFlag : __CODEGEN_BITFIELD( 0, 0) ; //!< slice_header_disable_deblocking_filter_flag 2387 uint32_t SliceTcOffsetDiv2OrFinalTcOffsetDiv2Encoder : __CODEGEN_BITFIELD( 1, 4) ; //!< slice_tc_offset_div2 or (final tc_offset_div2 Encoder) 2388 uint32_t SliceBetaOffsetDiv2OrFinalBetaOffsetDiv2Encoder : __CODEGEN_BITFIELD( 5, 8) ; //!< slice_beta_offset_div2 or (final Beta_Offset_div2 Encoder) 2389 uint32_t Reserved137 : __CODEGEN_BITFIELD( 9, 9) ; //!< Reserved 2390 uint32_t SliceLoopFilterAcrossSlicesEnabledFlag : __CODEGEN_BITFIELD(10, 10) ; //!< slice_loop_filter_across_slices_enabled_flag 2391 uint32_t SliceSaoChromaFlag : __CODEGEN_BITFIELD(11, 11) ; //!< slice_sao_chroma_flag 2392 uint32_t SliceSaoLumaFlag : __CODEGEN_BITFIELD(12, 12) ; //!< slice_sao_luma_flag 2393 uint32_t MvdL1ZeroFlag : __CODEGEN_BITFIELD(13, 13) ; //!< mvd_l1_zero_flag 2394 uint32_t Islowdelay : __CODEGEN_BITFIELD(14, 14) ; //!< isLowDelay 2395 uint32_t CollocatedFromL0Flag : __CODEGEN_BITFIELD(15, 15) ; //!< collocated_from_l0_flag 2396 uint32_t Chromalog2Weightdenom : __CODEGEN_BITFIELD(16, 18) ; //!< ChromaLog2WeightDenom 2397 uint32_t LumaLog2WeightDenom : __CODEGEN_BITFIELD(19, 21) ; //!< luma_log2_weight_denom 2398 uint32_t CabacInitFlag : __CODEGEN_BITFIELD(22, 22) ; //!< cabac_init_flag 2399 uint32_t Maxmergeidx : __CODEGEN_BITFIELD(23, 25) ; //!< MAXMERGEIDX 2400 uint32_t Collocatedrefidx : __CODEGEN_BITFIELD(26, 28) ; //!< CollocatedRefIDX 2401 uint32_t Reserved157 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 2402 }; 2403 uint32_t Value; 2404 } DW4; 2405 union 2406 { 2407 struct 2408 { 2409 uint32_t Sliceheaderlength : __CODEGEN_BITFIELD( 0, 15) ; //!< SliceHeaderLength 2410 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 2411 }; 2412 uint32_t Value; 2413 } DW5; 2414 union 2415 { 2416 struct 2417 { 2418 uint32_t Reserved192 : __CODEGEN_BITFIELD( 0, 19) ; //!< Reserved 2419 uint32_t Roundintra : __CODEGEN_BITFIELD(20, 23) ; //!< ROUNDINTRA 2420 uint32_t Reserved216 : __CODEGEN_BITFIELD(24, 25) ; //!< Reserved 2421 uint32_t Roundinter : __CODEGEN_BITFIELD(26, 29) ; //!< ROUNDINTER 2422 uint32_t Reserved222 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 2423 }; 2424 uint32_t Value; 2425 } DW6; 2426 union 2427 { 2428 struct 2429 { 2430 uint32_t DependentSliceDueToTileSplit : __CODEGEN_BITFIELD( 0, 0) ; //!< Dependent Slice due to Tile Split 2431 uint32_t Cabaczerowordinsertionenable : __CODEGEN_BITFIELD( 1, 1) ; //!< CABACZEROWORDINSERTIONENABLE 2432 uint32_t Emulationbytesliceinsertenable : __CODEGEN_BITFIELD( 2, 2) ; //!< EMULATIONBYTESLICEINSERTENABLE 2433 uint32_t Reserved227 : __CODEGEN_BITFIELD( 3, 7) ; //!< Reserved 2434 uint32_t TailInsertionEnable : __CODEGEN_BITFIELD( 8, 8) ; //!< TAIL_INSERTION_ENABLE 2435 uint32_t SlicedataEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< SLICEDATA_ENABLE 2436 uint32_t HeaderInsertionEnable : __CODEGEN_BITFIELD(10, 10) ; //!< HEADER_INSERTION_ENABLE 2437 uint32_t Reserved235 : __CODEGEN_BITFIELD(11, 31) ; //!< Reserved 2438 }; 2439 uint32_t Value; 2440 } DW7; 2441 union 2442 { 2443 struct 2444 { 2445 uint32_t Reserved256 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 2446 uint32_t IndirectPakBseDataStartOffsetWrite : __CODEGEN_BITFIELD( 6, 28) ; //!< Indirect PAK-BSE Data Start Offset (Write) 2447 uint32_t Reserved285 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 2448 }; 2449 uint32_t Value; 2450 } DW8; 2451 union 2452 { 2453 struct 2454 { 2455 uint32_t TransformskipLambda : __CODEGEN_BITFIELD( 0, 15) ; //!< Transformskip_lambda 2456 uint32_t Reserved304 : __CODEGEN_BITFIELD(16, 30) ; //!< Reserved 2457 uint32_t ForceSaoParametersToZero : __CODEGEN_BITFIELD(31, 31) ; //!< Force SAO parameters to zero 2458 }; 2459 uint32_t Value; 2460 } DW9; 2461 union 2462 { 2463 struct 2464 { 2465 uint32_t TransformskipNumzerocoeffsFactor0 : __CODEGEN_BITFIELD( 0, 7) ; //!< Transformskip_numzerocoeffs_factor0 2466 uint32_t TransformskipNumnonzerocoeffsFactor0 : __CODEGEN_BITFIELD( 8, 15) ; //!< Transformskip_numnonzerocoeffs_factor0 2467 uint32_t TransformskipNumzerocoeffsFactor1 : __CODEGEN_BITFIELD(16, 23) ; //!< Transformskip_numzerocoeffs_factor1 2468 uint32_t TransformskipNumnonzerocoeffsFactor1 : __CODEGEN_BITFIELD(24, 31) ; //!< Transformskip_numnonzerocoeffs_factor1 2469 }; 2470 uint32_t Value; 2471 } DW10; 2472 union 2473 { 2474 struct 2475 { 2476 uint32_t Originalslicestartctbx : __CODEGEN_BITFIELD( 0, 9) ; //!< OriginalSliceStartCtbX 2477 uint32_t Reserved362 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 2478 uint32_t Originalslicestartctby : __CODEGEN_BITFIELD(16, 25) ; //!< OriginalSliceStartCtbY 2479 uint32_t Reserved378 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 2480 }; 2481 uint32_t Value; 2482 } DW11; 2483 union 2484 { 2485 struct 2486 { 2487 uint32_t SliceActCrQpOffset : __CODEGEN_BITFIELD( 0, 5) ; //!< slice_act_cr_qp_offset 2488 uint32_t SliceActCbQpOffset : __CODEGEN_BITFIELD( 6, 11) ; //!< slice_act_cb_qp_offset 2489 uint32_t SliceActYQpOffset : __CODEGEN_BITFIELD(12, 17) ; //!< slice_act_y_qp_offset 2490 uint32_t Reserved402 : __CODEGEN_BITFIELD(18, 30) ; //!< Reserved 2491 uint32_t UseIntegerMvFlag : __CODEGEN_BITFIELD(31, 31) ; //!< use_integer_mv_flag 2492 }; 2493 uint32_t Value; 2494 } DW12; 2495 2496 //! \name Local enumerations 2497 2498 enum MEDIA_INSTRUCTION_COMMAND 2499 { 2500 MEDIA_INSTRUCTION_COMMAND_HCPSLICESTATE = 20, //!< No additional details 2501 }; 2502 2503 //! \brief MEDIA_INSTRUCTION_OPCODE 2504 //! \details 2505 //! Codec/Engine Name = HCP = 7h 2506 enum MEDIA_INSTRUCTION_OPCODE 2507 { 2508 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 2509 }; 2510 2511 enum PIPELINE_TYPE 2512 { 2513 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 2514 }; 2515 2516 enum COMMAND_TYPE 2517 { 2518 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2519 }; 2520 2521 //! \brief SLICE_TYPE 2522 //! \details 2523 //! In VDENC mode, for HEVC standard this field can be 0 or 2 only. 2524 enum SLICE_TYPE 2525 { 2526 SLICE_TYPE_B_SLICE = 0, //!< No additional details 2527 SLICE_TYPE_P_SLICE = 1, //!< No additional details 2528 SLICE_TYPE_I_SLICE = 2, //!< No additional details 2529 SLICE_TYPE_ILLEGALRESERVED = 3, //!< No additional details 2530 }; 2531 2532 //! \brief LASTSLICEOFPIC 2533 //! \details 2534 //! This indicates the current slice is the very last slice of the current 2535 //! picture 2536 enum LASTSLICEOFPIC 2537 { 2538 LASTSLICEOFPIC_NOTTHELASTSLICEOFTHEPICTURE = 0, //!< No additional details 2539 LASTSLICEOFPIC_LASTSLICEOFTHEPICTURE = 1, //!< No additional details 2540 }; 2541 2542 //! \brief SLICE_CB_QP_OFFSET 2543 //! \details 2544 //! For deblocking purpose, the pic and slice level cb qp offset must be 2545 //! provided separately. 2546 enum SLICE_CB_QP_OFFSET 2547 { 2548 SLICE_CB_QP_OFFSET_0 = 0, //!< No additional details 2549 SLICE_CB_QP_OFFSET_1 = 1, //!< No additional details 2550 SLICE_CB_QP_OFFSET_2 = 2, //!< No additional details 2551 SLICE_CB_QP_OFFSET_3 = 3, //!< No additional details 2552 SLICE_CB_QP_OFFSET_4 = 4, //!< No additional details 2553 SLICE_CB_QP_OFFSET_5 = 5, //!< No additional details 2554 SLICE_CB_QP_OFFSET_6 = 6, //!< No additional details 2555 SLICE_CB_QP_OFFSET_7 = 7, //!< No additional details 2556 SLICE_CB_QP_OFFSET_8 = 8, //!< No additional details 2557 SLICE_CB_QP_OFFSET_9 = 9, //!< No additional details 2558 SLICE_CB_QP_OFFSET_10 = 10, //!< No additional details 2559 SLICE_CB_QP_OFFSET_11 = 11, //!< No additional details 2560 SLICE_CB_QP_OFFSET_12 = 12, //!< No additional details 2561 SLICE_CB_QP_OFFSET_NEG_12 = 20, //!< No additional details 2562 SLICE_CB_QP_OFFSET_NEG_11 = 21, //!< No additional details 2563 SLICE_CB_QP_OFFSET_NEG_10 = 22, //!< No additional details 2564 SLICE_CB_QP_OFFSET_NEG_9 = 23, //!< No additional details 2565 SLICE_CB_QP_OFFSET_NEG_8 = 24, //!< No additional details 2566 SLICE_CB_QP_OFFSET_NEG_7 = 25, //!< No additional details 2567 SLICE_CB_QP_OFFSET_NEG_6 = 26, //!< No additional details 2568 SLICE_CB_QP_OFFSET_NEG_5 = 27, //!< No additional details 2569 SLICE_CB_QP_OFFSET_NEG_4 = 28, //!< No additional details 2570 SLICE_CB_QP_OFFSET_NEG_3 = 29, //!< No additional details 2571 SLICE_CB_QP_OFFSET_NEG_2 = 30, //!< No additional details 2572 SLICE_CB_QP_OFFSET_NEG_1 = 31, //!< No additional details 2573 }; 2574 2575 //! \brief SLICE_CR_QP_OFFSET 2576 //! \details 2577 //! For deblocking purpose, the pic and slice level cr qp offset must be 2578 //! provided separately. 2579 enum SLICE_CR_QP_OFFSET 2580 { 2581 SLICE_CR_QP_OFFSET_0 = 0, //!< No additional details 2582 SLICE_CR_QP_OFFSET_1 = 1, //!< No additional details 2583 SLICE_CR_QP_OFFSET_2 = 2, //!< No additional details 2584 SLICE_CR_QP_OFFSET_3 = 3, //!< No additional details 2585 SLICE_CR_QP_OFFSET_4 = 4, //!< No additional details 2586 SLICE_CR_QP_OFFSET_5 = 5, //!< No additional details 2587 SLICE_CR_QP_OFFSET_6 = 6, //!< No additional details 2588 SLICE_CR_QP_OFFSET_7 = 7, //!< No additional details 2589 SLICE_CR_QP_OFFSET_8 = 8, //!< No additional details 2590 SLICE_CR_QP_OFFSET_9 = 9, //!< No additional details 2591 SLICE_CR_QP_OFFSET_10 = 10, //!< No additional details 2592 SLICE_CR_QP_OFFSET_11 = 11, //!< No additional details 2593 SLICE_CR_QP_OFFSET_12 = 12, //!< No additional details 2594 SLICE_CR_QP_OFFSET_NEG_12 = 20, //!< No additional details 2595 SLICE_CR_QP_OFFSET_NEG_11 = 21, //!< No additional details 2596 SLICE_CR_QP_OFFSET_NEG_10 = 22, //!< No additional details 2597 SLICE_CR_QP_OFFSET_NEG_9 = 23, //!< No additional details 2598 SLICE_CR_QP_OFFSET_NEG_8 = 24, //!< No additional details 2599 SLICE_CR_QP_OFFSET_NEG_7 = 25, //!< No additional details 2600 SLICE_CR_QP_OFFSET_NEG_6 = 26, //!< No additional details 2601 SLICE_CR_QP_OFFSET_NEG_5 = 27, //!< No additional details 2602 SLICE_CR_QP_OFFSET_NEG_4 = 28, //!< No additional details 2603 SLICE_CR_QP_OFFSET_NEG_3 = 29, //!< No additional details 2604 SLICE_CR_QP_OFFSET_NEG_2 = 30, //!< No additional details 2605 SLICE_CR_QP_OFFSET_NEG_1 = 31, //!< No additional details 2606 }; 2607 2608 //! \brief MAXMERGEIDX 2609 //! \details 2610 //! MaxNumMergeCand = 5 - five_minus_max_num_merge_cand -1. 2611 enum MAXMERGEIDX 2612 { 2613 MAXMERGEIDX_0 = 0, //!< No additional details 2614 MAXMERGEIDX_1 = 1, //!< No additional details 2615 MAXMERGEIDX_2 = 2, //!< No additional details 2616 MAXMERGEIDX_3 = 3, //!< No additional details 2617 MAXMERGEIDX_4 = 4, //!< No additional details 2618 }; 2619 2620 //! \brief ROUNDINTRA 2621 //! \details 2622 //! In VDENC mode, this field is ignored. 2623 enum ROUNDINTRA 2624 { 2625 ROUNDINTRA_132 = 0, //!< No additional details 2626 ROUNDINTRA_232 = 1, //!< No additional details 2627 ROUNDINTRA_332 = 2, //!< No additional details 2628 ROUNDINTRA_432 = 3, //!< No additional details 2629 ROUNDINTRA_532 = 4, //!< No additional details 2630 ROUNDINTRA_632 = 5, //!< No additional details 2631 ROUNDINTRA_732 = 6, //!< No additional details 2632 ROUNDINTRA_832 = 7, //!< No additional details 2633 ROUNDINTRA_932 = 8, //!< No additional details 2634 ROUNDINTRA_1032 = 9, //!< No additional details 2635 ROUNDINTRA_1132 = 10, //!< No additional details 2636 ROUNDINTRA_1232 = 11, //!< No additional details 2637 ROUNDINTRA_1332 = 12, //!< No additional details 2638 ROUNDINTRA_1432 = 13, //!< No additional details 2639 ROUNDINTRA_1532 = 14, //!< No additional details 2640 ROUNDINTRA_1632 = 15, //!< No additional details 2641 }; 2642 2643 //! \brief ROUNDINTER 2644 //! \details 2645 //! In VDENC mode, this field is ignored. 2646 enum ROUNDINTER 2647 { 2648 ROUNDINTER_132 = 0, //!< No additional details 2649 ROUNDINTER_232 = 1, //!< No additional details 2650 ROUNDINTER_332 = 2, //!< No additional details 2651 ROUNDINTER_432 = 3, //!< No additional details 2652 ROUNDINTER_532 = 4, //!< No additional details 2653 ROUNDINTER_632 = 5, //!< No additional details 2654 ROUNDINTER_732 = 6, //!< No additional details 2655 ROUNDINTER_832 = 7, //!< No additional details 2656 ROUNDINTER_932 = 8, //!< No additional details 2657 ROUNDINTER_1032 = 9, //!< No additional details 2658 ROUNDINTER_1132 = 10, //!< No additional details 2659 ROUNDINTER_1232 = 11, //!< No additional details 2660 ROUNDINTER_1332 = 12, //!< No additional details 2661 ROUNDINTER_1432 = 13, //!< No additional details 2662 ROUNDINTER_1532 = 14, //!< No additional details 2663 ROUNDINTER_1632 = 15, //!< No additional details 2664 }; 2665 2666 //! \brief CABACZEROWORDINSERTIONENABLE 2667 //! \details 2668 //! To pad the end of a SliceLayer RBSP to meet the encoded size 2669 //! requirement. 2670 enum CABACZEROWORDINSERTIONENABLE 2671 { 2672 CABACZEROWORDINSERTIONENABLE_UNNAMED0 = 0, //!< No Cabac_Zero_Word Insertion. 2673 CABACZEROWORDINSERTIONENABLE_UNNAMED1 = 1, //!< Allow internal Cabac_Zero_Word generation and append to the end of RBSP (effectively can be usedas an indicator for last slice of a picture, if the assumption is only the last slice of a pictureneeds to insert CABAC_ZERO_WORDs). 2674 }; 2675 2676 //! \brief EMULATIONBYTESLICEINSERTENABLE 2677 //! \details 2678 //! To have PAK outputting SODB or EBSP to the output bitstream buffer. 2679 enum EMULATIONBYTESLICEINSERTENABLE 2680 { 2681 EMULATIONBYTESLICEINSERTENABLE_OUTPUTTINGRBSP = 0, //!< No additional details 2682 EMULATIONBYTESLICEINSERTENABLE_OUTPUTTINGEBSP = 1, //!< No additional details 2683 }; 2684 2685 //! \brief TAIL_INSERTION_ENABLE 2686 //! \details 2687 //! Must be followed by the PAK Insertion Object Command to perform the 2688 //! actual insertion. 2689 enum TAIL_INSERTION_ENABLE 2690 { 2691 TAIL_INSERTION_ENABLE_UNNAMED0 = 0, //!< No tail insertion into the output bitstream buffer, after the current slice encoded bits. 2692 TAIL_INSERTION_ENABLE_UNNAMED1 = 1, //!< Tail insertion into the output bitstream buffer is present, and is after the current slice encoded bits.SKL restriction: Tail insertion is only possible at the end of frame but not in the middle (say slice end) 2693 }; 2694 2695 //! \brief SLICEDATA_ENABLE 2696 //! \details 2697 //! <p>Must always be enabled.</p> 2698 //! <p>Encoder only feature.</p> 2699 enum SLICEDATA_ENABLE 2700 { 2701 SLICEDATA_ENABLE_UNNAMED0 = 0, //!< No operation; no insertion. 2702 SLICEDATA_ENABLE_UNNAMED1 = 1, //!< Slice Data insertion by PAK Object Commands into the output bitstream buffer. 2703 }; 2704 2705 //! \brief HEADER_INSERTION_ENABLE 2706 //! \details 2707 //! Must be followed by the PAK Insertion Object Command to perform the 2708 //! actual insertion. 2709 enum HEADER_INSERTION_ENABLE 2710 { 2711 HEADER_INSERTION_ENABLE_UNNAMED0 = 0, //!< No header insertion into the output bitstream buffer, before the current slice encoded bits. 2712 HEADER_INSERTION_ENABLE_UNNAMED1 = 1, //!< Header insertion into the output bitstream buffer is present, and is before the current slice encoded bits. 2713 }; 2714 2715 //! \name Initializations 2716 2717 //! \brief Explicit member initialization function 2718 HCP_SLICE_STATE_CMD(); 2719 2720 static const size_t dwSize = 13; 2721 static const size_t byteSize = 52; 2722 }; 2723 2724 //! 2725 //! \brief HCP_BSD_OBJECT 2726 //! \details 2727 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 2728 //! Commands. Each HCP command has assigned a media instruction command as 2729 //! defined in DWord 0, BitField 22:16. 2730 //! 2731 //! The HCP_BSD_OBJECT command fetches the HEVC bit stream for a slice 2732 //! starting with the first byte in the slice. The bit stream ends with the 2733 //! last non-zero bit of the frame and does not include any zero-padding at 2734 //! the end of the bit stream. There can be multiple slices in a HEVC frame 2735 //! and thus this command can be issued multiple times per frame. 2736 //! 2737 //! The HCP_BSD_OBJECT command must be the last command issued in the 2738 //! sequence of batch commands before the HCP starts decoding. Prior to 2739 //! issuing this command, it is assumed that all configuration parameters in 2740 //! the HCP have been loaded including workload configuration registers and 2741 //! configuration tables. When this command is issued, the HCP is waiting 2742 //! for bit stream data to be presented to the shift register. 2743 //! 2744 struct HCP_BSD_OBJECT_CMD 2745 { 2746 union 2747 { 2748 struct 2749 { 2750 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2751 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2752 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 2753 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 2754 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 2755 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2756 }; 2757 uint32_t Value; 2758 } DW0; 2759 union 2760 { 2761 struct 2762 { 2763 uint32_t IndirectBsdDataLength ; //!< Indirect BSD Data Length 2764 }; 2765 uint32_t Value; 2766 } DW1; 2767 union 2768 { 2769 struct 2770 { 2771 uint32_t IndirectDataStartAddress : __CODEGEN_BITFIELD( 0, 28) ; //!< Indirect Data Start Address 2772 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 2773 }; 2774 uint32_t Value; 2775 } DW2; 2776 2777 //! \name Local enumerations 2778 2779 enum MEDIA_INSTRUCTION_COMMAND 2780 { 2781 MEDIA_INSTRUCTION_COMMAND_HCPBSDOBJECTSTATE = 32, //!< No additional details 2782 }; 2783 2784 //! \brief MEDIA_INSTRUCTION_OPCODE 2785 //! \details 2786 //! Codec/Engine Name = HCP = 7h 2787 enum MEDIA_INSTRUCTION_OPCODE 2788 { 2789 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 2790 }; 2791 2792 enum PIPELINE_TYPE 2793 { 2794 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 2795 }; 2796 2797 enum COMMAND_TYPE 2798 { 2799 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2800 }; 2801 2802 //! \name Initializations 2803 2804 //! \brief Explicit member initialization function 2805 HCP_BSD_OBJECT_CMD(); 2806 2807 static const size_t dwSize = 3; 2808 static const size_t byteSize = 12; 2809 }; 2810 2811 //! 2812 //! \brief HCP_VP9_SEGMENT_STATE 2813 //! \details 2814 //! 2815 //! 2816 struct HCP_VP9_SEGMENT_STATE_CMD 2817 { 2818 union 2819 { 2820 struct 2821 { 2822 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2823 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2824 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 2825 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 2826 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 2827 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2828 }; 2829 uint32_t Value; 2830 } DW0; 2831 union 2832 { 2833 struct 2834 { 2835 uint32_t SegmentId : __CODEGEN_BITFIELD( 0, 2) ; //!< Segment ID 2836 uint32_t Reserved35 : __CODEGEN_BITFIELD( 3, 31) ; //!< Reserved 2837 }; 2838 uint32_t Value; 2839 } DW1; 2840 union 2841 { 2842 struct 2843 { 2844 uint32_t SegmentSkipped : __CODEGEN_BITFIELD( 0, 0) ; //!< Segment Skipped 2845 uint32_t SegmentReference : __CODEGEN_BITFIELD( 1, 2) ; //!< Segment Reference 2846 uint32_t SegmentReferenceEnabled : __CODEGEN_BITFIELD( 3, 3) ; //!< Segment Reference Enabled 2847 uint32_t Reserved68 : __CODEGEN_BITFIELD( 4, 31) ; //!< Reserved 2848 }; 2849 uint32_t Value; 2850 } DW2; 2851 union 2852 { 2853 struct 2854 { 2855 uint32_t Filterlevelref0Mode0 : __CODEGEN_BITFIELD( 0, 5) ; //!< FilterLevelRef0Mode0 2856 uint32_t Reserved102 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 2857 uint32_t Filterlevelref0Mode1 : __CODEGEN_BITFIELD( 8, 13) ; //!< FilterLevelRef0Mode1 2858 uint32_t Reserved110 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 2859 uint32_t Filterlevelref1Mode0 : __CODEGEN_BITFIELD(16, 21) ; //!< FilterLevelRef1Mode0 2860 uint32_t Reserved118 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 2861 uint32_t Filterlevelref1Mode1 : __CODEGEN_BITFIELD(24, 29) ; //!< FilterLevelRef1Mode1 2862 uint32_t Reserved126 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 2863 }; 2864 uint32_t Value; 2865 } DW3; 2866 union 2867 { 2868 struct 2869 { 2870 uint32_t Filterlevelref2Mode0 : __CODEGEN_BITFIELD( 0, 5) ; //!< FilterLevelRef2Mode0 2871 uint32_t Reserved134 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 2872 uint32_t Filterlevelref2Mode1 : __CODEGEN_BITFIELD( 8, 13) ; //!< FilterLevelRef2Mode1 2873 uint32_t Reserved142 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 2874 uint32_t Filterlevelref3Mode0 : __CODEGEN_BITFIELD(16, 21) ; //!< FilterLevelRef3Mode0 2875 uint32_t Reserved150 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 2876 uint32_t Filterlevelref3Mode1 : __CODEGEN_BITFIELD(24, 29) ; //!< FilterLevelRef3Mode1 2877 uint32_t Reserved158 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 2878 }; 2879 uint32_t Value; 2880 } DW4; 2881 union 2882 { 2883 struct 2884 { 2885 uint32_t LumaDcQuantScaleDecodeModeOnly : __CODEGEN_BITFIELD( 0, 15) ; //!< Luma DC Quant Scale (Decode mode Only) 2886 uint32_t LumaAcQuantScaleDecodeModeOnly : __CODEGEN_BITFIELD(16, 31) ; //!< Luma AC Quant Scale (Decode mode Only) 2887 }; 2888 uint32_t Value; 2889 } DW5; 2890 union 2891 { 2892 struct 2893 { 2894 uint32_t ChromaDcQuantScaleDecodeModeOnly : __CODEGEN_BITFIELD( 0, 15) ; //!< Chroma DC Quant Scale (Decode mode Only) 2895 uint32_t ChromaAcQuantScaleDecodeModeOnly : __CODEGEN_BITFIELD(16, 31) ; //!< Chroma AC Quant Scale (Decode mode Only) 2896 }; 2897 uint32_t Value; 2898 } DW6; 2899 union 2900 { 2901 struct 2902 { 2903 uint32_t SegmentQindexDeltaEncodeModeOnly : __CODEGEN_BITFIELD( 0, 8) ; //!< Segment QIndex Delta (encode mode only) 2904 uint32_t Reserved233 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved 2905 uint32_t SegmentLfLevelDeltaEncodeModeOnly : __CODEGEN_BITFIELD(16, 22) ; //!< Segment LF Level Delta (Encode mode Only) 2906 uint32_t Reserved247 : __CODEGEN_BITFIELD(23, 31) ; //!< Reserved 2907 }; 2908 uint32_t Value; 2909 } DW7; 2910 2911 //! \name Local enumerations 2912 2913 enum MEDIA_INSTRUCTION_COMMAND 2914 { 2915 MEDIA_INSTRUCTION_COMMAND_HCPVP9SEGMENTSTATE = 50, //!< No additional details 2916 }; 2917 2918 //! \brief MEDIA_INSTRUCTION_OPCODE 2919 //! \details 2920 //! Codec/Engine Name = HUC = Bh 2921 enum MEDIA_INSTRUCTION_OPCODE 2922 { 2923 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 2924 }; 2925 2926 enum PIPELINE_TYPE 2927 { 2928 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 2929 }; 2930 2931 enum COMMAND_TYPE 2932 { 2933 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2934 }; 2935 2936 //! \name Initializations 2937 2938 //! \brief Explicit member initialization function 2939 HCP_VP9_SEGMENT_STATE_CMD(); 2940 2941 static const size_t dwSize = 8; 2942 static const size_t byteSize = 32; 2943 }; 2944 2945 //! 2946 //! \brief HCP_FQM_STATE 2947 //! \details 2948 //! The HCP_FQM_STATE command loads the custom HEVC quantization tables into 2949 //! local RAM and may be issued up to 8 times: 4 scaling list per intra and 2950 //! inter. 2951 //! 2952 //! Driver is responsible for performing the Scaling List division. So, save 2953 //! the division HW cost in HW. The 1/x value is provided in 16-bit 2954 //! fixed-point precision as ((1<<17)/QM +1) >> 1. . 2955 //! 2956 //! Note: FQM is computed as (2^16)/QM. If QM=1, FQM=all 1's. 2957 //! 2958 //! To simplify the design, only a limited number of scaling lists are 2959 //! provided at the PAK interface: default two SizeID0 and two SizeID123 2960 //! (one set for inter and the other set for intra), and the encoder only 2961 //! allows custom entries for these four matrices. The DC value of SizeID2 2962 //! and SizeID3 will be provided. 2963 //! 2964 //! When the scaling_list_enable_flag is set to disable, the scaling matrix 2965 //! is still sent to the PAK, and with all entries programmed to the same 2966 //! value of 16. 2967 //! 2968 //! This is a picture level state command and is issued in encoding 2969 //! processes only. 2970 //! 2971 //! Dwords 2-33 form a table for the DCT coefficients, 2 16-bit 2972 //! coefficients/DWord. Size 4x4 for SizeID0, DWords 2-9. 2973 //! Size 8x8 for SizeID1/2/3, DWords 2-33. 2974 //! 2975 //! 2976 //! SizeID 0 (Table 4-13) 2977 //! 2978 struct HCP_FQM_STATE_CMD 2979 { 2980 union 2981 { 2982 struct 2983 { 2984 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2985 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2986 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 2987 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 2988 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 2989 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2990 }; 2991 uint32_t Value; 2992 } DW0; 2993 union 2994 { 2995 struct 2996 { 2997 uint32_t IntraInter : __CODEGEN_BITFIELD( 0, 0) ; //!< INTRAINTER 2998 uint32_t Sizeid : __CODEGEN_BITFIELD( 1, 2) ; //!< SIZEID 2999 uint32_t ColorComponent : __CODEGEN_BITFIELD( 3, 4) ; //!< COLOR_COMPONENT 3000 uint32_t Reserved37 : __CODEGEN_BITFIELD( 5, 15) ; //!< Reserved 3001 uint32_t FqmDcValue1Dc : __CODEGEN_BITFIELD(16, 31) ; //!< FQM DC Value: (1/DC): 3002 }; 3003 uint32_t Value; 3004 } DW1; 3005 uint32_t Quantizermatrix[32]; //!< QuantizerMatrix 3006 3007 //! \name Local enumerations 3008 3009 enum MEDIA_INSTRUCTION_COMMAND 3010 { 3011 MEDIA_INSTRUCTION_COMMAND_HCPFQMSTATE = 5, //!< No additional details 3012 }; 3013 3014 //! \brief MEDIA_INSTRUCTION_OPCODE 3015 //! \details 3016 //! Codec/Engine Name = HCP = 7h 3017 enum MEDIA_INSTRUCTION_OPCODE 3018 { 3019 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 3020 }; 3021 3022 enum PIPELINE_TYPE 3023 { 3024 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 3025 }; 3026 3027 enum COMMAND_TYPE 3028 { 3029 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3030 }; 3031 3032 //! \brief INTRAINTER 3033 //! \details 3034 //! This field specifies the quant matrix intra or inter type. 3035 enum INTRAINTER 3036 { 3037 INTRAINTER_INTRA = 0, //!< No additional details 3038 INTRAINTER_INTER = 1, //!< No additional details 3039 }; 3040 3041 enum SIZEID 3042 { 3043 SIZEID_SIZEID04X4 = 0, //!< No additional details 3044 SIZEID_SIZEID1_2_3_8X8_16X16_32X32 = 1, //!< No additional details 3045 SIZEID_SIZEID2_FORDCVALUEIN16X16 = 2, //!< No additional details 3046 SIZEID_SIZEID3_FORDCVALUEIN32X32 = 3, //!< No additional details 3047 }; 3048 3049 //! \brief COLOR_COMPONENT 3050 //! \details 3051 //! <p>Luma and Chroma's share the same scaling list and DC value for the 3052 //! same SizeID.</p> 3053 enum COLOR_COMPONENT 3054 { 3055 COLOR_COMPONENT_LUMA = 0, //!< No additional details 3056 COLOR_COMPONENT_CHROMACB = 1, //!< No additional details 3057 COLOR_COMPONENT_CHROMACR = 2, //!< No additional details 3058 }; 3059 3060 //! \name Initializations 3061 3062 //! \brief Explicit member initialization function 3063 HCP_FQM_STATE_CMD(); 3064 3065 static const size_t dwSize = 34; 3066 static const size_t byteSize = 136; 3067 }; 3068 3069 //! 3070 //! \brief HCP_PAK_INSERT_OBJECT 3071 //! \details 3072 //! It is an encoder only command, operating at bitstream level, before and 3073 //! after SliceData compressed bitstream. It is setup by the header and tail 3074 //! present flags in the Slice State command. If these flags are set and no 3075 //! subsequent PAK_INSERT_OBJECT commands are issued, the pipeline will 3076 //! hang. 3077 //! 3078 //! The HCP_ PAK_ INSERT _OBJECT command supports both inline and indirect 3079 //! data payload, but only one can be active at any time. It is issued to 3080 //! insert a chunk of bits (payload) into the current compressed bitstream 3081 //! output buffer (specified in the HCP_PAK-BSE Object Base Address field of 3082 //! the HCP_IND_OBJ_BASE_ADDR_STATE command) starting at its current write 3083 //! pointer bit position. Hardware will keep track of this write pointer's 3084 //! byte position and the associated next bit insertion position index. 3085 //! 3086 //! It is a variable length command when the payload (data to be inserted) 3087 //! is presented as inline data within the command itself. The inline 3088 //! payload is a multiple of 32-bit (1 DW), as the data bus to the 3089 //! compressed bitstream output buffer is 32-bit wide. 3090 //! 3091 //! The payload data is required to be byte aligned on the left (first 3092 //! transmitted bit order) and may or may not be byte aligned on the right 3093 //! (last transmitted bits). The command will specify the bit offset of the 3094 //! last valid DW. Note that : Stitch Command is used if the beginning 3095 //! position of data is in bit position. When PAK Insert Command is used the 3096 //! beginning position must be in byte position. 3097 //! 3098 //! Multiple insertion commands can be issued back to back in a series. It 3099 //! is host software's responsibility to make sure their corresponding data 3100 //! will properly stitch together to form a valid bitstream. 3101 //! 3102 //! Internally, HCP hardware will keep track of the very last two bytes' 3103 //! (the very last byte can be a partial byte) values of the previous 3104 //! insertion. It is required that the next Insertion Object Command or the 3105 //! next PAK Object Command to perform the start code emulation sequence 3106 //! check and prevention 0x03 byte insertion with this end condition of the 3107 //! previous insertion. 3108 //! 3109 //! The payload data may have already been processed for start code 3110 //! emulation byte insertion, except the possibility of the last 2 bytes 3111 //! plus the very last partial byte (if any). Hence, when hardware 3112 //! performing the concatenation of multiple consecutive insertion commands, 3113 //! or concatenation of an insertion command and a PAK object command, it 3114 //! must check and perform the necessary start code emulation byte insert at 3115 //! the junction. 3116 //! 3117 //! Data to be inserted can be a valid NAL units or a partial NAL unit. It 3118 //! can be any encoded syntax elements bit data before the encoded Slice 3119 //! Data (PAK Object Command) of the current Slice - SPS NAL, PPS NAL, SEI 3120 //! NAL and Other Non-Slice NAL, Leading_Zero_8_bits (as many bytes as there 3121 //! is), Start Code , Slice Header. Any encoded syntax elements bit data 3122 //! after the encoded Slice Data (PAK Object Command) of the current Slice 3123 //! and prior to the next encoded Slice Data of the next Slice or prior to 3124 //! the end of the bitstream, whichever comes first Cabac_Zero_Word or 3125 //! Trailing_Zero_8bits (as many bytes as there is). 3126 //! 3127 //! Certain NAL unit has a minimum byte size requirement. As such the 3128 //! hardware will optionally (enabled by SLICE STATE Command) determines the 3129 //! number of CABAC_ZERO_WORD to be inserted to the end of the current NAL, 3130 //! based on the minimum byte size of a NAL and the actual bin count of the 3131 //! encoded Slice. Since prior to the CABAC_ZERO_WORD insertion, the RBSP or 3132 //! EBSP is already byte-aligned, so each CABAC_ZERO_WORD insertion is 3133 //! actually a 3-byte sequence 0x00 00 03. 3134 //! 3135 //! Context switch interrupt is not supported by this command. 3136 //! 3137 struct HCP_PAK_INSERT_OBJECT_CMD 3138 { 3139 union 3140 { 3141 struct 3142 { 3143 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< Dword Length 3144 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3145 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 3146 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 3147 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 3148 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3149 }; 3150 uint32_t Value; 3151 } DW0; 3152 union 3153 { 3154 struct 3155 { 3156 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 3157 uint32_t EndofsliceflagLastdstdatainsertcommandflag : __CODEGEN_BITFIELD( 1, 1) ; //!< EndOfSliceFlag - LastDstDataInsertCommandFlag 3158 uint32_t LastheaderflagLastsrcheaderdatainsertcommandflag : __CODEGEN_BITFIELD( 2, 2) ; //!< LastHeaderFlag - LastSrcHeaderDataInsertCommandFlag 3159 uint32_t EmulationflagEmulationbytebitsinsertenable : __CODEGEN_BITFIELD( 3, 3) ; //!< EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE 3160 uint32_t SkipemulbytecntSkipEmulationByteCount : __CODEGEN_BITFIELD( 4, 7) ; //!< SkipEmulByteCnt - Skip Emulation Byte Count 3161 uint32_t DatabitsinlastdwSrcdataendingbitinclusion50 : __CODEGEN_BITFIELD( 8, 13) ; //!< DataBitsInLastDW - SrCDataEndingBitInclusion[5:0] 3162 uint32_t SliceHeaderIndicator : __CODEGEN_BITFIELD(14, 14) ; //!< Slice Header Indicator 3163 uint32_t Headerlengthexcludefrmsize : __CODEGEN_BITFIELD(15, 15) ; //!< HEADERLENGTHEXCLUDEFRMSIZE_ 3164 uint32_t DatabyteoffsetSrcdatastartingbyteoffset10 : __CODEGEN_BITFIELD(16, 17) ; //!< DataByteOffset - SrcDataStartingByteOffset[1:0] 3165 uint32_t Reserved50 : __CODEGEN_BITFIELD(18, 30) ; //!< Reserved 3166 uint32_t IndirectPayloadEnable : __CODEGEN_BITFIELD(31, 31) ; //!< INDIRECT_PAYLOAD_ENABLE 3167 }; 3168 uint32_t Value; 3169 } DW1; 3170 3171 //! \name Local enumerations 3172 3173 enum MEDIA_INSTRUCTION_COMMAND 3174 { 3175 MEDIA_INSTRUCTION_COMMAND_HCPPAKINSERTOBJECT = 34, //!< No additional details 3176 }; 3177 3178 //! \brief MEDIA_INSTRUCTION_OPCODE 3179 //! \details 3180 //! Codec/Engine Name = HCP = 7h 3181 enum MEDIA_INSTRUCTION_OPCODE 3182 { 3183 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 3184 }; 3185 3186 enum PIPELINE_TYPE 3187 { 3188 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 3189 }; 3190 3191 enum COMMAND_TYPE 3192 { 3193 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3194 }; 3195 3196 //! \brief EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE 3197 //! \details 3198 //! Only valid for HEVC and reserved for VP9. 3199 enum EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE 3200 { 3201 EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE_STARTCODEPREFIX = 1, //!< Instruct the hardware to perform Start Code Prefix (0x 00 00 01/02/03/00) Search and Prevention Byte (0x 03) insertion on the insertion data of this command. It is required that hardware will handle a start code prefix crossing the boundary between. 3202 EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE_INSERTIONCOMMAND = 2, //!< Insertion commands, or an insertion command followed by a PAK Object command. 3203 }; 3204 3205 //! \brief HEADERLENGTHEXCLUDEFRMSIZE_ 3206 //! \details 3207 //! <p>In case this flag is on, bits are NOT accumulated during current 3208 //! access unit coding neither for Cabac Zero Word insertion bits counting 3209 //! or for output in MMIO register 3210 //! HCP_BITSTREAM_BYTECOUNT_FRAME_NO_HEADER.</p> 3211 //! <p>When using HeaderLenghtExcludeFrmSize for header insertion, the 3212 //! software needs to make sure that data comes already with inserted start 3213 //! code emulation bytes. SW shouldn't set EmulationFlag bit ( Bit 3 of 3214 //! DWORD1 of HCP_PAK_INSERT_OBJECT).</p> 3215 //! <table border="1" cellpadding="0" cellspacing="0" style="width: 100%;" 3216 //! width="100%"> 3217 //! <tbody> 3218 //! <tr> 3219 //! <td> 3220 //! <p align="center"><b>Value</b></p></td> 3221 //! <td> 3222 //! <p align="center"><b style="text-align: 3223 //! -webkit-center;">Description</b></p></td> 3224 //! </tr> 3225 //! <tr> 3226 //! <td> 3227 //! <p>0</p></td> 3228 //! <td> 3229 //! <p>All bits accumulated</p></td> 3230 //! </tr> 3231 //! <tr> 3232 //! <td> 3233 //! <p>1</p></td> 3234 //! <td> 3235 //! <p>Bits during current call are not accumulated</p></td> 3236 //! </tr> 3237 //! </tbody> 3238 //! </table> 3239 //! 3240 //! <p></p> 3241 enum HEADERLENGTHEXCLUDEFRMSIZE_ 3242 { 3243 HEADERLENGTHEXCLUDEFRMSIZE_ALLBITSACCUMULATED = 0, //!< No additional details 3244 HEADERLENGTHEXCLUDEFRMSIZE_BITSDURINGCURRENTCALLARENOTACCUMULATED = 1, //!< No additional details 3245 }; 3246 3247 //! \brief INDIRECT_PAYLOAD_ENABLE 3248 //! \details 3249 //! <p>Only one of these two payload modes can be active at any time.</p> 3250 //! <p>When Slice Size Conformance is enable the Payload(header) must be 3251 //! inline only so this bit set to MBZ.</p> 3252 enum INDIRECT_PAYLOAD_ENABLE 3253 { 3254 INDIRECT_PAYLOAD_ENABLE_INLINEPAYLOADISUSED = 0, //!< No additional details 3255 INDIRECT_PAYLOAD_ENABLE_INDIRECTPAYLOADISUSED = 1, //!< No additional details 3256 }; 3257 3258 //! \name Initializations 3259 3260 //! \brief Explicit member initialization function 3261 HCP_PAK_INSERT_OBJECT_CMD(); 3262 3263 static const size_t dwSize = 2; 3264 static const size_t byteSize = 8; 3265 }; 3266 3267 //! 3268 //! \brief HCP_VP9_PIC_STATE 3269 //! \details 3270 //! 3271 //! 3272 struct HCP_VP9_PIC_STATE_CMD 3273 { 3274 union 3275 { 3276 struct 3277 { 3278 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3279 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3280 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 3281 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 3282 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 3283 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3284 }; 3285 uint32_t Value; 3286 } DW0; 3287 union 3288 { 3289 struct 3290 { 3291 uint32_t FrameWidthInPixelsMinus1 : __CODEGEN_BITFIELD( 0, 13) ; //!< Frame Width In Pixels Minus 1 3292 uint32_t Reserved46 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 3293 uint32_t FrameHeightInPixelsMinus1 : __CODEGEN_BITFIELD(16, 29) ; //!< Frame Height In Pixels Minus 1 3294 uint32_t Reserved62 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 3295 }; 3296 uint32_t Value; 3297 } DW1; 3298 union 3299 { 3300 struct 3301 { 3302 uint32_t FrameType : __CODEGEN_BITFIELD( 0, 0) ; //!< FRAME_TYPE 3303 uint32_t AdaptProbabilitiesFlag : __CODEGEN_BITFIELD( 1, 1) ; //!< ADAPT_PROBABILITIES_FLAG 3304 uint32_t IntraonlyFlag : __CODEGEN_BITFIELD( 2, 2) ; //!< IntraOnly Flag 3305 uint32_t AllowHiPrecisionMv : __CODEGEN_BITFIELD( 3, 3) ; //!< ALLOW_HI_PRECISION_MV 3306 uint32_t McompFilterType : __CODEGEN_BITFIELD( 4, 6) ; //!< MCOMP_FILTER_TYPE 3307 uint32_t RefFrameSignBias02 : __CODEGEN_BITFIELD( 7, 9) ; //!< Ref Frame Sign Bias[0..2] 3308 uint32_t UsePrevInFindMvReferences : __CODEGEN_BITFIELD(10, 10) ; //!< Use Prev in Find MV References 3309 uint32_t HybridPredictionMode : __CODEGEN_BITFIELD(11, 11) ; //!< HYBRID_PREDICTION_MODE 3310 uint32_t SelectableTxMode : __CODEGEN_BITFIELD(12, 12) ; //!< SELECTABLE_TX_MODE 3311 uint32_t LastFrameType : __CODEGEN_BITFIELD(13, 13) ; //!< LAST_FRAME_TYPE 3312 uint32_t RefreshFrameContext : __CODEGEN_BITFIELD(14, 14) ; //!< REFRESH_FRAME_CONTEXT 3313 uint32_t ErrorResilientMode : __CODEGEN_BITFIELD(15, 15) ; //!< ERROR_RESILIENT_MODE 3314 uint32_t FrameParallelDecodingMode : __CODEGEN_BITFIELD(16, 16) ; //!< FRAME_PARALLEL_DECODING_MODE 3315 uint32_t FilterLevel : __CODEGEN_BITFIELD(17, 22) ; //!< Filter Level 3316 uint32_t SharpnessLevel : __CODEGEN_BITFIELD(23, 25) ; //!< Sharpness Level 3317 uint32_t SegmentationEnabled : __CODEGEN_BITFIELD(26, 26) ; //!< SEGMENTATION_ENABLED 3318 uint32_t SegmentationUpdateMap : __CODEGEN_BITFIELD(27, 27) ; //!< SEGMENTATION_UPDATE_MAP 3319 uint32_t SegmentationTemporalUpdate : __CODEGEN_BITFIELD(28, 28) ; //!< SEGMENTATION_TEMPORAL_UPDATE 3320 uint32_t LosslessMode : __CODEGEN_BITFIELD(29, 29) ; //!< LOSSLESS_MODE 3321 uint32_t SegmentIdStreamoutEnable : __CODEGEN_BITFIELD(30, 30) ; //!< SEGMENT_ID_STREAMOUT_ENABLE 3322 uint32_t SegmentIdStreaminEnable : __CODEGEN_BITFIELD(31, 31) ; //!< SEGMENT_ID_STREAMIN_ENABLE 3323 }; 3324 uint32_t Value; 3325 } DW2; 3326 union 3327 { 3328 struct 3329 { 3330 uint32_t Log2TileColumn : __CODEGEN_BITFIELD( 0, 3) ; //!< LOG2_TILE_COLUMN 3331 uint32_t Reserved100 : __CODEGEN_BITFIELD( 4, 7) ; //!< Reserved 3332 uint32_t Log2TileRow : __CODEGEN_BITFIELD( 8, 9) ; //!< LOG2_TILE_ROW 3333 uint32_t Reserved106 : __CODEGEN_BITFIELD(10, 20) ; //!< Reserved 3334 uint32_t SseEnable : __CODEGEN_BITFIELD(21, 21) ; //!< SSE Enable 3335 uint32_t ChromaSamplingFormat : __CODEGEN_BITFIELD(22, 23) ; //!< CHROMA_SAMPLING_FORMAT 3336 uint32_t Bitdepthminus8 : __CODEGEN_BITFIELD(24, 27) ; //!< BITDEPTHMINUS8 3337 uint32_t ProfileLevel : __CODEGEN_BITFIELD(28, 31) ; //!< PROFILE_LEVEL 3338 }; 3339 uint32_t Value; 3340 } DW3; 3341 union 3342 { 3343 struct 3344 { 3345 uint32_t VerticalScaleFactorForLast : __CODEGEN_BITFIELD( 0, 15) ; //!< Vertical Scale Factor for LAST 3346 uint32_t HorizontalScaleFactorForLast : __CODEGEN_BITFIELD(16, 31) ; //!< Horizontal Scale Factor for LAST 3347 }; 3348 uint32_t Value; 3349 } DW4; 3350 union 3351 { 3352 struct 3353 { 3354 uint32_t VerticalScaleFactorForGolden : __CODEGEN_BITFIELD( 0, 15) ; //!< Vertical Scale Factor for GOLDEN 3355 uint32_t HorizontalScaleFactorForGolden : __CODEGEN_BITFIELD(16, 31) ; //!< Horizontal Scale Factor for GOLDEN 3356 }; 3357 uint32_t Value; 3358 } DW5; 3359 union 3360 { 3361 struct 3362 { 3363 uint32_t VerticalScaleFactorForAltref : __CODEGEN_BITFIELD( 0, 15) ; //!< Vertical Scale Factor for ALTREF 3364 uint32_t HorizontalScaleFactorForAltref : __CODEGEN_BITFIELD(16, 31) ; //!< Horizontal Scale Factor for ALTREF 3365 }; 3366 uint32_t Value; 3367 } DW6; 3368 union 3369 { 3370 struct 3371 { 3372 uint32_t LastFrameWidthInPixelsMinus1 : __CODEGEN_BITFIELD( 0, 13) ; //!< Last Frame Width In Pixels Minus 1 3373 uint32_t Reserved238 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 3374 uint32_t LastFrameHieghtInPixelsMinus1 : __CODEGEN_BITFIELD(16, 29) ; //!< Last Frame Hieght In Pixels Minus 1 3375 uint32_t Reserved254 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 3376 }; 3377 uint32_t Value; 3378 } DW7; 3379 union 3380 { 3381 struct 3382 { 3383 uint32_t GoldenFrameWidthInPixelsMinus1 : __CODEGEN_BITFIELD( 0, 13) ; //!< Golden Frame Width In Pixels Minus 1 3384 uint32_t Reserved270 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 3385 uint32_t GoldenFrameHieghtInPixelsMinus1 : __CODEGEN_BITFIELD(16, 29) ; //!< Golden Frame Hieght In Pixels Minus 1 3386 uint32_t Reserved286 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 3387 }; 3388 uint32_t Value; 3389 } DW8; 3390 union 3391 { 3392 struct 3393 { 3394 uint32_t AltrefFrameWidthInPixelsMinus1 : __CODEGEN_BITFIELD( 0, 13) ; //!< Altref Frame Width In Pixels Minus 1 3395 uint32_t Reserved302 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 3396 uint32_t AltrefFrameHieghtInPixelsMinus1 : __CODEGEN_BITFIELD(16, 29) ; //!< Altref Frame Hieght In Pixels Minus 1 3397 uint32_t Reserved318 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 3398 }; 3399 uint32_t Value; 3400 } DW9; 3401 union 3402 { 3403 struct 3404 { 3405 uint32_t UncompressedHeaderLengthInBytes70 : __CODEGEN_BITFIELD( 0, 7) ; //!< Uncompressed Header Length in Bytes [7:0] 3406 uint32_t Reserved328 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 3407 uint32_t FirstPartitionSizeInBytes150 : __CODEGEN_BITFIELD(16, 31) ; //!< First Partition Size in Bytes [15:0] 3408 }; 3409 uint32_t Value; 3410 } DW10; 3411 union 3412 { 3413 struct 3414 { 3415 uint32_t Reserved352 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 3416 uint32_t MotionCompScalingEnableBit : __CODEGEN_BITFIELD( 1, 1) ; //!< MOTION_COMP_SCALING_ENABLE_BIT 3417 uint32_t Reserved354 : __CODEGEN_BITFIELD( 2, 31) ; //!< Reserved 3418 }; 3419 uint32_t Value; 3420 } DW11; 3421 union 3422 { 3423 struct 3424 { 3425 uint32_t Reserved384 ; //!< Reserved 3426 }; 3427 uint32_t Value; 3428 } DW12; 3429 union 3430 { 3431 struct 3432 { 3433 uint32_t CompressedHeaderBinCount : __CODEGEN_BITFIELD( 0, 15) ; //!< Compressed header BIN count 3434 uint32_t BaseQIndexSameAsLumaAc : __CODEGEN_BITFIELD(16, 23) ; //!< Base Q Index (Same as Luma AC) 3435 uint32_t TailInsertionEnable : __CODEGEN_BITFIELD(24, 24) ; //!< Tail Insertion Enable 3436 uint32_t HeaderInsertionEnable : __CODEGEN_BITFIELD(25, 25) ; //!< Header Insertion Enable 3437 uint32_t Reserved442 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 3438 }; 3439 uint32_t Value; 3440 } DW13; 3441 union 3442 { 3443 struct 3444 { 3445 uint32_t ChromaacQindexdelta : __CODEGEN_BITFIELD( 0, 4) ; //!< ChromaAC_QindexDelta 3446 uint32_t Reserved453 : __CODEGEN_BITFIELD( 5, 7) ; //!< Reserved 3447 uint32_t ChromadcQindexdelta : __CODEGEN_BITFIELD( 8, 12) ; //!< ChromaDC_QindexDelta 3448 uint32_t Reserved461 : __CODEGEN_BITFIELD(13, 15) ; //!< Reserved 3449 uint32_t LumaDcQIndexDelta : __CODEGEN_BITFIELD(16, 20) ; //!< Luma DC Q Index Delta 3450 uint32_t Reserved469 : __CODEGEN_BITFIELD(21, 31) ; //!< Reserved 3451 }; 3452 uint32_t Value; 3453 } DW14; 3454 union 3455 { 3456 struct 3457 { 3458 uint32_t LfRefDelta0 : __CODEGEN_BITFIELD( 0, 6) ; //!< LF_ref_delta0 3459 uint32_t Reserved487 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved 3460 uint32_t LfRefDelta1 : __CODEGEN_BITFIELD( 8, 14) ; //!< LF_ref_delta1 3461 uint32_t Reserved495 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 3462 uint32_t LfRefDelta2 : __CODEGEN_BITFIELD(16, 22) ; //!< LF_ref_delta2 3463 uint32_t Reserved503 : __CODEGEN_BITFIELD(23, 23) ; //!< Reserved 3464 uint32_t LfRefDelta3 : __CODEGEN_BITFIELD(24, 30) ; //!< LF_ref_delta3 3465 uint32_t Reserved511 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 3466 }; 3467 uint32_t Value; 3468 } DW15; 3469 union 3470 { 3471 struct 3472 { 3473 uint32_t LfModeDelta0 : __CODEGEN_BITFIELD( 0, 6) ; //!< LF Mode Delta 0 3474 uint32_t Reserved519 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved 3475 uint32_t LfModeDelta1 : __CODEGEN_BITFIELD( 8, 14) ; //!< LF Mode Delta 1 3476 uint32_t Reserved527 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 3477 }; 3478 uint32_t Value; 3479 } DW16; 3480 union 3481 { 3482 struct 3483 { 3484 uint32_t Bitoffsetforlfrefdelta : __CODEGEN_BITFIELD( 0, 15) ; //!< BitOffsetForLFRefDelta 3485 uint32_t Bitoffsetforlfmodedelta : __CODEGEN_BITFIELD(16, 31) ; //!< BitOffsetForLFModeDelta 3486 }; 3487 uint32_t Value; 3488 } DW17; 3489 union 3490 { 3491 struct 3492 { 3493 uint32_t Bitoffsetforqindex : __CODEGEN_BITFIELD( 0, 15) ; //!< BitOffsetForQindex 3494 uint32_t Bitoffsetforlflevel : __CODEGEN_BITFIELD(16, 31) ; //!< BitOffsetForLFLevel 3495 }; 3496 uint32_t Value; 3497 } DW18; 3498 union 3499 { 3500 struct 3501 { 3502 uint32_t Reserved608 : __CODEGEN_BITFIELD( 0, 15) ; //!< Reserved 3503 uint32_t Nonfirstpassflag : __CODEGEN_BITFIELD(16, 16) ; //!< NONFIRSTPASSFLAG 3504 uint32_t VdencPakOnlyPass : __CODEGEN_BITFIELD(17, 17) ; //!< VDENC PAK_ONLY PASS 3505 uint32_t Reserved626 : __CODEGEN_BITFIELD(18, 24) ; //!< Reserved 3506 uint32_t FrameszoverstatusenFramebitratemaxreportmask : __CODEGEN_BITFIELD(25, 25) ; //!< FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK 3507 uint32_t FrameszunderstatusenFramebitrateminreportmask : __CODEGEN_BITFIELD(26, 26) ; //!< FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK 3508 uint32_t Reserved635 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 3509 }; 3510 uint32_t Value; 3511 } DW19; 3512 union 3513 { 3514 struct 3515 { 3516 uint32_t Framebitratemax : __CODEGEN_BITFIELD( 0, 13) ; //!< FrameBitRateMax 3517 uint32_t Reserved654 : __CODEGEN_BITFIELD(14, 30) ; //!< Reserved 3518 uint32_t Framebitratemaxunit : __CODEGEN_BITFIELD(31, 31) ; //!< FRAMEBITRATEMAXUNIT 3519 }; 3520 uint32_t Value; 3521 } DW20; 3522 union 3523 { 3524 struct 3525 { 3526 uint32_t Framebitratemin : __CODEGEN_BITFIELD( 0, 13) ; //!< FrameBitRateMin 3527 uint32_t Reserved686 : __CODEGEN_BITFIELD(14, 30) ; //!< Reserved 3528 uint32_t Framebitrateminunit : __CODEGEN_BITFIELD(31, 31) ; //!< FRAMEBITRATEMINUNIT 3529 }; 3530 uint32_t Value; 3531 } DW21; 3532 union 3533 { 3534 struct 3535 { 3536 uint64_t Framedeltaqindexmax ; //!< FrameDeltaQindexMax 3537 }; 3538 uint32_t Value[2]; 3539 } DW22_23; 3540 union 3541 { 3542 struct 3543 { 3544 uint32_t Framedeltaqindexmin ; //!< FrameDeltaQindexMin 3545 }; 3546 uint32_t Value; 3547 } DW24; 3548 union 3549 { 3550 struct 3551 { 3552 uint64_t Framedeltalfmax ; //!< FrameDeltaLFMax 3553 }; 3554 uint32_t Value[2]; 3555 } DW25_26; 3556 union 3557 { 3558 struct 3559 { 3560 uint32_t Framedeltalfmin ; //!< FrameDeltaLFMin 3561 }; 3562 uint32_t Value; 3563 } DW27; 3564 union 3565 { 3566 struct 3567 { 3568 uint64_t Framedeltaqindexlfmaxrange ; //!< FrameDeltaQindexLFMaxRange 3569 }; 3570 uint32_t Value[2]; 3571 } DW28_29; 3572 union 3573 { 3574 struct 3575 { 3576 uint32_t Framedeltaqindexlfminrange ; //!< FrameDeltaQindexLFMinRange 3577 }; 3578 uint32_t Value; 3579 } DW30; 3580 union 3581 { 3582 struct 3583 { 3584 uint32_t Minframsize : __CODEGEN_BITFIELD( 0, 15) ; //!< MinFramSize 3585 uint32_t Reserved1008 : __CODEGEN_BITFIELD(16, 29) ; //!< Reserved 3586 uint32_t Minframesizeunits : __CODEGEN_BITFIELD(30, 31) ; //!< MINFRAMESIZEUNITS 3587 }; 3588 uint32_t Value; 3589 } DW31; 3590 union 3591 { 3592 struct 3593 { 3594 uint32_t Bitoffsetforfirstpartitionsize : __CODEGEN_BITFIELD( 0, 15) ; //!< BitOffsetForFirstPartitionSize 3595 uint32_t Reserved1040 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 3596 }; 3597 uint32_t Value; 3598 } DW32; 3599 union 3600 { 3601 struct 3602 { 3603 uint32_t Class0SseThreshold0 : __CODEGEN_BITFIELD( 0, 15) ; //!< Class0_SSE_Threshold0 3604 uint32_t Class0SseThreshold1 : __CODEGEN_BITFIELD(16, 31) ; //!< Class0_SSE_Threshold1 3605 }; 3606 uint32_t Value; 3607 } DW33; 3608 uint32_t SseThresholdsForClass18[8]; //!< SSE thresholds for Class1-8 3609 3610 //! \name Local enumerations 3611 3612 enum MEDIA_INSTRUCTION_COMMAND 3613 { 3614 MEDIA_INSTRUCTION_COMMAND_HCPVP9PICSTATE = 48, //!< No additional details 3615 }; 3616 3617 //! \brief MEDIA_INSTRUCTION_OPCODE 3618 //! \details 3619 //! Codec/Engine Name = HUC = Bh 3620 enum MEDIA_INSTRUCTION_OPCODE 3621 { 3622 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 3623 }; 3624 3625 enum PIPELINE_TYPE 3626 { 3627 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 3628 }; 3629 3630 enum COMMAND_TYPE 3631 { 3632 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3633 }; 3634 3635 //! \brief FRAME_TYPE 3636 //! \details 3637 //! Specifies the VP9 frame type 3638 enum FRAME_TYPE 3639 { 3640 FRAME_TYPE_KEYFRAME = 0, //!< No additional details 3641 FRAME_TYPE_INTERFRAME = 1, //!< No additional details 3642 }; 3643 3644 //! \brief ADAPT_PROBABILITIES_FLAG 3645 //! \details 3646 //! Indicates that the probabilities used to decode this frame should be 3647 //! adapted 3648 enum ADAPT_PROBABILITIES_FLAG 3649 { 3650 ADAPT_PROBABILITIES_FLAG_0DONOTADAPT_ERRORRESILIENTORFRAMEPARALLELMODEARESET = 0, //!< No additional details 3651 ADAPT_PROBABILITIES_FLAG_1ADAPT_NOTERRORRESILIENTANDNOTFRAMEPARALLELMODE = 1, //!< No additional details 3652 }; 3653 3654 //! \brief ALLOW_HI_PRECISION_MV 3655 //! \details 3656 //! Indicate high precision mode for Motion Vector prediction 3657 enum ALLOW_HI_PRECISION_MV 3658 { 3659 ALLOW_HI_PRECISION_MV_NORMALMODE = 0, //!< No additional details 3660 ALLOW_HI_PRECISION_MV_HIGHPRECISIONMODE = 1, //!< No additional details 3661 }; 3662 3663 //! \brief MCOMP_FILTER_TYPE 3664 //! \details 3665 //! Indicate Motion Compensation Filter type. 3666 enum MCOMP_FILTER_TYPE 3667 { 3668 MCOMP_FILTER_TYPE_EIGHT_TAP = 0, //!< No additional details 3669 MCOMP_FILTER_TYPE_EIGHT_TAP_SMOOTH = 1, //!< No additional details 3670 MCOMP_FILTER_TYPE_EIGHT_TAP_SHARP = 2, //!< No additional details 3671 MCOMP_FILTER_TYPE_BILINEAR = 3, //!< No additional details 3672 MCOMP_FILTER_TYPE_SWITCHABLE = 4, //!< No additional details 3673 }; 3674 3675 //! \brief HYBRID_PREDICTION_MODE 3676 //! \details 3677 //! Indicates if comp_pred_mode is hybrid 3678 enum HYBRID_PREDICTION_MODE 3679 { 3680 HYBRID_PREDICTION_MODE_COMPPREDICTIONMODEHYBRID_ENCODERDOESNOTPACKCOMPPREDMODEINTERPREDCOMPINPAKOBJINTOBITSTREAM = 0, //!< No additional details 3681 HYBRID_PREDICTION_MODE_COMPPREDICTIONMODEHYBRID_ENCODERPACKSCOMPPREDMODEINTOBITSTREAMTHISHELPSREDUCEBITSTREAMSIZEFURTHER = 1, //!< No additional details 3682 }; 3683 3684 //! \brief SELECTABLE_TX_MODE 3685 //! \details 3686 //! Indicates if tx_mode is selectable 3687 enum SELECTABLE_TX_MODE 3688 { 3689 SELECTABLE_TX_MODE_ENCODERDOESNOTPACKTUSIZEINTOBITSTREAMTHISHELPSREDUCEBITSTREAMSIZEFURTHER = 0, //!< No additional details 3690 SELECTABLE_TX_MODE_ENCODERPACKSTUSIZEINTOBITSTREAM = 1, //!< No additional details 3691 }; 3692 3693 //! \brief LAST_FRAME_TYPE 3694 //! \details 3695 //! <p>It indicates the frame type of previous frame (Key or Non-Key 3696 //! Frame)</p> 3697 enum LAST_FRAME_TYPE 3698 { 3699 LAST_FRAME_TYPE_KEYFRAME = 0, //!< No additional details 3700 LAST_FRAME_TYPE_NONKEYFRAME = 1, //!< No additional details 3701 }; 3702 3703 //! \brief REFRESH_FRAME_CONTEXT 3704 //! \details 3705 //! <p>Indicates if Frame Context should be refresh. This bit should come 3706 //! from Uncompressed header</p> 3707 enum REFRESH_FRAME_CONTEXT 3708 { 3709 REFRESH_FRAME_CONTEXT_DISABLE = 0, //!< No additional details 3710 REFRESH_FRAME_CONTEXT_ENABLE = 1, //!< No additional details 3711 }; 3712 3713 //! \brief ERROR_RESILIENT_MODE 3714 //! \details 3715 //! <p>Indicates if error resilient mode is enabled. This bit should come 3716 //! from Uncompressed header.When error resilient is 1, Frame Parallel 3717 //! Decoding Mode will be 1, and Refresh Frame Context will be 0.When error 3718 //! resilient is 0, Frame Parallel Decoding Mode and Refresh Frame Context 3719 //! read from bit stream.Together with Frame Parallel Decoding mode, they 3720 //! decide the value of AdaptProbabilityFlag.</p> 3721 enum ERROR_RESILIENT_MODE 3722 { 3723 ERROR_RESILIENT_MODE_DISABLE = 0, //!< No additional details 3724 ERROR_RESILIENT_MODE_ENABLE = 1, //!< No additional details 3725 }; 3726 3727 //! \brief FRAME_PARALLEL_DECODING_MODE 3728 //! \details 3729 //! <p>Indicates if parallel decoding mode is enabled. This bit should come 3730 //! from Uncompressed header. Together with Error Resilient mode, they 3731 //! decide the value of AdaptProbabilityFlag.</p> 3732 enum FRAME_PARALLEL_DECODING_MODE 3733 { 3734 FRAME_PARALLEL_DECODING_MODE_DISABLE = 0, //!< No additional details 3735 FRAME_PARALLEL_DECODING_MODE_ENABLE = 1, //!< No additional details 3736 }; 3737 3738 //! \brief SEGMENTATION_ENABLED 3739 //! \details 3740 //! Indicate if segementation is enabled or not 3741 enum SEGMENTATION_ENABLED 3742 { 3743 SEGMENTATION_ENABLED_ALLBLOCKSAREIMPLIEDTOBELONGTOSEGMENT0 = 0, //!< No additional details 3744 SEGMENTATION_ENABLED_SEGIDDETERMINATIONDEPENDSONSEGMENTATIONUPDATEMAPSETTING = 1, //!< No additional details 3745 }; 3746 3747 //! \brief SEGMENTATION_UPDATE_MAP 3748 //! \details 3749 //! Indicates how hardware determines segmentation ID 3750 enum SEGMENTATION_UPDATE_MAP 3751 { 3752 SEGMENTATION_UPDATE_MAP_UNNAMED0 = 0, //!< Intra block: segment ID is zero Inter block: get segment ID from previous frame (streamIN) 3753 SEGMENTATION_UPDATE_MAP_UNNAMED1 = 1, //!< Intra block: decode segment ID from bitstream. Inter block: determins from segmentation_temporal_update setting 3754 }; 3755 3756 //! \brief SEGMENTATION_TEMPORAL_UPDATE 3757 //! \details 3758 //! Indicates whether segID is decoding from bitstream or predicted from 3759 //! previous frame. 3760 enum SEGMENTATION_TEMPORAL_UPDATE 3761 { 3762 SEGMENTATION_TEMPORAL_UPDATE_DECODESEGIDFROMBITSTREAM = 0, //!< No additional details 3763 SEGMENTATION_TEMPORAL_UPDATE_GETSEGIDEITHERFROMBITSTREAMORFROMPREVIOUSFRAME = 1, //!< No additional details 3764 }; 3765 3766 //! \brief LOSSLESS_MODE 3767 //! \details 3768 //! This bitSet to indicate lossless coding mode. 3769 enum LOSSLESS_MODE 3770 { 3771 LOSSLESS_MODE_NORMALMODE = 0, //!< No additional details 3772 LOSSLESS_MODE_LOLESSMODE = 1, //!< No additional details 3773 }; 3774 3775 //! \brief SEGMENT_ID_STREAMOUT_ENABLE 3776 //! \details 3777 //! Indicates SegmentID of current frame needs to be streamOut for next 3778 //! frame 3779 enum SEGMENT_ID_STREAMOUT_ENABLE 3780 { 3781 SEGMENT_ID_STREAMOUT_ENABLE_DISABLE = 0, //!< No additional details 3782 SEGMENT_ID_STREAMOUT_ENABLE_ENABLE = 1, //!< No additional details 3783 }; 3784 3785 //! \brief SEGMENT_ID_STREAMIN_ENABLE 3786 //! \details 3787 //! Indicates SegmentID from previous frame needs to be streamIn for Segment 3788 //! ID prediction 3789 enum SEGMENT_ID_STREAMIN_ENABLE 3790 { 3791 SEGMENT_ID_STREAMIN_ENABLE_DISABLE = 0, //!< No additional details 3792 SEGMENT_ID_STREAMIN_ENABLE_ENABLE = 1, //!< No additional details 3793 }; 3794 3795 //! \brief LOG2_TILE_COLUMN 3796 //! \details 3797 //! This indicates the number of tile rows (log2). 3798 enum LOG2_TILE_COLUMN 3799 { 3800 LOG2_TILE_COLUMN_1TILECOLUMN = 0, //!< No additional details 3801 LOG2_TILE_COLUMN_2TILECOLUMN = 1, //!< No additional details 3802 LOG2_TILE_COLUMN_4TILECOLUMN = 2, //!< No additional details 3803 LOG2_TILE_COLUMN_8TILECOLUMN = 3, //!< No additional details 3804 LOG2_TILE_COLUMN_16TILECOLUMN = 4, //!< No additional details 3805 LOG2_TILE_COLUMN_32TILECOLUMN = 5, //!< No additional details 3806 LOG2_TILE_COLUMN_64TILECOLUMN = 6, //!< No additional details 3807 }; 3808 3809 //! \brief LOG2_TILE_ROW 3810 //! \details 3811 //! This indicates the number of tile rows (log2). 3812 enum LOG2_TILE_ROW 3813 { 3814 LOG2_TILE_ROW_1TILEROW = 0, //!< No additional details 3815 LOG2_TILE_ROW_2TILEROW = 1, //!< No additional details 3816 LOG2_TILE_ROW_4TILEROW = 2, //!< No additional details 3817 }; 3818 3819 //! \brief CHROMA_SAMPLING_FORMAT 3820 //! \details 3821 //! This indicates the chroma sampling format of the bitstream 3822 enum CHROMA_SAMPLING_FORMAT 3823 { 3824 CHROMA_SAMPLING_FORMAT_FORMAT420 = 0, //!< No additional details 3825 CHROMA_SAMPLING_FORMAT_FORMAT444 = 2, //!< No additional details 3826 }; 3827 3828 //! \brief BITDEPTHMINUS8 3829 //! \details 3830 //! This indicates the bitdepth (minus 8) of the pixels 3831 enum BITDEPTHMINUS8 3832 { 3833 BITDEPTHMINUS8_BITDEPTH8 = 0, //!< No additional details 3834 BITDEPTHMINUS8_BITDEPTH10 = 2, //!< No additional details 3835 BITDEPTHMINUS8_BITDEPTH12 = 4, //!< No additional details 3836 }; 3837 3838 //! \brief PROFILE_LEVEL 3839 //! \details 3840 //! This indicates VP9 Profile level from bitstream 3841 enum PROFILE_LEVEL 3842 { 3843 PROFILE_LEVEL_PROFILE0 = 0, //!< Profile 0 only supports 8 bit 420 only 3844 PROFILE_LEVEL_PROFILE1 = 1, //!< Profile 1 only supports 8 bit 444 only 3845 PROFILE_LEVEL_PROFILE2 = 2, //!< Profile 2 only supports 10 bits 420 only 3846 PROFILE_LEVEL_PROFILE3 = 3, //!< Profile 3 only supports 10-bit 444 only 3847 }; 3848 3849 //! \brief MOTION_COMP_SCALING_ENABLE_BIT 3850 //! \details 3851 //! This bit must be set to "1" 3852 enum MOTION_COMP_SCALING_ENABLE_BIT 3853 { 3854 MOTION_COMP_SCALING_ENABLE_BIT_ENABLE = 1, //!< This enables Motion Comp Scaling 3855 }; 3856 3857 //! \brief NONFIRSTPASSFLAG 3858 //! \details 3859 //! This signals the current pass is not the first pass. It will imply 3860 //! designate HW behavior. 3861 enum NONFIRSTPASSFLAG 3862 { 3863 NONFIRSTPASSFLAG_DISABLE = 0, //!< If it is initial-Pass, this bit is set to 0. 3864 NONFIRSTPASSFLAG_ENABLE = 1, //!< For subsequent passes, this bit is set to 1. 3865 }; 3866 3867 //! \brief FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK 3868 //! \details 3869 //! This is a mask bit controlling if the condition of frame level bit count 3870 //! exceeds FrameBitRateMax. 3871 enum FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK 3872 { 3873 FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK_DISABLE = 0, //!< Do not update bit 1 of HCP_VP9_IMAGE_STATUS control register. 3874 FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK_ENABLE = 1, //!< Set bit 1 of HCP_VP9_IMAGE_STATUS control register if the total frame level bit counter is greater than or equal to Frame Bit Rate Maximum limit. 3875 }; 3876 3877 //! \brief FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK 3878 //! \details 3879 //! This is a mask bit controlling if the condition of frame level bit count 3880 //! is less than FrameBitRateMin. 3881 enum FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK 3882 { 3883 FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK_DISABLE = 0, //!< Do not update bit 2 (Frame Bit Count Violate -- under run) of HCP_VP9_IMAGE_STATUS control register. 3884 FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK_ENABLE = 1, //!< Set bit 2 (Frame Bit Count Violate -- under run) of HCP_VP9_IMAGE_STATUS control register if the total frame level bit counter is less than or equal to Frame Bit Rate Minimum limit. 3885 }; 3886 3887 //! \brief FRAMEBITRATEMAXUNIT 3888 //! \details 3889 //! This field is the Frame Bitrate Maximum Limit Units. 3890 enum FRAMEBITRATEMAXUNIT 3891 { 3892 FRAMEBITRATEMAXUNIT_BYTE = 0, //!< 32byte unit 3893 FRAMEBITRATEMAXUNIT_KILOBYTE = 1, //!< 4Kbyte unit 3894 }; 3895 3896 //! \brief FRAMEBITRATEMINUNIT 3897 //! \details 3898 //! This field is the Frame Bitrate Maximum Limit Units. 3899 enum FRAMEBITRATEMINUNIT 3900 { 3901 FRAMEBITRATEMINUNIT_BYTE = 0, //!< 32byte unit 3902 FRAMEBITRATEMINUNIT_KILOBYTE = 1, //!< 4Kbyte unit 3903 }; 3904 3905 //! \brief MINFRAMESIZEUNITS 3906 //! \details 3907 //! This field is the Minimum Frame Size Units 3908 enum MINFRAMESIZEUNITS 3909 { 3910 MINFRAMESIZEUNITS_4KB = 0, //!< Minimum Frame Size is in 4Kbytes. 3911 MINFRAMESIZEUNITS_16KB = 1, //!< Minimum Frame Size is in 4Kbytes. 3912 MINFRAMESIZEUNITS_COMAPTIBILITYMODE = 2, //!< No additional details 3913 MINFRAMESIZEUNITS_6BYTES = 3, //!< No additional details 3914 }; 3915 3916 //! \name Initializations 3917 3918 //! \brief Explicit member initialization function 3919 HCP_VP9_PIC_STATE_CMD(); 3920 3921 static const size_t dwSize = 42; 3922 static const size_t byteSize = 168; 3923 }; 3924 3925 //! 3926 //! \brief HEVC_VP9_RDOQ_LAMBDA_FIELDS 3927 //! \details 3928 //! 3929 //! 3930 struct HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD 3931 { 3932 union 3933 { 3934 struct 3935 { 3936 uint32_t Lambdavalue0 : __CODEGEN_BITFIELD( 0, 15) ; //!< LambdaValue0 3937 uint32_t Lambdavalue1 : __CODEGEN_BITFIELD(16, 31) ; //!< LambdaValue1 3938 }; 3939 uint32_t Value; 3940 } DW0; 3941 3942 //! \name Local enumerations 3943 3944 //! \name Initializations 3945 3946 //! \brief Explicit member initialization function 3947 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD(); 3948 3949 static const size_t dwSize = 1; 3950 static const size_t byteSize = 4; 3951 }; 3952 3953 //! 3954 //! \brief HEVC_VP9_RDOQ_STATE 3955 //! \details 3956 //! 3957 //! 3958 struct HEVC_VP9_RDOQ_STATE_CMD 3959 { 3960 union 3961 { 3962 struct 3963 { 3964 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3965 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3966 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 3967 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 3968 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 3969 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 3970 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3971 }; 3972 uint32_t Value; 3973 } DW0; 3974 union 3975 { 3976 struct 3977 { 3978 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 29) ; //!< Reserved 3979 uint32_t DisableHtqPerformanceFix1 : __CODEGEN_BITFIELD(30, 30) ; //!< Disable HTQ performance fix1 3980 uint32_t DisableHtqPerformanceFix0 : __CODEGEN_BITFIELD(31, 31) ; //!< Disable HTQ performance fix0 3981 }; 3982 uint32_t Value; 3983 } DW1; 3984 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD Intralumalambda[32]; //!< DW2..33, IntraLumaLambda 3985 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD Intrachromalambda[32]; //!< DW34..65, IntraChromaLambda 3986 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD Interlumalambda[32]; //!< DW66..97, InterLumaLambda 3987 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD Interchromalambda[32]; //!< DW98..129, InterChromaLambda 3988 3989 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD Intralumalambda12bit[6]; //!< DW130..135, IntraLumaLambda 3990 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD Intrachromalambda12bit[6]; //!< DW136..141, IntraChromaLambda 3991 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD Interlumalambda12bit[6]; //!< DW142..147, InterLumaLambda 3992 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD Interchromalambda12bit[6]; //!< DW148..153, InterChromaLambda 3993 3994 //! \name Local enumerations 3995 3996 enum SUBOPB 3997 { 3998 SUBOPB_UNNAMED8 = 8, //!< No additional details 3999 }; 4000 4001 enum SUBOPA 4002 { 4003 SUBOPA_UNNAMED0 = 0, //!< No additional details 4004 }; 4005 4006 //! \brief OPCODE 4007 //! \details 4008 //! Codec/Engine Name = HCP = 7h 4009 enum OPCODE 4010 { 4011 OPCODE_UNNAMED7 = 7, //!< No additional details 4012 }; 4013 4014 //! \brief PIPELINE 4015 //! \details 4016 //! MFX_COMMON 4017 enum PIPELINE 4018 { 4019 PIPELINE_UNNAMED2 = 2, //!< No additional details 4020 }; 4021 4022 //! \brief COMMAND_TYPE 4023 //! \details 4024 //! PARALLEL_VIDEO_PIPE 4025 enum COMMAND_TYPE 4026 { 4027 COMMAND_TYPE_UNNAMED3 = 3, //!< No additional details 4028 }; 4029 4030 //! \name Initializations 4031 4032 //! \brief Explicit member initialization function 4033 HEVC_VP9_RDOQ_STATE_CMD(); 4034 4035 static const size_t dwSize = 154; 4036 static const size_t byteSize = 616; 4037 }; 4038 4039 //! 4040 //! \brief HCP_TILE_CODING 4041 //! \details 4042 //! This command is used for both HEVC and VP9 codecs 4043 //! 4044 struct HCP_TILE_CODING_CMD 4045 { 4046 union 4047 { 4048 struct 4049 { 4050 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 4051 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 4052 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 4053 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 4054 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 4055 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 4056 }; 4057 uint32_t Value; 4058 } DW0; 4059 union 4060 { 4061 struct 4062 { 4063 uint32_t NumberOfActiveBePipes : __CODEGEN_BITFIELD( 0, 7) ; //!< Number of Active BE Pipes 4064 uint32_t TileRowStoreSelect : __CODEGEN_BITFIELD( 8, 8) ; //!< Tile Row store Select 4065 uint32_t TileColumnStoreSelect : __CODEGEN_BITFIELD( 9, 9) ; //!< Tile Column store Select 4066 uint32_t Reserved42 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved MBZ 4067 uint32_t NumOfTileColumnsInAFrame : __CODEGEN_BITFIELD(16, 31) ; //!< Num of Tile columns in a Frame 4068 }; 4069 uint32_t Value; 4070 } DW1; 4071 union 4072 { 4073 struct 4074 { 4075 uint32_t TileColumnPosition : __CODEGEN_BITFIELD( 0, 9) ; //!< Tile Column Position 4076 uint32_t NonFirstPassTile : __CODEGEN_BITFIELD(10, 10) ; //!< Non First Pass Tile 4077 uint32_t Reserved75 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 4078 uint32_t TileRowPosition : __CODEGEN_BITFIELD(16, 25) ; //!< Tile Row Position 4079 uint32_t Reserved90 : __CODEGEN_BITFIELD(26, 29) ; //!< Reserved 4080 uint32_t Islasttileofrow : __CODEGEN_BITFIELD(30, 30) ; //!< IsLastTileOfRow 4081 uint32_t Islasttileofcolumn : __CODEGEN_BITFIELD(31, 31) ; //!< IsLastTileOfColumn 4082 }; 4083 uint32_t Value; 4084 } DW2; 4085 union 4086 { 4087 struct 4088 { 4089 uint32_t Tileheightinmincbminus1 : __CODEGEN_BITFIELD( 0, 10) ; //!< TileHeightInMinCbMinus1 4090 uint32_t Reserved107 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 4091 uint32_t Tilewidthinmincbminus1 : __CODEGEN_BITFIELD(16, 26) ; //!< TileWidthInMinCbMinus1 4092 uint32_t Reserved123 : __CODEGEN_BITFIELD(27, 30) ; //!< Reserved 4093 uint32_t LastpassoftileValidationonly : __CODEGEN_BITFIELD(31, 31) ; //!< LastPassOfTile (ValidationOnly) 4094 }; 4095 uint32_t Value; 4096 } DW3; 4097 union 4098 { 4099 struct 4100 { 4101 uint32_t BitstreamByteOffsetEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< Bitstream Byte Offset Enable 4102 uint32_t Reserved129 : __CODEGEN_BITFIELD( 1, 5) ; //!< Reserved 4103 uint32_t BitstreamByteOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< Bitstream Byte Offset 4104 }; 4105 uint32_t Value; 4106 } DW4; 4107 union 4108 { 4109 struct 4110 { 4111 uint32_t Reserved160 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 4112 uint32_t PakFrameStatisticsOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< PAK Frame Statistics Offset 4113 }; 4114 uint32_t Value; 4115 } DW5; 4116 union 4117 { 4118 struct 4119 { 4120 uint32_t Reserved192 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 4121 uint32_t CuLevelStreamoutOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< CU Level Streamout Offset 4122 }; 4123 uint32_t Value; 4124 } DW6; 4125 union 4126 { 4127 struct 4128 { 4129 uint32_t Reserved224 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 4130 uint32_t SliceSizeStreamoutOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< Slice Size Streamout Offset 4131 }; 4132 uint32_t Value; 4133 } DW7; 4134 union 4135 { 4136 struct 4137 { 4138 uint32_t Reserved256 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 4139 uint32_t CuRecordOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< CU record offset 4140 }; 4141 uint32_t Value; 4142 } DW8; 4143 union 4144 { 4145 struct 4146 { 4147 uint32_t Reserved288 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 4148 uint32_t SseRowstoreOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< SSE RowStore offset 4149 }; 4150 uint32_t Value; 4151 } DW9; 4152 union 4153 { 4154 struct 4155 { 4156 uint32_t Reserved320 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 4157 uint32_t SaoRowstoreOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< SAO RowStore offset 4158 }; 4159 uint32_t Value; 4160 } DW10; 4161 union 4162 { 4163 struct 4164 { 4165 uint32_t Reserved352 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 4166 uint32_t TileSizeStreamoutOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< Tile Size StreamOut Offset 4167 }; 4168 uint32_t Value; 4169 } DW11; 4170 union 4171 { 4172 struct 4173 { 4174 uint32_t Reserved384 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 4175 uint32_t Vp9ProbabilityCounterStreamoutOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< VP9 Probability Counter Streamout Offset 4176 }; 4177 uint32_t Value; 4178 } DW12; 4179 SPLITBASEADDRESS64BYTEALIGNED_CMD HcpScalabilitySynchronizeBufferBaseAddress; //!< DW13..14, HCP Scalability Synchronize Buffer - Base Address 4180 MEMORYADDRESSATTRIBUTES_CMD HcpScalabilitySynchronizeBufferAttributes; //!< DW15, HCP Scalability Synchronize Buffer - Attributes 4181 union 4182 { 4183 struct 4184 { 4185 uint32_t Reserved512 ; //!< Reserved 4186 }; 4187 uint32_t Value; 4188 } DW16; 4189 union 4190 { 4191 struct 4192 { 4193 uint32_t Reserved544 : __CODEGEN_BITFIELD( 0, 7) ; //!< Reserved 4194 uint32_t TileNumber : __CODEGEN_BITFIELD( 8, 13) ; //!< Tile number 4195 uint32_t FrameNumber : __CODEGEN_BITFIELD(14, 17) ; //!< Frame Number 4196 uint32_t Reserved562 : __CODEGEN_BITFIELD(18, 31) ; //!< Reserved 4197 }; 4198 uint32_t Value; 4199 } DW17; 4200 union 4201 { 4202 struct 4203 { 4204 uint32_t TilemetadataDw1 ; //!< TileMetaData_DW1 4205 }; 4206 uint32_t Value; 4207 } DW18; 4208 union 4209 { 4210 struct 4211 { 4212 uint32_t TilemetadataDw2 ; //!< TileMetaData_DW2 4213 }; 4214 uint32_t Value; 4215 } DW19; 4216 4217 //! \name Local enumerations 4218 4219 enum MEDIA_INSTRUCTION_COMMAND 4220 { 4221 MEDIA_INSTRUCTION_COMMAND_HCPTILECODING = 21, //!< No additional details 4222 }; 4223 4224 enum MEDIA_INSTRUCTION_OPCODE 4225 { 4226 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 4227 }; 4228 4229 enum PIPELINE_TYPE 4230 { 4231 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 4232 }; 4233 4234 enum COMMAND_TYPE 4235 { 4236 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 4237 }; 4238 4239 //! \name Initializations 4240 4241 //! \brief Explicit member initialization function 4242 HCP_TILE_CODING_CMD(); 4243 4244 static const size_t dwSize = 20; 4245 static const size_t byteSize = 80; 4246 }; 4247 4248 //! 4249 //! \brief VDENC_CONTROL_STATE 4250 //! \details 4251 //! 4252 //! 4253 struct VDENC_CONTROL_STATE_CMD 4254 { 4255 union 4256 { 4257 struct 4258 { 4259 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 4260 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 4261 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 4262 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 4263 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 4264 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 4265 }; 4266 uint32_t Value; 4267 } DW0; 4268 union 4269 { 4270 struct 4271 { 4272 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 4273 uint32_t VdencInitialization : __CODEGEN_BITFIELD( 1, 1) ; //!< VDenc Initialization 4274 uint32_t Reserved34 : __CODEGEN_BITFIELD( 2, 31) ; //!< Reserved 4275 }; 4276 uint32_t Value; 4277 } DW1; 4278 4279 //! \name Local enumerations 4280 4281 enum MEDIA_INSTRUCTION_COMMAND 4282 { 4283 MEDIA_INSTRUCTION_COMMAND_VDCONTROLSTATEFORVDNEC = 11, //!< No additional details 4284 }; 4285 4286 //! \brief MEDIA_INSTRUCTION_OPCODE 4287 //! \details 4288 //! <p></p> 4289 //! <p>Codec/Engine Name = VDNEC = 1h;</p> 4290 enum MEDIA_INSTRUCTION_OPCODE 4291 { 4292 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAMEFORVDENC = 1, //!< No additional details 4293 }; 4294 4295 enum PIPELINE_TYPE 4296 { 4297 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 4298 }; 4299 4300 enum COMMAND_TYPE 4301 { 4302 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 4303 }; 4304 4305 //! \name Initializations 4306 4307 //! \brief Explicit member initialization function 4308 VDENC_CONTROL_STATE_CMD(); 4309 4310 static const size_t dwSize = 2; 4311 static const size_t byteSize = 8; 4312 }; 4313 4314 //! 4315 //! \brief HCP_PALETTE_INITIALIZER_STATE 4316 //! \details 4317 //! The HCP is selected with theMedia Instruction Opcode "7h"for all HCP 4318 //! Commands. Each HCP command has assigned a media instruction command as 4319 //! defined in DWord 0, BitField 22:16. 4320 //! 4321 //! The HCP_PALETTE_INITIALIZER_STATE command loads in the SCC Palette 4322 //! Initilizer Table to the HW. 4323 //! Decoder only command. 4324 //! 4325 //! Dword#2 - 193form a fixed size table for the Palette Initializer Table. 4326 //! Max PaletteInitializer Table is 128entries. Each entry has 3 components 4327 //! (Y, Cb and Cr) for a color. 4328 //! Each component is 16-bits, even though currently only support up to 4329 //! 10-bit SCC extension. The upper (higher bits) 6 bits are set to zero - 4330 //! that is Least Significant Bit alignment. 4331 //! Each entry of thePalette Initializer Table will consume 1.5 Dwords. 4332 //! Every two entries will consume 2 Dwords. Hence, total requires 96 4333 //! Dwords. 4334 //! Dword#2 Bit 31 Cb#0 15:0 Luma#0 15:0 Bit 0 4335 //! Dword#3 Bit 31 Luma#115:0 Cr#015:0 Bit 0 4336 //! Dword#4 Bit 31 Cr#115:0 Cb#115:0 Bit 0 4337 //! Dword#2 correspondsto the entry# 0 of thePalette Initializer Table. 4338 //! Dword#193correspondsto the entry# 127of thePalette Initializer Table. 4339 //! 4340 //! Palette Initialization needs to happen at the beginning of each 4341 //! frame/tiles or start of each independent slice. Palette initialization 4342 //! is not needed at the start of dependent slices (except the start of a 4343 //! new tiles since each tile needs to re-initialize the palette list) and 4344 //! the palette list is inherited from previous slice. 4345 //! The following is the programming restriction: 4346 //! (1) Palette Initialization commandmust be programmedin palette mode at 4347 //! the beginning of each frame and tiles (regardless if the slice 4348 //! isindependent/dependent)and also the start of each independent slices. 4349 //! (2) Palette Initialization command must not be programmed for dependent 4350 //! slices except the dependent slices are start of tiles (first slice in 4351 //! frame must be independent slice). 4352 //! 4353 //! 4354 struct HCP_PALETTE_INITIALIZER_STATE_CMD 4355 { 4356 union 4357 { 4358 struct 4359 { 4360 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 4361 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 4362 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 4363 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 4364 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 4365 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 4366 }; 4367 uint32_t Value; 4368 } DW0; 4369 union 4370 { 4371 struct 4372 { 4373 uint32_t ActivePaletteInitializerTableEntries : __CODEGEN_BITFIELD( 0, 7) ; //!< Active Palette Initializer Table Entries 4374 uint32_t Reserved40 : __CODEGEN_BITFIELD( 8, 31) ; //!< Reserved 4375 }; 4376 uint32_t Value; 4377 } DW1; 4378 uint32_t First64ColorEntries[96]; //!< First 64 Color Entries 4379 uint32_t Second64ColorEntries[96]; //!< Second 64 Color Entries 4380 4381 //! \name Local enumerations 4382 4383 enum MEDIA_INSTRUCTION_COMMAND 4384 { 4385 MEDIA_INSTRUCTION_COMMAND_HCPPALETTEINITIALIZERSTATE = 9, //!< No additional details 4386 }; 4387 4388 //! \brief MEDIA_INSTRUCTION_OPCODE 4389 //! \details 4390 //! Codec/Engine Name = HCP = 7h 4391 enum MEDIA_INSTRUCTION_OPCODE 4392 { 4393 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 4394 }; 4395 4396 enum PIPELINE_TYPE 4397 { 4398 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 4399 }; 4400 4401 enum COMMAND_TYPE 4402 { 4403 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 4404 }; 4405 4406 //! \name Initializations 4407 4408 //! \brief Explicit member initialization function 4409 HCP_PALETTE_INITIALIZER_STATE_CMD(); 4410 4411 static const size_t dwSize = 194; 4412 static const size_t byteSize = 776; 4413 }; 4414 4415 }; 4416 4417 #pragma pack() 4418 4419 #endif // __MHW_VDBOX_HCP_HWCMD_G12_X_H__