1 /*
2 * Copyright (c) 2017-2019, Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 //!
23 //! \file mhw_vdbox_huc_g12_X.cpp
24 //! \brief Constructs VdBox Huc commands on Gen12-based platforms
25
26 #include "mhw_vdbox_huc_g12_X.h"
27 #include "mhw_vdbox_vdenc_hwcmd_g12_X.h"
28 #include "mhw_mi.h"
29 #include "mhw_mmio_g12.h"
30
InitMmioRegisters()31 void MhwVdboxHucInterfaceG12::InitMmioRegisters()
32 {
33 MmioRegistersHuc *mmioRegisters = &m_mmioRegisters[MHW_VDBOX_NODE_1];
34
35 mmioRegisters->hucUKernelHdrInfoRegOffset = HUC_UKERNEL_HDR_INFO_REG_OFFSET_NODE_1_INIT_G12;
36 mmioRegisters->hucStatusRegOffset = HUC_STATUS_REG_OFFSET_NODE_1_INIT_G12;
37 mmioRegisters->hucStatus2RegOffset = HUC_STATUS2_REG_OFFSET_NODE_1_INIT_G12;
38
39 m_mmioRegisters[MHW_VDBOX_NODE_2] = m_mmioRegisters[MHW_VDBOX_NODE_1];
40 }
41
GetHucStateCommandSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize,PMHW_VDBOX_STATE_CMDSIZE_PARAMS params)42 MOS_STATUS MhwVdboxHucInterfaceG12::GetHucStateCommandSize(
43 uint32_t mode,
44 uint32_t *commandsSize,
45 uint32_t *patchListSize,
46 PMHW_VDBOX_STATE_CMDSIZE_PARAMS params)
47 {
48 MHW_FUNCTION_ENTER;
49
50 MHW_MI_CHK_NULL(commandsSize);
51 MHW_MI_CHK_NULL(patchListSize);
52
53 MHW_MI_CHK_STATUS((MhwVdboxHucInterfaceGeneric<mhw_vdbox_huc_g12_X, mhw_mi_g12_X>::
54 GetHucStateCommandSize(mode, commandsSize, patchListSize, params)));
55
56 *commandsSize += mhw_vdbox_vdenc_g12_X::VD_PIPELINE_FLUSH_CMD::byteSize;
57 *patchListSize += PATCH_LIST_COMMAND(VD_PIPELINE_FLUSH_CMD);
58
59 if(params->uNumVdPipelineFlush)
60 {
61 *commandsSize += params->uNumVdPipelineFlush * mhw_vdbox_vdenc_g12_X::VD_PIPELINE_FLUSH_CMD::byteSize;
62 *patchListSize += params->uNumVdPipelineFlush * PATCH_LIST_COMMAND(VD_PIPELINE_FLUSH_CMD);
63 }
64
65 return MOS_STATUS_SUCCESS;
66 }
67
AddHucPipeModeSelectCmd(MOS_COMMAND_BUFFER * cmdBuffer,MHW_VDBOX_PIPE_MODE_SELECT_PARAMS * params)68 MOS_STATUS MhwVdboxHucInterfaceG12::AddHucPipeModeSelectCmd(
69 MOS_COMMAND_BUFFER *cmdBuffer,
70 MHW_VDBOX_PIPE_MODE_SELECT_PARAMS *params)
71 {
72
73 MHW_MI_CHK_NULL(cmdBuffer);
74 MHW_MI_CHK_NULL(params);
75
76 //for gen 11, we need to add MFX wait for both KIN and VRT before and after HUC Pipemode select...
77 MHW_MI_CHK_STATUS(m_MiInterface->AddMfxWaitCmd(cmdBuffer, nullptr, true));
78
79 mhw_vdbox_huc_g12_X::HUC_PIPE_MODE_SELECT_CMD cmd;
80
81 if (!params->disableProtectionSetting)
82 {
83 MHW_MI_CHK_STATUS(m_cpInterface->SetProtectionSettingsForHucPipeModeSelect((uint32_t *)&cmd));
84 }
85
86 cmd.DW1.IndirectStreamOutEnable = params->bStreamOutEnabled;
87 cmd.DW2.MediaSoftResetCounterPer1000Clocks = params->dwMediaSoftResetCounterValue;
88
89 MHW_MI_CHK_STATUS(Mos_AddCommand(cmdBuffer, &cmd, cmd.byteSize));
90
91 //for gen 11, we need to add MFX wait for both KIN and VRT before and after HUC Pipemode select...
92 MHW_MI_CHK_STATUS(m_MiInterface->AddMfxWaitCmd(cmdBuffer, nullptr, true));
93
94 return MOS_STATUS_SUCCESS;
95 }
96
AddHucImemStateCmd(MOS_COMMAND_BUFFER * cmdBuffer,MHW_VDBOX_HUC_IMEM_STATE_PARAMS * params)97 MOS_STATUS MhwVdboxHucInterfaceG12::AddHucImemStateCmd(
98 MOS_COMMAND_BUFFER *cmdBuffer,
99 MHW_VDBOX_HUC_IMEM_STATE_PARAMS *params)
100 {
101 MHW_MI_CHK_NULL(cmdBuffer);
102 MHW_MI_CHK_NULL(params);
103
104 mhw_vdbox_huc_g12_X::HUC_IMEM_STATE_CMD cmd;
105
106 cmd.DW4.HucFirmwareDescriptor = params->dwKernelDescriptor;
107
108 MHW_MI_CHK_STATUS(Mos_AddCommand(cmdBuffer, &cmd, cmd.byteSize));
109
110 MHW_MI_CHK_STATUS(m_MiInterface->AddMfxWaitCmd(cmdBuffer, nullptr, true));
111
112 return MOS_STATUS_SUCCESS;
113 }
114
115