1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 6 #ifndef _INTEL_HWCONFIG_TYPES_H_ 7 #define _INTEL_HWCONFIG_TYPES_H_ 8 9 /** 10 * enum intel_hwconfig - Global definition of hwconfig blob attributes 11 * 12 * Intel devices provide a KLV (Key/Length/Value) blob containing 13 * the static hardware configuration for that giving platform. 14 * This header defines the current attribute keys for this KLV. 15 */ 16 enum intel_hwconfig { 17 INTEL_HWCONFIG_MAX_SLICES_SUPPORTED = 1, 18 INTEL_HWCONFIG_MAX_DUAL_SUBSLICES_SUPPORTED, /* 2 */ 19 INTEL_HWCONFIG_MAX_NUM_EU_PER_DSS, /* 3 */ 20 INTEL_HWCONFIG_NUM_PIXEL_PIPES, /* 4 */ 21 INTEL_HWCONFIG_MAX_NUM_GEOMETRY_PIPES, /* 5 */ 22 INTEL_HWCONFIG_L3_CACHE_SIZE_IN_KB, /* 6 */ 23 INTEL_HWCONFIG_L3_BANK_COUNT, /* 7 */ 24 INTEL_HWCONFIG_L3_CACHE_WAYS_SIZE_IN_BYTES, /* 8 */ 25 INTEL_HWCONFIG_L3_CACHE_WAYS_PER_SECTOR, /* 9 */ 26 INTEL_HWCONFIG_MAX_MEMORY_CHANNELS, /* 10 */ 27 INTEL_HWCONFIG_MEMORY_TYPE, /* 11 */ 28 INTEL_HWCONFIG_CACHE_TYPES, /* 12 */ 29 /* 30 * Local Memory page sizes supported lists all possible supported sizes 31 * For example, 4KB and 64KB will be listed as (SZ_4K | SZ_64K) 32 */ 33 INTEL_HWCONFIG_LOCAL_MEMORY_PAGE_SIZES_SUPPORTED, /* 13 */ 34 INTEL_HWCONFIG_SLM_SIZE_IN_KB, /* 14 */ 35 INTEL_HWCONFIG_NUM_THREADS_PER_EU, /* 15 */ 36 INTEL_HWCONFIG_TOTAL_VS_THREADS, /* 16 */ 37 INTEL_HWCONFIG_TOTAL_GS_THREADS, /* 17 */ 38 INTEL_HWCONFIG_TOTAL_HS_THREADS, /* 18 */ 39 INTEL_HWCONFIG_TOTAL_DS_THREADS, /* 19 */ 40 INTEL_HWCONFIG_TOTAL_VS_THREADS_POCS, /* 20 */ 41 INTEL_HWCONFIG_TOTAL_PS_THREADS, /* 21 */ 42 INTEL_HWCONFIG_MAX_FILL_RATE, /* 22 */ 43 INTEL_HWCONFIG_MAX_RCS, /* 23 */ 44 INTEL_HWCONFIG_MAX_CCS, /* 24 */ 45 INTEL_HWCONFIG_MAX_VCS, /* 25 */ 46 INTEL_HWCONFIG_MAX_VECS, /* 26 */ 47 INTEL_HWCONFIG_MAX_COPY_CS, /* 27 */ 48 /* URB Size might be configurable by UMD in certain platforms */ 49 INTEL_HWCONFIG_URB_SIZE_IN_KB, /* 28 */ 50 INTEL_HWCONFIG_MIN_VS_URB_ENTRIES, /* 29 */ 51 INTEL_HWCONFIG_MAX_VS_URB_ENTRIES, /* 30 */ 52 INTEL_HWCONFIG_MIN_PCS_URB_ENTRIES, /* 31 */ 53 INTEL_HWCONFIG_MAX_PCS_URB_ENTRIES, /* 32 */ 54 INTEL_HWCONFIG_MIN_HS_URB_ENTRIES, /* 33 */ 55 INTEL_HWCONFIG_MAX_HS_URB_ENTRIES, /* 34 */ 56 INTEL_HWCONFIG_MIN_GS_URB_ENTRIES, /* 35 */ 57 INTEL_HWCONFIG_MAX_GS_URB_ENTRIES, /* 36 */ 58 INTEL_HWCONFIG_MIN_DS_URB_ENTRIES, /* 37 */ 59 INTEL_HWCONFIG_MAX_DS_URB_ENTRIES, /* 38 */ 60 INTEL_HWCONFIG_PUSH_CONSTANT_URB_RESERVED_SIZE, /* 39 */ 61 INTEL_HWCONFIG_POCS_PUSH_CONSTANT_URB_RESERVED_SIZE, /* 40 */ 62 INTEL_HWCONFIG_URB_REGION_ALIGNMENT_SIZE_IN_BYTES, /* 41 */ 63 INTEL_HWCONFIG_URB_ALLOCATION_SIZE_UNITS_IN_BYTES, /* 42 */ 64 INTEL_HWCONFIG_MAX_URB_SIZE_CCS_IN_BYTES, /* 43 */ 65 INTEL_HWCONFIG_VS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT, /* 44 */ 66 INTEL_HWCONFIG_DS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT, /* 45 */ 67 INTEL_HWCONFIG_NUM_RT_STACKS_PER_DSS, /* 46 */ 68 __INTEL_HWCONFIG_MAX 69 }; 70 71 #define INTEL_HWCONFIG_MAX (__INTEL_HWCONFIG_MAX - 1) 72 73 enum { 74 INTEL_HWCONFIG_MEMORY_TYPE_LPDDR4 = 0, 75 INTEL_HWCONFIG_MEMORY_TYPE_LPDDR5, 76 INTEL_HWCONFIG_MEMORY_TYPE_HBM2, 77 INTEL_HWCONFIG_MEMORY_TYPE_HBM2e, 78 INTEL_HWCONFIG_MEMORY_TYPE_GDDR6, 79 }; 80 81 #define INTEL_HWCONFIG_CACHE_TYPE_L3 BIT(0) 82 #define INTEL_HWCONFIG_CACHE_TYPE_LLC BIT(1) 83 #define INTEL_HWCONFIG_CACHE_TYPE_EDRAM BIT(2) 84 85 #endif /* _INTEL_HWCONFIG_TYPES_H_ */ 86