1 /*
2 * Copyright (c) 2020-2021, Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 //!
23 //! \file decode_hevc_packet_back_end_m12.cpp
24 //! \brief Defines the interface for hevc back end decode packet of M12
25 //!
26 #include "decode_hevc_packet_back_end_m12.h"
27 #include "decode_utils.h"
28 #include "decode_hevc_pipeline.h"
29 #include "decode_hevc_basic_feature.h"
30 #include "decode_status_report_defs.h"
31 #include "mos_solo_generic.h"
32 #include "decode_status_report_defs.h"
33 #include "decode_resource_auto_lock.h"
34 #include "hal_oca_interface.h"
35 #include "mhw_vdbox_vdenc_g12_X.h"
36 #include "decode_hevc_picture_packet_m12.h"
37
38 namespace decode
39 {
40
Init()41 MOS_STATUS HevcDecodeBackEndPktM12::Init()
42 {
43 DECODE_FUNC_CALL();
44
45 PERF_UTILITY_AUTO(__FUNCTION__, PERF_DECODE, PERF_LEVEL_HAL);
46
47 DECODE_CHK_STATUS(HevcDecodeBackEndPktXe_M_Base::Init());
48
49 DecodeSubPacket* subPacket = m_hevcPipeline->GetSubPacket(DecodePacketId(m_hevcPipeline, hevcTileSubPacketId));
50 m_tilePkt = dynamic_cast<HevcDecodeTilePktM12*>(subPacket);
51 DECODE_CHK_NULL(m_tilePkt);
52
53 return MOS_STATUS_SUCCESS;
54 }
55
Submit(MOS_COMMAND_BUFFER * cmdBuffer,uint8_t packetPhase)56 MOS_STATUS HevcDecodeBackEndPktM12::Submit(
57 MOS_COMMAND_BUFFER* cmdBuffer,
58 uint8_t packetPhase)
59 {
60 DECODE_FUNC_CALL();
61
62 PERF_UTILITY_AUTO(__FUNCTION__, PERF_DECODE, PERF_LEVEL_HAL);
63
64 DECODE_CHK_NULL(cmdBuffer);
65 DECODE_CHK_NULL(m_hwInterface);
66
67 DECODE_CHK_STATUS(m_picturePkt->SetPhase(m_phase));
68
69 DECODE_CHK_STATUS(Mos_Solo_PreProcessDecode(m_osInterface, &m_hevcBasicFeature->m_destSurface));
70
71 DECODE_CHK_STATUS(m_miInterface->SetWatchdogTimerThreshold(m_hevcBasicFeature->m_width, m_hevcBasicFeature->m_height, false));
72
73 if (IsPrologRequired())
74 {
75 DECODE_CHK_STATUS(AddForceWakeup(*cmdBuffer));
76 DECODE_CHK_STATUS(SendPrologWithFrameTracking(*cmdBuffer, true));
77 }
78
79 auto mmioRegisters = m_hwInterface->GetMfxInterface()->GetMmioRegisters(MHW_VDBOX_NODE_1);
80 HalOcaInterface::On1stLevelBBStart(*cmdBuffer, *m_osInterface->pOsContext, m_osInterface->CurrentGpuContextHandle, *m_miInterface, *mmioRegisters);
81
82 DECODE_CHK_STATUS(m_miInterface->AddWatchdogTimerStopCmd(cmdBuffer));
83 auto scalability = m_hevcPipeline->GetMediaScalability();
84 DECODE_CHK_STATUS(scalability->SyncPipe(syncAllPipes, 0, cmdBuffer));
85
86 HevcDecodePicPktM12 *picturePkt = dynamic_cast<HevcDecodePicPktM12 *>(m_picturePkt);
87 DECODE_CHK_NULL(picturePkt);
88 DECODE_CHK_STATUS(picturePkt->ValidateCabacStreamOutSize(*cmdBuffer));
89
90 if (m_hevcPipeline->IsShortFormat())
91 {
92 MOS_RESOURCE* osResource = nullptr;
93 uint32_t offset = 0;
94
95 DECODE_CHK_STATUS(m_statusReport->GetAddress(decode::DecodeStatusReportType::HucErrorStatusMask, osResource, offset));
96
97 // Check HuC_STATUS bit15, HW continue if bit15 > 0, otherwise send COND BB END cmd.
98 uint32_t compareOperation = mhw_mi_g12_X::MI_CONDITIONAL_BATCH_BUFFER_END_CMD::COMPARE_OPERATION_MADGREATERTHANIDD;
99 DECODE_CHK_STATUS(m_hwInterface->SendCondBbEndCmd(
100 osResource, offset, 0, false, false, compareOperation, cmdBuffer));
101 }
102
103 DECODE_CHK_STATUS(m_miInterface->AddWatchdogTimerStartCmd(cmdBuffer));
104 DECODE_CHK_STATUS(PackPictureLevelCmds(*cmdBuffer));
105
106 HalOcaInterface::On1stLevelBBEnd(*cmdBuffer, *m_osInterface);
107
108 DECODE_CHK_STATUS(m_allocator->SyncOnResource(&m_hevcBasicFeature->m_resDataBuffer, false));
109
110 DECODE_CHK_STATUS(Mos_Solo_PostProcessDecode(m_osInterface, &m_hevcBasicFeature->m_destSurface));
111
112 #if USE_CODECHAL_DEBUG_TOOL
113 DECODE_CHK_STATUS(DumpSecondaryCommandBuffer(*cmdBuffer));
114 #endif
115
116 return MOS_STATUS_SUCCESS;
117 }
118
VdMemoryFlush(MOS_COMMAND_BUFFER & cmdBuffer)119 MOS_STATUS HevcDecodeBackEndPktM12::VdMemoryFlush(MOS_COMMAND_BUFFER &cmdBuffer)
120 {
121 MHW_MI_VD_CONTROL_STATE_PARAMS vdCtrlParam;
122 MOS_ZeroMemory(&vdCtrlParam, sizeof(MHW_MI_VD_CONTROL_STATE_PARAMS));
123 vdCtrlParam.memoryImplicitFlush = true;
124
125 MhwMiInterfaceG12* miInterfaceG12 = dynamic_cast<MhwMiInterfaceG12*>(m_miInterface);
126 DECODE_CHK_NULL(miInterfaceG12);
127 DECODE_CHK_STATUS(miInterfaceG12->AddMiVdControlStateCmd(&cmdBuffer, &vdCtrlParam));
128
129 return MOS_STATUS_SUCCESS;
130 }
131
VdPipelineFlush(MOS_COMMAND_BUFFER & cmdBuffer)132 MOS_STATUS HevcDecodeBackEndPktM12::VdPipelineFlush(MOS_COMMAND_BUFFER & cmdBuffer)
133 {
134 DECODE_FUNC_CALL();
135
136 MHW_VDBOX_VD_PIPE_FLUSH_PARAMS_G12 vdpipeFlushParams;
137 MOS_ZeroMemory(&vdpipeFlushParams, sizeof(vdpipeFlushParams));
138 vdpipeFlushParams.Flags.bWaitDoneHEVC = 1;
139 vdpipeFlushParams.Flags.bFlushHEVC = 1;
140 vdpipeFlushParams.Flags.bWaitDoneVDCmdMsgParser = 1;
141 DECODE_CHK_STATUS(m_vdencInterface->AddVdPipelineFlushCmd(
142 &cmdBuffer, (MHW_VDBOX_VD_PIPE_FLUSH_PARAMS*)&vdpipeFlushParams));
143
144 return MOS_STATUS_SUCCESS;
145 }
146
VdScalabPipeUnLock(MOS_COMMAND_BUFFER & cmdBuffer)147 MOS_STATUS HevcDecodeBackEndPktM12::VdScalabPipeUnLock(MOS_COMMAND_BUFFER &cmdBuffer)
148 {
149 MHW_MI_VD_CONTROL_STATE_PARAMS vdCtrlParam;
150 MOS_ZeroMemory(&vdCtrlParam, sizeof(MHW_MI_VD_CONTROL_STATE_PARAMS));
151 vdCtrlParam.scalableModePipeUnlock = true;
152
153 MhwMiInterfaceG12* miInterfaceG12 = dynamic_cast<MhwMiInterfaceG12*>(m_miInterface);
154 DECODE_CHK_NULL(miInterfaceG12);
155 DECODE_CHK_STATUS(miInterfaceG12->AddMiVdControlStateCmd(&cmdBuffer, &vdCtrlParam));
156
157 return MOS_STATUS_SUCCESS;
158 }
159
PackPictureLevelCmds(MOS_COMMAND_BUFFER & cmdBuffer)160 MOS_STATUS HevcDecodeBackEndPktM12::PackPictureLevelCmds(MOS_COMMAND_BUFFER &cmdBuffer)
161 {
162 PERF_UTILITY_AUTO(__FUNCTION__, PERF_DECODE, PERF_LEVEL_HAL);
163
164 DECODE_CHK_STATUS(StartStatusReport(statusReportMfx, &cmdBuffer));
165
166 DECODE_CHK_STATUS(m_picturePkt->Execute(cmdBuffer));
167
168 // add tile coding command
169 DECODE_CHK_STATUS(m_tilePkt->Execute(cmdBuffer, m_hevcPipeline->GetCurrentPipe()));
170
171 DECODE_CHK_STATUS(VdMemoryFlush(cmdBuffer));
172 DECODE_CHK_STATUS(VdScalabPipeUnLock(cmdBuffer));
173 DECODE_CHK_STATUS(ReadVdboxId(cmdBuffer));
174 DECODE_CHK_STATUS(VdPipelineFlush(cmdBuffer));
175 DECODE_CHK_STATUS(MiFlush(cmdBuffer));
176
177 auto scalability = m_hevcPipeline->GetMediaScalability();
178 DECODE_CHK_STATUS(scalability->SyncPipe(syncOnePipeWaitOthers, 0, &cmdBuffer));
179
180 if (m_hevcPipeline->IsFirstPipe())
181 {
182 DECODE_CHK_STATUS(EndStatusReport(statusReportMfx, &cmdBuffer));
183 DECODE_CHK_STATUS(UpdateStatusReport(statusReportGlobalCount, &cmdBuffer));
184 }
185 else
186 {
187 DECODE_CHK_STATUS(NullHW::StopPredicate(m_miInterface, &cmdBuffer));
188 }
189 DECODE_CHK_STATUS(MiFlush(cmdBuffer));
190
191 DECODE_CHK_STATUS(m_miInterface->AddMiBatchBufferEnd(&cmdBuffer, nullptr));
192
193 return MOS_STATUS_SUCCESS;
194 }
195
196 }
197
198