1 /*
2 * Copyright (c) 2021, Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 //!
23 //! \file codec_hw_next.cpp
24 //! \brief This modules implements HW interface layer to be used on all platforms on all operating systems/DDIs, across CODECHAL components.
25 //!
26 #include "codec_hw_next.h"
27 #include "codechal_setting.h"
28
CodechalHwInterfaceNext(PMOS_INTERFACE osInterface,CODECHAL_FUNCTION codecFunction,MhwInterfacesNext * mhwInterfacesNext,bool disableScalability)29 CodechalHwInterfaceNext::CodechalHwInterfaceNext(
30 PMOS_INTERFACE osInterface,
31 CODECHAL_FUNCTION codecFunction,
32 MhwInterfacesNext *mhwInterfacesNext,
33 bool disableScalability)
34 {
35 CODEC_HW_FUNCTION_ENTER;
36
37 m_avpItf = mhwInterfacesNext->m_avpItf;
38 m_vdencItf = mhwInterfacesNext->m_vdencItf;
39 m_hucItf = mhwInterfacesNext->m_hucItf;
40 m_miItf = mhwInterfacesNext->m_miItf;
41 m_hcpItf = mhwInterfacesNext->m_hcpItf;
42
43 // Remove legacy mhw sub interfaces.
44 m_cpInterface = mhwInterfacesNext->m_cpInterface;
45 m_mfxInterface = mhwInterfacesNext->m_mfxInterface;
46 m_vdencInterface = mhwInterfacesNext->m_vdencInterface;
47 m_hcpInterface = mhwInterfacesNext->m_hcpInterface;
48 }
49
GetAvpStateCommandSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize,PMHW_VDBOX_STATE_CMDSIZE_PARAMS params)50 MOS_STATUS CodechalHwInterfaceNext::GetAvpStateCommandSize(
51 uint32_t mode,
52 uint32_t *commandsSize,
53 uint32_t *patchListSize,
54 PMHW_VDBOX_STATE_CMDSIZE_PARAMS params)
55 {
56 CODEC_HW_FUNCTION_ENTER;
57
58 //calculate AVP related commands size
59 uint32_t avpCommandsSize = 0;
60 uint32_t avpPatchListSize = 0;
61 uint32_t cpCmdsize = 0;
62 uint32_t cpPatchListSize = 0;
63
64 if (m_avpItf)
65 {
66 CODEC_HW_CHK_STATUS_RETURN(m_avpItf->GetAvpStateCmdSize(
67 (uint32_t *)&avpCommandsSize,
68 (uint32_t *)&avpPatchListSize,
69 params));
70 }
71
72 if (m_cpInterface != nullptr)
73 {
74 m_cpInterface->GetCpStateLevelCmdSize(cpCmdsize, cpPatchListSize);
75 }
76
77 //Calc final command size
78 *commandsSize = avpCommandsSize + cpCmdsize;
79 *patchListSize = avpPatchListSize + cpPatchListSize;
80
81 return MOS_STATUS_SUCCESS;
82 }
83
GetAvpPrimitiveCommandSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize)84 MOS_STATUS CodechalHwInterfaceNext::GetAvpPrimitiveCommandSize(
85 uint32_t mode,
86 uint32_t *commandsSize,
87 uint32_t *patchListSize)
88 {
89 CODEC_HW_FUNCTION_ENTER;
90
91 //calculate AVP related commands size
92 MHW_VDBOX_STATE_CMDSIZE_PARAMS stateCmdSizeParams;
93
94 if (mode == CODECHAL_DECODE_MODE_AV1VLD)
95 {
96 stateCmdSizeParams.bDecodeInUse = true;
97 }
98
99 uint32_t avpCommandsSize = 0;
100 uint32_t avpPatchListSize = 0;
101 uint32_t cpCmdsize = 0;
102 uint32_t cpPatchListSize = 0;
103
104 if (m_avpItf)
105 {
106 CODEC_HW_CHK_STATUS_RETURN(m_avpItf->GetAvpPrimitiveCmdSize(
107 (uint32_t*)&avpCommandsSize,
108 (uint32_t*)&avpPatchListSize,
109 &stateCmdSizeParams));
110 }
111
112 if (m_cpInterface)
113 {
114 m_cpInterface->GetCpSliceLevelCmdSize(cpCmdsize, cpPatchListSize);
115 }
116
117 //Calc final command size
118 *commandsSize = avpCommandsSize + cpCmdsize;
119 *patchListSize = avpPatchListSize + cpPatchListSize;
120
121 return MOS_STATUS_SUCCESS;
122 }
123
SetCacheabilitySettings(MHW_MEMORY_OBJECT_CONTROL_PARAMS cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_END_CODEC])124 MOS_STATUS CodechalHwInterfaceNext::SetCacheabilitySettings(
125 MHW_MEMORY_OBJECT_CONTROL_PARAMS cacheabilitySettings[MOS_CODEC_RESOURCE_USAGE_END_CODEC])
126 {
127 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
128
129 CODEC_HW_FUNCTION_ENTER;
130
131 // Next step: replace with new mhw sub interfaces, including vdenc, mfx, hcp.
132 /**********************************************************************/
133 if (m_mfxInterface)
134 {
135 CODEC_HW_CHK_STATUS_RETURN(m_mfxInterface->SetCacheabilitySettings(cacheabilitySettings));
136 }
137 if (m_hcpInterface)
138 {
139 CODEC_HW_CHK_STATUS_RETURN(m_hcpInterface->SetCacheabilitySettings(cacheabilitySettings));
140 }
141 if (m_vdencInterface)
142 {
143 CODEC_HW_CHK_STATUS_RETURN(m_vdencInterface->SetCacheabilitySettings(cacheabilitySettings));
144 }
145 /* */
146
147 /* New Mhw sub interfaces usage */
148 if (m_avpItf)
149 {
150 CODEC_HW_CHK_STATUS_RETURN(m_avpItf->SetCacheabilitySettings(cacheabilitySettings));
151 }
152 if (m_hcpItf)
153 {
154 CODEC_HW_CHK_STATUS_RETURN(m_hcpItf->SetCacheabilitySettings(cacheabilitySettings));
155 }
156
157 return eStatus;
158 }
159
GetHucStateCommandSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize,PMHW_VDBOX_STATE_CMDSIZE_PARAMS params)160 MOS_STATUS CodechalHwInterfaceNext::GetHucStateCommandSize(
161 uint32_t mode,
162 uint32_t* commandsSize,
163 uint32_t* patchListSize,
164 PMHW_VDBOX_STATE_CMDSIZE_PARAMS params)
165
166 {
167 MHW_FUNCTION_ENTER;
168
169 uint32_t maxSize = 0;
170 uint32_t patchListMaxSize = 0;
171 uint32_t standard = CodecHal_GetStandardFromMode(mode);
172 uint32_t numSlices = 1;
173 uint32_t numStoreDataImm = 1;
174 uint32_t numStoreReg = 1;
175
176 MHW_MI_CHK_NULL(commandsSize);
177 MHW_MI_CHK_NULL(patchListSize);
178 MHW_MI_CHK_NULL(params);
179
180 if(params->uNumStoreDataImm)
181 {
182 numStoreDataImm = params->uNumStoreDataImm;
183 }
184 if(params->uNumStoreReg)
185 {
186 numStoreReg = params->uNumStoreReg;
187 }
188
189 if (mode == CODECHAL_DECODE_MODE_HEVCVLD && params->bShortFormat)
190 {
191 numSlices = CODECHAL_HEVC_MAX_NUM_SLICES_LVL_6;
192 numStoreDataImm = 2;
193 numStoreReg = 2;
194
195 maxSize +=
196 2 * m_miItf->MHW_GETSIZE_F(MI_CONDITIONAL_BATCH_BUFFER_END)();
197
198 patchListMaxSize +=
199 2 * PATCH_LIST_COMMAND(MI_CONDITIONAL_BATCH_BUFFER_END_CMD);
200 }
201 else if (standard == CODECHAL_CENC)
202 {
203 numStoreDataImm = 3;
204 numStoreReg = 3;
205
206 maxSize +=
207 m_miItf->MHW_GETSIZE_F(MI_FLUSH_DW)() * 2 +
208 m_miItf->MHW_GETSIZE_F(MI_BATCH_BUFFER_END)();
209
210 patchListMaxSize +=
211 PATCH_LIST_COMMAND(MI_FLUSH_DW_CMD) * 2;
212
213 }
214 else if (mode == CODECHAL_ENCODE_MODE_VP9)
215 {
216 // for huc status 2 register and semaphore signal and reset
217 numStoreDataImm = 3;
218
219 maxSize +=
220 m_miItf->MHW_GETSIZE_F(MI_BATCH_BUFFER_END)() +
221 m_miItf->MHW_GETSIZE_F(MI_FLUSH_DW)();
222
223 patchListMaxSize +=
224 PATCH_LIST_COMMAND(MI_FLUSH_DW_CMD);
225 }
226 else if (mode == CODECHAL_ENCODE_MODE_AVC)
227 {
228 numStoreDataImm = 2;
229 numStoreReg = 2;
230
231 maxSize +=
232 2 * m_miItf->MHW_GETSIZE_F(MI_CONDITIONAL_BATCH_BUFFER_END)();
233
234 patchListMaxSize +=
235 2 * PATCH_LIST_COMMAND(MI_CONDITIONAL_BATCH_BUFFER_END_CMD);
236 }
237
238 maxSize +=
239 m_hucItf->MHW_GETSIZE_F(HUC_PIPE_MODE_SELECT)() +
240 m_hucItf->MHW_GETSIZE_F(HUC_IMEM_STATE)() +
241 m_hucItf->MHW_GETSIZE_F(HUC_DMEM_STATE)() +
242 m_hucItf->MHW_GETSIZE_F(HUC_VIRTUAL_ADDR_STATE)() +
243 m_hucItf->MHW_GETSIZE_F(HUC_IND_OBJ_BASE_ADDR_STATE)() +
244 numSlices * m_hucItf->MHW_GETSIZE_F(HUC_STREAM_OBJECT)() +
245 numSlices * m_hucItf->MHW_GETSIZE_F(HUC_START)() +
246 numStoreDataImm * m_miItf->MHW_GETSIZE_F(MI_STORE_DATA_IMM)() +
247 numStoreReg * m_miItf->MHW_GETSIZE_F(MI_STORE_REGISTER_MEM)();
248
249 if(params->uNumMfxWait)
250 {
251 maxSize +=
252 params->uNumMfxWait * m_miItf->MHW_GETSIZE_F(MFX_WAIT)();
253 }
254
255 patchListMaxSize +=
256 PATCH_LIST_COMMAND(HUC_PIPE_MODE_SELECT_CMD) +
257 PATCH_LIST_COMMAND(HUC_IMEM_STATE_CMD) +
258 PATCH_LIST_COMMAND(HUC_DMEM_STATE_CMD) +
259 PATCH_LIST_COMMAND(HUC_VIRTUAL_ADDR_STATE_CMD) +
260 PATCH_LIST_COMMAND(HUC_IND_OBJ_BASE_ADDR_STATE_CMD) +
261 numSlices * PATCH_LIST_COMMAND(HUC_STREAM_OBJECT_CMD) +
262 numSlices * PATCH_LIST_COMMAND(HUC_START_CMD) +
263 numStoreDataImm * PATCH_LIST_COMMAND(MI_STORE_DATA_IMM_CMD) +
264 numStoreReg * PATCH_LIST_COMMAND(MI_STORE_REGISTER_MEM_CMD);
265
266 if(params->uNumAddConBBEnd)
267 {
268 maxSize +=
269 params->uNumAddConBBEnd * m_miItf->MHW_GETSIZE_F(MI_CONDITIONAL_BATCH_BUFFER_END)();
270
271 patchListMaxSize +=
272 params->uNumAddConBBEnd * PATCH_LIST_COMMAND(MI_CONDITIONAL_BATCH_BUFFER_END_CMD);
273 }
274 if(params->uNumMiCopy)
275 {
276 maxSize +=
277 params->uNumMiCopy * m_miItf->MHW_GETSIZE_F(MI_COPY_MEM_MEM)();
278
279 patchListMaxSize +=
280 params->uNumMiCopy * PATCH_LIST_COMMAND(MI_COPY_MEM_MEM_CMD);
281 }
282 if(params->uNumMiFlush)
283 {
284 maxSize +=
285 params->uNumMiFlush * m_miItf->MHW_GETSIZE_F(MI_FLUSH_DW)();
286
287 patchListMaxSize +=
288 params->uNumMiFlush * PATCH_LIST_COMMAND(MI_FLUSH_DW_CMD);
289 }
290
291 if (params->bHucDummyStream || params->bPerformHucStreamOut)
292 {
293 uint32_t dummyTimes = params->bPerformHucStreamOut ? 2: 1;
294 for (uint32_t i = 0; i < dummyTimes; i++)
295 {
296 maxSize +=
297 m_hucItf->MHW_GETSIZE_F(HUC_PIPE_MODE_SELECT)() +
298 m_hucItf->MHW_GETSIZE_F(HUC_IMEM_STATE)() +
299 m_hucItf->MHW_GETSIZE_F(HUC_DMEM_STATE)() +
300 m_hucItf->MHW_GETSIZE_F(HUC_VIRTUAL_ADDR_STATE)() +
301 m_hucItf->MHW_GETSIZE_F(HUC_IND_OBJ_BASE_ADDR_STATE)() +
302 m_hucItf->MHW_GETSIZE_F(HUC_STREAM_OBJECT)() +
303 m_hucItf->MHW_GETSIZE_F(HUC_START)() +
304 m_miItf->MHW_GETSIZE_F(MI_FLUSH_DW)();
305
306 patchListMaxSize +=
307 PATCH_LIST_COMMAND(HUC_PIPE_MODE_SELECT_CMD) +
308 PATCH_LIST_COMMAND(HUC_IMEM_STATE_CMD) +
309 PATCH_LIST_COMMAND(HUC_DMEM_STATE_CMD) +
310 PATCH_LIST_COMMAND(HUC_VIRTUAL_ADDR_STATE_CMD) +
311 PATCH_LIST_COMMAND(HUC_IND_OBJ_BASE_ADDR_STATE_CMD) +
312 PATCH_LIST_COMMAND(HUC_STREAM_OBJECT_CMD) +
313 PATCH_LIST_COMMAND(HUC_START_CMD) +
314 PATCH_LIST_COMMAND(MI_FLUSH_DW_CMD);
315 }
316 if (params->bPerformHucStreamOut)
317 {
318 maxSize +=
319 m_hucItf->MHW_GETSIZE_F(HUC_PIPE_MODE_SELECT)() +
320 m_hucItf->MHW_GETSIZE_F(HUC_IND_OBJ_BASE_ADDR_STATE)() +
321 m_hucItf->MHW_GETSIZE_F(HUC_STREAM_OBJECT)() +
322 4 * m_miItf->MHW_GETSIZE_F(MI_FLUSH_DW)();
323
324 patchListMaxSize +=
325 PATCH_LIST_COMMAND(HUC_PIPE_MODE_SELECT_CMD) +
326 PATCH_LIST_COMMAND(HUC_IND_OBJ_BASE_ADDR_STATE_CMD) +
327 PATCH_LIST_COMMAND(HUC_STREAM_OBJECT_CMD) +
328 4 * PATCH_LIST_COMMAND(MI_FLUSH_DW_CMD);
329 }
330 }
331
332 *commandsSize = maxSize;
333 *patchListSize = patchListMaxSize;
334
335 return MOS_STATUS_SUCCESS;
336 }
337