1 /*
2 * Copyright (c) 2020-2021, Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 //!
23 //! \file     mhw_mi_itf.h
24 //! \brief    MHW MI interface common base
25 //! \details
26 //!
27 
28 #ifndef __MHW_MI_ITF_H__
29 #define __MHW_MI_ITF_H__
30 
31 #include "mhw_itf.h"
32 #include "mhw_mi_cmdpar.h"
33 #include "mhw_cp_interface.h"
34 
35 #define _MI_CMD_DEF(DEF)                  \
36     DEF(MI_SEMAPHORE_WAIT);               \
37     DEF(MI_CONDITIONAL_BATCH_BUFFER_END); \
38     DEF(PIPE_CONTROL);                    \
39     DEF(MI_BATCH_BUFFER_START);           \
40     DEF(MI_SET_PREDICATE);                \
41     DEF(MI_STORE_REGISTER_MEM);           \
42     DEF(MI_LOAD_REGISTER_MEM);            \
43     DEF(MI_LOAD_REGISTER_IMM);            \
44     DEF(MI_LOAD_REGISTER_REG);            \
45     DEF(MI_FORCE_WAKEUP);                 \
46     DEF(VD_CONTROL_STATE);                \
47     DEF(MEDIA_STATE_FLUSH);               \
48     DEF(MI_BATCH_BUFFER_END);             \
49     DEF(MI_FLUSH_DW);                     \
50     DEF(MI_NOOP);                         \
51     DEF(MI_ATOMIC);                       \
52     DEF(MI_STORE_DATA_IMM);               \
53     DEF(MI_MATH);                         \
54     DEF(MI_COPY_MEM_MEM);                 \
55     DEF(MFX_WAIT)
56 
57 namespace mhw
58 {
59 namespace mi
60 {
61 class Itf
62 {
63 public:
64     class ParSetting
65     {
66     public:
67         virtual ~ParSetting() = default;
68 
69         _MI_CMD_DEF(_MHW_SETPAR_DEF);
70     };
71 
72     virtual ~Itf() = default;
73 
74     virtual MOS_STATUS SetWatchdogTimerThreshold(uint32_t frameWidth, uint32_t frameHeight, bool isEncoder) = 0;
75 
76     virtual MOS_STATUS SetWatchdogTimerRegisterOffset(MOS_GPU_CONTEXT gpuContext) = 0;
77 
78     virtual MOS_STATUS AddWatchdogTimerStartCmd(PMOS_COMMAND_BUFFER cmdBuffer) = 0;
79 
80     virtual MOS_STATUS AddWatchdogTimerStopCmd(PMOS_COMMAND_BUFFER cmdBuffer) = 0;
81 
82     virtual MOS_STATUS AddMiBatchBufferEnd(PMOS_COMMAND_BUFFER cmdBuffer, PMHW_BATCH_BUFFER batchBuffer) = 0;
83 
84     virtual MHW_MI_MMIOREGISTERS* GetMmioRegisters() = 0;
85 
86     virtual MOS_STATUS SetCpInterface(MhwCpInterface *cpInterface) = 0;
87 
88     virtual uint32_t GetMmioInterfaces(MHW_MMIO_REGISTER_OPCODE opCode) = 0;
89 
90     _MI_CMD_DEF(_MHW_CMD_ALL_DEF_FOR_ITF);
91 };
92 }  // namespace mi
93 }  // namespace mhw
94 
95 #endif  // __MHW_MI_ITF_H__
96