1 /* 2 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan. 3 */ 4 #ifndef _ASM_POWERPC_PPC_ASM_H 5 #define _ASM_POWERPC_PPC_ASM_H 6 7 #include <linux/stringify.h> 8 #include <asm/asm-compat.h> 9 #include <asm/processor.h> 10 #include <asm/ppc-opcode.h> 11 #include <asm/firmware.h> 12 #include <asm/feature-fixups.h> 13 14 #ifdef __ASSEMBLY__ 15 16 #define SZL (BITS_PER_LONG/8) 17 18 /* 19 * Macros for storing registers into and loading registers from 20 * exception frames. 21 */ 22 #ifdef __powerpc64__ 23 #define SAVE_GPR(n, base) std n,GPR0+8*(n)(base) 24 #define REST_GPR(n, base) ld n,GPR0+8*(n)(base) 25 #define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base) 26 #define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base) 27 #else 28 #define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base) 29 #define REST_GPR(n, base) lwz n,GPR0+4*(n)(base) 30 #define SAVE_NVGPRS(base) stmw 13, GPR0+4*13(base) 31 #define REST_NVGPRS(base) lmw 13, GPR0+4*13(base) 32 #endif 33 34 #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base) 35 #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base) 36 #define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base) 37 #define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base) 38 #define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base) 39 #define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base) 40 #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base) 41 #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base) 42 43 #define SAVE_FPR(n, base) stfd n,8*TS_FPRWIDTH*(n)(base) 44 #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base) 45 #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base) 46 #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base) 47 #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base) 48 #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base) 49 #define REST_FPR(n, base) lfd n,8*TS_FPRWIDTH*(n)(base) 50 #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base) 51 #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base) 52 #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base) 53 #define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base) 54 #define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base) 55 56 #define SAVE_VR(n,b,base) li b,16*(n); stvx n,base,b 57 #define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base) 58 #define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base) 59 #define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base) 60 #define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base) 61 #define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base) 62 #define REST_VR(n,b,base) li b,16*(n); lvx n,base,b 63 #define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base) 64 #define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base) 65 #define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base) 66 #define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base) 67 #define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base) 68 69 #ifdef __BIG_ENDIAN__ 70 #define STXVD2X_ROT(n,b,base) STXVD2X(n,b,base) 71 #define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base) 72 #else 73 #define STXVD2X_ROT(n,b,base) XXSWAPD(n,n); \ 74 STXVD2X(n,b,base); \ 75 XXSWAPD(n,n) 76 77 #define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base); \ 78 XXSWAPD(n,n) 79 #endif 80 /* Save the lower 32 VSRs in the thread VSR region */ 81 #define SAVE_VSR(n,b,base) li b,16*(n); STXVD2X_ROT(n,R##base,R##b) 82 #define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base) 83 #define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base) 84 #define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base) 85 #define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base) 86 #define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base) 87 #define REST_VSR(n,b,base) li b,16*(n); LXVD2X_ROT(n,R##base,R##b) 88 #define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base) 89 #define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base) 90 #define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base) 91 #define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base) 92 #define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base) 93 94 /* 95 * b = base register for addressing, o = base offset from register of 1st EVR 96 * n = first EVR, s = scratch 97 */ 98 #define SAVE_EVR(n,s,b,o) evmergehi s,s,n; stw s,o+4*(n)(b) 99 #define SAVE_2EVRS(n,s,b,o) SAVE_EVR(n,s,b,o); SAVE_EVR(n+1,s,b,o) 100 #define SAVE_4EVRS(n,s,b,o) SAVE_2EVRS(n,s,b,o); SAVE_2EVRS(n+2,s,b,o) 101 #define SAVE_8EVRS(n,s,b,o) SAVE_4EVRS(n,s,b,o); SAVE_4EVRS(n+4,s,b,o) 102 #define SAVE_16EVRS(n,s,b,o) SAVE_8EVRS(n,s,b,o); SAVE_8EVRS(n+8,s,b,o) 103 #define SAVE_32EVRS(n,s,b,o) SAVE_16EVRS(n,s,b,o); SAVE_16EVRS(n+16,s,b,o) 104 #define REST_EVR(n,s,b,o) lwz s,o+4*(n)(b); evmergelo n,s,n 105 #define REST_2EVRS(n,s,b,o) REST_EVR(n,s,b,o); REST_EVR(n+1,s,b,o) 106 #define REST_4EVRS(n,s,b,o) REST_2EVRS(n,s,b,o); REST_2EVRS(n+2,s,b,o) 107 #define REST_8EVRS(n,s,b,o) REST_4EVRS(n,s,b,o); REST_4EVRS(n+4,s,b,o) 108 #define REST_16EVRS(n,s,b,o) REST_8EVRS(n,s,b,o); REST_8EVRS(n+8,s,b,o) 109 #define REST_32EVRS(n,s,b,o) REST_16EVRS(n,s,b,o); REST_16EVRS(n+16,s,b,o) 110 111 /* Macros to adjust thread priority for hardware multithreading */ 112 #define HMT_VERY_LOW or 31,31,31 # very low priority 113 #define HMT_LOW or 1,1,1 114 #define HMT_MEDIUM_LOW or 6,6,6 # medium low priority 115 #define HMT_MEDIUM or 2,2,2 116 #define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority 117 #define HMT_HIGH or 3,3,3 118 #define HMT_EXTRA_HIGH or 7,7,7 # power7 only 119 120 #ifdef CONFIG_PPC64 121 #define ULONG_SIZE 8 122 #else 123 #define ULONG_SIZE 4 124 #endif 125 #define __VCPU_GPR(n) (VCPU_GPRS + (n * ULONG_SIZE)) 126 #define VCPU_GPR(n) __VCPU_GPR(__REG_##n) 127 128 #ifdef __KERNEL__ 129 130 /* 131 * We use __powerpc64__ here because we want the compat VDSO to use the 32-bit 132 * version below in the else case of the ifdef. 133 */ 134 #ifdef __powerpc64__ 135 136 #define STACKFRAMESIZE 256 137 #define __STK_REG(i) (112 + ((i)-14)*8) 138 #define STK_REG(i) __STK_REG(__REG_##i) 139 140 #ifdef PPC64_ELF_ABI_v2 141 #define STK_GOT 24 142 #define __STK_PARAM(i) (32 + ((i)-3)*8) 143 #else 144 #define STK_GOT 40 145 #define __STK_PARAM(i) (48 + ((i)-3)*8) 146 #endif 147 #define STK_PARAM(i) __STK_PARAM(__REG_##i) 148 149 #ifdef PPC64_ELF_ABI_v2 150 151 #define _GLOBAL(name) \ 152 .align 2 ; \ 153 .type name,@function; \ 154 .globl name; \ 155 name: 156 157 #define _GLOBAL_TOC(name) \ 158 .align 2 ; \ 159 .type name,@function; \ 160 .globl name; \ 161 name: \ 162 0: addis r2,r12,(.TOC.-0b)@ha; \ 163 addi r2,r2,(.TOC.-0b)@l; \ 164 .localentry name,.-name 165 166 #define DOTSYM(a) a 167 168 #else 169 170 #define XGLUE(a,b) a##b 171 #define GLUE(a,b) XGLUE(a,b) 172 173 #define _GLOBAL(name) \ 174 .align 2 ; \ 175 .globl name; \ 176 .globl GLUE(.,name); \ 177 .pushsection ".opd","aw"; \ 178 name: \ 179 .quad GLUE(.,name); \ 180 .quad .TOC.@tocbase; \ 181 .quad 0; \ 182 .popsection; \ 183 .type GLUE(.,name),@function; \ 184 GLUE(.,name): 185 186 #define _GLOBAL_TOC(name) _GLOBAL(name) 187 188 #define DOTSYM(a) GLUE(.,a) 189 190 #endif 191 192 #else /* 32-bit */ 193 194 #define _ENTRY(n) \ 195 .globl n; \ 196 n: 197 198 #define _GLOBAL(n) \ 199 .stabs __stringify(n:F-1),N_FUN,0,0,n;\ 200 .globl n; \ 201 n: 202 203 #define _GLOBAL_TOC(name) _GLOBAL(name) 204 205 #define DOTSYM(a) a 206 207 #endif 208 209 /* 210 * __kprobes (the C annotation) puts the symbol into the .kprobes.text 211 * section, which gets emitted at the end of regular text. 212 * 213 * _ASM_NOKPROBE_SYMBOL and NOKPROBE_SYMBOL just adds the symbol to 214 * a blacklist. The former is for core kprobe functions/data, the 215 * latter is for those that incdentially must be excluded from probing 216 * and allows them to be linked at more optimal location within text. 217 */ 218 #ifdef CONFIG_KPROBES 219 #define _ASM_NOKPROBE_SYMBOL(entry) \ 220 .pushsection "_kprobe_blacklist","aw"; \ 221 PPC_LONG (entry) ; \ 222 .popsection 223 #else 224 #define _ASM_NOKPROBE_SYMBOL(entry) 225 #endif 226 227 #define FUNC_START(name) _GLOBAL(name) 228 #define FUNC_END(name) 229 230 /* 231 * LOAD_REG_IMMEDIATE(rn, expr) 232 * Loads the value of the constant expression 'expr' into register 'rn' 233 * using immediate instructions only. Use this when it's important not 234 * to reference other data (i.e. on ppc64 when the TOC pointer is not 235 * valid) and when 'expr' is a constant or absolute address. 236 * 237 * LOAD_REG_ADDR(rn, name) 238 * Loads the address of label 'name' into register 'rn'. Use this when 239 * you don't particularly need immediate instructions only, but you need 240 * the whole address in one register (e.g. it's a structure address and 241 * you want to access various offsets within it). On ppc32 this is 242 * identical to LOAD_REG_IMMEDIATE. 243 * 244 * LOAD_REG_ADDR_PIC(rn, name) 245 * Loads the address of label 'name' into register 'run'. Use this when 246 * the kernel doesn't run at the linked or relocated address. Please 247 * note that this macro will clobber the lr register. 248 * 249 * LOAD_REG_ADDRBASE(rn, name) 250 * ADDROFF(name) 251 * LOAD_REG_ADDRBASE loads part of the address of label 'name' into 252 * register 'rn'. ADDROFF(name) returns the remainder of the address as 253 * a constant expression. ADDROFF(name) is a signed expression < 16 bits 254 * in size, so is suitable for use directly as an offset in load and store 255 * instructions. Use this when loading/storing a single word or less as: 256 * LOAD_REG_ADDRBASE(rX, name) 257 * ld rY,ADDROFF(name)(rX) 258 */ 259 260 /* Be careful, this will clobber the lr register. */ 261 #define LOAD_REG_ADDR_PIC(reg, name) \ 262 bl 0f; \ 263 0: mflr reg; \ 264 addis reg,reg,(name - 0b)@ha; \ 265 addi reg,reg,(name - 0b)@l; 266 267 #if defined(__powerpc64__) && defined(HAVE_AS_ATHIGH) 268 #define __AS_ATHIGH high 269 #else 270 #define __AS_ATHIGH h 271 #endif 272 273 .macro __LOAD_REG_IMMEDIATE_32 r, x 274 .if (\x) >= 0x8000 || (\x) < -0x8000 275 lis \r, (\x)@__AS_ATHIGH 276 .if (\x) & 0xffff != 0 277 ori \r, \r, (\x)@l 278 .endif 279 .else 280 li \r, (\x)@l 281 .endif 282 .endm 283 284 .macro __LOAD_REG_IMMEDIATE r, x 285 .if (\x) >= 0x80000000 || (\x) < -0x80000000 286 __LOAD_REG_IMMEDIATE_32 \r, (\x) >> 32 287 sldi \r, \r, 32 288 .if (\x) & 0xffff0000 != 0 289 oris \r, \r, (\x)@__AS_ATHIGH 290 .endif 291 .if (\x) & 0xffff != 0 292 ori \r, \r, (\x)@l 293 .endif 294 .else 295 __LOAD_REG_IMMEDIATE_32 \r, \x 296 .endif 297 .endm 298 299 #ifdef __powerpc64__ 300 301 #define LOAD_REG_IMMEDIATE(reg, expr) __LOAD_REG_IMMEDIATE reg, expr 302 303 #define LOAD_REG_IMMEDIATE_SYM(reg, tmp, expr) \ 304 lis tmp, (expr)@highest; \ 305 lis reg, (expr)@__AS_ATHIGH; \ 306 ori tmp, tmp, (expr)@higher; \ 307 ori reg, reg, (expr)@l; \ 308 rldimi reg, tmp, 32, 0 309 310 #define LOAD_REG_ADDR(reg,name) \ 311 ld reg,name@got(r2) 312 313 #define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name) 314 #define ADDROFF(name) 0 315 316 /* offsets for stack frame layout */ 317 #define LRSAVE 16 318 319 #else /* 32-bit */ 320 321 #define LOAD_REG_IMMEDIATE(reg, expr) __LOAD_REG_IMMEDIATE_32 reg, expr 322 323 #define LOAD_REG_IMMEDIATE_SYM(reg,expr) \ 324 lis reg,(expr)@ha; \ 325 addi reg,reg,(expr)@l; 326 327 #define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE_SYM(reg, name) 328 329 #define LOAD_REG_ADDRBASE(reg, name) lis reg,name@ha 330 #define ADDROFF(name) name@l 331 332 /* offsets for stack frame layout */ 333 #define LRSAVE 4 334 335 #endif 336 337 /* various errata or part fixups */ 338 #if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E) 339 #define MFTB(dest) \ 340 90: mfspr dest, SPRN_TBRL; \ 341 BEGIN_FTR_SECTION_NESTED(96); \ 342 cmpwi dest,0; \ 343 beq- 90b; \ 344 END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96) 345 #else 346 #define MFTB(dest) MFTBL(dest) 347 #endif 348 349 #ifdef CONFIG_PPC_8xx 350 #define MFTBL(dest) mftb dest 351 #define MFTBU(dest) mftbu dest 352 #else 353 #define MFTBL(dest) mfspr dest, SPRN_TBRL 354 #define MFTBU(dest) mfspr dest, SPRN_TBRU 355 #endif 356 357 #ifndef CONFIG_SMP 358 #define TLBSYNC 359 #else 360 #define TLBSYNC tlbsync; sync 361 #endif 362 363 #ifdef CONFIG_PPC64 364 #define MTOCRF(FXM, RS) \ 365 BEGIN_FTR_SECTION_NESTED(848); \ 366 mtcrf (FXM), RS; \ 367 FTR_SECTION_ELSE_NESTED(848); \ 368 mtocrf (FXM), RS; \ 369 ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_NOEXECUTE, 848) 370 #endif 371 372 /* 373 * This instruction is not implemented on the PPC 603 or 601; however, on 374 * the 403GCX and 405GP tlbia IS defined and tlbie is not. 375 * All of these instructions exist in the 8xx, they have magical powers, 376 * and they must be used. 377 */ 378 379 #if !defined(CONFIG_4xx) && !defined(CONFIG_PPC_8xx) 380 #define tlbia \ 381 li r4,1024; \ 382 mtctr r4; \ 383 lis r4,KERNELBASE@h; \ 384 .machine push; \ 385 .machine "power4"; \ 386 0: tlbie r4; \ 387 .machine pop; \ 388 addi r4,r4,0x1000; \ 389 bdnz 0b 390 #endif 391 392 393 #ifdef CONFIG_IBM440EP_ERR42 394 #define PPC440EP_ERR42 isync 395 #else 396 #define PPC440EP_ERR42 397 #endif 398 399 /* The following stops all load and store data streams associated with stream 400 * ID (ie. streams created explicitly). The embedded and server mnemonics for 401 * dcbt are different so this must only be used for server. 402 */ 403 #define DCBT_BOOK3S_STOP_ALL_STREAM_IDS(scratch) \ 404 lis scratch,0x60000000@h; \ 405 dcbt 0,scratch,0b01010 406 407 /* 408 * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them 409 * keep the address intact to be compatible with code shared with 410 * 32-bit classic. 411 * 412 * On the other hand, I find it useful to have them behave as expected 413 * by their name (ie always do the addition) on 64-bit BookE 414 */ 415 #if defined(CONFIG_BOOKE) && !defined(CONFIG_PPC64) 416 #define toreal(rd) 417 #define fromreal(rd) 418 419 /* 420 * We use addis to ensure compatibility with the "classic" ppc versions of 421 * these macros, which use rs = 0 to get the tophys offset in rd, rather than 422 * converting the address in r0, and so this version has to do that too 423 * (i.e. set register rd to 0 when rs == 0). 424 */ 425 #define tophys(rd,rs) \ 426 addis rd,rs,0 427 428 #define tovirt(rd,rs) \ 429 addis rd,rs,0 430 431 #elif defined(CONFIG_PPC64) 432 #define toreal(rd) /* we can access c000... in real mode */ 433 #define fromreal(rd) 434 435 #define tophys(rd,rs) \ 436 clrldi rd,rs,2 437 438 #define tovirt(rd,rs) \ 439 rotldi rd,rs,16; \ 440 ori rd,rd,((KERNELBASE>>48)&0xFFFF);\ 441 rotldi rd,rd,48 442 #else 443 #define toreal(rd) tophys(rd,rd) 444 #define fromreal(rd) tovirt(rd,rd) 445 446 #define tophys(rd, rs) addis rd, rs, -PAGE_OFFSET@h 447 #define tovirt(rd, rs) addis rd, rs, PAGE_OFFSET@h 448 #endif 449 450 #ifdef CONFIG_PPC_BOOK3S_64 451 #define MTMSRD(r) mtmsrd r 452 #define MTMSR_EERI(reg) mtmsrd reg,1 453 #else 454 #define MTMSRD(r) mtmsr r 455 #define MTMSR_EERI(reg) mtmsr reg 456 #endif 457 458 #endif /* __KERNEL__ */ 459 460 /* The boring bits... */ 461 462 /* Condition Register Bit Fields */ 463 464 #define cr0 0 465 #define cr1 1 466 #define cr2 2 467 #define cr3 3 468 #define cr4 4 469 #define cr5 5 470 #define cr6 6 471 #define cr7 7 472 473 474 /* 475 * General Purpose Registers (GPRs) 476 * 477 * The lower case r0-r31 should be used in preference to the upper 478 * case R0-R31 as they provide more error checking in the assembler. 479 * Use R0-31 only when really nessesary. 480 */ 481 482 #define r0 %r0 483 #define r1 %r1 484 #define r2 %r2 485 #define r3 %r3 486 #define r4 %r4 487 #define r5 %r5 488 #define r6 %r6 489 #define r7 %r7 490 #define r8 %r8 491 #define r9 %r9 492 #define r10 %r10 493 #define r11 %r11 494 #define r12 %r12 495 #define r13 %r13 496 #define r14 %r14 497 #define r15 %r15 498 #define r16 %r16 499 #define r17 %r17 500 #define r18 %r18 501 #define r19 %r19 502 #define r20 %r20 503 #define r21 %r21 504 #define r22 %r22 505 #define r23 %r23 506 #define r24 %r24 507 #define r25 %r25 508 #define r26 %r26 509 #define r27 %r27 510 #define r28 %r28 511 #define r29 %r29 512 #define r30 %r30 513 #define r31 %r31 514 515 516 /* Floating Point Registers (FPRs) */ 517 518 #define fr0 0 519 #define fr1 1 520 #define fr2 2 521 #define fr3 3 522 #define fr4 4 523 #define fr5 5 524 #define fr6 6 525 #define fr7 7 526 #define fr8 8 527 #define fr9 9 528 #define fr10 10 529 #define fr11 11 530 #define fr12 12 531 #define fr13 13 532 #define fr14 14 533 #define fr15 15 534 #define fr16 16 535 #define fr17 17 536 #define fr18 18 537 #define fr19 19 538 #define fr20 20 539 #define fr21 21 540 #define fr22 22 541 #define fr23 23 542 #define fr24 24 543 #define fr25 25 544 #define fr26 26 545 #define fr27 27 546 #define fr28 28 547 #define fr29 29 548 #define fr30 30 549 #define fr31 31 550 551 /* AltiVec Registers (VPRs) */ 552 553 #define v0 0 554 #define v1 1 555 #define v2 2 556 #define v3 3 557 #define v4 4 558 #define v5 5 559 #define v6 6 560 #define v7 7 561 #define v8 8 562 #define v9 9 563 #define v10 10 564 #define v11 11 565 #define v12 12 566 #define v13 13 567 #define v14 14 568 #define v15 15 569 #define v16 16 570 #define v17 17 571 #define v18 18 572 #define v19 19 573 #define v20 20 574 #define v21 21 575 #define v22 22 576 #define v23 23 577 #define v24 24 578 #define v25 25 579 #define v26 26 580 #define v27 27 581 #define v28 28 582 #define v29 29 583 #define v30 30 584 #define v31 31 585 586 /* VSX Registers (VSRs) */ 587 588 #define vs0 0 589 #define vs1 1 590 #define vs2 2 591 #define vs3 3 592 #define vs4 4 593 #define vs5 5 594 #define vs6 6 595 #define vs7 7 596 #define vs8 8 597 #define vs9 9 598 #define vs10 10 599 #define vs11 11 600 #define vs12 12 601 #define vs13 13 602 #define vs14 14 603 #define vs15 15 604 #define vs16 16 605 #define vs17 17 606 #define vs18 18 607 #define vs19 19 608 #define vs20 20 609 #define vs21 21 610 #define vs22 22 611 #define vs23 23 612 #define vs24 24 613 #define vs25 25 614 #define vs26 26 615 #define vs27 27 616 #define vs28 28 617 #define vs29 29 618 #define vs30 30 619 #define vs31 31 620 #define vs32 32 621 #define vs33 33 622 #define vs34 34 623 #define vs35 35 624 #define vs36 36 625 #define vs37 37 626 #define vs38 38 627 #define vs39 39 628 #define vs40 40 629 #define vs41 41 630 #define vs42 42 631 #define vs43 43 632 #define vs44 44 633 #define vs45 45 634 #define vs46 46 635 #define vs47 47 636 #define vs48 48 637 #define vs49 49 638 #define vs50 50 639 #define vs51 51 640 #define vs52 52 641 #define vs53 53 642 #define vs54 54 643 #define vs55 55 644 #define vs56 56 645 #define vs57 57 646 #define vs58 58 647 #define vs59 59 648 #define vs60 60 649 #define vs61 61 650 #define vs62 62 651 #define vs63 63 652 653 /* SPE Registers (EVPRs) */ 654 655 #define evr0 0 656 #define evr1 1 657 #define evr2 2 658 #define evr3 3 659 #define evr4 4 660 #define evr5 5 661 #define evr6 6 662 #define evr7 7 663 #define evr8 8 664 #define evr9 9 665 #define evr10 10 666 #define evr11 11 667 #define evr12 12 668 #define evr13 13 669 #define evr14 14 670 #define evr15 15 671 #define evr16 16 672 #define evr17 17 673 #define evr18 18 674 #define evr19 19 675 #define evr20 20 676 #define evr21 21 677 #define evr22 22 678 #define evr23 23 679 #define evr24 24 680 #define evr25 25 681 #define evr26 26 682 #define evr27 27 683 #define evr28 28 684 #define evr29 29 685 #define evr30 30 686 #define evr31 31 687 688 /* some stab codes */ 689 #define N_FUN 36 690 #define N_RSYM 64 691 #define N_SLINE 68 692 #define N_SO 100 693 694 #define RFSCV .long 0x4c0000a4 695 696 /* 697 * Create an endian fixup trampoline 698 * 699 * This starts with a "tdi 0,0,0x48" instruction which is 700 * essentially a "trap never", and thus akin to a nop. 701 * 702 * The opcode for this instruction read with the wrong endian 703 * however results in a b . + 8 704 * 705 * So essentially we use that trick to execute the following 706 * trampoline in "reverse endian" if we are running with the 707 * MSR_LE bit set the "wrong" way for whatever endianness the 708 * kernel is built for. 709 */ 710 711 #ifdef CONFIG_PPC_BOOK3E 712 #define FIXUP_ENDIAN 713 #else 714 /* 715 * This version may be used in HV or non-HV context. 716 * MSR[EE] must be disabled. 717 */ 718 #define FIXUP_ENDIAN \ 719 tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \ 720 b 191f; /* Skip trampoline if endian is good */ \ 721 .long 0xa600607d; /* mfmsr r11 */ \ 722 .long 0x01006b69; /* xori r11,r11,1 */ \ 723 .long 0x00004039; /* li r10,0 */ \ 724 .long 0x6401417d; /* mtmsrd r10,1 */ \ 725 .long 0x05009f42; /* bcl 20,31,$+4 */ \ 726 .long 0xa602487d; /* mflr r10 */ \ 727 .long 0x14004a39; /* addi r10,r10,20 */ \ 728 .long 0xa6035a7d; /* mtsrr0 r10 */ \ 729 .long 0xa6037b7d; /* mtsrr1 r11 */ \ 730 .long 0x2400004c; /* rfid */ \ 731 191: 732 733 /* 734 * This version that may only be used with MSR[HV]=1 735 * - Does not clear MSR[RI], so more robust. 736 * - Slightly smaller and faster. 737 */ 738 #define FIXUP_ENDIAN_HV \ 739 tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \ 740 b 191f; /* Skip trampoline if endian is good */ \ 741 .long 0xa600607d; /* mfmsr r11 */ \ 742 .long 0x01006b69; /* xori r11,r11,1 */ \ 743 .long 0x05009f42; /* bcl 20,31,$+4 */ \ 744 .long 0xa602487d; /* mflr r10 */ \ 745 .long 0x14004a39; /* addi r10,r10,20 */ \ 746 .long 0xa64b5a7d; /* mthsrr0 r10 */ \ 747 .long 0xa64b7b7d; /* mthsrr1 r11 */ \ 748 .long 0x2402004c; /* hrfid */ \ 749 191: 750 751 #endif /* !CONFIG_PPC_BOOK3E */ 752 753 #endif /* __ASSEMBLY__ */ 754 755 /* 756 * Helper macro for exception table entries 757 */ 758 #define EX_TABLE(_fault, _target) \ 759 stringify_in_c(.section __ex_table,"a";)\ 760 stringify_in_c(.balign 4;) \ 761 stringify_in_c(.long (_fault) - . ;) \ 762 stringify_in_c(.long (_target) - . ;) \ 763 stringify_in_c(.previous) 764 765 #ifdef CONFIG_PPC_FSL_BOOK3E 766 #define BTB_FLUSH(reg) \ 767 lis reg,BUCSR_INIT@h; \ 768 ori reg,reg,BUCSR_INIT@l; \ 769 mtspr SPRN_BUCSR,reg; \ 770 isync; 771 #else 772 #define BTB_FLUSH(reg) 773 #endif /* CONFIG_PPC_FSL_BOOK3E */ 774 775 #endif /* _ASM_POWERPC_PPC_ASM_H */ 776