1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (C) 2015-2018 Etnaviv Project
4 */
5
6 #ifndef __ETNAVIV_GPU_H__
7 #define __ETNAVIV_GPU_H__
8
9 #include "etnaviv_cmdbuf.h"
10 #include "etnaviv_gem.h"
11 #include "etnaviv_mmu.h"
12 #include "etnaviv_drv.h"
13
14 struct etnaviv_gem_submit;
15 struct etnaviv_vram_mapping;
16
17 struct etnaviv_chip_identity {
18 u32 model;
19 u32 revision;
20 u32 product_id;
21 u32 customer_id;
22 u32 eco_id;
23
24 /* Supported feature fields. */
25 u32 features;
26
27 /* Supported minor feature fields. */
28 u32 minor_features0;
29 u32 minor_features1;
30 u32 minor_features2;
31 u32 minor_features3;
32 u32 minor_features4;
33 u32 minor_features5;
34 u32 minor_features6;
35 u32 minor_features7;
36 u32 minor_features8;
37 u32 minor_features9;
38 u32 minor_features10;
39 u32 minor_features11;
40
41 /* Number of streams supported. */
42 u32 stream_count;
43
44 /* Total number of temporary registers per thread. */
45 u32 register_max;
46
47 /* Maximum number of threads. */
48 u32 thread_count;
49
50 /* Number of shader cores. */
51 u32 shader_core_count;
52
53 /* Size of the vertex cache. */
54 u32 vertex_cache_size;
55
56 /* Number of entries in the vertex output buffer. */
57 u32 vertex_output_buffer_size;
58
59 /* Number of pixel pipes. */
60 u32 pixel_pipes;
61
62 /* Number of instructions. */
63 u32 instruction_count;
64
65 /* Number of constants. */
66 u32 num_constants;
67
68 /* Buffer size */
69 u32 buffer_size;
70
71 /* Number of varyings */
72 u8 varyings_count;
73 };
74
75 enum etnaviv_sec_mode {
76 ETNA_SEC_NONE = 0,
77 ETNA_SEC_KERNEL,
78 ETNA_SEC_TZ
79 };
80
81 struct etnaviv_event {
82 struct dma_fence *fence;
83 struct etnaviv_gem_submit *submit;
84
85 void (*sync_point)(struct etnaviv_gpu *gpu, struct etnaviv_event *event);
86 };
87
88 struct etnaviv_cmdbuf_suballoc;
89 struct regulator;
90 struct clk;
91
92 #define ETNA_NR_EVENTS 30
93
94 struct etnaviv_gpu {
95 struct drm_device *drm;
96 struct thermal_cooling_device *cooling;
97 struct device *dev;
98 struct mutex lock;
99 struct etnaviv_chip_identity identity;
100 enum etnaviv_sec_mode sec_mode;
101 struct workqueue_struct *wq;
102 struct drm_gpu_scheduler sched;
103 bool initialized;
104
105 /* 'ring'-buffer: */
106 struct etnaviv_cmdbuf buffer;
107 int exec_state;
108
109 /* event management: */
110 DECLARE_BITMAP(event_bitmap, ETNA_NR_EVENTS);
111 struct etnaviv_event event[ETNA_NR_EVENTS];
112 struct completion event_free;
113 spinlock_t event_spinlock;
114
115 u32 idle_mask;
116
117 /* Fencing support */
118 struct mutex fence_lock;
119 struct idr fence_idr;
120 u32 next_fence;
121 u32 completed_fence;
122 wait_queue_head_t fence_event;
123 u64 fence_context;
124 spinlock_t fence_spinlock;
125
126 /* worker for handling 'sync' points: */
127 struct work_struct sync_point_work;
128 int sync_point_event;
129
130 /* hang detection */
131 u32 hangcheck_dma_addr;
132
133 void __iomem *mmio;
134 int irq;
135
136 struct etnaviv_iommu_context *mmu_context;
137 unsigned int flush_seq;
138
139 /* Power Control: */
140 struct clk *clk_bus;
141 struct clk *clk_reg;
142 struct clk *clk_core;
143 struct clk *clk_shader;
144
145 unsigned int freq_scale;
146 unsigned long base_rate_core;
147 unsigned long base_rate_shader;
148 };
149
gpu_write(struct etnaviv_gpu * gpu,u32 reg,u32 data)150 static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data)
151 {
152 writel(data, gpu->mmio + reg);
153 }
154
gpu_read(struct etnaviv_gpu * gpu,u32 reg)155 static inline u32 gpu_read(struct etnaviv_gpu *gpu, u32 reg)
156 {
157 return readl(gpu->mmio + reg);
158 }
159
160 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value);
161
162 int etnaviv_gpu_init(struct etnaviv_gpu *gpu);
163 bool etnaviv_fill_identity_from_hwdb(struct etnaviv_gpu *gpu);
164
165 #ifdef CONFIG_DEBUG_FS
166 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m);
167 #endif
168
169 void etnaviv_gpu_recover_hang(struct etnaviv_gpu *gpu);
170 void etnaviv_gpu_retire(struct etnaviv_gpu *gpu);
171 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
172 u32 fence, struct drm_etnaviv_timespec *timeout);
173 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
174 struct etnaviv_gem_object *etnaviv_obj,
175 struct drm_etnaviv_timespec *timeout);
176 struct dma_fence *etnaviv_gpu_submit(struct etnaviv_gem_submit *submit);
177 int etnaviv_gpu_pm_get_sync(struct etnaviv_gpu *gpu);
178 void etnaviv_gpu_pm_put(struct etnaviv_gpu *gpu);
179 int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms);
180 void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch);
181
182 extern struct platform_driver etnaviv_gpu_driver;
183
184 #endif /* __ETNAVIV_GPU_H__ */
185