1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2020 Intel Corporation
4 */
5 #include <linux/kernel.h>
6
7 #include <drm/drm_atomic_helper.h>
8 #include <drm/drm_atomic_uapi.h>
9 #include <drm/drm_damage_helper.h>
10 #include <drm/drm_plane_helper.h>
11 #include <drm/drm_fourcc.h>
12
13 #include "intel_atomic.h"
14 #include "intel_atomic_plane.h"
15 #include "intel_cursor.h"
16 #include "intel_display_types.h"
17 #include "intel_display.h"
18 #include "intel_fb.h"
19
20 #include "intel_frontbuffer.h"
21 #include "intel_pm.h"
22 #include "intel_psr.h"
23 #include "intel_sprite.h"
24
25 /* Cursor formats */
26 static const u32 intel_cursor_formats[] = {
27 DRM_FORMAT_ARGB8888,
28 };
29
30 static const u64 cursor_format_modifiers[] = {
31 DRM_FORMAT_MOD_LINEAR,
32 DRM_FORMAT_MOD_INVALID
33 };
34
intel_cursor_base(const struct intel_plane_state * plane_state)35 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
36 {
37 struct drm_i915_private *dev_priv =
38 to_i915(plane_state->uapi.plane->dev);
39 const struct drm_framebuffer *fb = plane_state->hw.fb;
40 const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
41 u32 base;
42
43 if (INTEL_INFO(dev_priv)->display.cursor_needs_physical)
44 base = sg_dma_address(obj->mm.pages->sgl);
45 else
46 base = intel_plane_ggtt_offset(plane_state);
47
48 return base + plane_state->view.color_plane[0].offset;
49 }
50
intel_cursor_position(const struct intel_plane_state * plane_state)51 static u32 intel_cursor_position(const struct intel_plane_state *plane_state)
52 {
53 int x = plane_state->uapi.dst.x1;
54 int y = plane_state->uapi.dst.y1;
55 u32 pos = 0;
56
57 if (x < 0) {
58 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
59 x = -x;
60 }
61 pos |= x << CURSOR_X_SHIFT;
62
63 if (y < 0) {
64 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
65 y = -y;
66 }
67 pos |= y << CURSOR_Y_SHIFT;
68
69 return pos;
70 }
71
intel_cursor_size_ok(const struct intel_plane_state * plane_state)72 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
73 {
74 const struct drm_mode_config *config =
75 &plane_state->uapi.plane->dev->mode_config;
76 int width = drm_rect_width(&plane_state->uapi.dst);
77 int height = drm_rect_height(&plane_state->uapi.dst);
78
79 return width > 0 && width <= config->cursor_width &&
80 height > 0 && height <= config->cursor_height;
81 }
82
intel_cursor_check_surface(struct intel_plane_state * plane_state)83 static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
84 {
85 struct drm_i915_private *dev_priv =
86 to_i915(plane_state->uapi.plane->dev);
87 unsigned int rotation = plane_state->hw.rotation;
88 int src_x, src_y;
89 u32 offset;
90 int ret;
91
92 ret = intel_plane_compute_gtt(plane_state);
93 if (ret)
94 return ret;
95
96 if (!plane_state->uapi.visible)
97 return 0;
98
99 src_x = plane_state->uapi.src.x1 >> 16;
100 src_y = plane_state->uapi.src.y1 >> 16;
101
102 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
103 offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
104 plane_state, 0);
105
106 if (src_x != 0 || src_y != 0) {
107 drm_dbg_kms(&dev_priv->drm,
108 "Arbitrary cursor panning not supported\n");
109 return -EINVAL;
110 }
111
112 /*
113 * Put the final coordinates back so that the src
114 * coordinate checks will see the right values.
115 */
116 drm_rect_translate_to(&plane_state->uapi.src,
117 src_x << 16, src_y << 16);
118
119 /* ILK+ do this automagically in hardware */
120 if (HAS_GMCH(dev_priv) && rotation & DRM_MODE_ROTATE_180) {
121 const struct drm_framebuffer *fb = plane_state->hw.fb;
122 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
123 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
124
125 offset += (src_h * src_w - 1) * fb->format->cpp[0];
126 }
127
128 plane_state->view.color_plane[0].offset = offset;
129 plane_state->view.color_plane[0].x = src_x;
130 plane_state->view.color_plane[0].y = src_y;
131
132 return 0;
133 }
134
intel_check_cursor(struct intel_crtc_state * crtc_state,struct intel_plane_state * plane_state)135 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
136 struct intel_plane_state *plane_state)
137 {
138 const struct drm_framebuffer *fb = plane_state->hw.fb;
139 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
140 const struct drm_rect src = plane_state->uapi.src;
141 const struct drm_rect dst = plane_state->uapi.dst;
142 int ret;
143
144 if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) {
145 drm_dbg_kms(&i915->drm, "cursor cannot be tiled\n");
146 return -EINVAL;
147 }
148
149 ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
150 DRM_PLANE_HELPER_NO_SCALING,
151 DRM_PLANE_HELPER_NO_SCALING,
152 true);
153 if (ret)
154 return ret;
155
156 /* Use the unclipped src/dst rectangles, which we program to hw */
157 plane_state->uapi.src = src;
158 plane_state->uapi.dst = dst;
159
160 ret = intel_cursor_check_surface(plane_state);
161 if (ret)
162 return ret;
163
164 if (!plane_state->uapi.visible)
165 return 0;
166
167 ret = intel_plane_check_src_coordinates(plane_state);
168 if (ret)
169 return ret;
170
171 return 0;
172 }
173
174 static unsigned int
i845_cursor_max_stride(struct intel_plane * plane,u32 pixel_format,u64 modifier,unsigned int rotation)175 i845_cursor_max_stride(struct intel_plane *plane,
176 u32 pixel_format, u64 modifier,
177 unsigned int rotation)
178 {
179 return 2048;
180 }
181
i845_cursor_ctl_crtc(const struct intel_crtc_state * crtc_state)182 static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
183 {
184 u32 cntl = 0;
185
186 if (crtc_state->gamma_enable)
187 cntl |= CURSOR_GAMMA_ENABLE;
188
189 return cntl;
190 }
191
i845_cursor_ctl(const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state)192 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
193 const struct intel_plane_state *plane_state)
194 {
195 return CURSOR_ENABLE |
196 CURSOR_FORMAT_ARGB |
197 CURSOR_STRIDE(plane_state->view.color_plane[0].stride);
198 }
199
i845_cursor_size_ok(const struct intel_plane_state * plane_state)200 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
201 {
202 int width = drm_rect_width(&plane_state->uapi.dst);
203
204 /*
205 * 845g/865g are only limited by the width of their cursors,
206 * the height is arbitrary up to the precision of the register.
207 */
208 return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
209 }
210
i845_check_cursor(struct intel_crtc_state * crtc_state,struct intel_plane_state * plane_state)211 static int i845_check_cursor(struct intel_crtc_state *crtc_state,
212 struct intel_plane_state *plane_state)
213 {
214 const struct drm_framebuffer *fb = plane_state->hw.fb;
215 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
216 int ret;
217
218 ret = intel_check_cursor(crtc_state, plane_state);
219 if (ret)
220 return ret;
221
222 /* if we want to turn off the cursor ignore width and height */
223 if (!fb)
224 return 0;
225
226 /* Check for which cursor types we support */
227 if (!i845_cursor_size_ok(plane_state)) {
228 drm_dbg_kms(&i915->drm,
229 "Cursor dimension %dx%d not supported\n",
230 drm_rect_width(&plane_state->uapi.dst),
231 drm_rect_height(&plane_state->uapi.dst));
232 return -EINVAL;
233 }
234
235 drm_WARN_ON(&i915->drm, plane_state->uapi.visible &&
236 plane_state->view.color_plane[0].stride != fb->pitches[0]);
237
238 switch (fb->pitches[0]) {
239 case 256:
240 case 512:
241 case 1024:
242 case 2048:
243 break;
244 default:
245 drm_dbg_kms(&i915->drm, "Invalid cursor stride (%u)\n",
246 fb->pitches[0]);
247 return -EINVAL;
248 }
249
250 plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
251
252 return 0;
253 }
254
i845_update_cursor(struct intel_plane * plane,const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state)255 static void i845_update_cursor(struct intel_plane *plane,
256 const struct intel_crtc_state *crtc_state,
257 const struct intel_plane_state *plane_state)
258 {
259 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
260 u32 cntl = 0, base = 0, pos = 0, size = 0;
261 unsigned long irqflags;
262
263 if (plane_state && plane_state->uapi.visible) {
264 unsigned int width = drm_rect_width(&plane_state->uapi.dst);
265 unsigned int height = drm_rect_height(&plane_state->uapi.dst);
266
267 cntl = plane_state->ctl |
268 i845_cursor_ctl_crtc(crtc_state);
269
270 size = (height << 12) | width;
271
272 base = intel_cursor_base(plane_state);
273 pos = intel_cursor_position(plane_state);
274 }
275
276 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
277
278 /* On these chipsets we can only modify the base/size/stride
279 * whilst the cursor is disabled.
280 */
281 if (plane->cursor.base != base ||
282 plane->cursor.size != size ||
283 plane->cursor.cntl != cntl) {
284 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0);
285 intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base);
286 intel_de_write_fw(dev_priv, CURSIZE, size);
287 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
288 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl);
289
290 plane->cursor.base = base;
291 plane->cursor.size = size;
292 plane->cursor.cntl = cntl;
293 } else {
294 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
295 }
296
297 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
298 }
299
i845_disable_cursor(struct intel_plane * plane,const struct intel_crtc_state * crtc_state)300 static void i845_disable_cursor(struct intel_plane *plane,
301 const struct intel_crtc_state *crtc_state)
302 {
303 i845_update_cursor(plane, crtc_state, NULL);
304 }
305
i845_cursor_get_hw_state(struct intel_plane * plane,enum pipe * pipe)306 static bool i845_cursor_get_hw_state(struct intel_plane *plane,
307 enum pipe *pipe)
308 {
309 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
310 enum intel_display_power_domain power_domain;
311 intel_wakeref_t wakeref;
312 bool ret;
313
314 power_domain = POWER_DOMAIN_PIPE(PIPE_A);
315 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
316 if (!wakeref)
317 return false;
318
319 ret = intel_de_read(dev_priv, CURCNTR(PIPE_A)) & CURSOR_ENABLE;
320
321 *pipe = PIPE_A;
322
323 intel_display_power_put(dev_priv, power_domain, wakeref);
324
325 return ret;
326 }
327
328 static unsigned int
i9xx_cursor_max_stride(struct intel_plane * plane,u32 pixel_format,u64 modifier,unsigned int rotation)329 i9xx_cursor_max_stride(struct intel_plane *plane,
330 u32 pixel_format, u64 modifier,
331 unsigned int rotation)
332 {
333 return plane->base.dev->mode_config.cursor_width * 4;
334 }
335
i9xx_cursor_ctl_crtc(const struct intel_crtc_state * crtc_state)336 static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
337 {
338 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
339 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
340 u32 cntl = 0;
341
342 if (DISPLAY_VER(dev_priv) >= 11)
343 return cntl;
344
345 if (crtc_state->gamma_enable)
346 cntl = MCURSOR_GAMMA_ENABLE;
347
348 if (crtc_state->csc_enable)
349 cntl |= MCURSOR_PIPE_CSC_ENABLE;
350
351 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
352 cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
353
354 return cntl;
355 }
356
i9xx_cursor_ctl(const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state)357 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
358 const struct intel_plane_state *plane_state)
359 {
360 struct drm_i915_private *dev_priv =
361 to_i915(plane_state->uapi.plane->dev);
362 u32 cntl = 0;
363
364 if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv))
365 cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
366
367 switch (drm_rect_width(&plane_state->uapi.dst)) {
368 case 64:
369 cntl |= MCURSOR_MODE_64_ARGB_AX;
370 break;
371 case 128:
372 cntl |= MCURSOR_MODE_128_ARGB_AX;
373 break;
374 case 256:
375 cntl |= MCURSOR_MODE_256_ARGB_AX;
376 break;
377 default:
378 MISSING_CASE(drm_rect_width(&plane_state->uapi.dst));
379 return 0;
380 }
381
382 if (plane_state->hw.rotation & DRM_MODE_ROTATE_180)
383 cntl |= MCURSOR_ROTATE_180;
384
385 return cntl;
386 }
387
i9xx_cursor_size_ok(const struct intel_plane_state * plane_state)388 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
389 {
390 struct drm_i915_private *dev_priv =
391 to_i915(plane_state->uapi.plane->dev);
392 int width = drm_rect_width(&plane_state->uapi.dst);
393 int height = drm_rect_height(&plane_state->uapi.dst);
394
395 if (!intel_cursor_size_ok(plane_state))
396 return false;
397
398 /* Cursor width is limited to a few power-of-two sizes */
399 switch (width) {
400 case 256:
401 case 128:
402 case 64:
403 break;
404 default:
405 return false;
406 }
407
408 /*
409 * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
410 * height from 8 lines up to the cursor width, when the
411 * cursor is not rotated. Everything else requires square
412 * cursors.
413 */
414 if (HAS_CUR_FBC(dev_priv) &&
415 plane_state->hw.rotation & DRM_MODE_ROTATE_0) {
416 if (height < 8 || height > width)
417 return false;
418 } else {
419 if (height != width)
420 return false;
421 }
422
423 return true;
424 }
425
i9xx_check_cursor(struct intel_crtc_state * crtc_state,struct intel_plane_state * plane_state)426 static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
427 struct intel_plane_state *plane_state)
428 {
429 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
430 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
431 const struct drm_framebuffer *fb = plane_state->hw.fb;
432 enum pipe pipe = plane->pipe;
433 int ret;
434
435 ret = intel_check_cursor(crtc_state, plane_state);
436 if (ret)
437 return ret;
438
439 /* if we want to turn off the cursor ignore width and height */
440 if (!fb)
441 return 0;
442
443 /* Check for which cursor types we support */
444 if (!i9xx_cursor_size_ok(plane_state)) {
445 drm_dbg(&dev_priv->drm,
446 "Cursor dimension %dx%d not supported\n",
447 drm_rect_width(&plane_state->uapi.dst),
448 drm_rect_height(&plane_state->uapi.dst));
449 return -EINVAL;
450 }
451
452 drm_WARN_ON(&dev_priv->drm, plane_state->uapi.visible &&
453 plane_state->view.color_plane[0].stride != fb->pitches[0]);
454
455 if (fb->pitches[0] !=
456 drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) {
457 drm_dbg_kms(&dev_priv->drm,
458 "Invalid cursor stride (%u) (cursor width %d)\n",
459 fb->pitches[0],
460 drm_rect_width(&plane_state->uapi.dst));
461 return -EINVAL;
462 }
463
464 /*
465 * There's something wrong with the cursor on CHV pipe C.
466 * If it straddles the left edge of the screen then
467 * moving it away from the edge or disabling it often
468 * results in a pipe underrun, and often that can lead to
469 * dead pipe (constant underrun reported, and it scans
470 * out just a solid color). To recover from that, the
471 * display power well must be turned off and on again.
472 * Refuse the put the cursor into that compromised position.
473 */
474 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
475 plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) {
476 drm_dbg_kms(&dev_priv->drm,
477 "CHV cursor C not allowed to straddle the left screen edge\n");
478 return -EINVAL;
479 }
480
481 plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
482
483 return 0;
484 }
485
i9xx_update_cursor(struct intel_plane * plane,const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state)486 static void i9xx_update_cursor(struct intel_plane *plane,
487 const struct intel_crtc_state *crtc_state,
488 const struct intel_plane_state *plane_state)
489 {
490 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
491 enum pipe pipe = plane->pipe;
492 u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
493 unsigned long irqflags;
494
495 if (plane_state && plane_state->uapi.visible) {
496 int width = drm_rect_width(&plane_state->uapi.dst);
497 int height = drm_rect_height(&plane_state->uapi.dst);
498
499 cntl = plane_state->ctl |
500 i9xx_cursor_ctl_crtc(crtc_state);
501
502 if (width != height)
503 fbc_ctl = CUR_FBC_CTL_EN | (height - 1);
504
505 base = intel_cursor_base(plane_state);
506 pos = intel_cursor_position(plane_state);
507 }
508
509 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
510
511 /*
512 * On some platforms writing CURCNTR first will also
513 * cause CURPOS to be armed by the CURBASE write.
514 * Without the CURCNTR write the CURPOS write would
515 * arm itself. Thus we always update CURCNTR before
516 * CURPOS.
517 *
518 * On other platforms CURPOS always requires the
519 * CURBASE write to arm the update. Additonally
520 * a write to any of the cursor register will cancel
521 * an already armed cursor update. Thus leaving out
522 * the CURBASE write after CURPOS could lead to a
523 * cursor that doesn't appear to move, or even change
524 * shape. Thus we always write CURBASE.
525 *
526 * The other registers are armed by the CURBASE write
527 * except when the plane is getting enabled at which time
528 * the CURCNTR write arms the update.
529 */
530
531 if (DISPLAY_VER(dev_priv) >= 9)
532 skl_write_cursor_wm(plane, crtc_state);
533
534 if (!intel_crtc_needs_modeset(crtc_state))
535 intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, 0);
536
537 if (plane->cursor.base != base ||
538 plane->cursor.size != fbc_ctl ||
539 plane->cursor.cntl != cntl) {
540 if (HAS_CUR_FBC(dev_priv))
541 intel_de_write_fw(dev_priv, CUR_FBC_CTL(pipe),
542 fbc_ctl);
543 intel_de_write_fw(dev_priv, CURCNTR(pipe), cntl);
544 intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
545 intel_de_write_fw(dev_priv, CURBASE(pipe), base);
546
547 plane->cursor.base = base;
548 plane->cursor.size = fbc_ctl;
549 plane->cursor.cntl = cntl;
550 } else {
551 intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
552 intel_de_write_fw(dev_priv, CURBASE(pipe), base);
553 }
554
555 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
556 }
557
i9xx_disable_cursor(struct intel_plane * plane,const struct intel_crtc_state * crtc_state)558 static void i9xx_disable_cursor(struct intel_plane *plane,
559 const struct intel_crtc_state *crtc_state)
560 {
561 i9xx_update_cursor(plane, crtc_state, NULL);
562 }
563
i9xx_cursor_get_hw_state(struct intel_plane * plane,enum pipe * pipe)564 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
565 enum pipe *pipe)
566 {
567 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
568 enum intel_display_power_domain power_domain;
569 intel_wakeref_t wakeref;
570 bool ret;
571 u32 val;
572
573 /*
574 * Not 100% correct for planes that can move between pipes,
575 * but that's only the case for gen2-3 which don't have any
576 * display power wells.
577 */
578 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
579 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
580 if (!wakeref)
581 return false;
582
583 val = intel_de_read(dev_priv, CURCNTR(plane->pipe));
584
585 ret = val & MCURSOR_MODE;
586
587 if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
588 *pipe = plane->pipe;
589 else
590 *pipe = (val & MCURSOR_PIPE_SELECT_MASK) >>
591 MCURSOR_PIPE_SELECT_SHIFT;
592
593 intel_display_power_put(dev_priv, power_domain, wakeref);
594
595 return ret;
596 }
597
intel_cursor_format_mod_supported(struct drm_plane * _plane,u32 format,u64 modifier)598 static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
599 u32 format, u64 modifier)
600 {
601 return modifier == DRM_FORMAT_MOD_LINEAR &&
602 format == DRM_FORMAT_ARGB8888;
603 }
604
605 static int
intel_legacy_cursor_update(struct drm_plane * _plane,struct drm_crtc * _crtc,struct drm_framebuffer * fb,int crtc_x,int crtc_y,unsigned int crtc_w,unsigned int crtc_h,u32 src_x,u32 src_y,u32 src_w,u32 src_h,struct drm_modeset_acquire_ctx * ctx)606 intel_legacy_cursor_update(struct drm_plane *_plane,
607 struct drm_crtc *_crtc,
608 struct drm_framebuffer *fb,
609 int crtc_x, int crtc_y,
610 unsigned int crtc_w, unsigned int crtc_h,
611 u32 src_x, u32 src_y,
612 u32 src_w, u32 src_h,
613 struct drm_modeset_acquire_ctx *ctx)
614 {
615 struct intel_plane *plane = to_intel_plane(_plane);
616 struct intel_crtc *crtc = to_intel_crtc(_crtc);
617 struct intel_plane_state *old_plane_state =
618 to_intel_plane_state(plane->base.state);
619 struct intel_plane_state *new_plane_state;
620 struct intel_crtc_state *crtc_state =
621 to_intel_crtc_state(crtc->base.state);
622 struct intel_crtc_state *new_crtc_state;
623 int ret;
624
625 /*
626 * When crtc is inactive or there is a modeset pending,
627 * wait for it to complete in the slowpath
628 *
629 * FIXME bigjoiner fastpath would be good
630 */
631 if (!crtc_state->hw.active || intel_crtc_needs_modeset(crtc_state) ||
632 crtc_state->update_pipe || crtc_state->bigjoiner)
633 goto slow;
634
635 /*
636 * Don't do an async update if there is an outstanding commit modifying
637 * the plane. This prevents our async update's changes from getting
638 * overridden by a previous synchronous update's state.
639 */
640 if (old_plane_state->uapi.commit &&
641 !try_wait_for_completion(&old_plane_state->uapi.commit->hw_done))
642 goto slow;
643
644 /*
645 * If any parameters change that may affect watermarks,
646 * take the slowpath. Only changing fb or position should be
647 * in the fastpath.
648 */
649 if (old_plane_state->uapi.crtc != &crtc->base ||
650 old_plane_state->uapi.src_w != src_w ||
651 old_plane_state->uapi.src_h != src_h ||
652 old_plane_state->uapi.crtc_w != crtc_w ||
653 old_plane_state->uapi.crtc_h != crtc_h ||
654 !old_plane_state->uapi.fb != !fb)
655 goto slow;
656
657 new_plane_state = to_intel_plane_state(intel_plane_duplicate_state(&plane->base));
658 if (!new_plane_state)
659 return -ENOMEM;
660
661 new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(&crtc->base));
662 if (!new_crtc_state) {
663 ret = -ENOMEM;
664 goto out_free;
665 }
666
667 drm_atomic_set_fb_for_plane(&new_plane_state->uapi, fb);
668
669 new_plane_state->uapi.src_x = src_x;
670 new_plane_state->uapi.src_y = src_y;
671 new_plane_state->uapi.src_w = src_w;
672 new_plane_state->uapi.src_h = src_h;
673 new_plane_state->uapi.crtc_x = crtc_x;
674 new_plane_state->uapi.crtc_y = crtc_y;
675 new_plane_state->uapi.crtc_w = crtc_w;
676 new_plane_state->uapi.crtc_h = crtc_h;
677
678 intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state, crtc);
679
680 ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state,
681 old_plane_state, new_plane_state);
682 if (ret)
683 goto out_free;
684
685 ret = intel_plane_pin_fb(new_plane_state);
686 if (ret)
687 goto out_free;
688
689 intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->hw.fb),
690 ORIGIN_FLIP);
691 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
692 to_intel_frontbuffer(new_plane_state->hw.fb),
693 plane->frontbuffer_bit);
694
695 /* Swap plane state */
696 plane->base.state = &new_plane_state->uapi;
697
698 /*
699 * We cannot swap crtc_state as it may be in use by an atomic commit or
700 * page flip that's running simultaneously. If we swap crtc_state and
701 * destroy the old state, we will cause a use-after-free there.
702 *
703 * Only update active_planes, which is needed for our internal
704 * bookkeeping. Either value will do the right thing when updating
705 * planes atomically. If the cursor was part of the atomic update then
706 * we would have taken the slowpath.
707 */
708 crtc_state->active_planes = new_crtc_state->active_planes;
709
710 if (new_plane_state->uapi.visible)
711 intel_update_plane(plane, crtc_state, new_plane_state);
712 else
713 intel_disable_plane(plane, crtc_state);
714
715 intel_plane_unpin_fb(old_plane_state);
716
717 out_free:
718 if (new_crtc_state)
719 intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi);
720 if (ret)
721 intel_plane_destroy_state(&plane->base, &new_plane_state->uapi);
722 else
723 intel_plane_destroy_state(&plane->base, &old_plane_state->uapi);
724 return ret;
725
726 slow:
727 return drm_atomic_helper_update_plane(&plane->base, &crtc->base, fb,
728 crtc_x, crtc_y, crtc_w, crtc_h,
729 src_x, src_y, src_w, src_h, ctx);
730 }
731
732 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
733 .update_plane = intel_legacy_cursor_update,
734 .disable_plane = drm_atomic_helper_disable_plane,
735 .destroy = intel_plane_destroy,
736 .atomic_duplicate_state = intel_plane_duplicate_state,
737 .atomic_destroy_state = intel_plane_destroy_state,
738 .format_mod_supported = intel_cursor_format_mod_supported,
739 };
740
741 struct intel_plane *
intel_cursor_plane_create(struct drm_i915_private * dev_priv,enum pipe pipe)742 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
743 enum pipe pipe)
744 {
745 struct intel_plane *cursor;
746 int ret, zpos;
747
748 cursor = intel_plane_alloc();
749 if (IS_ERR(cursor))
750 return cursor;
751
752 cursor->pipe = pipe;
753 cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
754 cursor->id = PLANE_CURSOR;
755 cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
756
757 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
758 cursor->max_stride = i845_cursor_max_stride;
759 cursor->update_plane = i845_update_cursor;
760 cursor->disable_plane = i845_disable_cursor;
761 cursor->get_hw_state = i845_cursor_get_hw_state;
762 cursor->check_plane = i845_check_cursor;
763 } else {
764 cursor->max_stride = i9xx_cursor_max_stride;
765 cursor->update_plane = i9xx_update_cursor;
766 cursor->disable_plane = i9xx_disable_cursor;
767 cursor->get_hw_state = i9xx_cursor_get_hw_state;
768 cursor->check_plane = i9xx_check_cursor;
769 }
770
771 cursor->cursor.base = ~0;
772 cursor->cursor.cntl = ~0;
773
774 if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
775 cursor->cursor.size = ~0;
776
777 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
778 0, &intel_cursor_plane_funcs,
779 intel_cursor_formats,
780 ARRAY_SIZE(intel_cursor_formats),
781 cursor_format_modifiers,
782 DRM_PLANE_TYPE_CURSOR,
783 "cursor %c", pipe_name(pipe));
784 if (ret)
785 goto fail;
786
787 if (DISPLAY_VER(dev_priv) >= 4)
788 drm_plane_create_rotation_property(&cursor->base,
789 DRM_MODE_ROTATE_0,
790 DRM_MODE_ROTATE_0 |
791 DRM_MODE_ROTATE_180);
792
793 zpos = RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1;
794 drm_plane_create_zpos_immutable_property(&cursor->base, zpos);
795
796 if (DISPLAY_VER(dev_priv) >= 12)
797 drm_plane_enable_fb_damage_clips(&cursor->base);
798
799 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
800
801 return cursor;
802
803 fail:
804 intel_plane_free(cursor);
805
806 return ERR_PTR(ret);
807 }
808