1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26
27 #include <linux/backlight.h>
28 #include <linux/pci.h>
29
30 #include <drm/drm_crtc_helper.h>
31 #include <drm/drm_device.h>
32 #include <drm/drm_file.h>
33 #include <drm/drm_util.h>
34 #include <drm/radeon_drm.h>
35
36 #include "radeon.h"
37 #include "radeon_asic.h"
38 #include "radeon_legacy_encoders.h"
39 #include "atom.h"
40 #ifdef CONFIG_PMAC_BACKLIGHT
41 #include <asm/backlight.h>
42 #endif
43
radeon_legacy_encoder_disable(struct drm_encoder * encoder)44 static void radeon_legacy_encoder_disable(struct drm_encoder *encoder)
45 {
46 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
47 const struct drm_encoder_helper_funcs *encoder_funcs;
48
49 encoder_funcs = encoder->helper_private;
50 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
51 radeon_encoder->active_device = 0;
52 }
53
radeon_legacy_lvds_update(struct drm_encoder * encoder,int mode)54 static void radeon_legacy_lvds_update(struct drm_encoder *encoder, int mode)
55 {
56 struct drm_device *dev = encoder->dev;
57 struct radeon_device *rdev = dev->dev_private;
58 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
59 uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
60 int panel_pwr_delay = 2000;
61 bool is_mac = false;
62 uint8_t backlight_level;
63 DRM_DEBUG_KMS("\n");
64
65 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
66 backlight_level = (lvds_gen_cntl >> RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
67
68 if (radeon_encoder->enc_priv) {
69 if (rdev->is_atom_bios) {
70 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
71 panel_pwr_delay = lvds->panel_pwr_delay;
72 if (lvds->bl_dev)
73 backlight_level = lvds->backlight_level;
74 } else {
75 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
76 panel_pwr_delay = lvds->panel_pwr_delay;
77 if (lvds->bl_dev)
78 backlight_level = lvds->backlight_level;
79 }
80 }
81
82 /* macs (and possibly some x86 oem systems?) wire up LVDS strangely
83 * Taken from radeonfb.
84 */
85 if ((rdev->mode_info.connector_table == CT_IBOOK) ||
86 (rdev->mode_info.connector_table == CT_POWERBOOK_EXTERNAL) ||
87 (rdev->mode_info.connector_table == CT_POWERBOOK_INTERNAL) ||
88 (rdev->mode_info.connector_table == CT_POWERBOOK_VGA))
89 is_mac = true;
90
91 switch (mode) {
92 case DRM_MODE_DPMS_ON:
93 disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN);
94 disp_pwr_man |= RADEON_AUTO_PWRUP_EN;
95 WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man);
96 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
97 lvds_pll_cntl |= RADEON_LVDS_PLL_EN;
98 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
99 mdelay(1);
100
101 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
102 lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
103 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
104
105 lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS |
106 RADEON_LVDS_BL_MOD_LEVEL_MASK);
107 lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN |
108 RADEON_LVDS_DIGON | RADEON_LVDS_BLON |
109 (backlight_level << RADEON_LVDS_BL_MOD_LEVEL_SHIFT));
110 if (is_mac)
111 lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN;
112 mdelay(panel_pwr_delay);
113 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
114 break;
115 case DRM_MODE_DPMS_STANDBY:
116 case DRM_MODE_DPMS_SUSPEND:
117 case DRM_MODE_DPMS_OFF:
118 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
119 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
120 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
121 if (is_mac) {
122 lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_EN;
123 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
124 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_EN);
125 } else {
126 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
127 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
128 }
129 mdelay(panel_pwr_delay);
130 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
131 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
132 mdelay(panel_pwr_delay);
133 break;
134 }
135
136 if (rdev->is_atom_bios)
137 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
138 else
139 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
140
141 }
142
radeon_legacy_lvds_dpms(struct drm_encoder * encoder,int mode)143 static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
144 {
145 struct radeon_device *rdev = encoder->dev->dev_private;
146 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
147 DRM_DEBUG("\n");
148
149 if (radeon_encoder->enc_priv) {
150 if (rdev->is_atom_bios) {
151 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
152 lvds->dpms_mode = mode;
153 } else {
154 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
155 lvds->dpms_mode = mode;
156 }
157 }
158
159 radeon_legacy_lvds_update(encoder, mode);
160 }
161
radeon_legacy_lvds_prepare(struct drm_encoder * encoder)162 static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
163 {
164 struct radeon_device *rdev = encoder->dev->dev_private;
165
166 if (rdev->is_atom_bios)
167 radeon_atom_output_lock(encoder, true);
168 else
169 radeon_combios_output_lock(encoder, true);
170 radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
171 }
172
radeon_legacy_lvds_commit(struct drm_encoder * encoder)173 static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
174 {
175 struct radeon_device *rdev = encoder->dev->dev_private;
176
177 radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON);
178 if (rdev->is_atom_bios)
179 radeon_atom_output_lock(encoder, false);
180 else
181 radeon_combios_output_lock(encoder, false);
182 }
183
radeon_legacy_lvds_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)184 static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
185 struct drm_display_mode *mode,
186 struct drm_display_mode *adjusted_mode)
187 {
188 struct drm_device *dev = encoder->dev;
189 struct radeon_device *rdev = dev->dev_private;
190 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
191 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
192 uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl;
193
194 DRM_DEBUG_KMS("\n");
195
196 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
197 lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN;
198
199 lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
200 if (rdev->is_atom_bios) {
201 /* LVDS_GEN_CNTL parameters are computed in LVDSEncoderControl
202 * need to call that on resume to set up the reg properly.
203 */
204 radeon_encoder->pixel_clock = adjusted_mode->clock;
205 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
206 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
207 } else {
208 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
209 if (lvds) {
210 DRM_DEBUG_KMS("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl);
211 lvds_gen_cntl = lvds->lvds_gen_cntl;
212 lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
213 (0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
214 lvds_ss_gen_cntl |= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
215 (lvds->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
216 } else
217 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
218 }
219 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
220 lvds_gen_cntl &= ~(RADEON_LVDS_ON |
221 RADEON_LVDS_BLON |
222 RADEON_LVDS_EN |
223 RADEON_LVDS_RST_FM);
224
225 if (ASIC_IS_R300(rdev))
226 lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
227
228 if (radeon_crtc->crtc_id == 0) {
229 if (ASIC_IS_R300(rdev)) {
230 if (radeon_encoder->rmx_type != RMX_OFF)
231 lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX;
232 } else
233 lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
234 } else {
235 if (ASIC_IS_R300(rdev))
236 lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2;
237 else
238 lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2;
239 }
240
241 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
242 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
243 WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl);
244
245 if (rdev->family == CHIP_RV410)
246 WREG32(RADEON_CLOCK_CNTL_INDEX, 0);
247
248 if (rdev->is_atom_bios)
249 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
250 else
251 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
252 }
253
radeon_legacy_mode_fixup(struct drm_encoder * encoder,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)254 static bool radeon_legacy_mode_fixup(struct drm_encoder *encoder,
255 const struct drm_display_mode *mode,
256 struct drm_display_mode *adjusted_mode)
257 {
258 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
259
260 /* set the active encoder to connector routing */
261 radeon_encoder_set_active_device(encoder);
262 drm_mode_set_crtcinfo(adjusted_mode, 0);
263
264 /* get the native mode for LVDS */
265 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
266 radeon_panel_mode_fixup(encoder, adjusted_mode);
267
268 return true;
269 }
270
271 static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
272 .dpms = radeon_legacy_lvds_dpms,
273 .mode_fixup = radeon_legacy_mode_fixup,
274 .prepare = radeon_legacy_lvds_prepare,
275 .mode_set = radeon_legacy_lvds_mode_set,
276 .commit = radeon_legacy_lvds_commit,
277 .disable = radeon_legacy_encoder_disable,
278 };
279
280 u8
radeon_legacy_get_backlight_level(struct radeon_encoder * radeon_encoder)281 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder)
282 {
283 struct drm_device *dev = radeon_encoder->base.dev;
284 struct radeon_device *rdev = dev->dev_private;
285 u8 backlight_level;
286
287 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
288 RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
289
290 return backlight_level;
291 }
292
293 void
radeon_legacy_set_backlight_level(struct radeon_encoder * radeon_encoder,u8 level)294 radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
295 {
296 struct drm_device *dev = radeon_encoder->base.dev;
297 struct radeon_device *rdev = dev->dev_private;
298 int dpms_mode = DRM_MODE_DPMS_ON;
299
300 if (radeon_encoder->enc_priv) {
301 if (rdev->is_atom_bios) {
302 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
303 if (lvds->backlight_level > 0)
304 dpms_mode = lvds->dpms_mode;
305 else
306 dpms_mode = DRM_MODE_DPMS_OFF;
307 lvds->backlight_level = level;
308 } else {
309 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
310 if (lvds->backlight_level > 0)
311 dpms_mode = lvds->dpms_mode;
312 else
313 dpms_mode = DRM_MODE_DPMS_OFF;
314 lvds->backlight_level = level;
315 }
316 }
317
318 radeon_legacy_lvds_update(&radeon_encoder->base, dpms_mode);
319 }
320
321 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
322
radeon_legacy_lvds_level(struct backlight_device * bd)323 static uint8_t radeon_legacy_lvds_level(struct backlight_device *bd)
324 {
325 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
326 uint8_t level;
327
328 /* Convert brightness to hardware level */
329 if (bd->props.brightness < 0)
330 level = 0;
331 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
332 level = RADEON_MAX_BL_LEVEL;
333 else
334 level = bd->props.brightness;
335
336 if (pdata->negative)
337 level = RADEON_MAX_BL_LEVEL - level;
338
339 return level;
340 }
341
radeon_legacy_backlight_update_status(struct backlight_device * bd)342 static int radeon_legacy_backlight_update_status(struct backlight_device *bd)
343 {
344 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
345 struct radeon_encoder *radeon_encoder = pdata->encoder;
346
347 radeon_legacy_set_backlight_level(radeon_encoder,
348 radeon_legacy_lvds_level(bd));
349
350 return 0;
351 }
352
radeon_legacy_backlight_get_brightness(struct backlight_device * bd)353 static int radeon_legacy_backlight_get_brightness(struct backlight_device *bd)
354 {
355 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
356 struct radeon_encoder *radeon_encoder = pdata->encoder;
357 struct drm_device *dev = radeon_encoder->base.dev;
358 struct radeon_device *rdev = dev->dev_private;
359 uint8_t backlight_level;
360
361 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
362 RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
363
364 return pdata->negative ? RADEON_MAX_BL_LEVEL - backlight_level : backlight_level;
365 }
366
367 static const struct backlight_ops radeon_backlight_ops = {
368 .get_brightness = radeon_legacy_backlight_get_brightness,
369 .update_status = radeon_legacy_backlight_update_status,
370 };
371
radeon_legacy_backlight_init(struct radeon_encoder * radeon_encoder,struct drm_connector * drm_connector)372 void radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder,
373 struct drm_connector *drm_connector)
374 {
375 struct drm_device *dev = radeon_encoder->base.dev;
376 struct radeon_device *rdev = dev->dev_private;
377 struct backlight_device *bd;
378 struct backlight_properties props;
379 struct radeon_backlight_privdata *pdata;
380 uint8_t backlight_level;
381 char bl_name[16];
382
383 if (!radeon_encoder->enc_priv)
384 return;
385
386 #ifdef CONFIG_PMAC_BACKLIGHT
387 if (!pmac_has_backlight_type("ati") &&
388 !pmac_has_backlight_type("mnca"))
389 return;
390 #endif
391
392 pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
393 if (!pdata) {
394 DRM_ERROR("Memory allocation failed\n");
395 goto error;
396 }
397
398 memset(&props, 0, sizeof(props));
399 props.max_brightness = RADEON_MAX_BL_LEVEL;
400 props.type = BACKLIGHT_RAW;
401 snprintf(bl_name, sizeof(bl_name),
402 "radeon_bl%d", dev->primary->index);
403 bd = backlight_device_register(bl_name, drm_connector->kdev,
404 pdata, &radeon_backlight_ops, &props);
405 if (IS_ERR(bd)) {
406 DRM_ERROR("Backlight registration failed\n");
407 goto error;
408 }
409
410 pdata->encoder = radeon_encoder;
411
412 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
413 RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
414
415 /* First, try to detect backlight level sense based on the assumption
416 * that firmware set it up at full brightness
417 */
418 if (backlight_level == 0)
419 pdata->negative = true;
420 else if (backlight_level == 0xff)
421 pdata->negative = false;
422 else {
423 /* XXX hack... maybe some day we can figure out in what direction
424 * backlight should work on a given panel?
425 */
426 pdata->negative = (rdev->family != CHIP_RV200 &&
427 rdev->family != CHIP_RV250 &&
428 rdev->family != CHIP_RV280 &&
429 rdev->family != CHIP_RV350);
430
431 #ifdef CONFIG_PMAC_BACKLIGHT
432 pdata->negative = (pdata->negative ||
433 of_machine_is_compatible("PowerBook4,3") ||
434 of_machine_is_compatible("PowerBook6,3") ||
435 of_machine_is_compatible("PowerBook6,5"));
436 #endif
437 }
438
439 if (rdev->is_atom_bios) {
440 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
441 lvds->bl_dev = bd;
442 } else {
443 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
444 lvds->bl_dev = bd;
445 }
446
447 bd->props.brightness = radeon_legacy_backlight_get_brightness(bd);
448 bd->props.power = FB_BLANK_UNBLANK;
449 backlight_update_status(bd);
450
451 DRM_INFO("radeon legacy LVDS backlight initialized\n");
452 rdev->mode_info.bl_encoder = radeon_encoder;
453
454 return;
455
456 error:
457 kfree(pdata);
458 return;
459 }
460
radeon_legacy_backlight_exit(struct radeon_encoder * radeon_encoder)461 static void radeon_legacy_backlight_exit(struct radeon_encoder *radeon_encoder)
462 {
463 struct drm_device *dev = radeon_encoder->base.dev;
464 struct radeon_device *rdev = dev->dev_private;
465 struct backlight_device *bd = NULL;
466
467 if (!radeon_encoder->enc_priv)
468 return;
469
470 if (rdev->is_atom_bios) {
471 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
472 bd = lvds->bl_dev;
473 lvds->bl_dev = NULL;
474 } else {
475 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
476 bd = lvds->bl_dev;
477 lvds->bl_dev = NULL;
478 }
479
480 if (bd) {
481 struct radeon_backlight_privdata *pdata;
482
483 pdata = bl_get_data(bd);
484 backlight_device_unregister(bd);
485 kfree(pdata);
486
487 DRM_INFO("radeon legacy LVDS backlight unloaded\n");
488 }
489 }
490
491 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
492
radeon_legacy_backlight_init(struct radeon_encoder * encoder)493 void radeon_legacy_backlight_init(struct radeon_encoder *encoder)
494 {
495 }
496
radeon_legacy_backlight_exit(struct radeon_encoder * encoder)497 static void radeon_legacy_backlight_exit(struct radeon_encoder *encoder)
498 {
499 }
500
501 #endif
502
503
radeon_lvds_enc_destroy(struct drm_encoder * encoder)504 static void radeon_lvds_enc_destroy(struct drm_encoder *encoder)
505 {
506 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
507
508 if (radeon_encoder->enc_priv) {
509 radeon_legacy_backlight_exit(radeon_encoder);
510 kfree(radeon_encoder->enc_priv);
511 }
512 drm_encoder_cleanup(encoder);
513 kfree(radeon_encoder);
514 }
515
516 static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = {
517 .destroy = radeon_lvds_enc_destroy,
518 };
519
radeon_legacy_primary_dac_dpms(struct drm_encoder * encoder,int mode)520 static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode)
521 {
522 struct drm_device *dev = encoder->dev;
523 struct radeon_device *rdev = dev->dev_private;
524 uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
525 uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL);
526 uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
527
528 DRM_DEBUG_KMS("\n");
529
530 switch (mode) {
531 case DRM_MODE_DPMS_ON:
532 crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
533 dac_cntl &= ~RADEON_DAC_PDWN;
534 dac_macro_cntl &= ~(RADEON_DAC_PDWN_R |
535 RADEON_DAC_PDWN_G |
536 RADEON_DAC_PDWN_B);
537 break;
538 case DRM_MODE_DPMS_STANDBY:
539 case DRM_MODE_DPMS_SUSPEND:
540 case DRM_MODE_DPMS_OFF:
541 crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
542 dac_cntl |= RADEON_DAC_PDWN;
543 dac_macro_cntl |= (RADEON_DAC_PDWN_R |
544 RADEON_DAC_PDWN_G |
545 RADEON_DAC_PDWN_B);
546 break;
547 }
548
549 /* handled in radeon_crtc_dpms() */
550 if (!(rdev->flags & RADEON_SINGLE_CRTC))
551 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
552 WREG32(RADEON_DAC_CNTL, dac_cntl);
553 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
554
555 if (rdev->is_atom_bios)
556 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
557 else
558 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
559
560 }
561
radeon_legacy_primary_dac_prepare(struct drm_encoder * encoder)562 static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
563 {
564 struct radeon_device *rdev = encoder->dev->dev_private;
565
566 if (rdev->is_atom_bios)
567 radeon_atom_output_lock(encoder, true);
568 else
569 radeon_combios_output_lock(encoder, true);
570 radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
571 }
572
radeon_legacy_primary_dac_commit(struct drm_encoder * encoder)573 static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
574 {
575 struct radeon_device *rdev = encoder->dev->dev_private;
576
577 radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON);
578
579 if (rdev->is_atom_bios)
580 radeon_atom_output_lock(encoder, false);
581 else
582 radeon_combios_output_lock(encoder, false);
583 }
584
radeon_legacy_primary_dac_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)585 static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder,
586 struct drm_display_mode *mode,
587 struct drm_display_mode *adjusted_mode)
588 {
589 struct drm_device *dev = encoder->dev;
590 struct radeon_device *rdev = dev->dev_private;
591 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
592 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
593 uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl;
594
595 DRM_DEBUG_KMS("\n");
596
597 if (radeon_crtc->crtc_id == 0) {
598 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
599 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
600 ~(RADEON_DISP_DAC_SOURCE_MASK);
601 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
602 } else {
603 dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~(RADEON_DAC2_DAC_CLK_SEL);
604 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
605 }
606 } else {
607 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
608 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
609 ~(RADEON_DISP_DAC_SOURCE_MASK);
610 disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
611 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
612 } else {
613 dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL;
614 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
615 }
616 }
617
618 dac_cntl = (RADEON_DAC_MASK_ALL |
619 RADEON_DAC_VGA_ADR_EN |
620 /* TODO 6-bits */
621 RADEON_DAC_8BIT_EN);
622
623 WREG32_P(RADEON_DAC_CNTL,
624 dac_cntl,
625 RADEON_DAC_RANGE_CNTL |
626 RADEON_DAC_BLANKING);
627
628 if (radeon_encoder->enc_priv) {
629 struct radeon_encoder_primary_dac *p_dac = (struct radeon_encoder_primary_dac *)radeon_encoder->enc_priv;
630 dac_macro_cntl = p_dac->ps2_pdac_adj;
631 } else
632 dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
633 dac_macro_cntl |= RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | RADEON_DAC_PDWN_B;
634 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
635
636 if (rdev->is_atom_bios)
637 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
638 else
639 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
640 }
641
radeon_legacy_primary_dac_detect(struct drm_encoder * encoder,struct drm_connector * connector)642 static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder,
643 struct drm_connector *connector)
644 {
645 struct drm_device *dev = encoder->dev;
646 struct radeon_device *rdev = dev->dev_private;
647 uint32_t vclk_ecp_cntl, crtc_ext_cntl;
648 uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp;
649 enum drm_connector_status found = connector_status_disconnected;
650 bool color = true;
651
652 /* just don't bother on RN50 those chip are often connected to remoting
653 * console hw and often we get failure to load detect those. So to make
654 * everyone happy report the encoder as always connected.
655 */
656 if (ASIC_IS_RN50(rdev)) {
657 return connector_status_connected;
658 }
659
660 /* save the regs we need */
661 vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
662 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
663 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
664 dac_cntl = RREG32(RADEON_DAC_CNTL);
665 dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
666
667 tmp = vclk_ecp_cntl &
668 ~(RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb);
669 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
670
671 tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
672 WREG32(RADEON_CRTC_EXT_CNTL, tmp);
673
674 tmp = RADEON_DAC_FORCE_BLANK_OFF_EN |
675 RADEON_DAC_FORCE_DATA_EN;
676
677 if (color)
678 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
679 else
680 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
681
682 if (ASIC_IS_R300(rdev))
683 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
684 else if (ASIC_IS_RV100(rdev))
685 tmp |= (0x1ac << RADEON_DAC_FORCE_DATA_SHIFT);
686 else
687 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
688
689 WREG32(RADEON_DAC_EXT_CNTL, tmp);
690
691 tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN);
692 tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN;
693 WREG32(RADEON_DAC_CNTL, tmp);
694
695 tmp = dac_macro_cntl;
696 tmp &= ~(RADEON_DAC_PDWN_R |
697 RADEON_DAC_PDWN_G |
698 RADEON_DAC_PDWN_B);
699
700 WREG32(RADEON_DAC_MACRO_CNTL, tmp);
701
702 mdelay(2);
703
704 if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT)
705 found = connector_status_connected;
706
707 /* restore the regs we used */
708 WREG32(RADEON_DAC_CNTL, dac_cntl);
709 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
710 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
711 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
712 WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);
713
714 return found;
715 }
716
717 static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = {
718 .dpms = radeon_legacy_primary_dac_dpms,
719 .mode_fixup = radeon_legacy_mode_fixup,
720 .prepare = radeon_legacy_primary_dac_prepare,
721 .mode_set = radeon_legacy_primary_dac_mode_set,
722 .commit = radeon_legacy_primary_dac_commit,
723 .detect = radeon_legacy_primary_dac_detect,
724 .disable = radeon_legacy_encoder_disable,
725 };
726
727
728 static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = {
729 .destroy = radeon_enc_destroy,
730 };
731
radeon_legacy_tmds_int_dpms(struct drm_encoder * encoder,int mode)732 static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode)
733 {
734 struct drm_device *dev = encoder->dev;
735 struct radeon_device *rdev = dev->dev_private;
736 uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL);
737 DRM_DEBUG_KMS("\n");
738
739 switch (mode) {
740 case DRM_MODE_DPMS_ON:
741 fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
742 break;
743 case DRM_MODE_DPMS_STANDBY:
744 case DRM_MODE_DPMS_SUSPEND:
745 case DRM_MODE_DPMS_OFF:
746 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
747 break;
748 }
749
750 WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
751
752 if (rdev->is_atom_bios)
753 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
754 else
755 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
756
757 }
758
radeon_legacy_tmds_int_prepare(struct drm_encoder * encoder)759 static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
760 {
761 struct radeon_device *rdev = encoder->dev->dev_private;
762
763 if (rdev->is_atom_bios)
764 radeon_atom_output_lock(encoder, true);
765 else
766 radeon_combios_output_lock(encoder, true);
767 radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
768 }
769
radeon_legacy_tmds_int_commit(struct drm_encoder * encoder)770 static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
771 {
772 struct radeon_device *rdev = encoder->dev->dev_private;
773
774 radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON);
775
776 if (rdev->is_atom_bios)
777 radeon_atom_output_lock(encoder, true);
778 else
779 radeon_combios_output_lock(encoder, true);
780 }
781
radeon_legacy_tmds_int_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)782 static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
783 struct drm_display_mode *mode,
784 struct drm_display_mode *adjusted_mode)
785 {
786 struct drm_device *dev = encoder->dev;
787 struct radeon_device *rdev = dev->dev_private;
788 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
789 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
790 uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
791 int i;
792
793 DRM_DEBUG_KMS("\n");
794
795 tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL);
796 tmp &= 0xfffff;
797 if (rdev->family == CHIP_RV280) {
798 /* bit 22 of TMDS_PLL_CNTL is read-back inverted */
799 tmp ^= (1 << 22);
800 tmds_pll_cntl ^= (1 << 22);
801 }
802
803 if (radeon_encoder->enc_priv) {
804 struct radeon_encoder_int_tmds *tmds = (struct radeon_encoder_int_tmds *)radeon_encoder->enc_priv;
805
806 for (i = 0; i < 4; i++) {
807 if (tmds->tmds_pll[i].freq == 0)
808 break;
809 if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) {
810 tmp = tmds->tmds_pll[i].value ;
811 break;
812 }
813 }
814 }
815
816 if (ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV280)) {
817 if (tmp & 0xfff00000)
818 tmds_pll_cntl = tmp;
819 else {
820 tmds_pll_cntl &= 0xfff00000;
821 tmds_pll_cntl |= tmp;
822 }
823 } else
824 tmds_pll_cntl = tmp;
825
826 tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) &
827 ~(RADEON_TMDS_TRANSMITTER_PLLRST);
828
829 if (rdev->family == CHIP_R200 ||
830 rdev->family == CHIP_R100 ||
831 ASIC_IS_R300(rdev))
832 tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
833 else /* RV chips got this bit reversed */
834 tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN;
835
836 fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) |
837 (RADEON_FP_CRTC_DONT_SHADOW_VPAR |
838 RADEON_FP_CRTC_DONT_SHADOW_HEND));
839
840 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
841
842 fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN |
843 RADEON_FP_DFP_SYNC_SEL |
844 RADEON_FP_CRT_SYNC_SEL |
845 RADEON_FP_CRTC_LOCK_8DOT |
846 RADEON_FP_USE_SHADOW_EN |
847 RADEON_FP_CRTC_USE_SHADOW_VEND |
848 RADEON_FP_CRT_SYNC_ALT);
849
850 if (1) /* FIXME rgbBits == 8 */
851 fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */
852 else
853 fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
854
855 if (radeon_crtc->crtc_id == 0) {
856 if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
857 fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
858 if (radeon_encoder->rmx_type != RMX_OFF)
859 fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
860 else
861 fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
862 } else
863 fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2;
864 } else {
865 if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
866 fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
867 fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2;
868 } else
869 fp_gen_cntl |= RADEON_FP_SEL_CRTC2;
870 }
871
872 WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl);
873 WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl);
874 WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
875
876 if (rdev->is_atom_bios)
877 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
878 else
879 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
880 }
881
882 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = {
883 .dpms = radeon_legacy_tmds_int_dpms,
884 .mode_fixup = radeon_legacy_mode_fixup,
885 .prepare = radeon_legacy_tmds_int_prepare,
886 .mode_set = radeon_legacy_tmds_int_mode_set,
887 .commit = radeon_legacy_tmds_int_commit,
888 .disable = radeon_legacy_encoder_disable,
889 };
890
891
892 static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = {
893 .destroy = radeon_enc_destroy,
894 };
895
radeon_legacy_tmds_ext_dpms(struct drm_encoder * encoder,int mode)896 static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode)
897 {
898 struct drm_device *dev = encoder->dev;
899 struct radeon_device *rdev = dev->dev_private;
900 uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
901 DRM_DEBUG_KMS("\n");
902
903 switch (mode) {
904 case DRM_MODE_DPMS_ON:
905 fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
906 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
907 break;
908 case DRM_MODE_DPMS_STANDBY:
909 case DRM_MODE_DPMS_SUSPEND:
910 case DRM_MODE_DPMS_OFF:
911 fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
912 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
913 break;
914 }
915
916 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
917
918 if (rdev->is_atom_bios)
919 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
920 else
921 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
922
923 }
924
radeon_legacy_tmds_ext_prepare(struct drm_encoder * encoder)925 static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
926 {
927 struct radeon_device *rdev = encoder->dev->dev_private;
928
929 if (rdev->is_atom_bios)
930 radeon_atom_output_lock(encoder, true);
931 else
932 radeon_combios_output_lock(encoder, true);
933 radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
934 }
935
radeon_legacy_tmds_ext_commit(struct drm_encoder * encoder)936 static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
937 {
938 struct radeon_device *rdev = encoder->dev->dev_private;
939 radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON);
940
941 if (rdev->is_atom_bios)
942 radeon_atom_output_lock(encoder, false);
943 else
944 radeon_combios_output_lock(encoder, false);
945 }
946
radeon_legacy_tmds_ext_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)947 static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder,
948 struct drm_display_mode *mode,
949 struct drm_display_mode *adjusted_mode)
950 {
951 struct drm_device *dev = encoder->dev;
952 struct radeon_device *rdev = dev->dev_private;
953 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
954 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
955 uint32_t fp2_gen_cntl;
956
957 DRM_DEBUG_KMS("\n");
958
959 if (rdev->is_atom_bios) {
960 radeon_encoder->pixel_clock = adjusted_mode->clock;
961 atombios_dvo_setup(encoder, ATOM_ENABLE);
962 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
963 } else {
964 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
965
966 if (1) /* FIXME rgbBits == 8 */
967 fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
968 else
969 fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
970
971 fp2_gen_cntl &= ~(RADEON_FP2_ON |
972 RADEON_FP2_DVO_EN |
973 RADEON_FP2_DVO_RATE_SEL_SDR);
974
975 /* XXX: these are oem specific */
976 if (ASIC_IS_R300(rdev)) {
977 if ((rdev->pdev->device == 0x4850) &&
978 (rdev->pdev->subsystem_vendor == 0x1028) &&
979 (rdev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */
980 fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE;
981 else
982 fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE;
983
984 /*if (mode->clock > 165000)
985 fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;*/
986 }
987 if (!radeon_combios_external_tmds_setup(encoder))
988 radeon_external_tmds_setup(encoder);
989 }
990
991 if (radeon_crtc->crtc_id == 0) {
992 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
993 fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
994 if (radeon_encoder->rmx_type != RMX_OFF)
995 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
996 else
997 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1;
998 } else
999 fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
1000 } else {
1001 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
1002 fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
1003 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
1004 } else
1005 fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2;
1006 }
1007
1008 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1009
1010 if (rdev->is_atom_bios)
1011 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1012 else
1013 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1014 }
1015
radeon_ext_tmds_enc_destroy(struct drm_encoder * encoder)1016 static void radeon_ext_tmds_enc_destroy(struct drm_encoder *encoder)
1017 {
1018 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1019 /* don't destroy the i2c bus record here, this will be done in radeon_i2c_fini */
1020 kfree(radeon_encoder->enc_priv);
1021 drm_encoder_cleanup(encoder);
1022 kfree(radeon_encoder);
1023 }
1024
1025 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = {
1026 .dpms = radeon_legacy_tmds_ext_dpms,
1027 .mode_fixup = radeon_legacy_mode_fixup,
1028 .prepare = radeon_legacy_tmds_ext_prepare,
1029 .mode_set = radeon_legacy_tmds_ext_mode_set,
1030 .commit = radeon_legacy_tmds_ext_commit,
1031 .disable = radeon_legacy_encoder_disable,
1032 };
1033
1034
1035 static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = {
1036 .destroy = radeon_ext_tmds_enc_destroy,
1037 };
1038
radeon_legacy_tv_dac_dpms(struct drm_encoder * encoder,int mode)1039 static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
1040 {
1041 struct drm_device *dev = encoder->dev;
1042 struct radeon_device *rdev = dev->dev_private;
1043 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1044 uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0;
1045 uint32_t tv_master_cntl = 0;
1046 bool is_tv;
1047 DRM_DEBUG_KMS("\n");
1048
1049 is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
1050
1051 if (rdev->family == CHIP_R200)
1052 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
1053 else {
1054 if (is_tv)
1055 tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
1056 else
1057 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1058 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1059 }
1060
1061 switch (mode) {
1062 case DRM_MODE_DPMS_ON:
1063 if (rdev->family == CHIP_R200) {
1064 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
1065 } else {
1066 if (is_tv)
1067 tv_master_cntl |= RADEON_TV_ON;
1068 else
1069 crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
1070
1071 if (rdev->family == CHIP_R420 ||
1072 rdev->family == CHIP_R423 ||
1073 rdev->family == CHIP_RV410)
1074 tv_dac_cntl &= ~(R420_TV_DAC_RDACPD |
1075 R420_TV_DAC_GDACPD |
1076 R420_TV_DAC_BDACPD |
1077 RADEON_TV_DAC_BGSLEEP);
1078 else
1079 tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
1080 RADEON_TV_DAC_GDACPD |
1081 RADEON_TV_DAC_BDACPD |
1082 RADEON_TV_DAC_BGSLEEP);
1083 }
1084 break;
1085 case DRM_MODE_DPMS_STANDBY:
1086 case DRM_MODE_DPMS_SUSPEND:
1087 case DRM_MODE_DPMS_OFF:
1088 if (rdev->family == CHIP_R200)
1089 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
1090 else {
1091 if (is_tv)
1092 tv_master_cntl &= ~RADEON_TV_ON;
1093 else
1094 crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
1095
1096 if (rdev->family == CHIP_R420 ||
1097 rdev->family == CHIP_R423 ||
1098 rdev->family == CHIP_RV410)
1099 tv_dac_cntl |= (R420_TV_DAC_RDACPD |
1100 R420_TV_DAC_GDACPD |
1101 R420_TV_DAC_BDACPD |
1102 RADEON_TV_DAC_BGSLEEP);
1103 else
1104 tv_dac_cntl |= (RADEON_TV_DAC_RDACPD |
1105 RADEON_TV_DAC_GDACPD |
1106 RADEON_TV_DAC_BDACPD |
1107 RADEON_TV_DAC_BGSLEEP);
1108 }
1109 break;
1110 }
1111
1112 if (rdev->family == CHIP_R200) {
1113 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1114 } else {
1115 if (is_tv)
1116 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
1117 /* handled in radeon_crtc_dpms() */
1118 else if (!(rdev->flags & RADEON_SINGLE_CRTC))
1119 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1120 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1121 }
1122
1123 if (rdev->is_atom_bios)
1124 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1125 else
1126 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1127
1128 }
1129
radeon_legacy_tv_dac_prepare(struct drm_encoder * encoder)1130 static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
1131 {
1132 struct radeon_device *rdev = encoder->dev->dev_private;
1133
1134 if (rdev->is_atom_bios)
1135 radeon_atom_output_lock(encoder, true);
1136 else
1137 radeon_combios_output_lock(encoder, true);
1138 radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
1139 }
1140
radeon_legacy_tv_dac_commit(struct drm_encoder * encoder)1141 static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
1142 {
1143 struct radeon_device *rdev = encoder->dev->dev_private;
1144
1145 radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON);
1146
1147 if (rdev->is_atom_bios)
1148 radeon_atom_output_lock(encoder, true);
1149 else
1150 radeon_combios_output_lock(encoder, true);
1151 }
1152
radeon_legacy_tv_dac_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)1153 static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
1154 struct drm_display_mode *mode,
1155 struct drm_display_mode *adjusted_mode)
1156 {
1157 struct drm_device *dev = encoder->dev;
1158 struct radeon_device *rdev = dev->dev_private;
1159 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1160 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1161 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1162 uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0;
1163 uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0;
1164 bool is_tv = false;
1165
1166 DRM_DEBUG_KMS("\n");
1167
1168 is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
1169
1170 if (rdev->family != CHIP_R200) {
1171 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1172 if (rdev->family == CHIP_R420 ||
1173 rdev->family == CHIP_R423 ||
1174 rdev->family == CHIP_RV410) {
1175 tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
1176 RADEON_TV_DAC_BGADJ_MASK |
1177 R420_TV_DAC_DACADJ_MASK |
1178 R420_TV_DAC_RDACPD |
1179 R420_TV_DAC_GDACPD |
1180 R420_TV_DAC_BDACPD |
1181 R420_TV_DAC_TVENABLE);
1182 } else {
1183 tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
1184 RADEON_TV_DAC_BGADJ_MASK |
1185 RADEON_TV_DAC_DACADJ_MASK |
1186 RADEON_TV_DAC_RDACPD |
1187 RADEON_TV_DAC_GDACPD |
1188 RADEON_TV_DAC_BDACPD);
1189 }
1190
1191 tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD;
1192
1193 if (is_tv) {
1194 if (tv_dac->tv_std == TV_STD_NTSC ||
1195 tv_dac->tv_std == TV_STD_NTSC_J ||
1196 tv_dac->tv_std == TV_STD_PAL_M ||
1197 tv_dac->tv_std == TV_STD_PAL_60)
1198 tv_dac_cntl |= tv_dac->ntsc_tvdac_adj;
1199 else
1200 tv_dac_cntl |= tv_dac->pal_tvdac_adj;
1201
1202 if (tv_dac->tv_std == TV_STD_NTSC ||
1203 tv_dac->tv_std == TV_STD_NTSC_J)
1204 tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC;
1205 else
1206 tv_dac_cntl |= RADEON_TV_DAC_STD_PAL;
1207 } else
1208 tv_dac_cntl |= (RADEON_TV_DAC_STD_PS2 |
1209 tv_dac->ps2_tvdac_adj);
1210
1211 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1212 }
1213
1214 if (ASIC_IS_R300(rdev)) {
1215 gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1;
1216 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1217 } else if (rdev->family != CHIP_R200)
1218 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
1219 else if (rdev->family == CHIP_R200)
1220 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
1221
1222 if (rdev->family >= CHIP_R200)
1223 disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL);
1224
1225 if (is_tv) {
1226 uint32_t dac_cntl;
1227
1228 dac_cntl = RREG32(RADEON_DAC_CNTL);
1229 dac_cntl &= ~RADEON_DAC_TVO_EN;
1230 WREG32(RADEON_DAC_CNTL, dac_cntl);
1231
1232 if (ASIC_IS_R300(rdev))
1233 gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1;
1234
1235 dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL;
1236 if (radeon_crtc->crtc_id == 0) {
1237 if (ASIC_IS_R300(rdev)) {
1238 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1239 disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC |
1240 RADEON_DISP_TV_SOURCE_CRTC);
1241 }
1242 if (rdev->family >= CHIP_R200) {
1243 disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2;
1244 } else {
1245 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1246 }
1247 } else {
1248 if (ASIC_IS_R300(rdev)) {
1249 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1250 disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC;
1251 }
1252 if (rdev->family >= CHIP_R200) {
1253 disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2;
1254 } else {
1255 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
1256 }
1257 }
1258 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1259 } else {
1260
1261 dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL;
1262
1263 if (radeon_crtc->crtc_id == 0) {
1264 if (ASIC_IS_R300(rdev)) {
1265 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1266 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
1267 } else if (rdev->family == CHIP_R200) {
1268 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
1269 RADEON_FP2_DVO_RATE_SEL_SDR);
1270 } else
1271 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1272 } else {
1273 if (ASIC_IS_R300(rdev)) {
1274 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1275 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1276 } else if (rdev->family == CHIP_R200) {
1277 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
1278 RADEON_FP2_DVO_RATE_SEL_SDR);
1279 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
1280 } else
1281 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
1282 }
1283 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1284 }
1285
1286 if (ASIC_IS_R300(rdev)) {
1287 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1288 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1289 } else if (rdev->family != CHIP_R200)
1290 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1291 else if (rdev->family == CHIP_R200)
1292 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1293
1294 if (rdev->family >= CHIP_R200)
1295 WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl);
1296
1297 if (is_tv)
1298 radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode);
1299
1300 if (rdev->is_atom_bios)
1301 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1302 else
1303 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1304
1305 }
1306
r300_legacy_tv_detect(struct drm_encoder * encoder,struct drm_connector * connector)1307 static bool r300_legacy_tv_detect(struct drm_encoder *encoder,
1308 struct drm_connector *connector)
1309 {
1310 struct drm_device *dev = encoder->dev;
1311 struct radeon_device *rdev = dev->dev_private;
1312 uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1313 uint32_t disp_output_cntl, gpiopad_a, tmp;
1314 bool found = false;
1315
1316 /* save regs needed */
1317 gpiopad_a = RREG32(RADEON_GPIOPAD_A);
1318 dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1319 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1320 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1321 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1322 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1323
1324 WREG32_P(RADEON_GPIOPAD_A, 0, ~1);
1325
1326 WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL);
1327
1328 WREG32(RADEON_CRTC2_GEN_CNTL,
1329 RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT);
1330
1331 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1332 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1333 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1334
1335 WREG32(RADEON_DAC_EXT_CNTL,
1336 RADEON_DAC2_FORCE_BLANK_OFF_EN |
1337 RADEON_DAC2_FORCE_DATA_EN |
1338 RADEON_DAC_FORCE_DATA_SEL_RGB |
1339 (0xec << RADEON_DAC_FORCE_DATA_SHIFT));
1340
1341 WREG32(RADEON_TV_DAC_CNTL,
1342 RADEON_TV_DAC_STD_NTSC |
1343 (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1344 (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1345
1346 RREG32(RADEON_TV_DAC_CNTL);
1347 mdelay(4);
1348
1349 WREG32(RADEON_TV_DAC_CNTL,
1350 RADEON_TV_DAC_NBLANK |
1351 RADEON_TV_DAC_NHOLD |
1352 RADEON_TV_MONITOR_DETECT_EN |
1353 RADEON_TV_DAC_STD_NTSC |
1354 (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1355 (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1356
1357 RREG32(RADEON_TV_DAC_CNTL);
1358 mdelay(6);
1359
1360 tmp = RREG32(RADEON_TV_DAC_CNTL);
1361 if ((tmp & RADEON_TV_DAC_GDACDET) != 0) {
1362 found = true;
1363 DRM_DEBUG_KMS("S-video TV connection detected\n");
1364 } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1365 found = true;
1366 DRM_DEBUG_KMS("Composite TV connection detected\n");
1367 }
1368
1369 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1370 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1371 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1372 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1373 WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1374 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1375 return found;
1376 }
1377
radeon_legacy_tv_detect(struct drm_encoder * encoder,struct drm_connector * connector)1378 static bool radeon_legacy_tv_detect(struct drm_encoder *encoder,
1379 struct drm_connector *connector)
1380 {
1381 struct drm_device *dev = encoder->dev;
1382 struct radeon_device *rdev = dev->dev_private;
1383 uint32_t tv_dac_cntl, dac_cntl2;
1384 uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp;
1385 bool found = false;
1386
1387 if (ASIC_IS_R300(rdev))
1388 return r300_legacy_tv_detect(encoder, connector);
1389
1390 dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1391 tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
1392 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1393 config_cntl = RREG32(RADEON_CONFIG_CNTL);
1394 tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL);
1395
1396 tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL;
1397 WREG32(RADEON_DAC_CNTL2, tmp);
1398
1399 tmp = tv_master_cntl | RADEON_TV_ON;
1400 tmp &= ~(RADEON_TV_ASYNC_RST |
1401 RADEON_RESTART_PHASE_FIX |
1402 RADEON_CRT_FIFO_CE_EN |
1403 RADEON_TV_FIFO_CE_EN |
1404 RADEON_RE_SYNC_NOW_SEL_MASK);
1405 tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST;
1406 WREG32(RADEON_TV_MASTER_CNTL, tmp);
1407
1408 tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD |
1409 RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC |
1410 (8 << RADEON_TV_DAC_BGADJ_SHIFT);
1411
1412 if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK)
1413 tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT);
1414 else
1415 tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT);
1416 WREG32(RADEON_TV_DAC_CNTL, tmp);
1417
1418 tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN |
1419 RADEON_RED_MX_FORCE_DAC_DATA |
1420 RADEON_GRN_MX_FORCE_DAC_DATA |
1421 RADEON_BLU_MX_FORCE_DAC_DATA |
1422 (0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT);
1423 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp);
1424
1425 mdelay(3);
1426 tmp = RREG32(RADEON_TV_DAC_CNTL);
1427 if (tmp & RADEON_TV_DAC_GDACDET) {
1428 found = true;
1429 DRM_DEBUG_KMS("S-video TV connection detected\n");
1430 } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1431 found = true;
1432 DRM_DEBUG_KMS("Composite TV connection detected\n");
1433 }
1434
1435 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl);
1436 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1437 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
1438 WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1439 return found;
1440 }
1441
radeon_legacy_ext_dac_detect(struct drm_encoder * encoder,struct drm_connector * connector)1442 static bool radeon_legacy_ext_dac_detect(struct drm_encoder *encoder,
1443 struct drm_connector *connector)
1444 {
1445 struct drm_device *dev = encoder->dev;
1446 struct radeon_device *rdev = dev->dev_private;
1447 uint32_t gpio_monid, fp2_gen_cntl, disp_output_cntl, crtc2_gen_cntl;
1448 uint32_t disp_lin_trans_grph_a, disp_lin_trans_grph_b, disp_lin_trans_grph_c;
1449 uint32_t disp_lin_trans_grph_d, disp_lin_trans_grph_e, disp_lin_trans_grph_f;
1450 uint32_t tmp, crtc2_h_total_disp, crtc2_v_total_disp;
1451 uint32_t crtc2_h_sync_strt_wid, crtc2_v_sync_strt_wid;
1452 bool found = false;
1453 int i;
1454
1455 /* save the regs we need */
1456 gpio_monid = RREG32(RADEON_GPIO_MONID);
1457 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
1458 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1459 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1460 disp_lin_trans_grph_a = RREG32(RADEON_DISP_LIN_TRANS_GRPH_A);
1461 disp_lin_trans_grph_b = RREG32(RADEON_DISP_LIN_TRANS_GRPH_B);
1462 disp_lin_trans_grph_c = RREG32(RADEON_DISP_LIN_TRANS_GRPH_C);
1463 disp_lin_trans_grph_d = RREG32(RADEON_DISP_LIN_TRANS_GRPH_D);
1464 disp_lin_trans_grph_e = RREG32(RADEON_DISP_LIN_TRANS_GRPH_E);
1465 disp_lin_trans_grph_f = RREG32(RADEON_DISP_LIN_TRANS_GRPH_F);
1466 crtc2_h_total_disp = RREG32(RADEON_CRTC2_H_TOTAL_DISP);
1467 crtc2_v_total_disp = RREG32(RADEON_CRTC2_V_TOTAL_DISP);
1468 crtc2_h_sync_strt_wid = RREG32(RADEON_CRTC2_H_SYNC_STRT_WID);
1469 crtc2_v_sync_strt_wid = RREG32(RADEON_CRTC2_V_SYNC_STRT_WID);
1470
1471 tmp = RREG32(RADEON_GPIO_MONID);
1472 tmp &= ~RADEON_GPIO_A_0;
1473 WREG32(RADEON_GPIO_MONID, tmp);
1474
1475 WREG32(RADEON_FP2_GEN_CNTL, (RADEON_FP2_ON |
1476 RADEON_FP2_PANEL_FORMAT |
1477 R200_FP2_SOURCE_SEL_TRANS_UNIT |
1478 RADEON_FP2_DVO_EN |
1479 R200_FP2_DVO_RATE_SEL_SDR));
1480
1481 WREG32(RADEON_DISP_OUTPUT_CNTL, (RADEON_DISP_DAC_SOURCE_RMX |
1482 RADEON_DISP_TRANS_MATRIX_GRAPHICS));
1483
1484 WREG32(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_EN |
1485 RADEON_CRTC2_DISP_REQ_EN_B));
1486
1487 WREG32(RADEON_DISP_LIN_TRANS_GRPH_A, 0x00000000);
1488 WREG32(RADEON_DISP_LIN_TRANS_GRPH_B, 0x000003f0);
1489 WREG32(RADEON_DISP_LIN_TRANS_GRPH_C, 0x00000000);
1490 WREG32(RADEON_DISP_LIN_TRANS_GRPH_D, 0x000003f0);
1491 WREG32(RADEON_DISP_LIN_TRANS_GRPH_E, 0x00000000);
1492 WREG32(RADEON_DISP_LIN_TRANS_GRPH_F, 0x000003f0);
1493
1494 WREG32(RADEON_CRTC2_H_TOTAL_DISP, 0x01000008);
1495 WREG32(RADEON_CRTC2_H_SYNC_STRT_WID, 0x00000800);
1496 WREG32(RADEON_CRTC2_V_TOTAL_DISP, 0x00080001);
1497 WREG32(RADEON_CRTC2_V_SYNC_STRT_WID, 0x00000080);
1498
1499 for (i = 0; i < 200; i++) {
1500 tmp = RREG32(RADEON_GPIO_MONID);
1501 if (tmp & RADEON_GPIO_Y_0)
1502 found = true;
1503
1504 if (found)
1505 break;
1506
1507 if (!drm_can_sleep())
1508 mdelay(1);
1509 else
1510 msleep(1);
1511 }
1512
1513 /* restore the regs we used */
1514 WREG32(RADEON_DISP_LIN_TRANS_GRPH_A, disp_lin_trans_grph_a);
1515 WREG32(RADEON_DISP_LIN_TRANS_GRPH_B, disp_lin_trans_grph_b);
1516 WREG32(RADEON_DISP_LIN_TRANS_GRPH_C, disp_lin_trans_grph_c);
1517 WREG32(RADEON_DISP_LIN_TRANS_GRPH_D, disp_lin_trans_grph_d);
1518 WREG32(RADEON_DISP_LIN_TRANS_GRPH_E, disp_lin_trans_grph_e);
1519 WREG32(RADEON_DISP_LIN_TRANS_GRPH_F, disp_lin_trans_grph_f);
1520 WREG32(RADEON_CRTC2_H_TOTAL_DISP, crtc2_h_total_disp);
1521 WREG32(RADEON_CRTC2_V_TOTAL_DISP, crtc2_v_total_disp);
1522 WREG32(RADEON_CRTC2_H_SYNC_STRT_WID, crtc2_h_sync_strt_wid);
1523 WREG32(RADEON_CRTC2_V_SYNC_STRT_WID, crtc2_v_sync_strt_wid);
1524 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1525 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1526 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1527 WREG32(RADEON_GPIO_MONID, gpio_monid);
1528
1529 return found;
1530 }
1531
radeon_legacy_tv_dac_detect(struct drm_encoder * encoder,struct drm_connector * connector)1532 static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder,
1533 struct drm_connector *connector)
1534 {
1535 struct drm_device *dev = encoder->dev;
1536 struct radeon_device *rdev = dev->dev_private;
1537 uint32_t crtc2_gen_cntl = 0, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1538 uint32_t gpiopad_a = 0, pixclks_cntl, tmp;
1539 uint32_t disp_output_cntl = 0, disp_hw_debug = 0, crtc_ext_cntl = 0;
1540 enum drm_connector_status found = connector_status_disconnected;
1541 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1542 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1543 bool color = true;
1544 struct drm_crtc *crtc;
1545
1546 /* find out if crtc2 is in use or if this encoder is using it */
1547 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1548 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1549 if ((radeon_crtc->crtc_id == 1) && crtc->enabled) {
1550 if (encoder->crtc != crtc) {
1551 return connector_status_disconnected;
1552 }
1553 }
1554 }
1555
1556 if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO ||
1557 connector->connector_type == DRM_MODE_CONNECTOR_Composite ||
1558 connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) {
1559 bool tv_detect;
1560
1561 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT))
1562 return connector_status_disconnected;
1563
1564 tv_detect = radeon_legacy_tv_detect(encoder, connector);
1565 if (tv_detect && tv_dac)
1566 found = connector_status_connected;
1567 return found;
1568 }
1569
1570 /* don't probe if the encoder is being used for something else not CRT related */
1571 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) {
1572 DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device);
1573 return connector_status_disconnected;
1574 }
1575
1576 /* R200 uses an external DAC for secondary DAC */
1577 if (rdev->family == CHIP_R200) {
1578 if (radeon_legacy_ext_dac_detect(encoder, connector))
1579 found = connector_status_connected;
1580 return found;
1581 }
1582
1583 /* save the regs we need */
1584 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
1585
1586 if (rdev->flags & RADEON_SINGLE_CRTC) {
1587 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
1588 } else {
1589 if (ASIC_IS_R300(rdev)) {
1590 gpiopad_a = RREG32(RADEON_GPIOPAD_A);
1591 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1592 } else {
1593 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
1594 }
1595 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1596 }
1597 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1598 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1599 dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1600
1601 tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb
1602 | RADEON_PIX2CLK_DAC_ALWAYS_ONb);
1603 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
1604
1605 if (rdev->flags & RADEON_SINGLE_CRTC) {
1606 tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
1607 WREG32(RADEON_CRTC_EXT_CNTL, tmp);
1608 } else {
1609 tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
1610 tmp |= RADEON_CRTC2_CRT2_ON |
1611 (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT);
1612 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
1613
1614 if (ASIC_IS_R300(rdev)) {
1615 WREG32_P(RADEON_GPIOPAD_A, 1, ~1);
1616 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1617 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1618 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1619 } else {
1620 tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL;
1621 WREG32(RADEON_DISP_HW_DEBUG, tmp);
1622 }
1623 }
1624
1625 tmp = RADEON_TV_DAC_NBLANK |
1626 RADEON_TV_DAC_NHOLD |
1627 RADEON_TV_MONITOR_DETECT_EN |
1628 RADEON_TV_DAC_STD_PS2;
1629
1630 WREG32(RADEON_TV_DAC_CNTL, tmp);
1631
1632 tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN |
1633 RADEON_DAC2_FORCE_DATA_EN;
1634
1635 if (color)
1636 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
1637 else
1638 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
1639
1640 if (ASIC_IS_R300(rdev))
1641 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
1642 else
1643 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
1644
1645 WREG32(RADEON_DAC_EXT_CNTL, tmp);
1646
1647 tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN;
1648 WREG32(RADEON_DAC_CNTL2, tmp);
1649
1650 mdelay(10);
1651
1652 if (ASIC_IS_R300(rdev)) {
1653 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B)
1654 found = connector_status_connected;
1655 } else {
1656 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT)
1657 found = connector_status_connected;
1658 }
1659
1660 /* restore regs we used */
1661 WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1662 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1663 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1664
1665 if (rdev->flags & RADEON_SINGLE_CRTC) {
1666 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
1667 } else {
1668 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1669 if (ASIC_IS_R300(rdev)) {
1670 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1671 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1672 } else {
1673 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1674 }
1675 }
1676
1677 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
1678
1679 return found;
1680
1681 }
1682
1683 static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = {
1684 .dpms = radeon_legacy_tv_dac_dpms,
1685 .mode_fixup = radeon_legacy_mode_fixup,
1686 .prepare = radeon_legacy_tv_dac_prepare,
1687 .mode_set = radeon_legacy_tv_dac_mode_set,
1688 .commit = radeon_legacy_tv_dac_commit,
1689 .detect = radeon_legacy_tv_dac_detect,
1690 .disable = radeon_legacy_encoder_disable,
1691 };
1692
1693
1694 static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = {
1695 .destroy = radeon_enc_destroy,
1696 };
1697
1698
radeon_legacy_get_tmds_info(struct radeon_encoder * encoder)1699 static struct radeon_encoder_int_tmds *radeon_legacy_get_tmds_info(struct radeon_encoder *encoder)
1700 {
1701 struct drm_device *dev = encoder->base.dev;
1702 struct radeon_device *rdev = dev->dev_private;
1703 struct radeon_encoder_int_tmds *tmds = NULL;
1704 bool ret;
1705
1706 tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
1707
1708 if (!tmds)
1709 return NULL;
1710
1711 if (rdev->is_atom_bios)
1712 ret = radeon_atombios_get_tmds_info(encoder, tmds);
1713 else
1714 ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds);
1715
1716 if (!ret)
1717 radeon_legacy_get_tmds_info_from_table(encoder, tmds);
1718
1719 return tmds;
1720 }
1721
radeon_legacy_get_ext_tmds_info(struct radeon_encoder * encoder)1722 static struct radeon_encoder_ext_tmds *radeon_legacy_get_ext_tmds_info(struct radeon_encoder *encoder)
1723 {
1724 struct drm_device *dev = encoder->base.dev;
1725 struct radeon_device *rdev = dev->dev_private;
1726 struct radeon_encoder_ext_tmds *tmds = NULL;
1727 bool ret;
1728
1729 if (rdev->is_atom_bios)
1730 return NULL;
1731
1732 tmds = kzalloc(sizeof(struct radeon_encoder_ext_tmds), GFP_KERNEL);
1733
1734 if (!tmds)
1735 return NULL;
1736
1737 ret = radeon_legacy_get_ext_tmds_info_from_combios(encoder, tmds);
1738
1739 if (!ret)
1740 radeon_legacy_get_ext_tmds_info_from_table(encoder, tmds);
1741
1742 return tmds;
1743 }
1744
1745 void
radeon_add_legacy_encoder(struct drm_device * dev,uint32_t encoder_enum,uint32_t supported_device)1746 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device)
1747 {
1748 struct radeon_device *rdev = dev->dev_private;
1749 struct drm_encoder *encoder;
1750 struct radeon_encoder *radeon_encoder;
1751
1752 /* see if we already added it */
1753 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1754 radeon_encoder = to_radeon_encoder(encoder);
1755 if (radeon_encoder->encoder_enum == encoder_enum) {
1756 radeon_encoder->devices |= supported_device;
1757 return;
1758 }
1759
1760 }
1761
1762 /* add a new one */
1763 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1764 if (!radeon_encoder)
1765 return;
1766
1767 encoder = &radeon_encoder->base;
1768 if (rdev->flags & RADEON_SINGLE_CRTC)
1769 encoder->possible_crtcs = 0x1;
1770 else
1771 encoder->possible_crtcs = 0x3;
1772
1773 radeon_encoder->enc_priv = NULL;
1774
1775 radeon_encoder->encoder_enum = encoder_enum;
1776 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1777 radeon_encoder->devices = supported_device;
1778 radeon_encoder->rmx_type = RMX_OFF;
1779
1780 switch (radeon_encoder->encoder_id) {
1781 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1782 encoder->possible_crtcs = 0x1;
1783 drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs,
1784 DRM_MODE_ENCODER_LVDS, NULL);
1785 drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs);
1786 if (rdev->is_atom_bios)
1787 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1788 else
1789 radeon_encoder->enc_priv = radeon_combios_get_lvds_info(radeon_encoder);
1790 radeon_encoder->rmx_type = RMX_FULL;
1791 break;
1792 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1793 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs,
1794 DRM_MODE_ENCODER_TMDS, NULL);
1795 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs);
1796 radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder);
1797 break;
1798 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1799 drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs,
1800 DRM_MODE_ENCODER_DAC, NULL);
1801 drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs);
1802 if (rdev->is_atom_bios)
1803 radeon_encoder->enc_priv = radeon_atombios_get_primary_dac_info(radeon_encoder);
1804 else
1805 radeon_encoder->enc_priv = radeon_combios_get_primary_dac_info(radeon_encoder);
1806 break;
1807 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1808 drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs,
1809 DRM_MODE_ENCODER_TVDAC, NULL);
1810 drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs);
1811 if (rdev->is_atom_bios)
1812 radeon_encoder->enc_priv = radeon_atombios_get_tv_dac_info(radeon_encoder);
1813 else
1814 radeon_encoder->enc_priv = radeon_combios_get_tv_dac_info(radeon_encoder);
1815 break;
1816 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1817 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs,
1818 DRM_MODE_ENCODER_TMDS, NULL);
1819 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs);
1820 if (!rdev->is_atom_bios)
1821 radeon_encoder->enc_priv = radeon_legacy_get_ext_tmds_info(radeon_encoder);
1822 break;
1823 }
1824 }
1825