1 /*
2 tda18273.c - driver for the NXP TDA18273 silicon tuner
3 Copyright (C) 2014 CrazyCat <crazycat69@narod.ru>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/slab.h>
24 #include <linux/string.h>
25
26 #include "dvb_frontend.h"
27
28 #include "tda18273_priv.h"
29
30 static unsigned int verbose;
31 module_param(verbose, int, 0644);
32 MODULE_PARM_DESC(verbose, "Set Verbosity level");
33
34 #define FE_ERROR 0
35 #define FE_NOTICE 1
36 #define FE_INFO 2
37 #define FE_DEBUG 3
38 #define FE_DEBUGREG 4
39
40 #define dprintk(__y, __z, format, arg...) do { \
41 if (__z) { \
42 if ((verbose > FE_ERROR) && (verbose > __y)) \
43 printk(KERN_ERR "%s: " format "\n", __func__ , ##arg); \
44 else if ((verbose > FE_NOTICE) && (verbose > __y)) \
45 printk(KERN_NOTICE "%s: " format "\n", __func__ , ##arg); \
46 else if ((verbose > FE_INFO) && (verbose > __y)) \
47 printk(KERN_INFO "%s: " format "\n", __func__ , ##arg); \
48 else if ((verbose > FE_DEBUG) && (verbose > __y)) \
49 printk(KERN_DEBUG "%s: " format "\n", __func__ , ##arg); \
50 } else { \
51 if (verbose > __y) \
52 printk(format, ##arg); \
53 } \
54 } while (0)
55
56 #define TDA18273_REG_ADD_SZ (0x01)
57 #define TDA18273_REG_DATA_MAX_SZ (0x01)
58 #define TDA18273_REG_MAP_NB_BYTES (0x6D)
59
60 #define TDA18273_REG_DATA_LEN(_FIRST_REG, _LAST_REG) ( (_LAST_REG.Address - _FIRST_REG.Address) + 1)
61
62 struct tda18273_state {
63 struct dvb_frontend *fe;
64 struct i2c_adapter *i2c;
65 u8 i2c_addr;
66
67 unsigned int if_freq;
68 unsigned int freq_hz;
69 unsigned int bandwidth;
70 unsigned char freq_band;
71 unsigned char agc_mode;
72 unsigned char pll_step;
73 unsigned char pll_step_val;
74 unsigned char pll_charge_pump;
75
76 unsigned int power_state;
77 unsigned char regmap[TDA18273_REG_MAP_NB_BYTES];
78
79 pTDA18273Object_t pObj;
80 };
81
82 TDA18273Object_t gTDA18273Instance =
83 {
84 0,
85 0,
86 0,
87 TDA18273_StandardMode_Unknown,
88 NULL,
89 TDA18273_INSTANCE_CUSTOM_STD_DEF
90 };
91
92
93 /* TDA18273 Register ID_byte_1 0x00 */
94 const TDA18273_BitField_t gTDA18273_Reg_ID_byte_1 = { 0x00, 0x00, 0x08, 0x00 };
95 /* MS bit(s): Indicate if Device is a Master or a Slave */
96 /* 1 => Master device */
97 /* 0 => Slave device */
98 const TDA18273_BitField_t gTDA18273_Reg_ID_byte_1__MS = { 0x00, 0x07, 0x01, 0x00 };
99 /* Ident_1 bit(s): MSB of device identifier */
100 const TDA18273_BitField_t gTDA18273_Reg_ID_byte_1__Ident_1 = { 0x00, 0x00, 0x07, 0x00 };
101
102
103 /* TDA18273 Register ID_byte_2 0x01 */
104 const TDA18273_BitField_t gTDA18273_Reg_ID_byte_2 = { 0x01, 0x00, 0x08, 0x00 };
105 /* Ident_2 bit(s): LSB of device identifier */
106 const TDA18273_BitField_t gTDA18273_Reg_ID_byte_2__Ident_2 = { 0x01, 0x00, 0x08, 0x00 };
107
108
109 /* TDA18273 Register ID_byte_3 0x02 */
110 const TDA18273_BitField_t gTDA18273_Reg_ID_byte_3 = { 0x02, 0x00, 0x08, 0x00 };
111 /* Major_rev bit(s): Major revision of device */
112 const TDA18273_BitField_t gTDA18273_Reg_ID_byte_3__Major_rev = { 0x02, 0x04, 0x04, 0x00 };
113 /* Major_rev bit(s): Minor revision of device */
114 const TDA18273_BitField_t gTDA18273_Reg_ID_byte_3__Minor_rev = { 0x02, 0x00, 0x04, 0x00 };
115
116
117 /* TDA18273 Register Thermo_byte_1 0x03 */
118 const TDA18273_BitField_t gTDA18273_Reg_Thermo_byte_1 = { 0x03, 0x00, 0x08, 0x00 };
119 /* TM_D bit(s): Device temperature */
120 const TDA18273_BitField_t gTDA18273_Reg_Thermo_byte_1__TM_D = { 0x03, 0x00, 0x07, 0x00 };
121
122
123 /* TDA18273 Register Thermo_byte_2 0x04 */
124 const TDA18273_BitField_t gTDA18273_Reg_Thermo_byte_2 = { 0x04, 0x00, 0x08, 0x00 };
125 /* TM_ON bit(s): Set device temperature measurement to ON or OFF */
126 /* 1 => Temperature measurement ON */
127 /* 0 => Temperature measurement OFF */
128 const TDA18273_BitField_t gTDA18273_Reg_Thermo_byte_2__TM_ON = { 0x04, 0x00, 0x01, 0x00 };
129
130
131 /* TDA18273 Register Power_state_byte_1 0x05 */
132 const TDA18273_BitField_t gTDA18273_Reg_Power_state_byte_1 = { 0x05, 0x00, 0x08, 0x00 };
133 /* POR bit(s): Indicates that device just powered ON */
134 /* 1 => POR: No access done to device */
135 /* 0 => At least one access has been done to device */
136 const TDA18273_BitField_t gTDA18273_Reg_Power_state_byte_1__POR = { 0x05, 0x07, 0x01, 0x00 };
137 /* AGCs_Lock bit(s): Indicates that AGCs are locked */
138 /* 1 => AGCs locked */
139 /* 0 => AGCs not locked */
140 const TDA18273_BitField_t gTDA18273_Reg_Power_state_byte_1__AGCs_Lock = { 0x05, 0x02, 0x01, 0x00 };
141 /* Vsync_Lock bit(s): Indicates that VSync is locked */
142 /* 1 => VSync locked */
143 /* 0 => VSync not locked */
144 const TDA18273_BitField_t gTDA18273_Reg_Power_state_byte_1__Vsync_Lock = { 0x05, 0x01, 0x01, 0x00 };
145 /* LO_Lock bit(s): Indicates that LO is locked */
146 /* 1 => LO locked */
147 /* 0 => LO not locked */
148 const TDA18273_BitField_t gTDA18273_Reg_Power_state_byte_1__LO_Lock = { 0x05, 0x00, 0x01, 0x00 };
149
150
151 /* TDA18273 Register Power_state_byte_2 0x06 */
152 const TDA18273_BitField_t gTDA18273_Reg_Power_state_byte_2 = { 0x06, 0x00, 0x08, 0x00 };
153 /* SM bit(s): */
154 const TDA18273_BitField_t gTDA18273_Reg_Power_state_byte_2__SM = { 0x06, 0x01, 0x01, 0x00 };
155 /* SM_XT bit(s): */
156 const TDA18273_BitField_t gTDA18273_Reg_Power_state_byte_2__SM_XT = { 0x06, 0x00, 0x01, 0x00 };
157
158
159 /* TDA18273 Register Input_Power_Level_byte 0x07 */
160 const TDA18273_BitField_t gTDA18273_Reg_Input_Power_Level_byte = { 0x07, 0x00, 0x08, 0x00 };
161 /* Power_Level bit(s): */
162 const TDA18273_BitField_t gTDA18273_Reg_Input_Power_Level_byte__Power_Level = { 0x07, 0x00, 0x08, 0x00 };
163
164
165 /* TDA18273 Register IRQ_status 0x08 */
166 const TDA18273_BitField_t gTDA18273_Reg_IRQ_status = { 0x08, 0x00, 0x08, 0x00 };
167 /* IRQ_status bit(s): */
168 const TDA18273_BitField_t gTDA18273_Reg_IRQ_status__IRQ_status = { 0x08, 0x07, 0x01, 0x00 };
169 /* MSM_XtalCal_End bit(s): */
170 const TDA18273_BitField_t gTDA18273_Reg_IRQ_status__MSM_XtalCal_End = { 0x08, 0x05, 0x01, 0x00 };
171 /* MSM_RSSI_End bit(s): */
172 const TDA18273_BitField_t gTDA18273_Reg_IRQ_status__MSM_RSSI_End = { 0x08, 0x04, 0x01, 0x00 };
173 /* MSM_LOCalc_End bit(s): */
174 const TDA18273_BitField_t gTDA18273_Reg_IRQ_status__MSM_LOCalc_End = { 0x08, 0x03, 0x01, 0x00 };
175 /* MSM_RFCal_End bit(s): */
176 const TDA18273_BitField_t gTDA18273_Reg_IRQ_status__MSM_RFCal_End = { 0x08, 0x02, 0x01, 0x00 };
177 /* MSM_IRCAL_End bit(s): */
178 const TDA18273_BitField_t gTDA18273_Reg_IRQ_status__MSM_IRCAL_End = { 0x08, 0x01, 0x01, 0x00 };
179 /* MSM_RCCal_End bit(s): */
180 const TDA18273_BitField_t gTDA18273_Reg_IRQ_status__MSM_RCCal_End = { 0x08, 0x00, 0x01, 0x00 };
181
182
183 /* TDA18273 Register IRQ_enable 0x09 */
184 const TDA18273_BitField_t gTDA18273_Reg_IRQ_enable = { 0x09, 0x00, 0x08, 0x00 };
185 /* IRQ_Enable bit(s): */
186 const TDA18273_BitField_t gTDA18273_Reg_IRQ_enable__IRQ_Enable = { 0x09, 0x07, 0x01, 0x00 };
187 /* MSM_XtalCal_Enable bit(s): */
188 const TDA18273_BitField_t gTDA18273_Reg_IRQ_enable__MSM_XtalCal_Enable = { 0x09, 0x05, 0x01, 0x00 };
189 /* MSM_RSSI_Enable bit(s): */
190 const TDA18273_BitField_t gTDA18273_Reg_IRQ_enable__MSM_RSSI_Enable = { 0x09, 0x04, 0x01, 0x00 };
191 /* MSM_LOCalc_Enable bit(s): */
192 const TDA18273_BitField_t gTDA18273_Reg_IRQ_enable__MSM_LOCalc_Enable = { 0x09, 0x03, 0x01, 0x00 };
193 /* MSM_RFCal_Enable bit(s): */
194 const TDA18273_BitField_t gTDA18273_Reg_IRQ_enable__MSM_RFCal_Enable = { 0x09, 0x02, 0x01, 0x00 };
195 /* MSM_IRCAL_Enable bit(s): */
196 const TDA18273_BitField_t gTDA18273_Reg_IRQ_enable__MSM_IRCAL_Enable = { 0x09, 0x01, 0x01, 0x00 };
197 /* MSM_RCCal_Enable bit(s): */
198 const TDA18273_BitField_t gTDA18273_Reg_IRQ_enable__MSM_RCCal_Enable = { 0x09, 0x00, 0x01, 0x00 };
199
200
201 /* TDA18273 Register IRQ_clear 0x0A */
202 const TDA18273_BitField_t gTDA18273_Reg_IRQ_clear = { 0x0A, 0x00, 0x08, 0x00 };
203 /* IRQ_Clear bit(s): */
204 const TDA18273_BitField_t gTDA18273_Reg_IRQ_clear__IRQ_Clear = { 0x0A, 0x07, 0x01, 0x00 };
205 /* MSM_XtalCal_Clear bit(s): */
206 const TDA18273_BitField_t gTDA18273_Reg_IRQ_clear__MSM_XtalCal_Clear = { 0x0A, 0x05, 0x01, 0x00 };
207 /* MSM_RSSI_Clear bit(s): */
208 const TDA18273_BitField_t gTDA18273_Reg_IRQ_clear__MSM_RSSI_Clear = { 0x0A, 0x04, 0x01, 0x00 };
209 /* MSM_LOCalc_Clear bit(s): */
210 const TDA18273_BitField_t gTDA18273_Reg_IRQ_clear__MSM_LOCalc_Clear = { 0x0A, 0x03, 0x01, 0x00 };
211 /* MSM_RFCal_Clear bit(s): */
212 const TDA18273_BitField_t gTDA18273_Reg_IRQ_clear__MSM_RFCal_Clear = { 0x0A, 0x02, 0x01, 0x00 };
213 /* MSM_IRCAL_Clear bit(s): */
214 const TDA18273_BitField_t gTDA18273_Reg_IRQ_clear__MSM_IRCAL_Clear = { 0x0A, 0x01, 0x01, 0x00 };
215 /* MSM_RCCal_Clear bit(s): */
216 const TDA18273_BitField_t gTDA18273_Reg_IRQ_clear__MSM_RCCal_Clear = { 0x0A, 0x00, 0x01, 0x00 };
217
218
219 /* TDA18273 Register IRQ_set 0x0B */
220 const TDA18273_BitField_t gTDA18273_Reg_IRQ_set = { 0x0B, 0x00, 0x08, 0x00 };
221 /* IRQ_Set bit(s): */
222 const TDA18273_BitField_t gTDA18273_Reg_IRQ_set__IRQ_Set = { 0x0B, 0x07, 0x01, 0x00 };
223 /* MSM_XtalCal_Set bit(s): */
224 const TDA18273_BitField_t gTDA18273_Reg_IRQ_set__MSM_XtalCal_Set = { 0x0B, 0x05, 0x01, 0x00 };
225 /* MSM_RSSI_Set bit(s): */
226 const TDA18273_BitField_t gTDA18273_Reg_IRQ_set__MSM_RSSI_Set = { 0x0B, 0x04, 0x01, 0x00 };
227 /* MSM_LOCalc_Set bit(s): */
228 const TDA18273_BitField_t gTDA18273_Reg_IRQ_set__MSM_LOCalc_Set = { 0x0B, 0x03, 0x01, 0x00 };
229 /* MSM_RFCal_Set bit(s): */
230 const TDA18273_BitField_t gTDA18273_Reg_IRQ_set__MSM_RFCal_Set = { 0x0B, 0x02, 0x01, 0x00 };
231 /* MSM_IRCAL_Set bit(s): */
232 const TDA18273_BitField_t gTDA18273_Reg_IRQ_set__MSM_IRCAL_Set = { 0x0B, 0x01, 0x01, 0x00 };
233 /* MSM_RCCal_Set bit(s): */
234 const TDA18273_BitField_t gTDA18273_Reg_IRQ_set__MSM_RCCal_Set = { 0x0B, 0x00, 0x01, 0x00 };
235
236
237 /* TDA18273 Register AGC1_byte_1 0x0C */
238 const TDA18273_BitField_t gTDA18273_Reg_AGC1_byte_1 = { 0x0C, 0x00, 0x08, 0x00 };
239 /* AGC1_TOP bit(s): */
240 const TDA18273_BitField_t gTDA18273_Reg_AGC1_byte_1__AGC1_TOP = { 0x0C, 0x00, 0x04, 0x00 };
241
242
243 /* TDA18273 Register AGC1_byte_2 0x0D */
244 const TDA18273_BitField_t gTDA18273_Reg_AGC1_byte_2 = { 0x0D, 0x00, 0x08, 0x00 };
245 /* AGC1_Top_Mode_Val bit(s): */
246 const TDA18273_BitField_t gTDA18273_Reg_AGC1_byte_2__AGC1_Top_Mode_Val = { 0x0D, 0x03, 0x02, 0x00 };
247 /* AGC1_Top_Mode bit(s): */
248 const TDA18273_BitField_t gTDA18273_Reg_AGC1_byte_2__AGC1_Top_Mode = { 0x0D, 0x00, 0x03, 0x00 };
249
250
251 /* TDA18273 Register AGC2_byte_1 0x0E */
252 const TDA18273_BitField_t gTDA18273_Reg_AGC2_byte_1 = { 0x0E, 0x00, 0x08, 0x00 };
253 /* AGC2_TOP bit(s): */
254 const TDA18273_BitField_t gTDA18273_Reg_AGC2_byte_1__AGC2_TOP = { 0x0E, 0x00, 0x03, 0x00 };
255
256
257 /* TDA18273 Register AGCK_byte_1 0x0F */
258 const TDA18273_BitField_t gTDA18273_Reg_AGCK_byte_1 = { 0x0F, 0x00, 0x08, 0x00 };
259 /* AGCs_Up_Step_assym bit(s): */
260 const TDA18273_BitField_t gTDA18273_Reg_AGCK_byte_1__AGCs_Up_Step_assym = { 0x0F, 0x06, 0x02, 0x00 };
261 /* Pulse_Shaper_Disable bit(s): */
262 const TDA18273_BitField_t gTDA18273_Reg_AGCK_byte_1__Pulse_Shaper_Disable = { 0x0F, 0x04, 0x01, 0x00 };
263 /* AGCK_Step bit(s): */
264 const TDA18273_BitField_t gTDA18273_Reg_AGCK_byte_1__AGCK_Step = { 0x0F, 0x02, 0x02, 0x00 };
265 /* AGCK_Mode bit(s): */
266 const TDA18273_BitField_t gTDA18273_Reg_AGCK_byte_1__AGCK_Mode = { 0x0F, 0x00, 0x02, 0x00 };
267
268
269 /* TDA18273 Register RF_AGC_byte 0x10 */
270 const TDA18273_BitField_t gTDA18273_Reg_RF_AGC_byte = { 0x10, 0x00, 0x08, 0x00 };
271 /* PD_AGC_Adapt3x bit(s): */
272 const TDA18273_BitField_t gTDA18273_Reg_RF_AGC_byte__PD_AGC_Adapt3x = { 0x10, 0x06, 0x02, 0x00 };
273 /* RFAGC_Adapt_TOP bit(s): */
274 const TDA18273_BitField_t gTDA18273_Reg_RF_AGC_byte__RFAGC_Adapt_TOP = { 0x10, 0x04, 0x02, 0x00 };
275 /* RFAGC_Low_BW bit(s): */
276 const TDA18273_BitField_t gTDA18273_Reg_RF_AGC_byte__RFAGC_Low_BW = { 0x10, 0x03, 0x01, 0x00 };
277 /* RFAGC_Top bit(s): */
278 const TDA18273_BitField_t gTDA18273_Reg_RF_AGC_byte__RFAGC_Top = { 0x10, 0x00, 0x03, 0x00 };
279
280
281 /* TDA18273 Register W_Filter_byte 0x11 */
282 const TDA18273_BitField_t gTDA18273_Reg_W_Filter_byte = { 0x11, 0x00, 0x08, 0x00 };
283 /* VHF_III_mode bit(s): */
284 const TDA18273_BitField_t gTDA18273_Reg_W_Filter_byte__VHF_III_mode = { 0x11, 0x07, 0x01, 0x00 };
285 /* RF_Atten_3dB bit(s): */
286 const TDA18273_BitField_t gTDA18273_Reg_W_Filter_byte__RF_Atten_3dB = { 0x11, 0x06, 0x01, 0x00 };
287 /* W_Filter_Enable bit(s): */
288 const TDA18273_BitField_t gTDA18273_Reg_W_Filter_byte__W_Filter_Enable = { 0x11, 0x05, 0x01, 0x00 };
289 /* W_Filter_Bypass bit(s): */
290 const TDA18273_BitField_t gTDA18273_Reg_W_Filter_byte__W_Filter_Bypass = { 0x11, 0x04, 0x01, 0x00 };
291 /* W_Filter bit(s): */
292 const TDA18273_BitField_t gTDA18273_Reg_W_Filter_byte__W_Filter = { 0x11, 0x02, 0x02, 0x00 };
293 /* W_Filter_Offset bit(s): */
294 const TDA18273_BitField_t gTDA18273_Reg_W_Filter_byte__W_Filter_Offset = { 0x11, 0x00, 0x02, 0x00 };
295
296
297 /* TDA18273 Register IR_Mixer_byte_1 0x12 */
298 const TDA18273_BitField_t gTDA18273_Reg_IR_Mixer_byte_1 = { 0x12, 0x00, 0x08, 0x00 };
299 /* S2D_Gain bit(s): */
300 const TDA18273_BitField_t gTDA18273_Reg_IR_Mixer_byte_1__S2D_Gain = { 0x12, 0x04, 0x02, 0x00 };
301 /* IR_Mixer_Top bit(s): */
302 const TDA18273_BitField_t gTDA18273_Reg_IR_Mixer_byte_1__IR_Mixer_Top = { 0x12, 0x00, 0x04, 0x00 };
303
304
305 /* TDA18273 Register AGC5_byte_1 0x13 */
306 const TDA18273_BitField_t gTDA18273_Reg_AGC5_byte_1 = { 0x13, 0x00, 0x08, 0x00 };
307 /* AGCs_Do_Step_assym bit(s): */
308 const TDA18273_BitField_t gTDA18273_Reg_AGC5_byte_1__AGCs_Do_Step_assym = { 0x13, 0x05, 0x02, 0x00 };
309 /* AGC5_Ana bit(s): */
310 const TDA18273_BitField_t gTDA18273_Reg_AGC5_byte_1__AGC5_Ana = { 0x13, 0x04, 0x01, 0x00 };
311 /* AGC5_TOP bit(s): */
312 const TDA18273_BitField_t gTDA18273_Reg_AGC5_byte_1__AGC5_TOP = { 0x13, 0x00, 0x04, 0x00 };
313
314
315 /* TDA18273 Register IF_AGC_byte 0x14 */
316 const TDA18273_BitField_t gTDA18273_Reg_IF_AGC_byte = { 0x14, 0x00, 0x08, 0x00 };
317 /* IFnotchToRSSI bit(s): */
318 const TDA18273_BitField_t gTDA18273_Reg_IF_AGC_byte__IFnotchToRSSI = { 0x14, 0x07, 0x01, 0x00 };
319 /* LPF_DCOffset_Corr bit(s): */
320 const TDA18273_BitField_t gTDA18273_Reg_IF_AGC_byte__LPF_DCOffset_Corr = { 0x14, 0x06, 0x01, 0x00 };
321 /* IF_level bit(s): */
322 const TDA18273_BitField_t gTDA18273_Reg_IF_AGC_byte__IF_level = { 0x14, 0x00, 0x03, 0x00 };
323
324
325 /* TDA18273 Register IF_Byte_1 0x15 */
326 const TDA18273_BitField_t gTDA18273_Reg_IF_Byte_1 = { 0x15, 0x00, 0x08, 0x00 };
327 /* IF_HP_Fc bit(s): */
328 const TDA18273_BitField_t gTDA18273_Reg_IF_Byte_1__IF_HP_Fc = { 0x15, 0x06, 0x02, 0x00 };
329 /* IF_ATSC_Notch bit(s): */
330 const TDA18273_BitField_t gTDA18273_Reg_IF_Byte_1__IF_ATSC_Notch = { 0x15, 0x05, 0x01, 0x00 };
331 /* LP_FC_Offset bit(s): */
332 const TDA18273_BitField_t gTDA18273_Reg_IF_Byte_1__LP_FC_Offset = { 0x15, 0x03, 0x02, 0x00 };
333 /* LP_Fc bit(s): */
334 const TDA18273_BitField_t gTDA18273_Reg_IF_Byte_1__LP_Fc = { 0x15, 0x00, 0x03, 0x00 };
335
336
337 /* TDA18273 Register Reference_Byte 0x16 */
338 const TDA18273_BitField_t gTDA18273_Reg_Reference_Byte = { 0x16, 0x00, 0x08, 0x00 };
339 /* Digital_Clock_Mode bit(s): */
340 const TDA18273_BitField_t gTDA18273_Reg_Reference_Byte__Digital_Clock_Mode = { 0x16, 0x06, 0x02, 0x00 };
341 /* XTout bit(s): */
342 const TDA18273_BitField_t gTDA18273_Reg_Reference_Byte__XTout = { 0x16, 0x00, 0x02, 0x00 };
343
344
345 /* TDA18273 Register IF_Frequency_byte 0x17 */
346 const TDA18273_BitField_t gTDA18273_Reg_IF_Frequency_byte = { 0x17, 0x00, 0x08, 0x00 };
347 /* IF_Freq bit(s): */
348 const TDA18273_BitField_t gTDA18273_Reg_IF_Frequency_byte__IF_Freq = { 0x17, 0x00, 0x08, 0x00 };
349
350
351 /* TDA18273 Register RF_Frequency_byte_1 0x18 */
352 const TDA18273_BitField_t gTDA18273_Reg_RF_Frequency_byte_1 = { 0x18, 0x00, 0x08, 0x00 };
353 /* RF_Freq_1 bit(s): */
354 const TDA18273_BitField_t gTDA18273_Reg_RF_Frequency_byte_1__RF_Freq_1 = { 0x18, 0x00, 0x04, 0x00 };
355
356
357 /* TDA18273 Register RF_Frequency_byte_2 0x19 */
358 const TDA18273_BitField_t gTDA18273_Reg_RF_Frequency_byte_2 = { 0x19, 0x00, 0x08, 0x00 };
359 /* RF_Freq_2 bit(s): */
360 const TDA18273_BitField_t gTDA18273_Reg_RF_Frequency_byte_2__RF_Freq_2 = { 0x19, 0x00, 0x08, 0x00 };
361
362
363 /* TDA18273 Register RF_Frequency_byte_3 0x1A */
364 const TDA18273_BitField_t gTDA18273_Reg_RF_Frequency_byte_3 = { 0x1A, 0x00, 0x08, 0x00 };
365 /* RF_Freq_3 bit(s): */
366 const TDA18273_BitField_t gTDA18273_Reg_RF_Frequency_byte_3__RF_Freq_3 = { 0x1A, 0x00, 0x08, 0x00 };
367
368
369 /* TDA18273 Register MSM_byte_1 0x1B */
370 const TDA18273_BitField_t gTDA18273_Reg_MSM_byte_1 = { 0x1B, 0x00, 0x08, 0x00 };
371 /* RSSI_Meas bit(s): */
372 const TDA18273_BitField_t gTDA18273_Reg_MSM_byte_1__RSSI_Meas = { 0x1B, 0x07, 0x01, 0x00 };
373 /* RF_CAL_AV bit(s): */
374 const TDA18273_BitField_t gTDA18273_Reg_MSM_byte_1__RF_CAL_AV = { 0x1B, 0x06, 0x01, 0x00 };
375 /* RF_CAL bit(s): */
376 const TDA18273_BitField_t gTDA18273_Reg_MSM_byte_1__RF_CAL = { 0x1B, 0x05, 0x01, 0x00 };
377 /* IR_CAL_Loop bit(s): */
378 const TDA18273_BitField_t gTDA18273_Reg_MSM_byte_1__IR_CAL_Loop = { 0x1B, 0x04, 0x01, 0x00 };
379 /* IR_Cal_Image bit(s): */
380 const TDA18273_BitField_t gTDA18273_Reg_MSM_byte_1__IR_Cal_Image = { 0x1B, 0x03, 0x01, 0x00 };
381 /* IR_CAL_Wanted bit(s): */
382 const TDA18273_BitField_t gTDA18273_Reg_MSM_byte_1__IR_CAL_Wanted = { 0x1B, 0x02, 0x01, 0x00 };
383 /* RC_Cal bit(s): */
384 const TDA18273_BitField_t gTDA18273_Reg_MSM_byte_1__RC_Cal = { 0x1B, 0x01, 0x01, 0x00 };
385 /* Calc_PLL bit(s): */
386 const TDA18273_BitField_t gTDA18273_Reg_MSM_byte_1__Calc_PLL = { 0x1B, 0x00, 0x01, 0x00 };
387
388
389 /* TDA18273 Register MSM_byte_2 0x1C */
390 const TDA18273_BitField_t gTDA18273_Reg_MSM_byte_2 = { 0x1C, 0x00, 0x08, 0x00 };
391 /* XtalCal_Launch bit(s): */
392 const TDA18273_BitField_t gTDA18273_Reg_MSM_byte_2__XtalCal_Launch = { 0x1C, 0x01, 0x01, 0x00 };
393 /* MSM_Launch bit(s): */
394 const TDA18273_BitField_t gTDA18273_Reg_MSM_byte_2__MSM_Launch = { 0x1C, 0x00, 0x01, 0x00 };
395
396
397 /* TDA18273 Register PowerSavingMode 0x1D */
398 const TDA18273_BitField_t gTDA18273_Reg_PowerSavingMode = { 0x1D, 0x00, 0x08, 0x00 };
399 /* PSM_AGC1 bit(s): */
400 const TDA18273_BitField_t gTDA18273_Reg_PowerSavingMode__PSM_AGC1 = { 0x1D, 0x07, 0x01, 0x00 };
401 /* PSM_Bandsplit_Filter bit(s): */
402 const TDA18273_BitField_t gTDA18273_Reg_PowerSavingMode__PSM_Bandsplit_Filter = { 0x1D, 0x05, 0x02, 0x00 };
403 /* PSM_RFpoly bit(s): */
404 const TDA18273_BitField_t gTDA18273_Reg_PowerSavingMode__PSM_RFpoly = { 0x1D, 0x04, 0x01, 0x00 };
405 /* PSM_Mixer bit(s): */
406 const TDA18273_BitField_t gTDA18273_Reg_PowerSavingMode__PSM_Mixer = { 0x1D, 0x03, 0x01, 0x00 };
407 /* PSM_Ifpoly bit(s): */
408 const TDA18273_BitField_t gTDA18273_Reg_PowerSavingMode__PSM_Ifpoly = { 0x1D, 0x02, 0x01, 0x00 };
409 /* PSM_Lodriver bit(s): */
410 const TDA18273_BitField_t gTDA18273_Reg_PowerSavingMode__PSM_Lodriver = { 0x1D, 0x00, 0x02, 0x00 };
411
412
413 /* TDA18273 Register Power_Level_byte_2 0x1E */
414 const TDA18273_BitField_t gTDA18273_Reg_Power_Level_byte_2 = { 0x1E, 0x00, 0x08, 0x00 };
415 /* PD_PLD_read bit(s): */
416 const TDA18273_BitField_t gTDA18273_Reg_Power_Level_byte_2__PD_PLD_read = { 0x1E, 0x07, 0x01, 0x00 };
417 /* IR_Target bit(s): */
418 const TDA18273_BitField_t gTDA18273_Reg_Power_Level_byte_2__PLD_Temp_Slope = { 0x1E, 0x05, 0x02, 0x00 };
419 /* IR_GStep bit(s): */
420 const TDA18273_BitField_t gTDA18273_Reg_Power_Level_byte_2__PLD_Gain_Corr = { 0x1E, 0x00, 0x05, 0x00 };
421
422
423 /* TDA18273 Register Adapt_Top_byte 0x1F */
424 const TDA18273_BitField_t gTDA18273_Reg_Adapt_Top_byte = { 0x1F, 0x00, 0x08, 0x00 };
425 /* Fast_Mode_AGC bit(s): */
426 const TDA18273_BitField_t gTDA18273_Reg_Adapt_Top_byte__Fast_Mode_AGC = { 0x1F, 0x06, 0x01, 0x00 };
427 /* Range_LNA_Adapt bit(s): */
428 const TDA18273_BitField_t gTDA18273_Reg_Adapt_Top_byte__Range_LNA_Adapt = { 0x1F, 0x05, 0x01, 0x00 };
429 /* Index_K_LNA_Adapt bit(s): */
430 const TDA18273_BitField_t gTDA18273_Reg_Adapt_Top_byte__Index_K_LNA_Adapt = { 0x1F, 0x03, 0x02, 0x00 };
431 /* Index_K_Top_Adapt bit(s): */
432 const TDA18273_BitField_t gTDA18273_Reg_Adapt_Top_byte__Index_K_Top_Adapt = { 0x1F, 0x01, 0x02, 0x00 };
433 /* Ovld_Udld_FastUp bit(s): */
434 const TDA18273_BitField_t gTDA18273_Reg_Adapt_Top_byte__Ovld_Udld_FastUp = { 0x1F, 0x00, 0x01, 0x00 };
435
436
437 /* TDA18273 Register Vsync_byte 0x20 */
438 const TDA18273_BitField_t gTDA18273_Reg_Vsync_byte = { 0x20, 0x00, 0x08, 0x00 };
439 /* Neg_modulation bit(s): */
440 const TDA18273_BitField_t gTDA18273_Reg_Vsync_byte__Neg_modulation = { 0x20, 0x07, 0x01, 0x00 };
441 /* Tracer_Step bit(s): */
442 const TDA18273_BitField_t gTDA18273_Reg_Vsync_byte__Tracer_Step = { 0x20, 0x05, 0x02, 0x00 };
443 /* Vsync_int bit(s): */
444 const TDA18273_BitField_t gTDA18273_Reg_Vsync_byte__Vsync_int = { 0x20, 0x04, 0x01, 0x00 };
445 /* Vsync_Thresh bit(s): */
446 const TDA18273_BitField_t gTDA18273_Reg_Vsync_byte__Vsync_Thresh = { 0x20, 0x02, 0x02, 0x00 };
447 /* Vsync_Len bit(s): */
448 const TDA18273_BitField_t gTDA18273_Reg_Vsync_byte__Vsync_Len = { 0x20, 0x00, 0x02, 0x00 };
449
450
451 /* TDA18273 Register Vsync_Mgt_byte 0x21 */
452 const TDA18273_BitField_t gTDA18273_Reg_Vsync_Mgt_byte = { 0x21, 0x00, 0x08, 0x00 };
453 /* PD_Vsync_Mgt bit(s): */
454 const TDA18273_BitField_t gTDA18273_Reg_Vsync_Mgt_byte__PD_Vsync_Mgt = { 0x21, 0x07, 0x01, 0x00 };
455 /* PD_Ovld bit(s): */
456 const TDA18273_BitField_t gTDA18273_Reg_Vsync_Mgt_byte__PD_Ovld = { 0x21, 0x06, 0x01, 0x00 };
457 /* PD_Ovld_RF bit(s): */
458 const TDA18273_BitField_t gTDA18273_Reg_Vsync_Mgt_byte__PD_Ovld_RF = { 0x21, 0x05, 0x01, 0x00 };
459 /* AGC_Ovld_TOP bit(s): */
460 const TDA18273_BitField_t gTDA18273_Reg_Vsync_Mgt_byte__AGC_Ovld_TOP = { 0x21, 0x02, 0x03, 0x00 };
461 /* Up_Step_Ovld bit(s): */
462 const TDA18273_BitField_t gTDA18273_Reg_Vsync_Mgt_byte__Up_Step_Ovld = { 0x21, 0x01, 0x01, 0x00 };
463 /* AGC_Ovld_Timer bit(s): */
464 const TDA18273_BitField_t gTDA18273_Reg_Vsync_Mgt_byte__AGC_Ovld_Timer = { 0x21, 0x00, 0x01, 0x00 };
465
466
467 /* TDA18273 Register IR_Mixer_byte_2 0x22 */
468 const TDA18273_BitField_t gTDA18273_Reg_IR_Mixer_byte_2 = { 0x22, 0x00, 0x08, 0x00 };
469 /* IR_Mixer_loop_off bit(s): */
470 const TDA18273_BitField_t gTDA18273_Reg_IR_Mixer_byte_2__IR_Mixer_loop_off = { 0x22, 0x07, 0x01, 0x00 };
471 /* IR_Mixer_Do_step bit(s): */
472 const TDA18273_BitField_t gTDA18273_Reg_IR_Mixer_byte_2__IR_Mixer_Do_step = { 0x22, 0x05, 0x02, 0x00 };
473 /* Hi_Pass bit(s): */
474 const TDA18273_BitField_t gTDA18273_Reg_IR_Mixer_byte_2__Hi_Pass = { 0x22, 0x01, 0x01, 0x00 };
475 /* IF_Notch bit(s): */
476 const TDA18273_BitField_t gTDA18273_Reg_IR_Mixer_byte_2__IF_Notch = { 0x22, 0x00, 0x01, 0x00 };
477
478
479 /* TDA18273 Register AGC1_byte_3 0x23 */
480 const TDA18273_BitField_t gTDA18273_Reg_AGC1_byte_3 = { 0x23, 0x00, 0x08, 0x00 };
481 /* AGC1_loop_off bit(s): */
482 const TDA18273_BitField_t gTDA18273_Reg_AGC1_byte_3__AGC1_loop_off = { 0x23, 0x07, 0x01, 0x00 };
483 /* AGC1_Do_step bit(s): */
484 const TDA18273_BitField_t gTDA18273_Reg_AGC1_byte_3__AGC1_Do_step = { 0x23, 0x05, 0x02, 0x00 };
485 /* Force_AGC1_gain bit(s): */
486 const TDA18273_BitField_t gTDA18273_Reg_AGC1_byte_3__Force_AGC1_gain = { 0x23, 0x04, 0x01, 0x00 };
487 /* AGC1_Gain bit(s): */
488 const TDA18273_BitField_t gTDA18273_Reg_AGC1_byte_3__AGC1_Gain = { 0x23, 0x00, 0x04, 0x00 };
489
490
491 /* TDA18273 Register RFAGCs_Gain_byte_1 0x24 */
492 const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_1 = { 0x24, 0x00, 0x08, 0x00 };
493 /* PLD_DAC_Scale bit(s): */
494 const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_1__PLD_DAC_Scale = { 0x24, 0x07, 0x01, 0x00 };
495 /* PLD_CC_Enable bit(s): */
496 const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_1__PLD_CC_Enable = { 0x24, 0x06, 0x01, 0x00 };
497 /* PLD_Temp_Enable bit(s): */
498 const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_1__PLD_Temp_Enable = { 0x24, 0x05, 0x01, 0x00 };
499 /* TH_AGC_Adapt34 bit(s): */
500 const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_1__TH_AGC_Adapt34 = { 0x24, 0x04, 0x01, 0x00 };
501 /* RFAGC_Sense_Enable bit(s): */
502 const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_1__RFAGC_Sense_Enable = { 0x24, 0x02, 0x01, 0x00 };
503 /* RFAGC_K_Bypass bit(s): */
504 const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_1__RFAGC_K_Bypass = { 0x24, 0x01, 0x01, 0x00 };
505 /* RFAGC_K_8 bit(s): */
506 const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_1__RFAGC_K_8 = { 0x24, 0x00, 0x01, 0x00 };
507
508
509 /* TDA18273 Register RFAGCs_Gain_byte_2 0x25 */
510 const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_2 = { 0x25, 0x00, 0x08, 0x00 };
511 /* RFAGC_K bit(s): */
512 const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_2__RFAGC_K = { 0x25, 0x00, 0x08, 0x00 };
513
514
515 /* TDA18273 Register AGC5_byte_2 0x26 */
516 const TDA18273_BitField_t gTDA18273_Reg_AGC5_byte_2 = { 0x26, 0x00, 0x08, 0x00 };
517 /* AGC5_loop_off bit(s): */
518 const TDA18273_BitField_t gTDA18273_Reg_AGC5_byte_2__AGC5_loop_off = { 0x26, 0x07, 0x01, 0x00 };
519 /* AGC5_Do_step bit(s): */
520 const TDA18273_BitField_t gTDA18273_Reg_AGC5_byte_2__AGC5_Do_step = { 0x26, 0x05, 0x02, 0x00 };
521 /* Force_AGC5_gain bit(s): */
522 const TDA18273_BitField_t gTDA18273_Reg_AGC5_byte_2__Force_AGC5_gain = { 0x26, 0x03, 0x01, 0x00 };
523 /* AGC5_Gain bit(s): */
524 const TDA18273_BitField_t gTDA18273_Reg_AGC5_byte_2__AGC5_Gain = { 0x26, 0x00, 0x03, 0x00 };
525
526
527 /* TDA18273 Register RF_Cal_byte_1 0x27 */
528 const TDA18273_BitField_t gTDA18273_Reg_RF_Cal_byte_1 = { 0x27, 0x00, 0x08, 0x00 };
529 /* RFCAL_Offset_Cprog0 bit(s): */
530 const TDA18273_BitField_t gTDA18273_Reg_RF_Cal_byte_1__RFCAL_Offset_Cprog0 = { 0x27, 0x06, 0x02, 0x00 };
531 /* RFCAL_Offset_Cprog1 bit(s): */
532 const TDA18273_BitField_t gTDA18273_Reg_RF_Cal_byte_1__RFCAL_Offset_Cprog1 = { 0x27, 0x04, 0x02, 0x00 };
533 /* RFCAL_Offset_Cprog2 bit(s): */
534 const TDA18273_BitField_t gTDA18273_Reg_RF_Cal_byte_1__RFCAL_Offset_Cprog2 = { 0x27, 0x02, 0x02, 0x00 };
535 /* RFCAL_Offset_Cprog3 bit(s): */
536 const TDA18273_BitField_t gTDA18273_Reg_RF_Cal_byte_1__RFCAL_Offset_Cprog3 = { 0x27, 0x00, 0x02, 0x00 };
537
538
539 /* TDA18273 Register RF_Cal_byte_2 0x28 */
540 const TDA18273_BitField_t gTDA18273_Reg_RF_Cal_byte_2 = { 0x28, 0x00, 0x08, 0x00 };
541 /* RFCAL_Offset_Cprog4 bit(s): */
542 const TDA18273_BitField_t gTDA18273_Reg_RF_Cal_byte_2__RFCAL_Offset_Cprog4 = { 0x28, 0x06, 0x02, 0x00 };
543 /* RFCAL_Offset_Cprog5 bit(s): */
544 const TDA18273_BitField_t gTDA18273_Reg_RF_Cal_byte_2__RFCAL_Offset_Cprog5 = { 0x28, 0x04, 0x02, 0x00 };
545 /* RFCAL_Offset_Cprog6 bit(s): */
546 const TDA18273_BitField_t gTDA18273_Reg_RF_Cal_byte_2__RFCAL_Offset_Cprog6 = { 0x28, 0x02, 0x02, 0x00 };
547 /* RFCAL_Offset_Cprog7 bit(s): */
548 const TDA18273_BitField_t gTDA18273_Reg_RF_Cal_byte_2__RFCAL_Offset_Cprog7 = { 0x28, 0x00, 0x02, 0x00 };
549
550
551 /* TDA18273 Register RF_Cal_byte_3 0x29 */
552 const TDA18273_BitField_t gTDA18273_Reg_RF_Cal_byte_3 = { 0x29, 0x00, 0x08, 0x00 };
553 /* RFCAL_Offset_Cprog8 bit(s): */
554 const TDA18273_BitField_t gTDA18273_Reg_RF_Cal_byte_3__RFCAL_Offset_Cprog8 = { 0x29, 0x06, 0x02, 0x00 };
555 /* RFCAL_Offset_Cprog9 bit(s): */
556 const TDA18273_BitField_t gTDA18273_Reg_RF_Cal_byte_3__RFCAL_Offset_Cprog9 = { 0x29, 0x04, 0x02, 0x00 };
557 /* RFCAL_Offset_Cprog10 bit(s): */
558 const TDA18273_BitField_t gTDA18273_Reg_RF_Cal_byte_3__RFCAL_Offset_Cprog10 = { 0x29, 0x02, 0x02, 0x00 };
559 /* RFCAL_Offset_Cprog11 bit(s): */
560 const TDA18273_BitField_t gTDA18273_Reg_RF_Cal_byte_3__RFCAL_Offset_Cprog11 = { 0x29, 0x00, 0x02, 0x00 };
561
562
563 /* TDA18273 Register Bandsplit_Filter_byte 0x2A */
564 const TDA18273_BitField_t gTDA18273_Reg_Bandsplit_Filter_byte = { 0x2A, 0x00, 0x08, 0x00 };
565 /* Bandsplit_Filter_SubBand bit(s): */
566 const TDA18273_BitField_t gTDA18273_Reg_Bandsplit_Filter_byte__Bandsplit_Filter_SubBand = { 0x2A, 0x00, 0x02, 0x00 };
567
568
569 /* TDA18273 Register RF_Filters_byte_1 0x2B */
570 const TDA18273_BitField_t gTDA18273_Reg_RF_Filters_byte_1 = { 0x2B, 0x00, 0x08, 0x00 };
571 /* RF_Filter_Bypass bit(s): */
572 const TDA18273_BitField_t gTDA18273_Reg_RF_Filters_byte_1__RF_Filter_Bypass = { 0x2B, 0x07, 0x01, 0x00 };
573 /* AGC2_loop_off bit(s): */
574 const TDA18273_BitField_t gTDA18273_Reg_RF_Filters_byte_1__AGC2_loop_off = { 0x2B, 0x05, 0x01, 0x00 };
575 /* Force_AGC2_gain bit(s): */
576 const TDA18273_BitField_t gTDA18273_Reg_RF_Filters_byte_1__Force_AGC2_gain = { 0x2B, 0x04, 0x01, 0x00 };
577 /* RF_Filter_Gv bit(s): */
578 const TDA18273_BitField_t gTDA18273_Reg_RF_Filters_byte_1__RF_Filter_Gv = { 0x2B, 0x02, 0x02, 0x00 };
579 /* RF_Filter_Band bit(s): */
580 const TDA18273_BitField_t gTDA18273_Reg_RF_Filters_byte_1__RF_Filter_Band = { 0x2B, 0x00, 0x02, 0x00 };
581
582
583 /* TDA18273 Register RF_Filters_byte_2 0x2C */
584 const TDA18273_BitField_t gTDA18273_Reg_RF_Filters_byte_2 = { 0x2C, 0x00, 0x08, 0x00 };
585 /* RF_Filter_Cap bit(s): */
586 const TDA18273_BitField_t gTDA18273_Reg_RF_Filters_byte_2__RF_Filter_Cap = { 0x2C, 0x00, 0x08, 0x00 };
587
588
589 /* TDA18273 Register RF_Filters_byte_3 0x2D */
590 const TDA18273_BitField_t gTDA18273_Reg_RF_Filters_byte_3 = { 0x2D, 0x00, 0x08, 0x00 };
591 /* AGC2_Do_step bit(s): */
592 const TDA18273_BitField_t gTDA18273_Reg_RF_Filters_byte_3__AGC2_Do_step = { 0x2D, 0x06, 0x02, 0x00 };
593 /* Gain_Taper bit(s): */
594 const TDA18273_BitField_t gTDA18273_Reg_RF_Filters_byte_3__Gain_Taper = { 0x2D, 0x00, 0x06, 0x00 };
595
596
597 /* TDA18273 Register RF_Band_Pass_Filter_byte 0x2E */
598 const TDA18273_BitField_t gTDA18273_Reg_RF_Band_Pass_Filter_byte = { 0x2E, 0x00, 0x08, 0x00 };
599 /* RF_BPF_Bypass bit(s): */
600 const TDA18273_BitField_t gTDA18273_Reg_RF_Band_Pass_Filter_byte__RF_BPF_Bypass = { 0x2E, 0x07, 0x01, 0x00 };
601 /* RF_BPF bit(s): */
602 const TDA18273_BitField_t gTDA18273_Reg_RF_Band_Pass_Filter_byte__RF_BPF = { 0x2E, 0x00, 0x03, 0x00 };
603
604
605 /* TDA18273 Register CP_Current_byte 0x2F */
606 const TDA18273_BitField_t gTDA18273_Reg_CP_Current_byte = { 0x2F, 0x00, 0x08, 0x00 };
607 /* LO_CP_Current bit(s): */
608 const TDA18273_BitField_t gTDA18273_Reg_CP_Current_byte__LO_CP_Current = { 0x2F, 0x07, 0x01, 0x00 };
609 /* N_CP_Current bit(s): */
610 const TDA18273_BitField_t gTDA18273_Reg_CP_Current_byte__N_CP_Current = { 0x2F, 0x00, 0x07, 0x00 };
611
612
613 /* TDA18273 Register AGCs_DetOut_byte 0x30 */
614 const TDA18273_BitField_t gTDA18273_Reg_AGCs_DetOut_byte = { 0x30, 0x00, 0x08, 0x00 };
615 /* Up_AGC5 bit(s): */
616 const TDA18273_BitField_t gTDA18273_Reg_AGCs_DetOut_byte__Up_AGC5 = { 0x30, 0x07, 0x01, 0x00 };
617 /* Do_AGC5 bit(s): */
618 const TDA18273_BitField_t gTDA18273_Reg_AGCs_DetOut_byte__Do_AGC5 = { 0x30, 0x06, 0x01, 0x00 };
619 /* Up_AGC4 bit(s): */
620 const TDA18273_BitField_t gTDA18273_Reg_AGCs_DetOut_byte__Up_AGC4 = { 0x30, 0x05, 0x01, 0x00 };
621 /* Do_AGC4 bit(s): */
622 const TDA18273_BitField_t gTDA18273_Reg_AGCs_DetOut_byte__Do_AGC4 = { 0x30, 0x04, 0x01, 0x00 };
623 /* Up_AGC2 bit(s): */
624 const TDA18273_BitField_t gTDA18273_Reg_AGCs_DetOut_byte__Up_AGC2 = { 0x30, 0x03, 0x01, 0x00 };
625 /* Do_AGC2 bit(s): */
626 const TDA18273_BitField_t gTDA18273_Reg_AGCs_DetOut_byte__Do_AGC2 = { 0x30, 0x02, 0x01, 0x00 };
627 /* Up_AGC1 bit(s): */
628 const TDA18273_BitField_t gTDA18273_Reg_AGCs_DetOut_byte__Up_AGC1 = { 0x30, 0x01, 0x01, 0x00 };
629 /* Do_AGC1 bit(s): */
630 const TDA18273_BitField_t gTDA18273_Reg_AGCs_DetOut_byte__Do_AGC1 = { 0x30, 0x00, 0x01, 0x00 };
631
632
633 /* TDA18273 Register RFAGCs_Gain_byte_3 0x31 */
634 const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_3 = { 0x31, 0x00, 0x08, 0x00 };
635 /* AGC2_Gain_Read bit(s): */
636 const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_3__AGC2_Gain_Read = { 0x31, 0x04, 0x02, 0x00 };
637 /* AGC1_Gain_Read bit(s): */
638 const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_3__AGC1_Gain_Read = { 0x31, 0x00, 0x04, 0x00 };
639
640
641 /* TDA18273 Register RFAGCs_Gain_byte_4 0x32 */
642 const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_4 = { 0x32, 0x00, 0x08, 0x00 };
643 /* Cprog_Read bit(s): */
644 const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_4__Cprog_Read = { 0x32, 0x00, 0x08, 0x00 };
645
646
647 /* TDA18273 Register RFAGCs_Gain_byte_5 0x33 */
648 const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_5 = { 0x33, 0x00, 0x08, 0x00 };
649 /* RFAGC_Read_K_8 bit(s): */
650 const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_5__RFAGC_Read_K_8 = { 0x33, 0x07, 0x01, 0x00 };
651 /* Do_AGC1bis bit(s): */
652 const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_5__Do_AGC1bis = { 0x33, 0x06, 0x01, 0x00 };
653 /* AGC1_Top_Adapt_Low bit(s): */
654 const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_5__AGC1_Top_Adapt_Low = { 0x33, 0x05, 0x01, 0x00 };
655 /* Up_LNA_Adapt bit(s): */
656 const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_5__Up_LNA_Adapt = { 0x33, 0x04, 0x01, 0x00 };
657 /* Do_LNA_Adapt bit(s): */
658 const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_5__Do_LNA_Adapt = { 0x33, 0x03, 0x01, 0x00 };
659 /* TOP_AGC3_Read bit(s): */
660 const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_5__TOP_AGC3_Read = { 0x33, 0x00, 0x03, 0x00 };
661
662
663 /* TDA18273 Register RFAGCs_Gain_byte_6 0x34 */
664 const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_6 = { 0x34, 0x00, 0x08, 0x00 };
665 /* RFAGC_Read_K bit(s): */
666 const TDA18273_BitField_t gTDA18273_Reg_RFAGCs_Gain_byte_6__RFAGC_Read_K = { 0x34, 0x00, 0x08, 0x00 };
667
668
669 /* TDA18273 Register IFAGCs_Gain_byte 0x35 */
670 const TDA18273_BitField_t gTDA18273_Reg_IFAGCs_Gain_byte = { 0x35, 0x00, 0x08, 0x00 };
671 /* AGC5_Gain_Read bit(s): */
672 const TDA18273_BitField_t gTDA18273_Reg_IFAGCs_Gain_byte__AGC5_Gain_Read = { 0x35, 0x03, 0x03, 0x00 };
673 /* AGC4_Gain_Read bit(s): */
674 const TDA18273_BitField_t gTDA18273_Reg_IFAGCs_Gain_byte__AGC4_Gain_Read = { 0x35, 0x00, 0x03, 0x00 };
675
676
677 /* TDA18273 Register RSSI_byte_1 0x36 */
678 const TDA18273_BitField_t gTDA18273_Reg_RSSI_byte_1 = { 0x36, 0x00, 0x08, 0x00 };
679 /* RSSI bit(s): */
680 const TDA18273_BitField_t gTDA18273_Reg_RSSI_byte_1__RSSI = { 0x36, 0x00, 0x08, 0x00 };
681
682
683 /* TDA18273 Register RSSI_byte_2 0x37 */
684 const TDA18273_BitField_t gTDA18273_Reg_RSSI_byte_2 = { 0x37, 0x00, 0x08, 0x00 };
685 /* RSSI_AV bit(s): */
686 const TDA18273_BitField_t gTDA18273_Reg_RSSI_byte_2__RSSI_AV = { 0x37, 0x05, 0x01, 0x00 };
687 /* RSSI_Cap_Reset_En bit(s): */
688 const TDA18273_BitField_t gTDA18273_Reg_RSSI_byte_2__RSSI_Cap_Reset_En = { 0x37, 0x03, 0x01, 0x00 };
689 /* RSSI_Cap_Val bit(s): */
690 const TDA18273_BitField_t gTDA18273_Reg_RSSI_byte_2__RSSI_Cap_Val = { 0x37, 0x02, 0x01, 0x00 };
691 /* RSSI_Ck_Speed bit(s): */
692 const TDA18273_BitField_t gTDA18273_Reg_RSSI_byte_2__RSSI_Ck_Speed = { 0x37, 0x01, 0x01, 0x00 };
693 /* RSSI_Dicho_not bit(s): */
694 const TDA18273_BitField_t gTDA18273_Reg_RSSI_byte_2__RSSI_Dicho_not = { 0x37, 0x00, 0x01, 0x00 };
695
696
697 /* TDA18273 Register Misc_byte 0x38 */
698 const TDA18273_BitField_t gTDA18273_Reg_Misc_byte = { 0x38, 0x00, 0x08, 0x00 };
699 /* RFCALPOR_I2C bit(s): */
700 const TDA18273_BitField_t gTDA18273_Reg_Misc_byte__RFCALPOR_I2C = { 0x38, 0x06, 0x01, 0x00 };
701 /* PD_Underload bit(s): */
702 const TDA18273_BitField_t gTDA18273_Reg_Misc_byte__PD_Underload = { 0x38, 0x05, 0x01, 0x00 };
703 /* DDS_Polarity bit(s): */
704 const TDA18273_BitField_t gTDA18273_Reg_Misc_byte__DDS_Polarity = { 0x38, 0x04, 0x01, 0x00 };
705 /* IRQ_Mode bit(s): */
706 const TDA18273_BitField_t gTDA18273_Reg_Misc_byte__IRQ_Mode = { 0x38, 0x01, 0x01, 0x00 };
707 /* IRQ_Polarity bit(s): */
708 const TDA18273_BitField_t gTDA18273_Reg_Misc_byte__IRQ_Polarity = { 0x38, 0x00, 0x01, 0x00 };
709
710
711 /* TDA18273 Register rfcal_log_0 0x39 */
712 const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_0 = { 0x39, 0x00, 0x08, 0x00 };
713 /* rfcal_log_0 bit(s): */
714 const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_0__rfcal_log_0 = { 0x39, 0x00, 0x08, 0x00 };
715
716
717 /* TDA18273 Register rfcal_log_1 0x3A */
718 const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_1 = { 0x3A, 0x00, 0x08, 0x00 };
719 /* rfcal_log_1 bit(s): */
720 const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_1__rfcal_log_1 = { 0x3A, 0x00, 0x08, 0x00 };
721
722
723 /* TDA18273 Register rfcal_log_2 0x3B */
724 const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_2 = { 0x3B, 0x00, 0x08, 0x00 };
725 /* rfcal_log_2 bit(s): */
726 const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_2__rfcal_log_2 = { 0x3B, 0x00, 0x08, 0x00 };
727
728
729 /* TDA18273 Register rfcal_log_3 0x3C */
730 const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_3 = { 0x3C, 0x00, 0x08, 0x00 };
731 /* rfcal_log_3 bit(s): */
732 const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_3__rfcal_log_3 = { 0x3C, 0x00, 0x08, 0x00 };
733
734
735 /* TDA18273 Register rfcal_log_4 0x3D */
736 const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_4 = { 0x3D, 0x00, 0x08, 0x00 };
737 /* rfcal_log_4 bit(s): */
738 const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_4__rfcal_log_4 = { 0x3D, 0x00, 0x08, 0x00 };
739
740
741 /* TDA18273 Register rfcal_log_5 0x3E */
742 const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_5 = { 0x3E, 0x00, 0x08, 0x00 };
743 /* rfcal_log_5 bit(s): */
744 const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_5__rfcal_log_5 = { 0x3E, 0x00, 0x08, 0x00 };
745
746
747 /* TDA18273 Register rfcal_log_6 0x3F */
748 const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_6 = { 0x3F, 0x00, 0x08, 0x00 };
749 /* rfcal_log_6 bit(s): */
750 const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_6__rfcal_log_6 = { 0x3F, 0x00, 0x08, 0x00 };
751
752
753 /* TDA18273 Register rfcal_log_7 0x40 */
754 const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_7 = { 0x40, 0x00, 0x08, 0x00 };
755 /* rfcal_log_7 bit(s): */
756 const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_7__rfcal_log_7 = { 0x40, 0x00, 0x08, 0x00 };
757
758
759 /* TDA18273 Register rfcal_log_8 0x41 */
760 const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_8 = { 0x41, 0x00, 0x08, 0x00 };
761 /* rfcal_log_8 bit(s): */
762 const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_8__rfcal_log_8 = { 0x41, 0x00, 0x08, 0x00 };
763
764
765 /* TDA18273 Register rfcal_log_9 0x42 */
766 const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_9 = { 0x42, 0x00, 0x08, 0x00 };
767 /* rfcal_log_9 bit(s): */
768 const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_9__rfcal_log_9 = { 0x42, 0x00, 0x08, 0x00 };
769
770
771 /* TDA18273 Register rfcal_log_10 0x43 */
772 const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_10 = { 0x43, 0x00, 0x08, 0x00 };
773 /* rfcal_log_10 bit(s): */
774 const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_10__rfcal_log_10 = { 0x43, 0x00, 0x08, 0x00 };
775
776
777 /* TDA18273 Register rfcal_log_11 0x44 */
778 const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_11 = { 0x44, 0x00, 0x08, 0x00 };
779 /* rfcal_log_11 bit(s): */
780 const TDA18273_BitField_t gTDA18273_Reg_rfcal_log_11__rfcal_log_11 = { 0x44, 0x00, 0x08, 0x00 };
781
782
783
784 /* TDA18273 Register Main_Post_Divider_byte 0x51 */
785 const TDA18273_BitField_t gTDA18273_Reg_Main_Post_Divider_byte = { 0x51, 0x00, 0x08, 0x00 };
786 /* LOPostDiv bit(s): */
787 const TDA18273_BitField_t gTDA18273_Reg_Main_Post_Divider_byte__LOPostDiv = { 0x51, 0x04, 0x03, 0x00 };
788 /* LOPresc bit(s): */
789 const TDA18273_BitField_t gTDA18273_Reg_Main_Post_Divider_byte__LOPresc = { 0x51, 0x00, 0x04, 0x00 };
790
791
792 /* TDA18273 Register Sigma_delta_byte_1 0x52 */
793 const TDA18273_BitField_t gTDA18273_Reg_Sigma_delta_byte_1 = { 0x52, 0x00, 0x08, 0x00 };
794 /* LO_Int bit(s): */
795 const TDA18273_BitField_t gTDA18273_Reg_Sigma_delta_byte_1__LO_Int = { 0x52, 0x00, 0x07, 0x00 };
796
797
798 /* TDA18273 Register Sigma_delta_byte_2 0x53 */
799 const TDA18273_BitField_t gTDA18273_Reg_Sigma_delta_byte_2 = { 0x53, 0x00, 0x08, 0x00 };
800 /* LO_Frac_2 bit(s): */
801 const TDA18273_BitField_t gTDA18273_Reg_Sigma_delta_byte_2__LO_Frac_2 = { 0x53, 0x00, 0x07, 0x00 };
802
803
804 /* TDA18273 Register Sigma_delta_byte_3 0x54 */
805 const TDA18273_BitField_t gTDA18273_Reg_Sigma_delta_byte_3 = { 0x54, 0x00, 0x08, 0x00 };
806 /* LO_Frac_1 bit(s): */
807 const TDA18273_BitField_t gTDA18273_Reg_Sigma_delta_byte_3__LO_Frac_1 = { 0x54, 0x00, 0x08, 0x00 };
808
809
810 /* TDA18273 Register Sigma_delta_byte_4 0x55 */
811 const TDA18273_BitField_t gTDA18273_Reg_Sigma_delta_byte_4 = { 0x55, 0x00, 0x08, 0x00 };
812 /* LO_Frac_0 bit(s): */
813 const TDA18273_BitField_t gTDA18273_Reg_Sigma_delta_byte_4__LO_Frac_0 = { 0x55, 0x00, 0x08, 0x00 };
814
815
816 /* TDA18273 Register Sigma_delta_byte_5 0x56 */
817 const TDA18273_BitField_t gTDA18273_Reg_Sigma_delta_byte_5 = { 0x56, 0x00, 0x08, 0x00 };
818 /* N_K_correct_manual bit(s): */
819 const TDA18273_BitField_t gTDA18273_Reg_Sigma_delta_byte_5__N_K_correct_manual = { 0x56, 0x01, 0x01, 0x00 };
820 /* LO_Calc_Disable bit(s): */
821 const TDA18273_BitField_t gTDA18273_Reg_Sigma_delta_byte_5__LO_Calc_Disable = { 0x56, 0x00, 0x01, 0x00 };
822
823
824 /* TDA18273 Register Regulators_byte 0x58 */
825 const TDA18273_BitField_t gTDA18273_Reg_Regulators_byte = { 0x58, 0x00, 0x08, 0x00 };
826 /* RF_Reg bit(s): */
827 const TDA18273_BitField_t gTDA18273_Reg_Regulators_byte__RF_Reg = { 0x58, 0x02, 0x02, 0x00 };
828
829
830 /* TDA18273 Register IR_Cal_byte_5 0x5B */
831 const TDA18273_BitField_t gTDA18273_Reg_IR_Cal_byte_5 = { 0x5B, 0x00, 0x08, 0x00 };
832 /* Mixer_Gain_Bypass bit(s): */
833 const TDA18273_BitField_t gTDA18273_Reg_IR_Cal_byte_5__Mixer_Gain_Bypass = { 0x5B, 0x07, 0x01, 0x00 };
834 /* IR_Mixer_Gain bit(s): */
835 const TDA18273_BitField_t gTDA18273_Reg_IR_Cal_byte_5__IR_Mixer_Gain = { 0x5B, 0x04, 0x03, 0x00 };
836
837
838 /* TDA18273 Register Power_Down_byte_2 0x5F */
839 const TDA18273_BitField_t gTDA18273_Reg_Power_Down_byte_2 = { 0x5F, 0x00, 0x08, 0x00 };
840 /* PD_LNA bit(s): */
841 const TDA18273_BitField_t gTDA18273_Reg_Power_Down_byte_2__PD_LNA = { 0x5F, 0x07, 0x01, 0x00 };
842 /* PD_Det4 bit(s): */
843 const TDA18273_BitField_t gTDA18273_Reg_Power_Down_byte_2__PD_Det4 = { 0x5F, 0x03, 0x01, 0x00 };
844 /* PD_Det3 bit(s): */
845 const TDA18273_BitField_t gTDA18273_Reg_Power_Down_byte_2__PD_Det3 = { 0x5F, 0x02, 0x01, 0x00 };
846 /* PD_Det1 bit(s): */
847 const TDA18273_BitField_t gTDA18273_Reg_Power_Down_byte_2__PD_Det1 = { 0x5F, 0x00, 0x01, 0x00 };
848
849 /* TDA18273 Register Power_Down_byte_3 0x60 */
850 const TDA18273_BitField_t gTDA18273_Reg_Power_Down_byte_3 = { 0x60, 0x00, 0x08, 0x00 };
851 /* Force_Soft_Reset bit(s): */
852 const TDA18273_BitField_t gTDA18273_Reg_Power_Down_byte_3__Force_Soft_Reset = { 0x60, 0x01, 0x01, 0x00 };
853 /* Soft_Reset bit(s): */
854 const TDA18273_BitField_t gTDA18273_Reg_Power_Down_byte_3__Soft_Reset = { 0x60, 0x00, 0x01, 0x00 };
855
856 /* TDA18273 Register Charge_pump_byte 0x64 */
857 const TDA18273_BitField_t gTDA18273_Reg_Charge_pump_byte = { 0x64, 0x00, 0x08, 0x00 };
858 /* ICP_Bypass bit(s): */
859 const TDA18273_BitField_t gTDA18273_Reg_Charge_pump_byte__ICP_Bypass = { 0x64, 0x07, 0x01, 0x00 };
860 /* ICP bit(s): */
861 const TDA18273_BitField_t gTDA18273_Reg_Charge_pump_byte__ICP = { 0x64, 0x00, 0x02, 0x00 };
862
863
tda18273_readreg(struct tda18273_state * priv,unsigned char reg,unsigned char * val)864 static int tda18273_readreg(struct tda18273_state *priv, unsigned char reg, unsigned char *val)
865 {
866 int ret = TDA_RESULT_SUCCESS;
867 struct dvb_frontend *fe = priv->fe;
868
869 struct i2c_msg msg[2] = {
870 { .addr = priv->i2c_addr,
871 .flags = 0, .buf = ®, .len = 1},
872 { .addr = priv->i2c_addr,
873 .flags = I2C_M_RD, .buf = val, .len = 1},
874 };
875
876 if (fe->ops.i2c_gate_ctrl)
877 fe->ops.i2c_gate_ctrl(fe, 1);
878
879 ret = i2c_transfer(priv->i2c, msg, 2);
880
881 if (ret != 2) {
882 dprintk(FE_ERROR, 1, "I2C read failed");
883 ret = TDA_RESULT_I2C_READ_FAILURE;
884 }
885
886 if (fe->ops.i2c_gate_ctrl)
887 fe->ops.i2c_gate_ctrl(fe, 0);
888
889 return ret;
890 }
891
tda18273_readregs(struct tda18273_state * priv,const TDA18273_BitField_t * pBitField,unsigned char * val,tmbslFrontEndBusAccess_t eBusAccess)892 static int tda18273_readregs(struct tda18273_state *priv, const TDA18273_BitField_t* pBitField, unsigned char *val, tmbslFrontEndBusAccess_t eBusAccess)
893 {
894 unsigned char RegAddr = 0;
895 unsigned char RegMask = 0;
896 unsigned char RegData = 0;
897 unsigned char* pRegData = NULL;
898
899 RegAddr = pBitField->Address;
900
901 if(RegAddr < TDA18273_REG_MAP_NB_BYTES) {
902 pRegData = (unsigned char *)(&(priv->regmap)) + RegAddr;
903 } else {
904 pRegData = &RegData;
905 }
906
907 if((eBusAccess & Bus_NoRead) == 0x00) {
908 if(tda18273_readreg(priv, RegAddr, pRegData) == TDA_RESULT_I2C_READ_FAILURE) {
909 return TDA_RESULT_I2C_READ_FAILURE;
910 }
911 }
912
913 *val = *pRegData;
914
915 RegMask = ((1 << pBitField->WidthInBits) - 1) << pBitField->PositionInBits;
916
917 *val &= RegMask;
918 *val = (*val) >> pBitField->PositionInBits;
919
920 return TDA_RESULT_SUCCESS;
921 }
922
tda18273_readregmap(struct tda18273_state * priv,unsigned char reg,unsigned int len)923 static int tda18273_readregmap(struct tda18273_state *priv, unsigned char reg, unsigned int len)
924 {
925 int ret, i;
926 unsigned char* pRegData = NULL;
927
928 if((reg < TDA18273_REG_MAP_NB_BYTES) && ((reg + len) <= TDA18273_REG_MAP_NB_BYTES)) {
929 pRegData = (unsigned char *)(&(priv->regmap)) + reg;
930
931 for(i=0; i<len; i++) {
932 /* Read data from TDA18273 */
933 ret = tda18273_readreg(priv, (reg + i), (pRegData + i));
934 }
935 }
936
937 return 0;
938 }
939
tda18273_writereg(struct tda18273_state * priv,unsigned char reg,unsigned char val)940 static int tda18273_writereg(struct tda18273_state *priv, unsigned char reg, unsigned char val)
941 {
942 int ret = TDA_RESULT_SUCCESS;
943 struct dvb_frontend *fe = priv->fe;
944 unsigned char tmp[2] = {reg, val};
945
946 struct i2c_msg msg = {
947 .addr = priv->i2c_addr,
948 .flags = 0, .buf = tmp, .len = 2};
949
950 if (fe->ops.i2c_gate_ctrl)
951 fe->ops.i2c_gate_ctrl(fe, 1);
952
953 ret = i2c_transfer(priv->i2c, &msg, 1);
954
955 if (ret != 1) {
956 dprintk(FE_ERROR, 1, "I2C write failed");
957 ret = TDA_RESULT_I2C_READ_FAILURE;
958 }
959
960 if (fe->ops.i2c_gate_ctrl)
961 fe->ops.i2c_gate_ctrl(fe, 0);
962
963 return ret;
964 }
965
tda18273_writeregs(struct tda18273_state * priv,const TDA18273_BitField_t * pBitField,unsigned char val,tmbslFrontEndBusAccess_t eBusAccess)966 static int tda18273_writeregs(struct tda18273_state *priv, const TDA18273_BitField_t* pBitField, unsigned char val, tmbslFrontEndBusAccess_t eBusAccess)
967 {
968 unsigned char RegAddr = 0;
969 unsigned char RegData = 0;
970 unsigned char RegMask = 0;
971 unsigned char* pRegData = NULL;
972
973 RegAddr = pBitField->Address;
974
975 if(RegAddr < TDA18273_REG_MAP_NB_BYTES) {
976 pRegData = (unsigned char *)(&(priv->regmap)) + RegAddr;
977 } else {
978 pRegData = &RegData;
979 }
980
981 if((eBusAccess & Bus_NoRead) == 0x00) {
982 if(tda18273_readreg(priv, RegAddr, pRegData) == TDA_RESULT_I2C_READ_FAILURE) {
983 return TDA_RESULT_I2C_READ_FAILURE;
984 }
985 }
986
987 RegMask = (1 << pBitField->WidthInBits) - 1;
988 val &= RegMask;
989
990 RegMask = RegMask << pBitField->PositionInBits;
991 *pRegData &= (UInt8)(~RegMask);
992 *pRegData |= val << pBitField->PositionInBits;
993
994 if((eBusAccess & Bus_NoWrite) == 0x00) {
995 if(tda18273_writereg(priv, RegAddr, *pRegData) == TDA_RESULT_I2C_READ_FAILURE) {
996 return TDA_RESULT_I2C_READ_FAILURE;
997 }
998 }
999
1000 return TDA_RESULT_SUCCESS;
1001 }
1002
tda18273_writeregmap(struct tda18273_state * priv,unsigned char reg,unsigned int len)1003 static int tda18273_writeregmap(struct tda18273_state *priv, unsigned char reg, unsigned int len)
1004 {
1005 int ret, i;
1006 unsigned char* pRegData = NULL;
1007
1008 if((reg < TDA18273_REG_MAP_NB_BYTES) && ((reg + len) <= TDA18273_REG_MAP_NB_BYTES)) {
1009 pRegData = (unsigned char *)(&(priv->regmap)) + reg;
1010
1011 for(i=0; i<len; i++) {
1012 /* Write data from TDA18273 */
1013 ret = tda18273_writereg(priv, (reg + i), *(pRegData + i));
1014 }
1015 }
1016
1017 return 0;
1018 }
1019
tda18273_regall_debug(struct tda18273_state * priv)1020 static void tda18273_regall_debug(struct tda18273_state *priv)
1021 {
1022 int i;
1023 unsigned char val=0;
1024
1025 for(i=0; i<0x45; i++) {
1026 tda18273_readreg(priv, i, &val);
1027 dprintk(FE_DEBUGREG, 1, "addr : 0x%02x => data : 0x%02x", i, val);
1028 }
1029 }
1030
tda18273_get_lock_status(struct tda18273_state * priv,unsigned short * lock_status)1031 static int tda18273_get_lock_status(struct tda18273_state *priv, unsigned short *lock_status)
1032 {
1033 int ret;
1034 unsigned char val=0;
1035 unsigned char val_lo=0;
1036
1037 ret = tda18273_readregs(priv, &gTDA18273_Reg_Power_state_byte_1__LO_Lock, &val_lo, Bus_RW);
1038 ret = tda18273_readregs(priv, &gTDA18273_Reg_IRQ_status__IRQ_status, &val, Bus_RW);
1039 *lock_status = val & val_lo;
1040
1041 dprintk(FE_INFO, 1, "lock=0x%02X/0x%02x, lock_status=0x%x", val, val_lo, *lock_status);
1042
1043 return 0;
1044 }
1045
tda18273_pwr_state(struct dvb_frontend * fe,int pwr_state)1046 static int tda18273_pwr_state(struct dvb_frontend *fe, int pwr_state)
1047 {
1048 struct tda18273_state *priv = fe->tuner_priv;
1049 int ret=0;
1050
1051 if(priv->power_state != pwr_state) {
1052 if(pwr_state == tmPowerOn) {
1053 /* Set TDA18273 power state to Normal Mode */
1054 ret = tda18273_writeregs(priv, &gTDA18273_Reg_Power_Down_byte_2__PD_LNA, 0x1, Bus_RW); /* PD LNA */
1055 ret = tda18273_writeregs(priv, &gTDA18273_Reg_Power_Down_byte_2__PD_Det1, 0x1, Bus_NoRead); /* PD Detector AGC1 */
1056 ret = tda18273_writeregs(priv, &gTDA18273_Reg_AGC1_byte_3__AGC1_loop_off, 0x1, Bus_RW); /* AGC1 Detector loop off */
1057 ret = tda18273_writeregs(priv, &gTDA18273_Reg_Power_state_byte_2, TDA18273_SM_NONE, Bus_RW);
1058 ret = tda18273_writeregs(priv, &gTDA18273_Reg_Reference_Byte__Digital_Clock_Mode, 0x03, Bus_RW); /* Set digital clock mode to sub-LO if normal mode is entered */
1059 } else if(pwr_state == tmPowerStandby) {
1060 /* Set TDA18273 power state to standby with Xtal ON */
1061 ret = tda18273_writeregs(priv, &gTDA18273_Reg_Reference_Byte__Digital_Clock_Mode, 0x00, Bus_RW);
1062 ret = tda18273_writeregs(priv, &gTDA18273_Reg_Power_state_byte_2, 0x02, Bus_RW);
1063 }
1064
1065 priv->power_state = pwr_state;
1066 }
1067
1068 return 0;
1069 }
1070
tda18273_firstpass_lnapwr(struct dvb_frontend * fe)1071 static int tda18273_firstpass_lnapwr(struct dvb_frontend *fe)
1072 {
1073 struct tda18273_state *priv = fe->tuner_priv;
1074
1075 int ret;
1076
1077 /* PD LNA */
1078 ret = tda18273_writeregs(priv, &gTDA18273_Reg_Power_Down_byte_2__PD_LNA, 0x1, Bus_RW);
1079 /* PD Detector AGC1 */
1080 ret = tda18273_writeregs(priv, &gTDA18273_Reg_Power_Down_byte_2__PD_Det1, 0x1, Bus_NoRead);
1081 /* AGC1 Detector loop off */
1082 ret = tda18273_writeregs(priv, &gTDA18273_Reg_AGC1_byte_3__AGC1_loop_off, 0x1, Bus_RW);
1083
1084 return 0;
1085 }
1086
tda18273_lastpass_lnapwr(struct dvb_frontend * fe)1087 static int tda18273_lastpass_lnapwr(struct dvb_frontend *fe)
1088 {
1089 struct tda18273_state *priv = fe->tuner_priv;
1090
1091 unsigned char val = 0;
1092 int ret;
1093
1094 /* Check if LNA is PD */
1095 ret = tda18273_readregs(priv, &gTDA18273_Reg_Power_Down_byte_2__PD_LNA, &val, Bus_NoWrite);
1096
1097 if(val == 1) {
1098 /* LNA is Powered Down, so power it up */
1099 /* Force gain to -10dB */
1100 ret = tda18273_writeregs(priv, &gTDA18273_Reg_AGC1_byte_3__AGC1_Gain, 0x0, Bus_RW);
1101 ret = tda18273_writeregs(priv, &gTDA18273_Reg_AGC1_byte_3__Force_AGC1_gain, 0x1, Bus_NoRead);
1102 /* PD LNA */
1103 ret = tda18273_writeregs(priv, &gTDA18273_Reg_Power_Down_byte_2__PD_LNA, 0x0, Bus_NoRead);
1104 /* Release LNA gain control */
1105 ret = tda18273_writeregs(priv, &gTDA18273_Reg_AGC1_byte_3__Force_AGC1_gain, 0x0, Bus_NoRead);
1106 /* PD Detector AGC1 */
1107 ret = tda18273_writeregs(priv, &gTDA18273_Reg_Power_Down_byte_2__PD_Det1, 0x0, Bus_NoRead);
1108 /* AGC1 Detector loop off */
1109 ret = tda18273_writeregs(priv, &gTDA18273_Reg_AGC1_byte_3__AGC1_loop_off, 0x0, Bus_NoRead);
1110 }
1111
1112 return 0;
1113 }
1114
tda18273_llpwr_state(struct dvb_frontend * fe,int llpwr_state)1115 static int tda18273_llpwr_state(struct dvb_frontend *fe, int llpwr_state)
1116 {
1117 struct tda18273_state *priv = fe->tuner_priv;
1118
1119 unsigned char val = 0;
1120 int ret;
1121
1122 if(llpwr_state == TDA18273_PowerNormalMode) {
1123 /* If we come from any standby mode, then power on the IC with LNA off */
1124 /* Then powering on LNA with the minimal gain on AGC1 to avoid glitches at RF input will */
1125 /* be done during SetRF */
1126
1127 /* Workaround to limit the spurs occurence on RF input, do it before entering normal mode */
1128 /* PD LNA */
1129 ret = tda18273_firstpass_lnapwr(fe);
1130 ret = tda18273_writeregs(priv, &gTDA18273_Reg_Power_state_byte_2, TDA18273_SM_NONE, Bus_RW);
1131 /* Set digital clock mode to sub-LO if normal mode is entered */
1132 ret = tda18273_writeregs(priv, &gTDA18273_Reg_Reference_Byte__Digital_Clock_Mode, 0x03, Bus_RW);
1133
1134 /* Reset val to use it as a flag for below test */
1135 val = 0;
1136 } else if(llpwr_state == TDA18273_PowerStandbyWithXtalOn) {
1137 val = TDA18273_SM;
1138 } else if(llpwr_state == TDA18273_PowerStandby) {
1139 /* power state not supported */
1140 val = TDA18273_SM|TDA18273_SM_XT;
1141 }
1142
1143 if(val) {
1144 /* Set digital clock mode to 16 Mhz before entering standby */
1145 ret = tda18273_writeregs(priv, &gTDA18273_Reg_Reference_Byte__Digital_Clock_Mode, 0x00, Bus_RW);
1146 ret = tda18273_writeregs(priv, &gTDA18273_Reg_Power_state_byte_2, val, Bus_RW);
1147 }
1148
1149 return 0;
1150 }
1151
tda18273_check_calcpll(struct dvb_frontend * fe)1152 static int tda18273_check_calcpll(struct dvb_frontend *fe)
1153 {
1154 struct tda18273_state *priv = fe->tuner_priv;
1155
1156 int ret;
1157 unsigned char val;
1158
1159 /* Check if Calc_PLL algorithm is in automatic mode */
1160 ret = tda18273_readregs(priv, &gTDA18273_Reg_Sigma_delta_byte_5__LO_Calc_Disable, &val, Bus_None);
1161
1162 if(val != 0x00) {
1163 /* Enable Calc_PLL algorithm by putting PLL in automatic mode */
1164 ret = tda18273_writeregs(priv, &gTDA18273_Reg_Sigma_delta_byte_5__N_K_correct_manual, 0x00, Bus_None);
1165 ret = tda18273_writeregs(priv, &gTDA18273_Reg_Sigma_delta_byte_5__LO_Calc_Disable, 0x00, Bus_NoRead);
1166 }
1167
1168 return 0;
1169 }
1170
tda18273_set_msm(struct dvb_frontend * fe,unsigned char val,int launch)1171 static int tda18273_set_msm(struct dvb_frontend *fe, unsigned char val, int launch)
1172 {
1173 struct tda18273_state *priv = fe->tuner_priv;
1174 int ret;
1175
1176 /* Set state machine and Launch it */
1177 ret = tda18273_writeregs(priv, &gTDA18273_Reg_MSM_byte_1, val, Bus_None);
1178 ret = tda18273_writeregs(priv, &gTDA18273_Reg_MSM_byte_2__MSM_Launch, 0x01, Bus_None);
1179 ret = tda18273_writeregmap(priv, gTDA18273_Reg_MSM_byte_1.Address, (launch ? 0x02 : 0x01));
1180 ret = tda18273_writeregs(priv, &gTDA18273_Reg_MSM_byte_2__MSM_Launch, 0x00, Bus_None);
1181
1182 return 0;
1183 }
1184
tda18273_override_bandsplit(struct dvb_frontend * fe)1185 static int tda18273_override_bandsplit(struct dvb_frontend *fe)
1186 {
1187 struct tda18273_state *priv = fe->tuner_priv;
1188
1189 int ret;
1190 unsigned char Bandsplit = 0;
1191 unsigned char uPrevPSM_Bandsplit_Filter = 0;
1192 unsigned char PSM_Bandsplit_Filter = 0;
1193
1194 /* Setting PSM bandsplit at -3.9 mA for some RF frequencies */
1195 ret = tda18273_readregs(priv, &gTDA18273_Reg_Bandsplit_Filter_byte__Bandsplit_Filter_SubBand, &Bandsplit, Bus_None);
1196 ret = tda18273_readregs(priv, &gTDA18273_Reg_PowerSavingMode__PSM_Bandsplit_Filter, &uPrevPSM_Bandsplit_Filter, Bus_None);
1197
1198 switch(Bandsplit)
1199 {
1200 default:
1201 case 0: /* LPF0 133MHz - LPF1 206MHz - HPF0 422MHz */
1202 if(priv->pObj->uProgRF < 133000000) {
1203 /* Set PSM bandsplit at -3.9 mA */
1204 PSM_Bandsplit_Filter = 0x03;
1205 } else {
1206 /* Set PSM bandsplit at nominal */
1207 PSM_Bandsplit_Filter = 0x02;
1208 }
1209 break;
1210 case 1: /* LPF0 139MHz - LPF1 218MHz - HPF0 446MHz */
1211 if(priv->pObj->uProgRF < 139000000) {
1212 /* Set PSM bandsplit at -3.9 mA */
1213 PSM_Bandsplit_Filter = 0x03;
1214 } else {
1215 /* Set PSM bandsplit at nominal */
1216 PSM_Bandsplit_Filter = 0x02;
1217 }
1218 break;
1219 case 2: /* LPF0 145MHz - LPF1 230MHz - HPF0 470MHz */
1220 if(priv->pObj->uProgRF < 145000000) {
1221 /* Set PSM bandsplit at -3.9 mA */
1222 PSM_Bandsplit_Filter = 0x03;
1223 } else {
1224 /* Set PSM bandsplit at nominal */
1225 PSM_Bandsplit_Filter = 0x02;
1226 }
1227 break;
1228 case 3: /* LPF0 151MHz - LPF1 242MHz - HPF0 494MHz */
1229 if(priv->pObj->uProgRF < 151000000) {
1230 /* Set PSM bandsplit at -3.9 mA */
1231 PSM_Bandsplit_Filter = 0x03;
1232 } else {
1233 /* Set PSM bandsplit at nominal */
1234 PSM_Bandsplit_Filter = 0x02;
1235 }
1236 break;
1237 }
1238
1239 if(uPrevPSM_Bandsplit_Filter != PSM_Bandsplit_Filter) {
1240 /* Write PSM bandsplit */
1241 ret = tda18273_writeregs(priv, &gTDA18273_Reg_PowerSavingMode__PSM_Bandsplit_Filter, PSM_Bandsplit_Filter, Bus_NoRead);
1242 }
1243
1244 return 0;
1245 }
1246
tda18273_set_standardmode(struct dvb_frontend * fe,TDA18273StandardMode_t StandardMode)1247 static int tda18273_set_standardmode(struct dvb_frontend *fe, TDA18273StandardMode_t StandardMode)
1248 {
1249 struct tda18273_state *priv = fe->tuner_priv;
1250 int ret;
1251
1252 unsigned char wantedValue=0;
1253 unsigned char checked=0;
1254
1255 priv->pObj->StandardMode = StandardMode;
1256
1257 if((priv->pObj->StandardMode > TDA18273_StandardMode_Unknown) && (priv->pObj->StandardMode < TDA18273_StandardMode_Max)) {
1258 /* Update standard map pointer */
1259 priv->pObj->pStandard = &priv->pObj->Std_Array[priv->pObj->StandardMode - 1];
1260
1261 /****************************************************************/
1262 /* IF SELECTIVITY Settings */
1263 /****************************************************************/
1264 /* Set LPF */
1265 ret = tda18273_writeregs(priv, &gTDA18273_Reg_IF_Byte_1__LP_Fc, priv->pObj->pStandard->LPF, Bus_None);
1266 /* Set LPF Offset */
1267 ret = tda18273_writeregs(priv, &gTDA18273_Reg_IF_Byte_1__LP_FC_Offset, priv->pObj->pStandard->LPF_Offset, Bus_None);
1268 /* Set DC_Notch_IF_PPF */
1269 ret = tda18273_writeregs(priv, &gTDA18273_Reg_IR_Mixer_byte_2__IF_Notch, priv->pObj->pStandard->DC_Notch_IF_PPF, Bus_None);
1270 /* Enable/disable HPF */
1271 if(priv->pObj->pStandard->IF_HPF == TDA18273_IF_HPF_Disabled) {
1272 ret = tda18273_writeregs(priv, &gTDA18273_Reg_IR_Mixer_byte_2__Hi_Pass, 0x00, Bus_None);
1273 } else {
1274 ret = tda18273_writeregs(priv, &gTDA18273_Reg_IR_Mixer_byte_2__Hi_Pass, 0x01, Bus_None);
1275 /* Set IF HPF */
1276 ret = tda18273_writeregs(priv, &gTDA18273_Reg_IF_Byte_1__IF_HP_Fc, (UInt8)(priv->pObj->pStandard->IF_HPF - 1), Bus_None);
1277 }
1278 /* Set IF Notch */
1279 ret = tda18273_writeregs(priv, &gTDA18273_Reg_IF_Byte_1__IF_ATSC_Notch, priv->pObj->pStandard->IF_Notch, Bus_None);
1280 /* Set IF notch to RSSI */
1281 ret = tda18273_writeregs(priv, &gTDA18273_Reg_IF_AGC_byte__IFnotchToRSSI, priv->pObj->pStandard->IFnotchToRSSI, Bus_None);
1282
1283 /****************************************************************/
1284 /* AGC TOP Settings */
1285 /****************************************************************/
1286 /* Set AGC1 TOP I2C DN/UP */
1287 ret = tda18273_writeregs(priv, &gTDA18273_Reg_AGC1_byte_1__AGC1_TOP, priv->pObj->pStandard->AGC1_TOP_I2C_DN_UP, Bus_None);
1288 /* Set AGC1 Adapt TOP DN/UP */
1289 ret = tda18273_writeregs(priv, &gTDA18273_Reg_AGC1_byte_2__AGC1_Top_Mode_Val, priv->pObj->pStandard->AGC1_Adapt_TOP_DN_UP, Bus_None);
1290 /* Set AGC1 DN Time Constant */
1291 ret = tda18273_writeregs(priv, &gTDA18273_Reg_AGC1_byte_3__AGC1_Do_step, priv->pObj->pStandard->AGC1_DN_Time_Constant, Bus_None);
1292 /* Set AGC1 mode */
1293 ret = tda18273_writeregs(priv, &gTDA18273_Reg_AGC1_byte_2__AGC1_Top_Mode, priv->pObj->pStandard->AGC1_Mode, Bus_None);
1294 /* Set Range_LNA_Adapt */
1295 ret = tda18273_writeregs(priv, &gTDA18273_Reg_Adapt_Top_byte__Range_LNA_Adapt, priv->pObj->pStandard->Range_LNA_Adapt, Bus_None);
1296 /* Set LNA_Adapt_RFAGC_Gv_Threshold */
1297 ret = tda18273_writeregs(priv, &gTDA18273_Reg_Adapt_Top_byte__Index_K_LNA_Adapt, priv->pObj->pStandard->LNA_Adapt_RFAGC_Gv_Threshold, Bus_None);
1298 /* Set AGC1_Top_Adapt_RFAGC_Gv_Threshold */
1299 ret = tda18273_writeregs(priv, &gTDA18273_Reg_Adapt_Top_byte__Index_K_Top_Adapt, priv->pObj->pStandard->AGC1_Top_Adapt_RFAGC_Gv_Threshold, Bus_None);
1300 /* Set AGC2 TOP DN/UP */
1301 ret = tda18273_writeregs(priv, &gTDA18273_Reg_AGC2_byte_1__AGC2_TOP, priv->pObj->pStandard->AGC2_TOP_DN_UP, Bus_None);
1302 /* Set AGC2 DN Time Constant */
1303 ret = tda18273_writeregs(priv, &gTDA18273_Reg_RF_Filters_byte_3__AGC2_Do_step, priv->pObj->pStandard->AGC2_DN_Time_Constant, Bus_None);
1304 /* Set AGC4 TOP DN/UP */
1305 ret = tda18273_writeregs(priv, &gTDA18273_Reg_IR_Mixer_byte_1__IR_Mixer_Top, priv->pObj->pStandard->AGC4_TOP_DN_UP, Bus_None);
1306 /* Set AGC5 TOP DN/UP */
1307 ret = tda18273_writeregs(priv, &gTDA18273_Reg_AGC5_byte_1__AGC5_TOP, priv->pObj->pStandard->AGC5_TOP_DN_UP, Bus_None);
1308 /* Set AGC3_Top_Adapt_Algorithm */
1309 ret = tda18273_writeregs(priv, &gTDA18273_Reg_RF_AGC_byte__PD_AGC_Adapt3x, priv->pObj->pStandard->AGC3_Top_Adapt_Algorithm, Bus_None);
1310 /* Set AGC Overload TOP */
1311 ret = tda18273_writeregs(priv, &gTDA18273_Reg_Vsync_Mgt_byte__AGC_Ovld_TOP, priv->pObj->pStandard->AGC_Overload_TOP, Bus_None);
1312 /* Set Adapt TOP 34 Gain Threshold */
1313 ret = tda18273_writeregs(priv, &gTDA18273_Reg_RFAGCs_Gain_byte_1__TH_AGC_Adapt34, priv->pObj->pStandard->TH_AGC_Adapt34, Bus_None);
1314 /* Set RF atten 3dB */
1315 ret = tda18273_writeregs(priv, &gTDA18273_Reg_W_Filter_byte__RF_Atten_3dB, priv->pObj->pStandard->RF_Atten_3dB, Bus_None);
1316 /* Set IF Output Level */
1317 ret = tda18273_writeregs(priv, &gTDA18273_Reg_IF_AGC_byte__IF_level, priv->pObj->pStandard->IF_Output_Level, Bus_None);
1318 /* Set S2D gain */
1319 ret = tda18273_writeregs(priv, &gTDA18273_Reg_IR_Mixer_byte_1__S2D_Gain, priv->pObj->pStandard->S2D_Gain, Bus_None);
1320 /* Set Negative modulation, write into register directly because vsync_int bit is checked afterwards */
1321 ret = tda18273_writeregs(priv, &gTDA18273_Reg_Vsync_byte__Neg_modulation, priv->pObj->pStandard->Negative_Modulation, Bus_RW);
1322
1323 /****************************************************************/
1324 /* GSK Settings */
1325 /****************************************************************/
1326 /* Set AGCK Step */
1327 ret = tda18273_writeregs(priv, &gTDA18273_Reg_AGCK_byte_1__AGCK_Step, priv->pObj->pStandard->AGCK_Steps, Bus_None);
1328 /* Set AGCK Time Constant */
1329 ret = tda18273_writeregs(priv, &gTDA18273_Reg_AGCK_byte_1__AGCK_Mode, priv->pObj->pStandard->AGCK_Time_Constant, Bus_None);
1330 /* Set AGC5 HPF */
1331 wantedValue = priv->pObj->pStandard->AGC5_HPF;
1332 if(priv->pObj->pStandard->AGC5_HPF == TDA18273_AGC5_HPF_Enabled) {
1333 /* Check if Internal Vsync is selected */
1334 ret = tda18273_readregs(priv, &gTDA18273_Reg_Vsync_byte__Vsync_int, &checked, Bus_RW);
1335
1336 if(checked == 0) {
1337 /* Internal Vsync is OFF, so override setting to OFF */
1338 wantedValue = TDA18273_AGC5_HPF_Disabled;
1339 }
1340 }
1341 ret = tda18273_writeregs(priv, &gTDA18273_Reg_AGC5_byte_1__AGC5_Ana, wantedValue, Bus_None);
1342 /* Set Pulse Shaper Disable */
1343 ret = tda18273_writeregs(priv, &gTDA18273_Reg_AGCK_byte_1__Pulse_Shaper_Disable, priv->pObj->pStandard->Pulse_Shaper_Disable, Bus_None);
1344
1345 /****************************************************************/
1346 /* H3H5 Settings */
1347 /****************************************************************/
1348 /* Set VHF_III_Mode */
1349 ret = tda18273_writeregs(priv, &gTDA18273_Reg_W_Filter_byte__VHF_III_mode, priv->pObj->pStandard->VHF_III_Mode, Bus_None);
1350
1351 /****************************************************************/
1352 /* PLL Settings */
1353 /****************************************************************/
1354 /* Set LO_CP_Current */
1355 ret = tda18273_writeregs(priv, &gTDA18273_Reg_CP_Current_byte__LO_CP_Current, priv->pObj->pStandard->LO_CP_Current, Bus_None);
1356
1357 /****************************************************************/
1358 /* IF Settings */
1359 /****************************************************************/
1360 /* Set IF */
1361 ret = tda18273_writeregs(priv, &gTDA18273_Reg_IF_Frequency_byte__IF_Freq, (UInt8)((priv->pObj->pStandard->IF - priv->pObj->pStandard->CF_Offset)/50000), Bus_None);
1362
1363 /****************************************************************/
1364 /* MISC Settings */
1365 /****************************************************************/
1366 /* Set PD Underload */
1367 ret = tda18273_writeregs(priv, &gTDA18273_Reg_Misc_byte__PD_Underload, priv->pObj->pStandard->PD_Underload, Bus_None);
1368
1369 /****************************************************************/
1370 /* Update Registers */
1371 /****************************************************************/
1372 /* Write AGC1_byte_1 (0x0C) to IF_Byte_1 (0x15) Registers */
1373 ret = tda18273_writeregmap(priv, gTDA18273_Reg_AGC1_byte_1.Address, TDA18273_REG_DATA_LEN(gTDA18273_Reg_AGC1_byte_1, gTDA18273_Reg_IF_Byte_1));
1374 /* Write IF_Frequency_byte (0x17) Register */
1375 ret = tda18273_writeregmap(priv, gTDA18273_Reg_IF_Frequency_byte.Address, 1);
1376 /* Write Adapt_Top_byte (0x1F) Register */
1377 ret = tda18273_writeregmap(priv, gTDA18273_Reg_Adapt_Top_byte.Address, 1);
1378 /* Write Vsync_byte (0x20) to RFAGCs_Gain_byte_1 (0x24) Registers */
1379 ret = tda18273_writeregmap(priv, gTDA18273_Reg_Vsync_byte.Address, TDA18273_REG_DATA_LEN(gTDA18273_Reg_Vsync_byte, gTDA18273_Reg_RFAGCs_Gain_byte_1));
1380 /* Write RF_Filters_byte_3 (0x2D) Register */
1381 ret = tda18273_writeregmap(priv, gTDA18273_Reg_RF_Filters_byte_3.Address, 1);
1382 /* Write CP_Current_byte (0x2F) Register */
1383 ret = tda18273_writeregmap(priv, gTDA18273_Reg_CP_Current_byte.Address, 1);
1384 /* Write Misc_byte (0x38) Register */
1385 ret = tda18273_writeregmap(priv, gTDA18273_Reg_Misc_byte.Address, 1);
1386 }
1387
1388 return 0;
1389 }
1390
1391 typedef struct _TDA18273_PostDivPrescalerTableDef_
1392 {
1393 unsigned int LO_max;
1394 unsigned int LO_min;
1395 unsigned char Prescaler;
1396 unsigned char PostDiv;
1397 } TDA18273_PostDivPrescalerTableDef;
1398
1399 /* Table that maps LO vs Prescaler & PostDiv values */
1400 static TDA18273_PostDivPrescalerTableDef PostDivPrescalerTable[35] =
1401 {
1402 /* PostDiv 1 */
1403 {974000, 852250, 7, 1},
1404 {852250, 745719, 8, 1},
1405 {757556, 662861, 9, 1},
1406 {681800, 596575, 10, 1},
1407 {619818, 542341, 11, 1},
1408 {568167, 497146, 12, 1},
1409 {524462, 458904, 13, 1},
1410 /* PostDiv 2 */
1411 {487000, 426125, 7, 2},
1412 {426125, 372859, 8, 2},
1413 {378778, 331431, 9, 2},
1414 {340900, 298288, 10, 2},
1415 {309909, 271170, 11, 2},
1416 {284083, 248573, 12, 2},
1417 {262231, 229452, 13, 2},
1418 /* PostDiv 4 */
1419 {243500, 213063, 7, 4},
1420 {213063, 186430, 8, 4},
1421 {189389, 165715, 9, 4},
1422 {170450, 149144, 10, 4},
1423 {154955, 135585, 11, 4},
1424 {142042, 124286, 12, 4},
1425 {131115, 114726, 13, 4},
1426 /* PostDiv 8 */
1427 {121750, 106531, 7, 8},
1428 {106531, 93215, 8, 8},
1429 {94694, 82858, 9, 8},
1430 {85225, 74572, 10, 8},
1431 {77477, 67793, 11, 8},
1432 {71021, 62143, 12, 8},
1433 {65558, 57363, 13, 8},
1434 /* PostDiv 16 */
1435 {60875, 53266, 7, 16},
1436 {53266, 46607, 8, 16},
1437 {47347, 41429, 9, 16},
1438 {42613, 37286, 10, 16},
1439 {38739, 33896, 11, 16},
1440 {35510, 31072, 12, 16},
1441 {32779, 28681, 13, 16}
1442 };
1443
tda18273_calculate_postdivandprescaler(unsigned int LO,int growingOrder,unsigned char * PostDiv,unsigned char * Prescaler)1444 static int tda18273_calculate_postdivandprescaler(unsigned int LO, int growingOrder, unsigned char* PostDiv, unsigned char* Prescaler)
1445 {
1446 int ret = 0;
1447
1448 int index;
1449 int sizeTable = sizeof(PostDivPrescalerTable) / sizeof(TDA18273_PostDivPrescalerTableDef);
1450
1451 if(growingOrder == 1) {
1452 /* Start from LO = 28.681 kHz */
1453 for(index=(sizeTable-1); index>=0; index--) {
1454 if((LO > PostDivPrescalerTable[index].LO_min) && (LO < PostDivPrescalerTable[index].LO_max)) {
1455 /* We are at correct index in the table */
1456 break;
1457 }
1458 }
1459 } else {
1460 /* Start from LO = 974000 kHz */
1461 for(index=0; index<sizeTable; index++) {
1462 if((LO > PostDivPrescalerTable[index].LO_min) && (LO < PostDivPrescalerTable[index].LO_max)) {
1463 /* We are at correct index in the table */
1464 break;
1465 }
1466 }
1467 }
1468
1469 if((index == -1) || (index == sizeTable)) {
1470 ret = -1;
1471 } else {
1472 /* Write Prescaler */
1473 *Prescaler = PostDivPrescalerTable[index].Prescaler;
1474
1475 /* Decode PostDiv */
1476 *PostDiv = PostDivPrescalerTable[index].PostDiv;
1477 }
1478
1479 return ret;
1480 }
1481
1482 /* Middle of VCO frequency excursion : VCOmin + (VCOmax - VCOmin)/2 in KHz */
1483 #define TDA18273_MIDDLE_FVCO_RANGE ((6818000 - 5965750) / 2 + 5965750)
1484
tda18273_find_postdivandprescalerwithbettermargin(unsigned int LO,unsigned char * PostDiv,unsigned char * Prescaler)1485 static int tda18273_find_postdivandprescalerwithbettermargin(unsigned int LO, unsigned char* PostDiv, unsigned char* Prescaler)
1486 {
1487 int ret;
1488
1489 unsigned char PostDivGrowing;
1490 unsigned char PrescalerGrowing;
1491 unsigned char PostDivDecreasing = 0;
1492 unsigned char PrescalerDecreasing = 0;
1493 unsigned int FCVOGrowing = 0;
1494 unsigned int DistanceFCVOGrowing = 0;
1495 unsigned int FVCODecreasing = 0;
1496 unsigned int DistanceFVCODecreasing = 0;
1497
1498 /* Get the 2 possible values for PostDiv & Prescaler to find the one
1499 which provides the better margin on LO */
1500 ret = tda18273_calculate_postdivandprescaler(LO, 1, &PostDivGrowing, &PrescalerGrowing);
1501 if(ret != -1) {
1502 /* Calculate corresponding FVCO value in kHz */
1503 FCVOGrowing = LO * PrescalerGrowing * PostDivGrowing;
1504 }
1505
1506 ret = tda18273_calculate_postdivandprescaler(LO, 0, &PostDivDecreasing, &PrescalerDecreasing);
1507 if(ret != -1) {
1508 /* Calculate corresponding FVCO value in kHz */
1509 FVCODecreasing = LO * PrescalerDecreasing * PostDivDecreasing;
1510 }
1511
1512 /* Now take the values that are providing the better margin, the goal is +-2 MHz on LO */
1513 /* So take the point that is the nearest of (FVCOmax - FVCOmin)/2 = 6391,875 MHz */
1514 if(FCVOGrowing != 0) {
1515 if(FCVOGrowing >= TDA18273_MIDDLE_FVCO_RANGE) {
1516 DistanceFCVOGrowing = FCVOGrowing - TDA18273_MIDDLE_FVCO_RANGE;
1517 } else {
1518 DistanceFCVOGrowing = TDA18273_MIDDLE_FVCO_RANGE - FCVOGrowing;
1519 }
1520 }
1521
1522 if(FVCODecreasing != 0) {
1523 if(FVCODecreasing >= TDA18273_MIDDLE_FVCO_RANGE) {
1524 DistanceFVCODecreasing = FVCODecreasing - TDA18273_MIDDLE_FVCO_RANGE;
1525 } else {
1526 DistanceFVCODecreasing = TDA18273_MIDDLE_FVCO_RANGE - FVCODecreasing;
1527 }
1528 }
1529
1530 if(FCVOGrowing == 0) {
1531 if(FVCODecreasing == 0) {
1532 /* No value at all are found */
1533 ret = -1;
1534 } else {
1535 /* No value in growing mode, so take the decreasing ones */
1536 *PostDiv = PostDivDecreasing;
1537 *Prescaler = PrescalerDecreasing;
1538 }
1539 } else {
1540 if(FVCODecreasing == 0) {
1541 /* No value in decreasing mode, so take the growing ones */
1542 *PostDiv = PostDivGrowing;
1543 *Prescaler = PrescalerGrowing;
1544 } else {
1545 /* Find the value which are the nearest of the middle of VCO range */
1546 if(DistanceFCVOGrowing <= DistanceFVCODecreasing) {
1547 *PostDiv = PostDivGrowing;
1548 *Prescaler = PrescalerGrowing;
1549 } else {
1550 *PostDiv = PostDivDecreasing;
1551 *Prescaler = PrescalerDecreasing;
1552 }
1553 }
1554 }
1555
1556 return ret;
1557 }
1558
tda18273_calculate_nintkint(unsigned int LO,unsigned char PostDiv,unsigned char Prescaler,unsigned int * NInt,unsigned int * KInt)1559 static int tda18273_calculate_nintkint(unsigned int LO, unsigned char PostDiv, unsigned char Prescaler, unsigned int* NInt, unsigned int* KInt)
1560 {
1561 /* Algorithm that calculates N_K */
1562 unsigned int FVCO = 0;
1563 unsigned int N_K_prog = 0;
1564
1565 /* Algorithm that calculates N, K corrected */
1566 unsigned int Nprime = 0;
1567 unsigned int KforceK0_1 = 0;
1568 unsigned int K2msb = 0;
1569 unsigned int N0 = 0;
1570 unsigned int Nm1 = 0;
1571
1572 /* Calculate N_K_Prog */
1573 FVCO = LO * Prescaler * PostDiv;
1574 N_K_prog = (FVCO * 128) / 125;
1575
1576 /* Calculate N & K corrected values */
1577 Nprime = N_K_prog & 0xFF0000;
1578
1579 /* Force LSB to 1 */
1580 KforceK0_1 = 2*(((N_K_prog - Nprime) << 7) / 2) + 1;
1581
1582 /* Check MSB bit around 2 */
1583 K2msb = KforceK0_1 >> 21;
1584 if(K2msb < 1) {
1585 N0 = 1;
1586 } else {
1587 if (K2msb >= 3) {
1588 N0 = 1;
1589 } else {
1590 N0 = 0;
1591 }
1592 }
1593
1594 if(K2msb < 1) {
1595 Nm1 = 1;
1596 } else {
1597 Nm1 = 0;
1598 }
1599
1600 /* Calculate N */
1601 *NInt = (2 * ((Nprime >> 16) - Nm1) + N0) - 128;
1602
1603 /* Calculate K */
1604 if(K2msb < 1) {
1605 *KInt = KforceK0_1 + (2 << 21);
1606 } else {
1607 if (K2msb >= 3) {
1608 *KInt = KforceK0_1 - (2 << 21);
1609 } else {
1610 *KInt = KforceK0_1;
1611 }
1612 }
1613
1614 /* Force last 7 bits of K_int to 0x5D, as the IC is doing for spurs optimization */
1615 *KInt &= 0xFFFFFF80;
1616 *KInt |= 0x5D;
1617
1618 return 0;
1619 }
1620
1621
tda18273_set_pll(struct dvb_frontend * fe)1622 static int tda18273_set_pll(struct dvb_frontend *fe)
1623 {
1624 struct tda18273_state *priv = fe->tuner_priv;
1625
1626 int ret;
1627
1628 /* LO wanted = RF wanted + IF in KHz */
1629 unsigned int LO = 0;
1630
1631 /* Algorithm that calculates PostDiv */
1632 unsigned char PostDiv = 0; /* absolute value */
1633 unsigned char LOPostDiv = 0; /* register value */
1634
1635 /* Algorithm that calculates Prescaler */
1636 unsigned char Prescaler = 0;
1637
1638 /* Algorithm that calculates N, K */
1639 unsigned int N_int = 0;
1640 unsigned int K_int = 0;
1641
1642 /* Calculate wanted LO = RF + IF in Hz */
1643 LO = (priv->pObj->uRF + priv->pObj->uIF) / 1000;
1644
1645 /* Calculate the best PostDiv and Prescaler : the ones that provide the best margin */
1646 /* in case of fine tuning +-2 MHz */
1647 ret = tda18273_find_postdivandprescalerwithbettermargin(LO, &PostDiv, &Prescaler);
1648
1649 if(ret != -1) {
1650 /* Program the PLL only if valid values are found, in that case err == TM_OK */
1651 /* Decode PostDiv */
1652 switch(PostDiv) {
1653 case 1: LOPostDiv = 1; break;
1654 case 2: LOPostDiv = 2; break;
1655 case 4: LOPostDiv = 3; break;
1656 case 8: LOPostDiv = 4; break;
1657 case 16: LOPostDiv = 5; break;
1658 default: dprintk(FE_INFO, 1, "%s *PostDiv value is wrong.", __func__); break;
1659 }
1660
1661 /* Affect register map without writing into IC */
1662 ret = tda18273_writeregs(priv, &gTDA18273_Reg_Main_Post_Divider_byte__LOPostDiv, LOPostDiv, Bus_None);
1663 ret = tda18273_writeregs(priv, &gTDA18273_Reg_Main_Post_Divider_byte__LOPresc, Prescaler, Bus_None);
1664 /* Calculate N & K values of the PLL */
1665 ret = tda18273_calculate_nintkint(LO, PostDiv, Prescaler, &N_int, &K_int);
1666 /* Affect registers map without writing to IC */
1667 ret = tda18273_writeregs(priv, &gTDA18273_Reg_Sigma_delta_byte_4__LO_Frac_0, (UInt8)(K_int & 0xFF), Bus_None);
1668 ret = tda18273_writeregs(priv, &gTDA18273_Reg_Sigma_delta_byte_3__LO_Frac_1, (UInt8)((K_int >> 8) & 0xFF), Bus_None);
1669 ret = tda18273_writeregs(priv, &gTDA18273_Reg_Sigma_delta_byte_2__LO_Frac_2, (UInt8)((K_int >> 16) & 0xFF), Bus_None);
1670 ret = tda18273_writeregs(priv, &gTDA18273_Reg_Sigma_delta_byte_1__LO_Int, (UInt8)(N_int & 0xFF), Bus_None);
1671 /* Force manual selection mode : 0x3 at @0x56 */
1672 ret = tda18273_writeregs(priv, &gTDA18273_Reg_Sigma_delta_byte_5__N_K_correct_manual, 0x01, Bus_None);
1673 /* Force manual selection mode : 0x3 at @0x56 */
1674 ret = tda18273_writeregs(priv, &gTDA18273_Reg_Sigma_delta_byte_5__LO_Calc_Disable, 0x01, Bus_None);
1675 /* Write bytes Main_Post_Divider_byte (0x51) to Sigma_delta_byte_5 (0x56) */
1676 ret = tda18273_writeregmap(priv, gTDA18273_Reg_Main_Post_Divider_byte.Address, TDA18273_REG_DATA_LEN(gTDA18273_Reg_Main_Post_Divider_byte, gTDA18273_Reg_Sigma_delta_byte_5));
1677 }
1678
1679 return 0;
1680 }
1681
tda18273_override_icp(struct dvb_frontend * fe,unsigned int uRF)1682 static int tda18273_override_icp(struct dvb_frontend *fe, unsigned int uRF)
1683 {
1684 struct tda18273_state *priv = fe->tuner_priv;
1685
1686 int ret;
1687 unsigned int uIF = 0;
1688 unsigned char ProgIF = 0;
1689 unsigned char LOPostdiv = 0;
1690 unsigned char LOPrescaler = 0;
1691 unsigned int FVCO = 0;
1692 unsigned char uICPBypass = 0;
1693 unsigned char ICP = 0;
1694 unsigned char uPrevICP = 0;
1695
1696 /* Read PostDiv et Prescaler */
1697 ret = tda18273_readregs(priv, &gTDA18273_Reg_Main_Post_Divider_byte, &LOPostdiv, Bus_RW);
1698 /* PostDiv */
1699 ret = tda18273_readregs(priv, &gTDA18273_Reg_Main_Post_Divider_byte__LOPostDiv, &LOPostdiv, Bus_NoRead);
1700 /* Prescaler */
1701 ret = tda18273_readregs(priv, &gTDA18273_Reg_Main_Post_Divider_byte__LOPresc, &LOPrescaler, Bus_NoRead);
1702 /* IF */
1703 ret = tda18273_readregs(priv, &gTDA18273_Reg_IF_Frequency_byte__IF_Freq, &ProgIF, Bus_NoRead);
1704 /* Decode IF */
1705 uIF = ProgIF*50000;
1706 /* Decode PostDiv */
1707 switch(LOPostdiv) {
1708 case 1: LOPostdiv = 1; break;
1709 case 2: LOPostdiv = 2; break;
1710 case 3: LOPostdiv = 4; break;
1711 case 4: LOPostdiv = 8; break;
1712 case 5: LOPostdiv = 16; break;
1713 default: ret = -1; break;
1714 }
1715
1716 if(ret != -1) {
1717 /* Calculate FVCO in MHz*/
1718 FVCO = LOPostdiv * LOPrescaler * ((uRF + uIF) / 1000000);
1719 /* Set correct ICP */
1720 if(FVCO < 6352) {
1721 /* Set ICP to 01 (= 150)*/
1722 ICP = 0x01;
1723 } else if(FVCO < 6592) {
1724 /* Set ICP to 10 (= 300)*/
1725 ICP = 0x02;
1726 } else {
1727 /* Set ICP to 00 (= 500)*/
1728 ICP = 0x00;
1729 }
1730 /* Get ICP_bypass bit */
1731 ret = tda18273_readregs(priv, &gTDA18273_Reg_Charge_pump_byte__ICP_Bypass, &uICPBypass, Bus_RW);
1732 /* Get ICP */
1733 ret = tda18273_readregs(priv, &gTDA18273_Reg_Charge_pump_byte__ICP, &uPrevICP, Bus_NoRead);
1734
1735 if(uICPBypass == 0x0 || uPrevICP != ICP) {
1736 /* Set ICP_bypass bit */
1737 ret = tda18273_writeregs(priv, &gTDA18273_Reg_Charge_pump_byte__ICP_Bypass, 0x01, Bus_None);
1738 /* Set ICP */
1739 ret = tda18273_writeregs(priv, &gTDA18273_Reg_Charge_pump_byte__ICP, ICP, Bus_None);
1740 /* Write Charge_pump_byte register */
1741 ret = tda18273_writeregmap(priv, gTDA18273_Reg_Charge_pump_byte.Address, 1);
1742 }
1743 }
1744
1745 return ret;
1746 }
1747
tda18273_override_digitalclock(struct dvb_frontend * fe,unsigned int uRF)1748 static int tda18273_override_digitalclock(struct dvb_frontend *fe, unsigned int uRF)
1749 {
1750 struct tda18273_state *priv = fe->tuner_priv;
1751
1752 int ret;
1753 unsigned char uDigClock = 0;
1754 unsigned char uPrevDigClock = 0;
1755 unsigned char uProgIF = 0;
1756
1757 /* LO < 55 MHz then Digital Clock set to 16 MHz else subLO */
1758 /* Read Current IF */
1759 ret = tda18273_readregs(priv, &gTDA18273_Reg_IF_Frequency_byte__IF_Freq, &uProgIF, Bus_NoWrite);
1760 /* Read Current Digital Clock */
1761 ret = tda18273_readregs(priv, &gTDA18273_Reg_Reference_Byte__Digital_Clock_Mode, &uPrevDigClock, Bus_NoWrite);
1762 /* LO = RF + IF */
1763 if((uRF + (uProgIF*50000)) < 55000000) {
1764 uDigClock = 0; /* '00' = 16 MHz */
1765 } else {
1766 uDigClock = 3; /* '11' = subLO */
1767 }
1768
1769 if(uPrevDigClock != uDigClock) {
1770 /* Set Digital Clock bits */
1771 ret = tda18273_writeregs(priv, &gTDA18273_Reg_Reference_Byte__Digital_Clock_Mode, uDigClock, Bus_NoRead);
1772 }
1773
1774 return 0;
1775 }
1776
tda18273_set_rffreq(struct dvb_frontend * fe)1777 static int tda18273_set_rffreq(struct dvb_frontend *fe)
1778 {
1779 struct tda18273_state *priv = fe->tuner_priv;
1780
1781 int ret;
1782 unsigned int uRF=priv->pObj->uProgRF;
1783 unsigned int uRFLocal=0;
1784
1785 /* Set the proper settings depending on the standard & RF frequency */
1786 /****************************************************************/
1787 /* AGC TOP Settings */
1788 /****************************************************************/
1789 /* Set AGC3 RF AGC Top */
1790 if(uRF < priv->pObj->pStandard->Freq_Start_LTE) {
1791 ret = tda18273_writeregs(priv, &gTDA18273_Reg_RF_AGC_byte__RFAGC_Top, priv->pObj->pStandard->AGC3_TOP_I2C_Low_Band, Bus_RW);
1792 } else {
1793 ret = tda18273_writeregs(priv, &gTDA18273_Reg_RF_AGC_byte__RFAGC_Top, priv->pObj->pStandard->AGC3_TOP_I2C_High_Band, Bus_RW);
1794 }
1795 /* Set AGC3 Adapt TOP */
1796 if(uRF < priv->pObj->pStandard->Freq_Start_LTE) {
1797 ret = tda18273_writeregs(priv, &gTDA18273_Reg_RF_AGC_byte__RFAGC_Adapt_TOP, priv->pObj->pStandard->AGC3_Adapt_TOP_Low_Band, Bus_NoRead);
1798 } else {
1799 ret = tda18273_writeregs(priv, &gTDA18273_Reg_RF_AGC_byte__RFAGC_Adapt_TOP, priv->pObj->pStandard->AGC3_Adapt_TOP_High_Band, Bus_NoRead);
1800 }
1801 /* Set IRQ_clear */
1802 ret = tda18273_writeregs(priv, &gTDA18273_Reg_IRQ_clear, TDA18273_IRQ_Global|TDA18273_IRQ_SetRF, Bus_NoRead);
1803 /* Set RF */
1804 uRFLocal = (uRF + 500) / 1000;
1805
1806 ret = tda18273_writeregs(priv, &gTDA18273_Reg_RF_Frequency_byte_1__RF_Freq_1, (unsigned char)((uRFLocal & 0x00FF0000) >> 16), Bus_None);
1807 ret = tda18273_writeregs(priv, &gTDA18273_Reg_RF_Frequency_byte_2__RF_Freq_2, (unsigned char)((uRFLocal & 0x0000FF00) >> 8), Bus_None);
1808 ret = tda18273_writeregs(priv, &gTDA18273_Reg_RF_Frequency_byte_3__RF_Freq_3, (unsigned char)(uRFLocal & 0x000000FF), Bus_None);
1809 ret = tda18273_writeregmap(priv, gTDA18273_Reg_RF_Frequency_byte_1.Address, TDA18273_REG_DATA_LEN(gTDA18273_Reg_RF_Frequency_byte_1, gTDA18273_Reg_RF_Frequency_byte_3));
1810 /* Set state machine and Launch it */
1811 ret = tda18273_set_msm(fe, TDA18273_MSM_SetRF, 0x1);
1812 /* Wait for IRQ to trigger */
1813 //ret = iTDA18273_WaitIRQ(pObj, 50, 5, TDA18273_IRQ_SetRF);
1814 mdelay(50);
1815
1816 /* Override the calculated PLL to get the best margin in case fine tuning is used */
1817 /* which means set the PLL in manual mode that provides the best occurence of LO tuning (+-2 MHz) */
1818 /* without touching PostDiv and Prescaler */
1819 ret = tda18273_set_pll(fe);
1820 /* Override ICP */
1821 ret = tda18273_override_icp(fe, priv->pObj->uProgRF);
1822 /* Override Digital Clock */
1823 if(ret != -1) {
1824 ret = tda18273_override_digitalclock(fe, priv->pObj->uProgRF);
1825 }
1826
1827 return 0;
1828 }
1829
tda18273_set_rf(struct dvb_frontend * fe,unsigned int uRF)1830 static int tda18273_set_rf(struct dvb_frontend *fe, unsigned int uRF)
1831 {
1832 struct tda18273_state *priv = fe->tuner_priv;
1833
1834 priv->pObj->uRF = uRF;
1835 priv->pObj->uProgRF = priv->pObj->uRF + priv->pObj->pStandard->CF_Offset;
1836
1837 tda18273_llpwr_state(fe, TDA18273_PowerNormalMode);
1838 tda18273_lastpass_lnapwr(fe);
1839 tda18273_check_calcpll(fe);
1840 tda18273_override_bandsplit(fe);
1841 tda18273_set_rffreq(fe);
1842
1843 return 0;
1844 }
1845
tda18273_hw_reset(struct dvb_frontend * fe)1846 static int tda18273_hw_reset(struct dvb_frontend *fe)
1847 {
1848 struct tda18273_state *priv = fe->tuner_priv;
1849 int ret;
1850
1851 tda18273_pwr_state(fe, tmPowerStandby);
1852 tda18273_llpwr_state(fe, TDA18273_PowerNormalMode);
1853
1854 /* Set digital clock mode to 16 Mhz before resetting the IC to avoid unclocking the digital part */
1855 ret = tda18273_writeregs(priv, &gTDA18273_Reg_Reference_Byte__Digital_Clock_Mode, 0x00, Bus_RW);
1856 /* Perform a SW reset to reset the digital calibrations & the IC machine state */
1857 ret = tda18273_writeregs(priv, &gTDA18273_Reg_Power_Down_byte_3, 0x03, Bus_RW);
1858 ret = tda18273_writeregs(priv, &gTDA18273_Reg_Power_Down_byte_3, 0x00, Bus_NoRead);
1859 /* Set power state on */
1860 //ret = tda18273_llpwr_state(fe, TDA18273_PowerNormalMode);
1861
1862 #if 0
1863 /* Only if tuner has a XTAL */
1864 if(1) { //if (priv->bBufferMode == False)
1865 /* Reset XTALCAL_End bit */
1866 /* Set IRQ_clear */
1867 ret = tda18273_writeregs(priv, &gTDA18273_Reg_IRQ_clear, TDA18273_IRQ_Global|TDA18273_IRQ_XtalCal|TDA18273_IRQ_HwInit|TDA18273_IRQ_IrCal, Bus_NoRead);
1868 /* Launch XTALCAL */
1869 ret = tda18273_writeregs(priv, &gTDA18273_Reg_MSM_byte_2__XtalCal_Launch, 0x01, Bus_NoRead);
1870 ret = tda18273_writeregs(priv, &gTDA18273_Reg_MSM_byte_2__XtalCal_Launch, 0x00, Bus_None);
1871 /* Wait XTALCAL_End bit */
1872 //ret = iTDA18273_WaitXtalCal_End(priv, 100, 10);
1873 }
1874 #endif
1875
1876 /* Read all bytes */
1877 ret = tda18273_readregmap(priv, 0x00, TDA18273_REG_MAP_NB_BYTES);
1878 /* Check if Calc_PLL algorithm is in automatic mode */
1879 ret = tda18273_check_calcpll(fe);
1880 /* Up_Step_Ovld: POR = 1 -> 0 */
1881 ret = tda18273_writeregs(priv, &gTDA18273_Reg_Vsync_Mgt_byte__Up_Step_Ovld, 0x00, Bus_NoRead);
1882 /* PLD_CC_Enable: POR = 1 -> 0 */
1883 ret = tda18273_writeregs(priv, &gTDA18273_Reg_RFAGCs_Gain_byte_1__PLD_CC_Enable, 0x00, Bus_NoRead);
1884 /* RFCAL_Offset0 : 0 */
1885 ret = tda18273_writeregs(priv, &gTDA18273_Reg_RF_Cal_byte_1__RFCAL_Offset_Cprog0, 0x00, Bus_None);
1886 /* RFCAL_Offset1 : 0 */
1887 ret = tda18273_writeregs(priv, &gTDA18273_Reg_RF_Cal_byte_1__RFCAL_Offset_Cprog1, 0x00, Bus_None);
1888 /* RFCAL_Offset2 : 0 */
1889 ret = tda18273_writeregs(priv, &gTDA18273_Reg_RF_Cal_byte_1__RFCAL_Offset_Cprog2, 0x00, Bus_None);
1890 /* RFCAL_Offset3 : 0 */
1891 ret = tda18273_writeregs(priv, &gTDA18273_Reg_RF_Cal_byte_1__RFCAL_Offset_Cprog3, 0x00, Bus_None);
1892 /* RFCAL_Offset4 : 3 */
1893 ret = tda18273_writeregs(priv, &gTDA18273_Reg_RF_Cal_byte_2__RFCAL_Offset_Cprog4, 0x03, Bus_None);
1894 /* RFCAL_Offset5 : 0 */
1895 ret = tda18273_writeregs(priv, &gTDA18273_Reg_RF_Cal_byte_2__RFCAL_Offset_Cprog5, 0x00, Bus_None);
1896 /* RFCAL_Offset6 : 3 */
1897 ret = tda18273_writeregs(priv, &gTDA18273_Reg_RF_Cal_byte_2__RFCAL_Offset_Cprog6, 0x03, Bus_None);
1898 /* RFCAL_Offset7 : 3 */
1899 ret = tda18273_writeregs(priv, &gTDA18273_Reg_RF_Cal_byte_2__RFCAL_Offset_Cprog7, 0x03, Bus_None);
1900 /* RFCAL_Offset8 : 1 */
1901 ret = tda18273_writeregs(priv, &gTDA18273_Reg_RF_Cal_byte_3__RFCAL_Offset_Cprog8, 0x01, Bus_None);
1902 /* Write RF_Cal_byte_1 (0x27) to RF_Cal_byte_3 (0x29) Registers */
1903 ret = tda18273_writeregmap(priv, gTDA18273_Reg_RF_Cal_byte_1.Address, TDA18273_REG_DATA_LEN(gTDA18273_Reg_RF_Cal_byte_1, gTDA18273_Reg_RF_Cal_byte_3));
1904 /* PLD_Temp_Enable: POR = 1 -> 0 */
1905 ret = tda18273_writeregs(priv, &gTDA18273_Reg_RFAGCs_Gain_byte_1__PLD_Temp_Enable, 0x00, Bus_NoRead);
1906 /* Power Down Vsync Management: POR = 0 -> 1 */
1907 ret = tda18273_writeregs(priv, &gTDA18273_Reg_Vsync_Mgt_byte__PD_Vsync_Mgt, 0x01, Bus_NoRead);
1908 /* Set IRQ_clear */
1909 ret = tda18273_writeregs(priv, &gTDA18273_Reg_IRQ_clear, TDA18273_IRQ_Global|TDA18273_IRQ_HwInit|TDA18273_IRQ_IrCal, Bus_NoRead);
1910 /* Set state machine (all CALs except IRCAL) and Launch it */
1911 ret = tda18273_set_msm(fe, TDA18273_MSM_HwInit, 0x1);
1912 /* Inform that init phase has started */
1913 /* State reached after 500 ms max */
1914 //ret = iTDA18273_WaitIRQ(priv, 500, 10, TDA18273_IRQ_HwInit);
1915 mdelay(500);
1916 /* Set IRQ_clear */
1917 ret = tda18273_writeregs(priv, &gTDA18273_Reg_IRQ_clear, TDA18273_IRQ_Global|TDA18273_IRQ_HwInit|TDA18273_IRQ_IrCal, Bus_NoRead);
1918 /* Launch IRCALs after all other CALs are finished */
1919 ret = tda18273_set_msm(fe, TDA18273_MSM_IrCal, 0x1);
1920 /* State reached after 500 ms max, 10 ms step due to CAL ~ 30ms */
1921 //ret = iTDA18273_WaitIRQ(priv, 500, 10, TDA18273_IRQ_IrCal);
1922 mdelay(500);
1923
1924 tda18273_llpwr_state(fe, TDA18273_PowerStandbyWithXtalOn);
1925
1926 return 0;
1927 }
1928
tda18273_hw_init(struct dvb_frontend * fe)1929 static int tda18273_hw_init(struct dvb_frontend *fe)
1930 {
1931 tda18273_pwr_state(fe, tmPowerOn);
1932
1933 tda18273_hw_reset(fe);
1934
1935 return 0;
1936 }
1937
tda18273_init(struct dvb_frontend * fe)1938 static int tda18273_init(struct dvb_frontend *fe)
1939 {
1940 struct tda18273_state *priv = fe->tuner_priv;
1941 int ret;
1942 unsigned char val=0;
1943 unsigned short id=0;
1944 unsigned char major;
1945 unsigned char minor;
1946
1947 ret = tda18273_readregs(priv, &gTDA18273_Reg_ID_byte_1__Ident_1, &val, Bus_RW);
1948 id = val << 8;
1949 ret = tda18273_readregs(priv, &gTDA18273_Reg_ID_byte_2__Ident_2, &val, Bus_RW);
1950 id |= val;
1951
1952 if(ret == TDA_RESULT_SUCCESS) {
1953 if(id == TDA_DEVICE_TYPE) {
1954 ret = tda18273_readregs(priv, &gTDA18273_Reg_ID_byte_3__Major_rev, &major, Bus_RW);
1955 ret = tda18273_readregs(priv, &gTDA18273_Reg_ID_byte_3__Minor_rev, &minor, Bus_RW);
1956 dprintk(FE_INFO, 1, "id:%d / ver:%d.%d", id, major, minor);
1957 } else {
1958 return -1;
1959 }
1960 } else {
1961 return -1;
1962 }
1963
1964 priv->pObj = &gTDA18273Instance;
1965
1966 tda18273_hw_init(fe);
1967
1968 return 0;
1969 }
1970
tda18273_get_status(struct dvb_frontend * fe,u32 * status)1971 static int tda18273_get_status(struct dvb_frontend *fe, u32 *status)
1972 {
1973 struct tda18273_state *priv = (struct tda18273_state*)fe->tuner_priv;
1974 unsigned short lock_status = 0;
1975 int ret = 0;
1976
1977 ret = tda18273_get_lock_status(priv, &lock_status);
1978 if (ret)
1979 goto err;
1980 err:
1981 dprintk(FE_DEBUG, 1, "ret=%d", ret);
1982 return ret;
1983 }
1984 #if 0
1985 static int tda18273_get_state(struct dvb_frontend *fe, enum tuner_param param, struct tuner_state *state)
1986 {
1987 struct tda18273_state *priv = fe->tuner_priv;
1988 int ret;
1989
1990 switch (param) {
1991 case DVBFE_TUNER_FREQUENCY:
1992 state->frequency = priv->freq_hz;
1993 ret = 0;
1994 break;
1995 case DVBFE_TUNER_TUNERSTEP:
1996 state->tunerstep = fe->ops.tuner_ops.info.frequency_step_hz;
1997 ret = 0;
1998 break;
1999 case DVBFE_TUNER_IFFREQ:
2000 state->ifreq = priv->if_freq;
2001 ret = 0;
2002 break;
2003 case DVBFE_TUNER_BANDWIDTH:
2004 if (fe->ops.info.type == FE_OFDM)
2005 state->bandwidth = priv->bandwidth;
2006 ret = 0;
2007 break;
2008 default:
2009 ret = -EINVAL;
2010 break;
2011 }
2012 return ret;
2013 }
2014 #endif
tda18273_set_params(struct dvb_frontend * fe)2015 static int tda18273_set_params(struct dvb_frontend *fe)
2016 {
2017 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
2018 struct tda18273_state *priv = fe->tuner_priv;
2019 u32 delsys = c->delivery_system;
2020 u32 bw = c->bandwidth_hz;
2021 u32 freq = c->frequency;
2022 unsigned short lock = 0;
2023 int ret;
2024
2025 BUG_ON(!priv);
2026
2027 dprintk(FE_DEBUG, 1, "freq=%d, bw=%d", freq, bw);
2028
2029 switch (delsys) {
2030 case SYS_ATSC:
2031 tda18273_set_standardmode(fe, TDA18273_ATSC_6MHz);
2032 break;
2033 case SYS_DVBT:
2034 case SYS_DVBT2:
2035 switch (bw) {
2036 case 1700000:
2037 tda18273_set_standardmode(fe, TDA18273_DVBT_1_7MHz);
2038 break;
2039 case 6000000:
2040 tda18273_set_standardmode(fe, TDA18273_DVBT_6MHz);
2041 break;
2042 case 7000000:
2043 tda18273_set_standardmode(fe, TDA18273_DVBT_7MHz);
2044 break;
2045 case 8000000:
2046 tda18273_set_standardmode(fe, TDA18273_DVBT_8MHz);
2047 break;
2048 case 10000000:
2049 tda18273_set_standardmode(fe, TDA18273_DVBT_10MHz);
2050 break;
2051 default:
2052 ret = -EINVAL;
2053 goto err;
2054 }
2055 break;
2056 case SYS_DVBC_ANNEX_A:
2057 case SYS_DVBC_ANNEX_C:
2058 tda18273_set_standardmode(fe, TDA18273_QAM_8MHz);
2059 break;
2060 case SYS_DVBC_ANNEX_B:
2061 tda18273_set_standardmode(fe, TDA18273_QAM_6MHz);
2062 break;
2063 }
2064
2065 ret = tda18273_pwr_state(fe, tmPowerOn);
2066 if (ret)
2067 goto err;
2068
2069 dprintk(FE_DEBUG, 1, "if_freq=%d", priv->pObj->pStandard->IF);
2070
2071 ret = tda18273_set_rf(fe, freq + priv->pObj->pStandard->IF);
2072 if (ret)
2073 goto err;
2074
2075 msleep(100);
2076 tda18273_get_lock_status(priv, &lock);
2077
2078 tda18273_regall_debug(priv);
2079
2080 dprintk(FE_INFO, 1, "Lock status = %d", lock);
2081 if (lock) {
2082 priv->freq_hz = freq;
2083 priv->if_freq = priv->pObj->pStandard->IF;
2084 priv->bandwidth = bw;
2085 }
2086 err:
2087 dprintk(FE_DEBUG, 1, "ret=%d", ret);
2088 return ret;
2089 }
2090
tda18273_get_freq(struct dvb_frontend * fe,u32 * frequency)2091 static int tda18273_get_freq(struct dvb_frontend *fe, u32 *frequency)
2092 {
2093 struct tda18273_state *priv = fe->tuner_priv;
2094
2095 *frequency = priv->freq_hz;
2096 return 0;
2097 }
2098
tda18273_get_if_freq(struct dvb_frontend * fe,u32 * frequency)2099 static int tda18273_get_if_freq(struct dvb_frontend *fe, u32 *frequency)
2100 {
2101 struct tda18273_state *priv = fe->tuner_priv;
2102
2103 *frequency = priv->if_freq;
2104 return 0;
2105 }
2106
tda18273_get_bandwidth(struct dvb_frontend * fe,u32 * bandwidth)2107 static int tda18273_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
2108 {
2109 struct tda18273_state *priv = fe->tuner_priv;
2110
2111 *bandwidth = priv->bandwidth;
2112 return 0;
2113 }
2114
tda18273_release(struct dvb_frontend * fe)2115 static void tda18273_release(struct dvb_frontend *fe)
2116 {
2117 struct tda18273_state *priv = fe->tuner_priv;
2118
2119 BUG_ON(!priv);
2120
2121 if(priv->power_state != tmPowerOff) {
2122 tda18273_pwr_state(fe, tmPowerStandby);
2123 }
2124
2125 fe->tuner_priv = NULL;
2126 kfree(priv);
2127 return;
2128 }
2129
2130 static struct dvb_tuner_ops tda18273_ops = {
2131 .info = {
2132 .name = "TDA18273 Silicon Tuner",
2133 .frequency_min_hz = 42000000,
2134 .frequency_max_hz = 870000000,
2135 .frequency_step_hz = 50000,
2136 },
2137 .init = tda18273_init,
2138 // .sleep = tda18273_sleep,
2139 .get_status = tda18273_get_status,
2140 .set_params = tda18273_set_params,
2141 .get_frequency = tda18273_get_freq,
2142 .get_bandwidth = tda18273_get_bandwidth,
2143 .get_if_frequency = tda18273_get_if_freq,
2144 .release = tda18273_release
2145 };
2146
tda18273_attach(struct dvb_frontend * fe,struct i2c_adapter * i2c,const u8 i2c_addr)2147 struct dvb_frontend *tda18273_attach(struct dvb_frontend *fe,
2148 struct i2c_adapter *i2c,
2149 const u8 i2c_addr)
2150 {
2151 struct tda18273_state *tda18273;
2152 int ret;
2153
2154 BUG_ON(!i2c);
2155
2156 tda18273 = kzalloc(sizeof (struct tda18273_state), GFP_KERNEL);
2157 if (!tda18273)
2158 goto err;
2159
2160 tda18273->i2c = i2c;
2161 tda18273->fe = fe;
2162 tda18273->i2c_addr = i2c_addr;
2163 tda18273->power_state = tmPowerOff;
2164
2165 fe->tuner_priv = tda18273;
2166 fe->ops.tuner_ops = tda18273_ops;
2167
2168 ret = tda18273_init(fe);
2169 if (ret) {
2170 dprintk(FE_ERROR, 1, "Error Initializing!");
2171 goto err;
2172 }
2173
2174 dprintk(FE_DEBUG, 1, "Done");
2175 return tda18273->fe;
2176 err:
2177 kfree(tda18273);
2178 return NULL;
2179 }
2180 EXPORT_SYMBOL(tda18273_attach);
2181
2182 MODULE_AUTHOR("Manu Abraham");
2183 MODULE_DESCRIPTION("TDA18273 Silicon tuner");
2184 MODULE_LICENSE("GPL");
2185