1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2020 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 #ifndef CPUCP_IF_H 9 #define CPUCP_IF_H 10 11 #include <linux/types.h> 12 #include <linux/if_ether.h> 13 14 #include "hl_boot_if.h" 15 16 #define NUM_HBM_PSEUDO_CH 2 17 #define NUM_HBM_CH_PER_DEV 8 18 #define CPUCP_PKT_HBM_ECC_INFO_WR_PAR_SHIFT 0 19 #define CPUCP_PKT_HBM_ECC_INFO_WR_PAR_MASK 0x00000001 20 #define CPUCP_PKT_HBM_ECC_INFO_RD_PAR_SHIFT 1 21 #define CPUCP_PKT_HBM_ECC_INFO_RD_PAR_MASK 0x00000002 22 #define CPUCP_PKT_HBM_ECC_INFO_CA_PAR_SHIFT 2 23 #define CPUCP_PKT_HBM_ECC_INFO_CA_PAR_MASK 0x00000004 24 #define CPUCP_PKT_HBM_ECC_INFO_DERR_SHIFT 3 25 #define CPUCP_PKT_HBM_ECC_INFO_DERR_MASK 0x00000008 26 #define CPUCP_PKT_HBM_ECC_INFO_SERR_SHIFT 4 27 #define CPUCP_PKT_HBM_ECC_INFO_SERR_MASK 0x00000010 28 #define CPUCP_PKT_HBM_ECC_INFO_TYPE_SHIFT 5 29 #define CPUCP_PKT_HBM_ECC_INFO_TYPE_MASK 0x00000020 30 #define CPUCP_PKT_HBM_ECC_INFO_HBM_CH_SHIFT 6 31 #define CPUCP_PKT_HBM_ECC_INFO_HBM_CH_MASK 0x000007C0 32 33 #define PLL_MAP_MAX_BITS 128 34 #define PLL_MAP_LEN (PLL_MAP_MAX_BITS / 8) 35 36 /* 37 * info of the pkt queue pointers in the first async occurrence 38 */ 39 struct cpucp_pkt_sync_err { 40 __le32 pi; 41 __le32 ci; 42 }; 43 44 struct hl_eq_hbm_ecc_data { 45 /* SERR counter */ 46 __le32 sec_cnt; 47 /* DERR counter */ 48 __le32 dec_cnt; 49 /* Supplemental Information according to the mask bits */ 50 __le32 hbm_ecc_info; 51 /* Address in hbm where the ecc happened */ 52 __le32 first_addr; 53 /* SERR continuous address counter */ 54 __le32 sec_cont_cnt; 55 __le32 pad; 56 }; 57 58 /* 59 * EVENT QUEUE 60 */ 61 62 struct hl_eq_header { 63 __le32 reserved; 64 __le32 ctl; 65 }; 66 67 struct hl_eq_ecc_data { 68 __le64 ecc_address; 69 __le64 ecc_syndrom; 70 __u8 memory_wrapper_idx; 71 __u8 pad[7]; 72 }; 73 74 enum hl_sm_sei_cause { 75 SM_SEI_SO_OVERFLOW, 76 SM_SEI_LBW_4B_UNALIGNED, 77 SM_SEI_AXI_RESPONSE_ERR 78 }; 79 80 struct hl_eq_sm_sei_data { 81 __le32 sei_log; 82 /* enum hl_sm_sei_cause */ 83 __u8 sei_cause; 84 __u8 pad[3]; 85 }; 86 87 struct hl_eq_entry { 88 struct hl_eq_header hdr; 89 union { 90 struct hl_eq_ecc_data ecc_data; 91 struct hl_eq_hbm_ecc_data hbm_ecc_data; 92 struct hl_eq_sm_sei_data sm_sei_data; 93 struct cpucp_pkt_sync_err pkt_sync_err; 94 __le64 data[7]; 95 }; 96 }; 97 98 #define HL_EQ_ENTRY_SIZE sizeof(struct hl_eq_entry) 99 100 #define EQ_CTL_READY_SHIFT 31 101 #define EQ_CTL_READY_MASK 0x80000000 102 103 #define EQ_CTL_EVENT_TYPE_SHIFT 16 104 #define EQ_CTL_EVENT_TYPE_MASK 0x03FF0000 105 106 enum pq_init_status { 107 PQ_INIT_STATUS_NA = 0, 108 PQ_INIT_STATUS_READY_FOR_CP, 109 PQ_INIT_STATUS_READY_FOR_HOST, 110 PQ_INIT_STATUS_READY_FOR_CP_SINGLE_MSI 111 }; 112 113 /* 114 * CpuCP Primary Queue Packets 115 * 116 * During normal operation, the host's kernel driver needs to send various 117 * messages to CpuCP, usually either to SET some value into a H/W periphery or 118 * to GET the current value of some H/W periphery. For example, SET the 119 * frequency of MME/TPC and GET the value of the thermal sensor. 120 * 121 * These messages can be initiated either by the User application or by the 122 * host's driver itself, e.g. power management code. In either case, the 123 * communication from the host's driver to CpuCP will *always* be in 124 * synchronous mode, meaning that the host will send a single message and poll 125 * until the message was acknowledged and the results are ready (if results are 126 * needed). 127 * 128 * This means that only a single message can be sent at a time and the host's 129 * driver must wait for its result before sending the next message. Having said 130 * that, because these are control messages which are sent in a relatively low 131 * frequency, this limitation seems acceptable. It's important to note that 132 * in case of multiple devices, messages to different devices *can* be sent 133 * at the same time. 134 * 135 * The message, inputs/outputs (if relevant) and fence object will be located 136 * on the device DDR at an address that will be determined by the host's driver. 137 * During device initialization phase, the host will pass to CpuCP that address. 138 * Most of the message types will contain inputs/outputs inside the message 139 * itself. The common part of each message will contain the opcode of the 140 * message (its type) and a field representing a fence object. 141 * 142 * When the host's driver wishes to send a message to CPU CP, it will write the 143 * message contents to the device DDR, clear the fence object and then write to 144 * the PSOC_ARC1_AUX_SW_INTR, to issue interrupt 121 to ARC Management CPU. 145 * 146 * Upon receiving the interrupt (#121), CpuCP will read the message from the 147 * DDR. In case the message is a SET operation, CpuCP will first perform the 148 * operation and then write to the fence object on the device DDR. In case the 149 * message is a GET operation, CpuCP will first fill the results section on the 150 * device DDR and then write to the fence object. If an error occurred, CpuCP 151 * will fill the rc field with the right error code. 152 * 153 * In the meantime, the host's driver will poll on the fence object. Once the 154 * host sees that the fence object is signaled, it will read the results from 155 * the device DDR (if relevant) and resume the code execution in the host's 156 * driver. 157 * 158 * To use QMAN packets, the opcode must be the QMAN opcode, shifted by 8 159 * so the value being put by the host's driver matches the value read by CpuCP 160 * 161 * Non-QMAN packets should be limited to values 1 through (2^8 - 1) 162 * 163 * Detailed description: 164 * 165 * CPUCP_PACKET_DISABLE_PCI_ACCESS - 166 * After receiving this packet the embedded CPU must NOT issue PCI 167 * transactions (read/write) towards the Host CPU. This also include 168 * sending MSI-X interrupts. 169 * This packet is usually sent before the device is moved to D3Hot state. 170 * 171 * CPUCP_PACKET_ENABLE_PCI_ACCESS - 172 * After receiving this packet the embedded CPU is allowed to issue PCI 173 * transactions towards the Host CPU, including sending MSI-X interrupts. 174 * This packet is usually send after the device is moved to D0 state. 175 * 176 * CPUCP_PACKET_TEMPERATURE_GET - 177 * Fetch the current temperature / Max / Max Hyst / Critical / 178 * Critical Hyst of a specified thermal sensor. The packet's 179 * arguments specify the desired sensor and the field to get. 180 * 181 * CPUCP_PACKET_VOLTAGE_GET - 182 * Fetch the voltage / Max / Min of a specified sensor. The packet's 183 * arguments specify the sensor and type. 184 * 185 * CPUCP_PACKET_CURRENT_GET - 186 * Fetch the current / Max / Min of a specified sensor. The packet's 187 * arguments specify the sensor and type. 188 * 189 * CPUCP_PACKET_FAN_SPEED_GET - 190 * Fetch the speed / Max / Min of a specified fan. The packet's 191 * arguments specify the sensor and type. 192 * 193 * CPUCP_PACKET_PWM_GET - 194 * Fetch the pwm value / mode of a specified pwm. The packet's 195 * arguments specify the sensor and type. 196 * 197 * CPUCP_PACKET_PWM_SET - 198 * Set the pwm value / mode of a specified pwm. The packet's 199 * arguments specify the sensor, type and value. 200 * 201 * CPUCP_PACKET_FREQUENCY_SET - 202 * Set the frequency of a specified PLL. The packet's arguments specify 203 * the PLL and the desired frequency. The actual frequency in the device 204 * might differ from the requested frequency. 205 * 206 * CPUCP_PACKET_FREQUENCY_GET - 207 * Fetch the frequency of a specified PLL. The packet's arguments specify 208 * the PLL. 209 * 210 * CPUCP_PACKET_LED_SET - 211 * Set the state of a specified led. The packet's arguments 212 * specify the led and the desired state. 213 * 214 * CPUCP_PACKET_I2C_WR - 215 * Write 32-bit value to I2C device. The packet's arguments specify the 216 * I2C bus, address and value. 217 * 218 * CPUCP_PACKET_I2C_RD - 219 * Read 32-bit value from I2C device. The packet's arguments specify the 220 * I2C bus and address. 221 * 222 * CPUCP_PACKET_INFO_GET - 223 * Fetch information from the device as specified in the packet's 224 * structure. The host's driver passes the max size it allows the CpuCP to 225 * write to the structure, to prevent data corruption in case of 226 * mismatched driver/FW versions. 227 * 228 * CPUCP_PACKET_FLASH_PROGRAM_REMOVED - this packet was removed 229 * 230 * CPUCP_PACKET_UNMASK_RAZWI_IRQ - 231 * Unmask the given IRQ. The IRQ number is specified in the value field. 232 * The packet is sent after receiving an interrupt and printing its 233 * relevant information. 234 * 235 * CPUCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY - 236 * Unmask the given IRQs. The IRQs numbers are specified in an array right 237 * after the cpucp_packet structure, where its first element is the array 238 * length. The packet is sent after a soft reset was done in order to 239 * handle any interrupts that were sent during the reset process. 240 * 241 * CPUCP_PACKET_TEST - 242 * Test packet for CpuCP connectivity. The CPU will put the fence value 243 * in the result field. 244 * 245 * CPUCP_PACKET_FREQUENCY_CURR_GET - 246 * Fetch the current frequency of a specified PLL. The packet's arguments 247 * specify the PLL. 248 * 249 * CPUCP_PACKET_MAX_POWER_GET - 250 * Fetch the maximal power of the device. 251 * 252 * CPUCP_PACKET_MAX_POWER_SET - 253 * Set the maximal power of the device. The packet's arguments specify 254 * the power. 255 * 256 * CPUCP_PACKET_EEPROM_DATA_GET - 257 * Get EEPROM data from the CpuCP kernel. The buffer is specified in the 258 * addr field. The CPU will put the returned data size in the result 259 * field. In addition, the host's driver passes the max size it allows the 260 * CpuCP to write to the structure, to prevent data corruption in case of 261 * mismatched driver/FW versions. 262 * 263 * CPUCP_PACKET_NIC_INFO_GET - 264 * Fetch information from the device regarding the NIC. the host's driver 265 * passes the max size it allows the CpuCP to write to the structure, to 266 * prevent data corruption in case of mismatched driver/FW versions. 267 * 268 * CPUCP_PACKET_TEMPERATURE_SET - 269 * Set the value of the offset property of a specified thermal sensor. 270 * The packet's arguments specify the desired sensor and the field to 271 * set. 272 * 273 * CPUCP_PACKET_VOLTAGE_SET - 274 * Trigger the reset_history property of a specified voltage sensor. 275 * The packet's arguments specify the desired sensor and the field to 276 * set. 277 * 278 * CPUCP_PACKET_CURRENT_SET - 279 * Trigger the reset_history property of a specified current sensor. 280 * The packet's arguments specify the desired sensor and the field to 281 * set. 282 * 283 * CPUCP_PACKET_PCIE_THROUGHPUT_GET 284 * Get throughput of PCIe. 285 * The packet's arguments specify the transaction direction (TX/RX). 286 * The window measurement is 10[msec], and the return value is in KB/sec. 287 * 288 * CPUCP_PACKET_PCIE_REPLAY_CNT_GET 289 * Replay count measures number of "replay" events, which is basicly 290 * number of retries done by PCIe. 291 * 292 * CPUCP_PACKET_TOTAL_ENERGY_GET 293 * Total Energy is measurement of energy from the time FW Linux 294 * is loaded. It is calculated by multiplying the average power 295 * by time (passed from armcp start). The units are in MilliJouls. 296 * 297 * CPUCP_PACKET_PLL_INFO_GET 298 * Fetch frequencies of PLL from the required PLL IP. 299 * The packet's arguments specify the device PLL type 300 * Pll type is the PLL from device pll_index enum. 301 * The result is composed of 4 outputs, each is 16-bit 302 * frequency in MHz. 303 * 304 * CPUCP_PACKET_POWER_GET 305 * Fetch the present power consumption of the device (Current * Voltage). 306 * 307 * CPUCP_PACKET_NIC_PFC_SET - 308 * Enable/Disable the NIC PFC feature. The packet's arguments specify the 309 * NIC port, relevant lanes to configure and one bit indication for 310 * enable/disable. 311 * 312 * CPUCP_PACKET_NIC_FAULT_GET - 313 * Fetch the current indication for local/remote faults from the NIC MAC. 314 * The result is 32-bit value of the relevant register. 315 * 316 * CPUCP_PACKET_NIC_LPBK_SET - 317 * Enable/Disable the MAC loopback feature. The packet's arguments specify 318 * the NIC port, relevant lanes to configure and one bit indication for 319 * enable/disable. 320 * 321 * CPUCP_PACKET_NIC_MAC_INIT - 322 * Configure the NIC MAC channels. The packet's arguments specify the 323 * NIC port and the speed. 324 * 325 * CPUCP_PACKET_MSI_INFO_SET - 326 * set the index number for each supported msi type going from 327 * host to device 328 */ 329 330 enum cpucp_packet_id { 331 CPUCP_PACKET_DISABLE_PCI_ACCESS = 1, /* internal */ 332 CPUCP_PACKET_ENABLE_PCI_ACCESS, /* internal */ 333 CPUCP_PACKET_TEMPERATURE_GET, /* sysfs */ 334 CPUCP_PACKET_VOLTAGE_GET, /* sysfs */ 335 CPUCP_PACKET_CURRENT_GET, /* sysfs */ 336 CPUCP_PACKET_FAN_SPEED_GET, /* sysfs */ 337 CPUCP_PACKET_PWM_GET, /* sysfs */ 338 CPUCP_PACKET_PWM_SET, /* sysfs */ 339 CPUCP_PACKET_FREQUENCY_SET, /* sysfs */ 340 CPUCP_PACKET_FREQUENCY_GET, /* sysfs */ 341 CPUCP_PACKET_LED_SET, /* debugfs */ 342 CPUCP_PACKET_I2C_WR, /* debugfs */ 343 CPUCP_PACKET_I2C_RD, /* debugfs */ 344 CPUCP_PACKET_INFO_GET, /* IOCTL */ 345 CPUCP_PACKET_FLASH_PROGRAM_REMOVED, 346 CPUCP_PACKET_UNMASK_RAZWI_IRQ, /* internal */ 347 CPUCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY, /* internal */ 348 CPUCP_PACKET_TEST, /* internal */ 349 CPUCP_PACKET_FREQUENCY_CURR_GET, /* sysfs */ 350 CPUCP_PACKET_MAX_POWER_GET, /* sysfs */ 351 CPUCP_PACKET_MAX_POWER_SET, /* sysfs */ 352 CPUCP_PACKET_EEPROM_DATA_GET, /* sysfs */ 353 CPUCP_PACKET_NIC_INFO_GET, /* internal */ 354 CPUCP_PACKET_TEMPERATURE_SET, /* sysfs */ 355 CPUCP_PACKET_VOLTAGE_SET, /* sysfs */ 356 CPUCP_PACKET_CURRENT_SET, /* sysfs */ 357 CPUCP_PACKET_PCIE_THROUGHPUT_GET, /* internal */ 358 CPUCP_PACKET_PCIE_REPLAY_CNT_GET, /* internal */ 359 CPUCP_PACKET_TOTAL_ENERGY_GET, /* internal */ 360 CPUCP_PACKET_PLL_INFO_GET, /* internal */ 361 CPUCP_PACKET_NIC_STATUS, /* internal */ 362 CPUCP_PACKET_POWER_GET, /* internal */ 363 CPUCP_PACKET_NIC_PFC_SET, /* internal */ 364 CPUCP_PACKET_NIC_FAULT_GET, /* internal */ 365 CPUCP_PACKET_NIC_LPBK_SET, /* internal */ 366 CPUCP_PACKET_NIC_MAC_CFG, /* internal */ 367 CPUCP_PACKET_MSI_INFO_SET, /* internal */ 368 }; 369 370 #define CPUCP_PACKET_FENCE_VAL 0xFE8CE7A5 371 372 #define CPUCP_PKT_CTL_RC_SHIFT 12 373 #define CPUCP_PKT_CTL_RC_MASK 0x0000F000 374 375 #define CPUCP_PKT_CTL_OPCODE_SHIFT 16 376 #define CPUCP_PKT_CTL_OPCODE_MASK 0x1FFF0000 377 378 #define CPUCP_PKT_RES_PLL_OUT0_SHIFT 0 379 #define CPUCP_PKT_RES_PLL_OUT0_MASK 0x000000000000FFFFull 380 #define CPUCP_PKT_RES_PLL_OUT1_SHIFT 16 381 #define CPUCP_PKT_RES_PLL_OUT1_MASK 0x00000000FFFF0000ull 382 #define CPUCP_PKT_RES_PLL_OUT2_SHIFT 32 383 #define CPUCP_PKT_RES_PLL_OUT2_MASK 0x0000FFFF00000000ull 384 #define CPUCP_PKT_RES_PLL_OUT3_SHIFT 48 385 #define CPUCP_PKT_RES_PLL_OUT3_MASK 0xFFFF000000000000ull 386 387 struct cpucp_packet { 388 union { 389 __le64 value; /* For SET packets */ 390 __le64 result; /* For GET packets */ 391 __le64 addr; /* For PQ */ 392 }; 393 394 __le32 ctl; 395 396 __le32 fence; /* Signal to host that message is completed */ 397 398 union { 399 struct {/* For temperature/current/voltage/fan/pwm get/set */ 400 __le16 sensor_index; 401 __le16 type; 402 }; 403 404 struct { /* For I2C read/write */ 405 __u8 i2c_bus; 406 __u8 i2c_addr; 407 __u8 i2c_reg; 408 __u8 pad; /* unused */ 409 }; 410 411 struct {/* For PLL info fetch */ 412 __le16 pll_type; 413 /* TODO pll_reg is kept temporary before removal */ 414 __le16 pll_reg; 415 }; 416 417 /* For any general request */ 418 __le32 index; 419 420 /* For frequency get/set */ 421 __le32 pll_index; 422 423 /* For led set */ 424 __le32 led_index; 425 426 /* For get CpuCP info/EEPROM data/NIC info */ 427 __le32 data_max_size; 428 }; 429 430 __le32 reserved; 431 }; 432 433 struct cpucp_unmask_irq_arr_packet { 434 struct cpucp_packet cpucp_pkt; 435 __le32 length; 436 __le32 irqs[0]; 437 }; 438 439 struct cpucp_array_data_packet { 440 struct cpucp_packet cpucp_pkt; 441 __le32 length; 442 __le32 data[0]; 443 }; 444 445 enum cpucp_packet_rc { 446 cpucp_packet_success, 447 cpucp_packet_invalid, 448 cpucp_packet_fault 449 }; 450 451 /* 452 * cpucp_temp_type should adhere to hwmon_temp_attributes 453 * defined in Linux kernel hwmon.h file 454 */ 455 enum cpucp_temp_type { 456 cpucp_temp_input, 457 cpucp_temp_max = 6, 458 cpucp_temp_max_hyst, 459 cpucp_temp_crit, 460 cpucp_temp_crit_hyst, 461 cpucp_temp_offset = 19, 462 cpucp_temp_highest = 22, 463 cpucp_temp_reset_history = 23 464 }; 465 466 enum cpucp_in_attributes { 467 cpucp_in_input, 468 cpucp_in_min, 469 cpucp_in_max, 470 cpucp_in_highest = 7, 471 cpucp_in_reset_history 472 }; 473 474 enum cpucp_curr_attributes { 475 cpucp_curr_input, 476 cpucp_curr_min, 477 cpucp_curr_max, 478 cpucp_curr_highest = 7, 479 cpucp_curr_reset_history 480 }; 481 482 enum cpucp_fan_attributes { 483 cpucp_fan_input, 484 cpucp_fan_min = 2, 485 cpucp_fan_max 486 }; 487 488 enum cpucp_pwm_attributes { 489 cpucp_pwm_input, 490 cpucp_pwm_enable 491 }; 492 493 enum cpucp_pcie_throughput_attributes { 494 cpucp_pcie_throughput_tx, 495 cpucp_pcie_throughput_rx 496 }; 497 498 /* TODO temporary kept before removal */ 499 enum cpucp_pll_reg_attributes { 500 cpucp_pll_nr_reg, 501 cpucp_pll_nf_reg, 502 cpucp_pll_od_reg, 503 cpucp_pll_div_factor_reg, 504 cpucp_pll_div_sel_reg 505 }; 506 507 /* TODO temporary kept before removal */ 508 enum cpucp_pll_type_attributes { 509 cpucp_pll_cpu, 510 cpucp_pll_pci, 511 }; 512 513 /* 514 * MSI type enumeration table for all ASICs and future SW versions. 515 * For future ASIC-LKD compatibility, we can only add new enumerations. 516 * at the end of the table (before CPUCP_NUM_OF_MSI_TYPES). 517 * Changing the order of entries or removing entries is not allowed. 518 */ 519 enum cpucp_msi_type { 520 CPUCP_EVENT_QUEUE_MSI_TYPE, 521 CPUCP_NIC_PORT1_MSI_TYPE, 522 CPUCP_NIC_PORT3_MSI_TYPE, 523 CPUCP_NIC_PORT5_MSI_TYPE, 524 CPUCP_NIC_PORT7_MSI_TYPE, 525 CPUCP_NIC_PORT9_MSI_TYPE, 526 CPUCP_NUM_OF_MSI_TYPES 527 }; 528 529 /* 530 * PLL enumeration table used for all ASICs and future SW versions. 531 * For future ASIC-LKD compatibility, we can only add new enumerations. 532 * at the end of the table. 533 * Changing the order of entries or removing entries is not allowed. 534 */ 535 enum pll_index { 536 CPU_PLL = 0, 537 PCI_PLL = 1, 538 NIC_PLL = 2, 539 DMA_PLL = 3, 540 MESH_PLL = 4, 541 MME_PLL = 5, 542 TPC_PLL = 6, 543 IF_PLL = 7, 544 SRAM_PLL = 8, 545 NS_PLL = 9, 546 HBM_PLL = 10, 547 MSS_PLL = 11, 548 DDR_PLL = 12, 549 VID_PLL = 13, 550 BANK_PLL = 14, 551 MMU_PLL = 15, 552 IC_PLL = 16, 553 MC_PLL = 17, 554 EMMC_PLL = 18, 555 PLL_MAX 556 }; 557 558 /* Event Queue Packets */ 559 560 struct eq_generic_event { 561 __le64 data[7]; 562 }; 563 564 /* 565 * CpuCP info 566 */ 567 568 #define CARD_NAME_MAX_LEN 16 569 #define CPUCP_MAX_SENSORS 128 570 #define CPUCP_MAX_NICS 128 571 #define CPUCP_LANES_PER_NIC 4 572 #define CPUCP_NIC_QSFP_EEPROM_MAX_LEN 1024 573 #define CPUCP_MAX_NIC_LANES (CPUCP_MAX_NICS * CPUCP_LANES_PER_NIC) 574 #define CPUCP_NIC_MASK_ARR_LEN ((CPUCP_MAX_NICS + 63) / 64) 575 #define CPUCP_NIC_POLARITY_ARR_LEN ((CPUCP_MAX_NIC_LANES + 63) / 64) 576 577 struct cpucp_sensor { 578 __le32 type; 579 __le32 flags; 580 }; 581 582 /** 583 * struct cpucp_card_types - ASIC card type. 584 * @cpucp_card_type_pci: PCI card. 585 * @cpucp_card_type_pmc: PCI Mezzanine Card. 586 */ 587 enum cpucp_card_types { 588 cpucp_card_type_pci, 589 cpucp_card_type_pmc 590 }; 591 592 #define CPUCP_SEC_CONF_ENABLED_SHIFT 0 593 #define CPUCP_SEC_CONF_ENABLED_MASK 0x00000001 594 595 #define CPUCP_SEC_CONF_FLASH_WP_SHIFT 1 596 #define CPUCP_SEC_CONF_FLASH_WP_MASK 0x00000002 597 598 #define CPUCP_SEC_CONF_EEPROM_WP_SHIFT 2 599 #define CPUCP_SEC_CONF_EEPROM_WP_MASK 0x00000004 600 601 /** 602 * struct cpucp_security_info - Security information. 603 * @config: configuration bit field 604 * @keys_num: number of stored keys 605 * @revoked_keys: revoked keys bit field 606 * @min_svn: minimal security version 607 */ 608 struct cpucp_security_info { 609 __u8 config; 610 __u8 keys_num; 611 __u8 revoked_keys; 612 __u8 min_svn; 613 }; 614 615 /** 616 * struct cpucp_info - Info from CpuCP that is necessary to the host's driver 617 * @sensors: available sensors description. 618 * @kernel_version: CpuCP linux kernel version. 619 * @reserved: reserved field. 620 * @card_type: card configuration type. 621 * @card_location: in a server, each card has different connections topology 622 * depending on its location (relevant for PMC card type) 623 * @cpld_version: CPLD programmed F/W version. 624 * @infineon_version: Infineon main DC-DC version. 625 * @fuse_version: silicon production FUSE information. 626 * @thermal_version: thermald S/W version. 627 * @cpucp_version: CpuCP S/W version. 628 * @dram_size: available DRAM size. 629 * @card_name: card name that will be displayed in HWMON subsystem on the host 630 * @sec_info: security information 631 * @pll_map: Bit map of supported PLLs for current ASIC version. 632 */ 633 struct cpucp_info { 634 struct cpucp_sensor sensors[CPUCP_MAX_SENSORS]; 635 __u8 kernel_version[VERSION_MAX_LEN]; 636 __le32 reserved; 637 __le32 card_type; 638 __le32 card_location; 639 __le32 cpld_version; 640 __le32 infineon_version; 641 __u8 fuse_version[VERSION_MAX_LEN]; 642 __u8 thermal_version[VERSION_MAX_LEN]; 643 __u8 cpucp_version[VERSION_MAX_LEN]; 644 __le32 reserved2; 645 __le64 dram_size; 646 char card_name[CARD_NAME_MAX_LEN]; 647 __le64 reserved3; 648 __le64 reserved4; 649 __u8 reserved5; 650 __u8 pad[7]; 651 struct cpucp_security_info sec_info; 652 __le32 reserved6; 653 __u8 pll_map[PLL_MAP_LEN]; 654 }; 655 656 struct cpucp_mac_addr { 657 __u8 mac_addr[ETH_ALEN]; 658 }; 659 660 struct cpucp_nic_info { 661 struct cpucp_mac_addr mac_addrs[CPUCP_MAX_NICS]; 662 __le64 link_mask[CPUCP_NIC_MASK_ARR_LEN]; 663 __le64 pol_tx_mask[CPUCP_NIC_POLARITY_ARR_LEN]; 664 __le64 pol_rx_mask[CPUCP_NIC_POLARITY_ARR_LEN]; 665 __le64 link_ext_mask[CPUCP_NIC_MASK_ARR_LEN]; 666 __u8 qsfp_eeprom[CPUCP_NIC_QSFP_EEPROM_MAX_LEN]; 667 __le64 auto_neg_mask[CPUCP_NIC_MASK_ARR_LEN]; 668 }; 669 670 #endif /* CPUCP_IF_H */ 671