1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Overview:
4 * This is the generic MTD driver for NAND flash devices. It should be
5 * capable of working with almost all NAND chips currently available.
6 *
7 * Additional technical information is available on
8 * http://www.linux-mtd.infradead.org/doc/nand.html
9 *
10 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
11 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
12 *
13 * Credits:
14 * David Woodhouse for adding multichip support
15 *
16 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
17 * rework for 2K page size chips
18 *
19 * TODO:
20 * Enable cached programming for 2k page size chips
21 * Check, if mtd->ecctype should be set to MTD_ECC_HW
22 * if we have HW ECC support.
23 * BBT table is not serialized, has to be fixed
24 */
25
26 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27
28 #include <linux/module.h>
29 #include <linux/delay.h>
30 #include <linux/errno.h>
31 #include <linux/err.h>
32 #include <linux/sched.h>
33 #include <linux/slab.h>
34 #include <linux/mm.h>
35 #include <linux/types.h>
36 #include <linux/mtd/mtd.h>
37 #include <linux/mtd/nand.h>
38 #include <linux/mtd/nand-ecc-sw-hamming.h>
39 #include <linux/mtd/nand-ecc-sw-bch.h>
40 #include <linux/interrupt.h>
41 #include <linux/bitops.h>
42 #include <linux/io.h>
43 #include <linux/mtd/partitions.h>
44 #include <linux/of.h>
45 #include <linux/gpio/consumer.h>
46
47 #include "internals.h"
48
nand_pairing_dist3_get_info(struct mtd_info * mtd,int page,struct mtd_pairing_info * info)49 static int nand_pairing_dist3_get_info(struct mtd_info *mtd, int page,
50 struct mtd_pairing_info *info)
51 {
52 int lastpage = (mtd->erasesize / mtd->writesize) - 1;
53 int dist = 3;
54
55 if (page == lastpage)
56 dist = 2;
57
58 if (!page || (page & 1)) {
59 info->group = 0;
60 info->pair = (page + 1) / 2;
61 } else {
62 info->group = 1;
63 info->pair = (page + 1 - dist) / 2;
64 }
65
66 return 0;
67 }
68
nand_pairing_dist3_get_wunit(struct mtd_info * mtd,const struct mtd_pairing_info * info)69 static int nand_pairing_dist3_get_wunit(struct mtd_info *mtd,
70 const struct mtd_pairing_info *info)
71 {
72 int lastpair = ((mtd->erasesize / mtd->writesize) - 1) / 2;
73 int page = info->pair * 2;
74 int dist = 3;
75
76 if (!info->group && !info->pair)
77 return 0;
78
79 if (info->pair == lastpair && info->group)
80 dist = 2;
81
82 if (!info->group)
83 page--;
84 else if (info->pair)
85 page += dist - 1;
86
87 if (page >= mtd->erasesize / mtd->writesize)
88 return -EINVAL;
89
90 return page;
91 }
92
93 const struct mtd_pairing_scheme dist3_pairing_scheme = {
94 .ngroups = 2,
95 .get_info = nand_pairing_dist3_get_info,
96 .get_wunit = nand_pairing_dist3_get_wunit,
97 };
98
check_offs_len(struct nand_chip * chip,loff_t ofs,uint64_t len)99 static int check_offs_len(struct nand_chip *chip, loff_t ofs, uint64_t len)
100 {
101 int ret = 0;
102
103 /* Start address must align on block boundary */
104 if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
105 pr_debug("%s: unaligned address\n", __func__);
106 ret = -EINVAL;
107 }
108
109 /* Length must align on block boundary */
110 if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
111 pr_debug("%s: length not block aligned\n", __func__);
112 ret = -EINVAL;
113 }
114
115 return ret;
116 }
117
118 /**
119 * nand_extract_bits - Copy unaligned bits from one buffer to another one
120 * @dst: destination buffer
121 * @dst_off: bit offset at which the writing starts
122 * @src: source buffer
123 * @src_off: bit offset at which the reading starts
124 * @nbits: number of bits to copy from @src to @dst
125 *
126 * Copy bits from one memory region to another (overlap authorized).
127 */
nand_extract_bits(u8 * dst,unsigned int dst_off,const u8 * src,unsigned int src_off,unsigned int nbits)128 void nand_extract_bits(u8 *dst, unsigned int dst_off, const u8 *src,
129 unsigned int src_off, unsigned int nbits)
130 {
131 unsigned int tmp, n;
132
133 dst += dst_off / 8;
134 dst_off %= 8;
135 src += src_off / 8;
136 src_off %= 8;
137
138 while (nbits) {
139 n = min3(8 - dst_off, 8 - src_off, nbits);
140
141 tmp = (*src >> src_off) & GENMASK(n - 1, 0);
142 *dst &= ~GENMASK(n - 1 + dst_off, dst_off);
143 *dst |= tmp << dst_off;
144
145 dst_off += n;
146 if (dst_off >= 8) {
147 dst++;
148 dst_off -= 8;
149 }
150
151 src_off += n;
152 if (src_off >= 8) {
153 src++;
154 src_off -= 8;
155 }
156
157 nbits -= n;
158 }
159 }
160 EXPORT_SYMBOL_GPL(nand_extract_bits);
161
162 /**
163 * nand_select_target() - Select a NAND target (A.K.A. die)
164 * @chip: NAND chip object
165 * @cs: the CS line to select. Note that this CS id is always from the chip
166 * PoV, not the controller one
167 *
168 * Select a NAND target so that further operations executed on @chip go to the
169 * selected NAND target.
170 */
nand_select_target(struct nand_chip * chip,unsigned int cs)171 void nand_select_target(struct nand_chip *chip, unsigned int cs)
172 {
173 /*
174 * cs should always lie between 0 and nanddev_ntargets(), when that's
175 * not the case it's a bug and the caller should be fixed.
176 */
177 if (WARN_ON(cs > nanddev_ntargets(&chip->base)))
178 return;
179
180 chip->cur_cs = cs;
181
182 if (chip->legacy.select_chip)
183 chip->legacy.select_chip(chip, cs);
184 }
185 EXPORT_SYMBOL_GPL(nand_select_target);
186
187 /**
188 * nand_deselect_target() - Deselect the currently selected target
189 * @chip: NAND chip object
190 *
191 * Deselect the currently selected NAND target. The result of operations
192 * executed on @chip after the target has been deselected is undefined.
193 */
nand_deselect_target(struct nand_chip * chip)194 void nand_deselect_target(struct nand_chip *chip)
195 {
196 if (chip->legacy.select_chip)
197 chip->legacy.select_chip(chip, -1);
198
199 chip->cur_cs = -1;
200 }
201 EXPORT_SYMBOL_GPL(nand_deselect_target);
202
203 /**
204 * nand_release_device - [GENERIC] release chip
205 * @chip: NAND chip object
206 *
207 * Release chip lock and wake up anyone waiting on the device.
208 */
nand_release_device(struct nand_chip * chip)209 static void nand_release_device(struct nand_chip *chip)
210 {
211 /* Release the controller and the chip */
212 mutex_unlock(&chip->controller->lock);
213 mutex_unlock(&chip->lock);
214 }
215
216 /**
217 * nand_bbm_get_next_page - Get the next page for bad block markers
218 * @chip: NAND chip object
219 * @page: First page to start checking for bad block marker usage
220 *
221 * Returns an integer that corresponds to the page offset within a block, for
222 * a page that is used to store bad block markers. If no more pages are
223 * available, -EINVAL is returned.
224 */
nand_bbm_get_next_page(struct nand_chip * chip,int page)225 int nand_bbm_get_next_page(struct nand_chip *chip, int page)
226 {
227 struct mtd_info *mtd = nand_to_mtd(chip);
228 int last_page = ((mtd->erasesize - mtd->writesize) >>
229 chip->page_shift) & chip->pagemask;
230 unsigned int bbm_flags = NAND_BBM_FIRSTPAGE | NAND_BBM_SECONDPAGE
231 | NAND_BBM_LASTPAGE;
232
233 if (page == 0 && !(chip->options & bbm_flags))
234 return 0;
235 if (page == 0 && chip->options & NAND_BBM_FIRSTPAGE)
236 return 0;
237 if (page <= 1 && chip->options & NAND_BBM_SECONDPAGE)
238 return 1;
239 if (page <= last_page && chip->options & NAND_BBM_LASTPAGE)
240 return last_page;
241
242 return -EINVAL;
243 }
244
245 /**
246 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
247 * @chip: NAND chip object
248 * @ofs: offset from device start
249 *
250 * Check, if the block is bad.
251 */
nand_block_bad(struct nand_chip * chip,loff_t ofs)252 static int nand_block_bad(struct nand_chip *chip, loff_t ofs)
253 {
254 int first_page, page_offset;
255 int res;
256 u8 bad;
257
258 first_page = (int)(ofs >> chip->page_shift) & chip->pagemask;
259 page_offset = nand_bbm_get_next_page(chip, 0);
260
261 while (page_offset >= 0) {
262 res = chip->ecc.read_oob(chip, first_page + page_offset);
263 if (res < 0)
264 return res;
265
266 bad = chip->oob_poi[chip->badblockpos];
267
268 if (likely(chip->badblockbits == 8))
269 res = bad != 0xFF;
270 else
271 res = hweight8(bad) < chip->badblockbits;
272 if (res)
273 return res;
274
275 page_offset = nand_bbm_get_next_page(chip, page_offset + 1);
276 }
277
278 return 0;
279 }
280
281 /**
282 * nand_region_is_secured() - Check if the region is secured
283 * @chip: NAND chip object
284 * @offset: Offset of the region to check
285 * @size: Size of the region to check
286 *
287 * Checks if the region is secured by comparing the offset and size with the
288 * list of secure regions obtained from DT. Returns true if the region is
289 * secured else false.
290 */
nand_region_is_secured(struct nand_chip * chip,loff_t offset,u64 size)291 static bool nand_region_is_secured(struct nand_chip *chip, loff_t offset, u64 size)
292 {
293 int i;
294
295 /* Skip touching the secure regions if present */
296 for (i = 0; i < chip->nr_secure_regions; i++) {
297 const struct nand_secure_region *region = &chip->secure_regions[i];
298
299 if (offset + size <= region->offset ||
300 offset >= region->offset + region->size)
301 continue;
302
303 pr_debug("%s: Region 0x%llx - 0x%llx is secured!",
304 __func__, offset, offset + size);
305
306 return true;
307 }
308
309 return false;
310 }
311
nand_isbad_bbm(struct nand_chip * chip,loff_t ofs)312 static int nand_isbad_bbm(struct nand_chip *chip, loff_t ofs)
313 {
314 struct mtd_info *mtd = nand_to_mtd(chip);
315
316 if (chip->options & NAND_NO_BBM_QUIRK)
317 return 0;
318
319 /* Check if the region is secured */
320 if (nand_region_is_secured(chip, ofs, mtd->erasesize))
321 return -EIO;
322
323 if (chip->legacy.block_bad)
324 return chip->legacy.block_bad(chip, ofs);
325
326 return nand_block_bad(chip, ofs);
327 }
328
329 /**
330 * nand_get_device - [GENERIC] Get chip for selected access
331 * @chip: NAND chip structure
332 *
333 * Lock the device and its controller for exclusive access
334 *
335 * Return: -EBUSY if the chip has been suspended, 0 otherwise
336 */
nand_get_device(struct nand_chip * chip)337 static int nand_get_device(struct nand_chip *chip)
338 {
339 mutex_lock(&chip->lock);
340 if (chip->suspended) {
341 mutex_unlock(&chip->lock);
342 return -EBUSY;
343 }
344 mutex_lock(&chip->controller->lock);
345
346 return 0;
347 }
348
349 /**
350 * nand_check_wp - [GENERIC] check if the chip is write protected
351 * @chip: NAND chip object
352 *
353 * Check, if the device is write protected. The function expects, that the
354 * device is already selected.
355 */
nand_check_wp(struct nand_chip * chip)356 static int nand_check_wp(struct nand_chip *chip)
357 {
358 u8 status;
359 int ret;
360
361 /* Broken xD cards report WP despite being writable */
362 if (chip->options & NAND_BROKEN_XD)
363 return 0;
364
365 /* Check the WP bit */
366 ret = nand_status_op(chip, &status);
367 if (ret)
368 return ret;
369
370 return status & NAND_STATUS_WP ? 0 : 1;
371 }
372
373 /**
374 * nand_fill_oob - [INTERN] Transfer client buffer to oob
375 * @chip: NAND chip object
376 * @oob: oob data buffer
377 * @len: oob data write length
378 * @ops: oob ops structure
379 */
nand_fill_oob(struct nand_chip * chip,uint8_t * oob,size_t len,struct mtd_oob_ops * ops)380 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob, size_t len,
381 struct mtd_oob_ops *ops)
382 {
383 struct mtd_info *mtd = nand_to_mtd(chip);
384 int ret;
385
386 /*
387 * Initialise to all 0xFF, to avoid the possibility of left over OOB
388 * data from a previous OOB read.
389 */
390 memset(chip->oob_poi, 0xff, mtd->oobsize);
391
392 switch (ops->mode) {
393
394 case MTD_OPS_PLACE_OOB:
395 case MTD_OPS_RAW:
396 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
397 return oob + len;
398
399 case MTD_OPS_AUTO_OOB:
400 ret = mtd_ooblayout_set_databytes(mtd, oob, chip->oob_poi,
401 ops->ooboffs, len);
402 BUG_ON(ret);
403 return oob + len;
404
405 default:
406 BUG();
407 }
408 return NULL;
409 }
410
411 /**
412 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
413 * @chip: NAND chip object
414 * @to: offset to write to
415 * @ops: oob operation description structure
416 *
417 * NAND write out-of-band.
418 */
nand_do_write_oob(struct nand_chip * chip,loff_t to,struct mtd_oob_ops * ops)419 static int nand_do_write_oob(struct nand_chip *chip, loff_t to,
420 struct mtd_oob_ops *ops)
421 {
422 struct mtd_info *mtd = nand_to_mtd(chip);
423 int chipnr, page, status, len, ret;
424
425 pr_debug("%s: to = 0x%08x, len = %i\n",
426 __func__, (unsigned int)to, (int)ops->ooblen);
427
428 len = mtd_oobavail(mtd, ops);
429
430 /* Do not allow write past end of page */
431 if ((ops->ooboffs + ops->ooblen) > len) {
432 pr_debug("%s: attempt to write past end of page\n",
433 __func__);
434 return -EINVAL;
435 }
436
437 /* Check if the region is secured */
438 if (nand_region_is_secured(chip, to, ops->ooblen))
439 return -EIO;
440
441 chipnr = (int)(to >> chip->chip_shift);
442
443 /*
444 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
445 * of my DiskOnChip 2000 test units) will clear the whole data page too
446 * if we don't do this. I have no clue why, but I seem to have 'fixed'
447 * it in the doc2000 driver in August 1999. dwmw2.
448 */
449 ret = nand_reset(chip, chipnr);
450 if (ret)
451 return ret;
452
453 nand_select_target(chip, chipnr);
454
455 /* Shift to get page */
456 page = (int)(to >> chip->page_shift);
457
458 /* Check, if it is write protected */
459 if (nand_check_wp(chip)) {
460 nand_deselect_target(chip);
461 return -EROFS;
462 }
463
464 /* Invalidate the page cache, if we write to the cached page */
465 if (page == chip->pagecache.page)
466 chip->pagecache.page = -1;
467
468 nand_fill_oob(chip, ops->oobbuf, ops->ooblen, ops);
469
470 if (ops->mode == MTD_OPS_RAW)
471 status = chip->ecc.write_oob_raw(chip, page & chip->pagemask);
472 else
473 status = chip->ecc.write_oob(chip, page & chip->pagemask);
474
475 nand_deselect_target(chip);
476
477 if (status)
478 return status;
479
480 ops->oobretlen = ops->ooblen;
481
482 return 0;
483 }
484
485 /**
486 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
487 * @chip: NAND chip object
488 * @ofs: offset from device start
489 *
490 * This is the default implementation, which can be overridden by a hardware
491 * specific driver. It provides the details for writing a bad block marker to a
492 * block.
493 */
nand_default_block_markbad(struct nand_chip * chip,loff_t ofs)494 static int nand_default_block_markbad(struct nand_chip *chip, loff_t ofs)
495 {
496 struct mtd_info *mtd = nand_to_mtd(chip);
497 struct mtd_oob_ops ops;
498 uint8_t buf[2] = { 0, 0 };
499 int ret = 0, res, page_offset;
500
501 memset(&ops, 0, sizeof(ops));
502 ops.oobbuf = buf;
503 ops.ooboffs = chip->badblockpos;
504 if (chip->options & NAND_BUSWIDTH_16) {
505 ops.ooboffs &= ~0x01;
506 ops.len = ops.ooblen = 2;
507 } else {
508 ops.len = ops.ooblen = 1;
509 }
510 ops.mode = MTD_OPS_PLACE_OOB;
511
512 page_offset = nand_bbm_get_next_page(chip, 0);
513
514 while (page_offset >= 0) {
515 res = nand_do_write_oob(chip,
516 ofs + (page_offset * mtd->writesize),
517 &ops);
518
519 if (!ret)
520 ret = res;
521
522 page_offset = nand_bbm_get_next_page(chip, page_offset + 1);
523 }
524
525 return ret;
526 }
527
528 /**
529 * nand_markbad_bbm - mark a block by updating the BBM
530 * @chip: NAND chip object
531 * @ofs: offset of the block to mark bad
532 */
nand_markbad_bbm(struct nand_chip * chip,loff_t ofs)533 int nand_markbad_bbm(struct nand_chip *chip, loff_t ofs)
534 {
535 if (chip->legacy.block_markbad)
536 return chip->legacy.block_markbad(chip, ofs);
537
538 return nand_default_block_markbad(chip, ofs);
539 }
540
541 /**
542 * nand_block_markbad_lowlevel - mark a block bad
543 * @chip: NAND chip object
544 * @ofs: offset from device start
545 *
546 * This function performs the generic NAND bad block marking steps (i.e., bad
547 * block table(s) and/or marker(s)). We only allow the hardware driver to
548 * specify how to write bad block markers to OOB (chip->legacy.block_markbad).
549 *
550 * We try operations in the following order:
551 *
552 * (1) erase the affected block, to allow OOB marker to be written cleanly
553 * (2) write bad block marker to OOB area of affected block (unless flag
554 * NAND_BBT_NO_OOB_BBM is present)
555 * (3) update the BBT
556 *
557 * Note that we retain the first error encountered in (2) or (3), finish the
558 * procedures, and dump the error in the end.
559 */
nand_block_markbad_lowlevel(struct nand_chip * chip,loff_t ofs)560 static int nand_block_markbad_lowlevel(struct nand_chip *chip, loff_t ofs)
561 {
562 struct mtd_info *mtd = nand_to_mtd(chip);
563 int res, ret = 0;
564
565 if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
566 struct erase_info einfo;
567
568 /* Attempt erase before marking OOB */
569 memset(&einfo, 0, sizeof(einfo));
570 einfo.addr = ofs;
571 einfo.len = 1ULL << chip->phys_erase_shift;
572 nand_erase_nand(chip, &einfo, 0);
573
574 /* Write bad block marker to OOB */
575 ret = nand_get_device(chip);
576 if (ret)
577 return ret;
578
579 ret = nand_markbad_bbm(chip, ofs);
580 nand_release_device(chip);
581 }
582
583 /* Mark block bad in BBT */
584 if (chip->bbt) {
585 res = nand_markbad_bbt(chip, ofs);
586 if (!ret)
587 ret = res;
588 }
589
590 if (!ret)
591 mtd->ecc_stats.badblocks++;
592
593 return ret;
594 }
595
596 /**
597 * nand_block_isreserved - [GENERIC] Check if a block is marked reserved.
598 * @mtd: MTD device structure
599 * @ofs: offset from device start
600 *
601 * Check if the block is marked as reserved.
602 */
nand_block_isreserved(struct mtd_info * mtd,loff_t ofs)603 static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
604 {
605 struct nand_chip *chip = mtd_to_nand(mtd);
606
607 if (!chip->bbt)
608 return 0;
609 /* Return info from the table */
610 return nand_isreserved_bbt(chip, ofs);
611 }
612
613 /**
614 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
615 * @chip: NAND chip object
616 * @ofs: offset from device start
617 * @allowbbt: 1, if its allowed to access the bbt area
618 *
619 * Check, if the block is bad. Either by reading the bad block table or
620 * calling of the scan function.
621 */
nand_block_checkbad(struct nand_chip * chip,loff_t ofs,int allowbbt)622 static int nand_block_checkbad(struct nand_chip *chip, loff_t ofs, int allowbbt)
623 {
624 /* Return info from the table */
625 if (chip->bbt)
626 return nand_isbad_bbt(chip, ofs, allowbbt);
627
628 return nand_isbad_bbm(chip, ofs);
629 }
630
631 /**
632 * nand_soft_waitrdy - Poll STATUS reg until RDY bit is set to 1
633 * @chip: NAND chip structure
634 * @timeout_ms: Timeout in ms
635 *
636 * Poll the STATUS register using ->exec_op() until the RDY bit becomes 1.
637 * If that does not happen whitin the specified timeout, -ETIMEDOUT is
638 * returned.
639 *
640 * This helper is intended to be used when the controller does not have access
641 * to the NAND R/B pin.
642 *
643 * Be aware that calling this helper from an ->exec_op() implementation means
644 * ->exec_op() must be re-entrant.
645 *
646 * Return 0 if the NAND chip is ready, a negative error otherwise.
647 */
nand_soft_waitrdy(struct nand_chip * chip,unsigned long timeout_ms)648 int nand_soft_waitrdy(struct nand_chip *chip, unsigned long timeout_ms)
649 {
650 const struct nand_sdr_timings *timings;
651 u8 status = 0;
652 int ret;
653
654 if (!nand_has_exec_op(chip))
655 return -ENOTSUPP;
656
657 /* Wait tWB before polling the STATUS reg. */
658 timings = nand_get_sdr_timings(nand_get_interface_config(chip));
659 ndelay(PSEC_TO_NSEC(timings->tWB_max));
660
661 ret = nand_status_op(chip, NULL);
662 if (ret)
663 return ret;
664
665 /*
666 * +1 below is necessary because if we are now in the last fraction
667 * of jiffy and msecs_to_jiffies is 1 then we will wait only that
668 * small jiffy fraction - possibly leading to false timeout
669 */
670 timeout_ms = jiffies + msecs_to_jiffies(timeout_ms) + 1;
671 do {
672 ret = nand_read_data_op(chip, &status, sizeof(status), true,
673 false);
674 if (ret)
675 break;
676
677 if (status & NAND_STATUS_READY)
678 break;
679
680 /*
681 * Typical lowest execution time for a tR on most NANDs is 10us,
682 * use this as polling delay before doing something smarter (ie.
683 * deriving a delay from the timeout value, timeout_ms/ratio).
684 */
685 udelay(10);
686 } while (time_before(jiffies, timeout_ms));
687
688 /*
689 * We have to exit READ_STATUS mode in order to read real data on the
690 * bus in case the WAITRDY instruction is preceding a DATA_IN
691 * instruction.
692 */
693 nand_exit_status_op(chip);
694
695 if (ret)
696 return ret;
697
698 return status & NAND_STATUS_READY ? 0 : -ETIMEDOUT;
699 };
700 EXPORT_SYMBOL_GPL(nand_soft_waitrdy);
701
702 /**
703 * nand_gpio_waitrdy - Poll R/B GPIO pin until ready
704 * @chip: NAND chip structure
705 * @gpiod: GPIO descriptor of R/B pin
706 * @timeout_ms: Timeout in ms
707 *
708 * Poll the R/B GPIO pin until it becomes ready. If that does not happen
709 * whitin the specified timeout, -ETIMEDOUT is returned.
710 *
711 * This helper is intended to be used when the controller has access to the
712 * NAND R/B pin over GPIO.
713 *
714 * Return 0 if the R/B pin indicates chip is ready, a negative error otherwise.
715 */
nand_gpio_waitrdy(struct nand_chip * chip,struct gpio_desc * gpiod,unsigned long timeout_ms)716 int nand_gpio_waitrdy(struct nand_chip *chip, struct gpio_desc *gpiod,
717 unsigned long timeout_ms)
718 {
719
720 /*
721 * Wait until R/B pin indicates chip is ready or timeout occurs.
722 * +1 below is necessary because if we are now in the last fraction
723 * of jiffy and msecs_to_jiffies is 1 then we will wait only that
724 * small jiffy fraction - possibly leading to false timeout.
725 */
726 timeout_ms = jiffies + msecs_to_jiffies(timeout_ms) + 1;
727 do {
728 if (gpiod_get_value_cansleep(gpiod))
729 return 0;
730
731 cond_resched();
732 } while (time_before(jiffies, timeout_ms));
733
734 return gpiod_get_value_cansleep(gpiod) ? 0 : -ETIMEDOUT;
735 };
736 EXPORT_SYMBOL_GPL(nand_gpio_waitrdy);
737
738 /**
739 * panic_nand_wait - [GENERIC] wait until the command is done
740 * @chip: NAND chip structure
741 * @timeo: timeout
742 *
743 * Wait for command done. This is a helper function for nand_wait used when
744 * we are in interrupt context. May happen when in panic and trying to write
745 * an oops through mtdoops.
746 */
panic_nand_wait(struct nand_chip * chip,unsigned long timeo)747 void panic_nand_wait(struct nand_chip *chip, unsigned long timeo)
748 {
749 int i;
750 for (i = 0; i < timeo; i++) {
751 if (chip->legacy.dev_ready) {
752 if (chip->legacy.dev_ready(chip))
753 break;
754 } else {
755 int ret;
756 u8 status;
757
758 ret = nand_read_data_op(chip, &status, sizeof(status),
759 true, false);
760 if (ret)
761 return;
762
763 if (status & NAND_STATUS_READY)
764 break;
765 }
766 mdelay(1);
767 }
768 }
769
nand_supports_get_features(struct nand_chip * chip,int addr)770 static bool nand_supports_get_features(struct nand_chip *chip, int addr)
771 {
772 return (chip->parameters.supports_set_get_features &&
773 test_bit(addr, chip->parameters.get_feature_list));
774 }
775
nand_supports_set_features(struct nand_chip * chip,int addr)776 static bool nand_supports_set_features(struct nand_chip *chip, int addr)
777 {
778 return (chip->parameters.supports_set_get_features &&
779 test_bit(addr, chip->parameters.set_feature_list));
780 }
781
782 /**
783 * nand_reset_interface - Reset data interface and timings
784 * @chip: The NAND chip
785 * @chipnr: Internal die id
786 *
787 * Reset the Data interface and timings to ONFI mode 0.
788 *
789 * Returns 0 for success or negative error code otherwise.
790 */
nand_reset_interface(struct nand_chip * chip,int chipnr)791 static int nand_reset_interface(struct nand_chip *chip, int chipnr)
792 {
793 const struct nand_controller_ops *ops = chip->controller->ops;
794 int ret;
795
796 if (!nand_controller_can_setup_interface(chip))
797 return 0;
798
799 /*
800 * The ONFI specification says:
801 * "
802 * To transition from NV-DDR or NV-DDR2 to the SDR data
803 * interface, the host shall use the Reset (FFh) command
804 * using SDR timing mode 0. A device in any timing mode is
805 * required to recognize Reset (FFh) command issued in SDR
806 * timing mode 0.
807 * "
808 *
809 * Configure the data interface in SDR mode and set the
810 * timings to timing mode 0.
811 */
812
813 chip->current_interface_config = nand_get_reset_interface_config();
814 ret = ops->setup_interface(chip, chipnr,
815 chip->current_interface_config);
816 if (ret)
817 pr_err("Failed to configure data interface to SDR timing mode 0\n");
818
819 return ret;
820 }
821
822 /**
823 * nand_setup_interface - Setup the best data interface and timings
824 * @chip: The NAND chip
825 * @chipnr: Internal die id
826 *
827 * Configure what has been reported to be the best data interface and NAND
828 * timings supported by the chip and the driver.
829 *
830 * Returns 0 for success or negative error code otherwise.
831 */
nand_setup_interface(struct nand_chip * chip,int chipnr)832 static int nand_setup_interface(struct nand_chip *chip, int chipnr)
833 {
834 const struct nand_controller_ops *ops = chip->controller->ops;
835 u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = { };
836 int ret;
837
838 if (!nand_controller_can_setup_interface(chip))
839 return 0;
840
841 /*
842 * A nand_reset_interface() put both the NAND chip and the NAND
843 * controller in timings mode 0. If the default mode for this chip is
844 * also 0, no need to proceed to the change again. Plus, at probe time,
845 * nand_setup_interface() uses ->set/get_features() which would
846 * fail anyway as the parameter page is not available yet.
847 */
848 if (!chip->best_interface_config)
849 return 0;
850
851 tmode_param[0] = chip->best_interface_config->timings.mode;
852
853 /* Change the mode on the chip side (if supported by the NAND chip) */
854 if (nand_supports_set_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE)) {
855 nand_select_target(chip, chipnr);
856 ret = nand_set_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE,
857 tmode_param);
858 nand_deselect_target(chip);
859 if (ret)
860 return ret;
861 }
862
863 /* Change the mode on the controller side */
864 ret = ops->setup_interface(chip, chipnr, chip->best_interface_config);
865 if (ret)
866 return ret;
867
868 /* Check the mode has been accepted by the chip, if supported */
869 if (!nand_supports_get_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE))
870 goto update_interface_config;
871
872 memset(tmode_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
873 nand_select_target(chip, chipnr);
874 ret = nand_get_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE,
875 tmode_param);
876 nand_deselect_target(chip);
877 if (ret)
878 goto err_reset_chip;
879
880 if (tmode_param[0] != chip->best_interface_config->timings.mode) {
881 pr_warn("timing mode %d not acknowledged by the NAND chip\n",
882 chip->best_interface_config->timings.mode);
883 goto err_reset_chip;
884 }
885
886 update_interface_config:
887 chip->current_interface_config = chip->best_interface_config;
888
889 return 0;
890
891 err_reset_chip:
892 /*
893 * Fallback to mode 0 if the chip explicitly did not ack the chosen
894 * timing mode.
895 */
896 nand_reset_interface(chip, chipnr);
897 nand_select_target(chip, chipnr);
898 nand_reset_op(chip);
899 nand_deselect_target(chip);
900
901 return ret;
902 }
903
904 /**
905 * nand_choose_best_sdr_timings - Pick up the best SDR timings that both the
906 * NAND controller and the NAND chip support
907 * @chip: the NAND chip
908 * @iface: the interface configuration (can eventually be updated)
909 * @spec_timings: specific timings, when not fitting the ONFI specification
910 *
911 * If specific timings are provided, use them. Otherwise, retrieve supported
912 * timing modes from ONFI information.
913 */
nand_choose_best_sdr_timings(struct nand_chip * chip,struct nand_interface_config * iface,struct nand_sdr_timings * spec_timings)914 int nand_choose_best_sdr_timings(struct nand_chip *chip,
915 struct nand_interface_config *iface,
916 struct nand_sdr_timings *spec_timings)
917 {
918 const struct nand_controller_ops *ops = chip->controller->ops;
919 int best_mode = 0, mode, ret;
920
921 iface->type = NAND_SDR_IFACE;
922
923 if (spec_timings) {
924 iface->timings.sdr = *spec_timings;
925 iface->timings.mode = onfi_find_closest_sdr_mode(spec_timings);
926
927 /* Verify the controller supports the requested interface */
928 ret = ops->setup_interface(chip, NAND_DATA_IFACE_CHECK_ONLY,
929 iface);
930 if (!ret) {
931 chip->best_interface_config = iface;
932 return ret;
933 }
934
935 /* Fallback to slower modes */
936 best_mode = iface->timings.mode;
937 } else if (chip->parameters.onfi) {
938 best_mode = fls(chip->parameters.onfi->async_timing_mode) - 1;
939 }
940
941 for (mode = best_mode; mode >= 0; mode--) {
942 onfi_fill_interface_config(chip, iface, NAND_SDR_IFACE, mode);
943
944 ret = ops->setup_interface(chip, NAND_DATA_IFACE_CHECK_ONLY,
945 iface);
946 if (!ret)
947 break;
948 }
949
950 chip->best_interface_config = iface;
951
952 return 0;
953 }
954
955 /**
956 * nand_choose_interface_config - find the best data interface and timings
957 * @chip: The NAND chip
958 *
959 * Find the best data interface and NAND timings supported by the chip
960 * and the driver. Eventually let the NAND manufacturer driver propose his own
961 * set of timings.
962 *
963 * After this function nand_chip->interface_config is initialized with the best
964 * timing mode available.
965 *
966 * Returns 0 for success or negative error code otherwise.
967 */
nand_choose_interface_config(struct nand_chip * chip)968 static int nand_choose_interface_config(struct nand_chip *chip)
969 {
970 struct nand_interface_config *iface;
971 int ret;
972
973 if (!nand_controller_can_setup_interface(chip))
974 return 0;
975
976 iface = kzalloc(sizeof(*iface), GFP_KERNEL);
977 if (!iface)
978 return -ENOMEM;
979
980 if (chip->ops.choose_interface_config)
981 ret = chip->ops.choose_interface_config(chip, iface);
982 else
983 ret = nand_choose_best_sdr_timings(chip, iface, NULL);
984
985 if (ret)
986 kfree(iface);
987
988 return ret;
989 }
990
991 /**
992 * nand_fill_column_cycles - fill the column cycles of an address
993 * @chip: The NAND chip
994 * @addrs: Array of address cycles to fill
995 * @offset_in_page: The offset in the page
996 *
997 * Fills the first or the first two bytes of the @addrs field depending
998 * on the NAND bus width and the page size.
999 *
1000 * Returns the number of cycles needed to encode the column, or a negative
1001 * error code in case one of the arguments is invalid.
1002 */
nand_fill_column_cycles(struct nand_chip * chip,u8 * addrs,unsigned int offset_in_page)1003 static int nand_fill_column_cycles(struct nand_chip *chip, u8 *addrs,
1004 unsigned int offset_in_page)
1005 {
1006 struct mtd_info *mtd = nand_to_mtd(chip);
1007
1008 /* Make sure the offset is less than the actual page size. */
1009 if (offset_in_page > mtd->writesize + mtd->oobsize)
1010 return -EINVAL;
1011
1012 /*
1013 * On small page NANDs, there's a dedicated command to access the OOB
1014 * area, and the column address is relative to the start of the OOB
1015 * area, not the start of the page. Asjust the address accordingly.
1016 */
1017 if (mtd->writesize <= 512 && offset_in_page >= mtd->writesize)
1018 offset_in_page -= mtd->writesize;
1019
1020 /*
1021 * The offset in page is expressed in bytes, if the NAND bus is 16-bit
1022 * wide, then it must be divided by 2.
1023 */
1024 if (chip->options & NAND_BUSWIDTH_16) {
1025 if (WARN_ON(offset_in_page % 2))
1026 return -EINVAL;
1027
1028 offset_in_page /= 2;
1029 }
1030
1031 addrs[0] = offset_in_page;
1032
1033 /*
1034 * Small page NANDs use 1 cycle for the columns, while large page NANDs
1035 * need 2
1036 */
1037 if (mtd->writesize <= 512)
1038 return 1;
1039
1040 addrs[1] = offset_in_page >> 8;
1041
1042 return 2;
1043 }
1044
nand_sp_exec_read_page_op(struct nand_chip * chip,unsigned int page,unsigned int offset_in_page,void * buf,unsigned int len)1045 static int nand_sp_exec_read_page_op(struct nand_chip *chip, unsigned int page,
1046 unsigned int offset_in_page, void *buf,
1047 unsigned int len)
1048 {
1049 const struct nand_sdr_timings *sdr =
1050 nand_get_sdr_timings(nand_get_interface_config(chip));
1051 struct mtd_info *mtd = nand_to_mtd(chip);
1052 u8 addrs[4];
1053 struct nand_op_instr instrs[] = {
1054 NAND_OP_CMD(NAND_CMD_READ0, 0),
1055 NAND_OP_ADDR(3, addrs, PSEC_TO_NSEC(sdr->tWB_max)),
1056 NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tR_max),
1057 PSEC_TO_NSEC(sdr->tRR_min)),
1058 NAND_OP_DATA_IN(len, buf, 0),
1059 };
1060 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1061 int ret;
1062
1063 /* Drop the DATA_IN instruction if len is set to 0. */
1064 if (!len)
1065 op.ninstrs--;
1066
1067 if (offset_in_page >= mtd->writesize)
1068 instrs[0].ctx.cmd.opcode = NAND_CMD_READOOB;
1069 else if (offset_in_page >= 256 &&
1070 !(chip->options & NAND_BUSWIDTH_16))
1071 instrs[0].ctx.cmd.opcode = NAND_CMD_READ1;
1072
1073 ret = nand_fill_column_cycles(chip, addrs, offset_in_page);
1074 if (ret < 0)
1075 return ret;
1076
1077 addrs[1] = page;
1078 addrs[2] = page >> 8;
1079
1080 if (chip->options & NAND_ROW_ADDR_3) {
1081 addrs[3] = page >> 16;
1082 instrs[1].ctx.addr.naddrs++;
1083 }
1084
1085 return nand_exec_op(chip, &op);
1086 }
1087
nand_lp_exec_read_page_op(struct nand_chip * chip,unsigned int page,unsigned int offset_in_page,void * buf,unsigned int len)1088 static int nand_lp_exec_read_page_op(struct nand_chip *chip, unsigned int page,
1089 unsigned int offset_in_page, void *buf,
1090 unsigned int len)
1091 {
1092 const struct nand_sdr_timings *sdr =
1093 nand_get_sdr_timings(nand_get_interface_config(chip));
1094 u8 addrs[5];
1095 struct nand_op_instr instrs[] = {
1096 NAND_OP_CMD(NAND_CMD_READ0, 0),
1097 NAND_OP_ADDR(4, addrs, 0),
1098 NAND_OP_CMD(NAND_CMD_READSTART, PSEC_TO_NSEC(sdr->tWB_max)),
1099 NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tR_max),
1100 PSEC_TO_NSEC(sdr->tRR_min)),
1101 NAND_OP_DATA_IN(len, buf, 0),
1102 };
1103 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1104 int ret;
1105
1106 /* Drop the DATA_IN instruction if len is set to 0. */
1107 if (!len)
1108 op.ninstrs--;
1109
1110 ret = nand_fill_column_cycles(chip, addrs, offset_in_page);
1111 if (ret < 0)
1112 return ret;
1113
1114 addrs[2] = page;
1115 addrs[3] = page >> 8;
1116
1117 if (chip->options & NAND_ROW_ADDR_3) {
1118 addrs[4] = page >> 16;
1119 instrs[1].ctx.addr.naddrs++;
1120 }
1121
1122 return nand_exec_op(chip, &op);
1123 }
1124
1125 /**
1126 * nand_read_page_op - Do a READ PAGE operation
1127 * @chip: The NAND chip
1128 * @page: page to read
1129 * @offset_in_page: offset within the page
1130 * @buf: buffer used to store the data
1131 * @len: length of the buffer
1132 *
1133 * This function issues a READ PAGE operation.
1134 * This function does not select/unselect the CS line.
1135 *
1136 * Returns 0 on success, a negative error code otherwise.
1137 */
nand_read_page_op(struct nand_chip * chip,unsigned int page,unsigned int offset_in_page,void * buf,unsigned int len)1138 int nand_read_page_op(struct nand_chip *chip, unsigned int page,
1139 unsigned int offset_in_page, void *buf, unsigned int len)
1140 {
1141 struct mtd_info *mtd = nand_to_mtd(chip);
1142
1143 if (len && !buf)
1144 return -EINVAL;
1145
1146 if (offset_in_page + len > mtd->writesize + mtd->oobsize)
1147 return -EINVAL;
1148
1149 if (nand_has_exec_op(chip)) {
1150 if (mtd->writesize > 512)
1151 return nand_lp_exec_read_page_op(chip, page,
1152 offset_in_page, buf,
1153 len);
1154
1155 return nand_sp_exec_read_page_op(chip, page, offset_in_page,
1156 buf, len);
1157 }
1158
1159 chip->legacy.cmdfunc(chip, NAND_CMD_READ0, offset_in_page, page);
1160 if (len)
1161 chip->legacy.read_buf(chip, buf, len);
1162
1163 return 0;
1164 }
1165 EXPORT_SYMBOL_GPL(nand_read_page_op);
1166
1167 /**
1168 * nand_read_param_page_op - Do a READ PARAMETER PAGE operation
1169 * @chip: The NAND chip
1170 * @page: parameter page to read
1171 * @buf: buffer used to store the data
1172 * @len: length of the buffer
1173 *
1174 * This function issues a READ PARAMETER PAGE operation.
1175 * This function does not select/unselect the CS line.
1176 *
1177 * Returns 0 on success, a negative error code otherwise.
1178 */
nand_read_param_page_op(struct nand_chip * chip,u8 page,void * buf,unsigned int len)1179 int nand_read_param_page_op(struct nand_chip *chip, u8 page, void *buf,
1180 unsigned int len)
1181 {
1182 unsigned int i;
1183 u8 *p = buf;
1184
1185 if (len && !buf)
1186 return -EINVAL;
1187
1188 if (nand_has_exec_op(chip)) {
1189 const struct nand_sdr_timings *sdr =
1190 nand_get_sdr_timings(nand_get_interface_config(chip));
1191 struct nand_op_instr instrs[] = {
1192 NAND_OP_CMD(NAND_CMD_PARAM, 0),
1193 NAND_OP_ADDR(1, &page, PSEC_TO_NSEC(sdr->tWB_max)),
1194 NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tR_max),
1195 PSEC_TO_NSEC(sdr->tRR_min)),
1196 NAND_OP_8BIT_DATA_IN(len, buf, 0),
1197 };
1198 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1199
1200 /* Drop the DATA_IN instruction if len is set to 0. */
1201 if (!len)
1202 op.ninstrs--;
1203
1204 return nand_exec_op(chip, &op);
1205 }
1206
1207 chip->legacy.cmdfunc(chip, NAND_CMD_PARAM, page, -1);
1208 for (i = 0; i < len; i++)
1209 p[i] = chip->legacy.read_byte(chip);
1210
1211 return 0;
1212 }
1213
1214 /**
1215 * nand_change_read_column_op - Do a CHANGE READ COLUMN operation
1216 * @chip: The NAND chip
1217 * @offset_in_page: offset within the page
1218 * @buf: buffer used to store the data
1219 * @len: length of the buffer
1220 * @force_8bit: force 8-bit bus access
1221 *
1222 * This function issues a CHANGE READ COLUMN operation.
1223 * This function does not select/unselect the CS line.
1224 *
1225 * Returns 0 on success, a negative error code otherwise.
1226 */
nand_change_read_column_op(struct nand_chip * chip,unsigned int offset_in_page,void * buf,unsigned int len,bool force_8bit)1227 int nand_change_read_column_op(struct nand_chip *chip,
1228 unsigned int offset_in_page, void *buf,
1229 unsigned int len, bool force_8bit)
1230 {
1231 struct mtd_info *mtd = nand_to_mtd(chip);
1232
1233 if (len && !buf)
1234 return -EINVAL;
1235
1236 if (offset_in_page + len > mtd->writesize + mtd->oobsize)
1237 return -EINVAL;
1238
1239 /* Small page NANDs do not support column change. */
1240 if (mtd->writesize <= 512)
1241 return -ENOTSUPP;
1242
1243 if (nand_has_exec_op(chip)) {
1244 const struct nand_sdr_timings *sdr =
1245 nand_get_sdr_timings(nand_get_interface_config(chip));
1246 u8 addrs[2] = {};
1247 struct nand_op_instr instrs[] = {
1248 NAND_OP_CMD(NAND_CMD_RNDOUT, 0),
1249 NAND_OP_ADDR(2, addrs, 0),
1250 NAND_OP_CMD(NAND_CMD_RNDOUTSTART,
1251 PSEC_TO_NSEC(sdr->tCCS_min)),
1252 NAND_OP_DATA_IN(len, buf, 0),
1253 };
1254 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1255 int ret;
1256
1257 ret = nand_fill_column_cycles(chip, addrs, offset_in_page);
1258 if (ret < 0)
1259 return ret;
1260
1261 /* Drop the DATA_IN instruction if len is set to 0. */
1262 if (!len)
1263 op.ninstrs--;
1264
1265 instrs[3].ctx.data.force_8bit = force_8bit;
1266
1267 return nand_exec_op(chip, &op);
1268 }
1269
1270 chip->legacy.cmdfunc(chip, NAND_CMD_RNDOUT, offset_in_page, -1);
1271 if (len)
1272 chip->legacy.read_buf(chip, buf, len);
1273
1274 return 0;
1275 }
1276 EXPORT_SYMBOL_GPL(nand_change_read_column_op);
1277
1278 /**
1279 * nand_read_oob_op - Do a READ OOB operation
1280 * @chip: The NAND chip
1281 * @page: page to read
1282 * @offset_in_oob: offset within the OOB area
1283 * @buf: buffer used to store the data
1284 * @len: length of the buffer
1285 *
1286 * This function issues a READ OOB operation.
1287 * This function does not select/unselect the CS line.
1288 *
1289 * Returns 0 on success, a negative error code otherwise.
1290 */
nand_read_oob_op(struct nand_chip * chip,unsigned int page,unsigned int offset_in_oob,void * buf,unsigned int len)1291 int nand_read_oob_op(struct nand_chip *chip, unsigned int page,
1292 unsigned int offset_in_oob, void *buf, unsigned int len)
1293 {
1294 struct mtd_info *mtd = nand_to_mtd(chip);
1295
1296 if (len && !buf)
1297 return -EINVAL;
1298
1299 if (offset_in_oob + len > mtd->oobsize)
1300 return -EINVAL;
1301
1302 if (nand_has_exec_op(chip))
1303 return nand_read_page_op(chip, page,
1304 mtd->writesize + offset_in_oob,
1305 buf, len);
1306
1307 chip->legacy.cmdfunc(chip, NAND_CMD_READOOB, offset_in_oob, page);
1308 if (len)
1309 chip->legacy.read_buf(chip, buf, len);
1310
1311 return 0;
1312 }
1313 EXPORT_SYMBOL_GPL(nand_read_oob_op);
1314
nand_exec_prog_page_op(struct nand_chip * chip,unsigned int page,unsigned int offset_in_page,const void * buf,unsigned int len,bool prog)1315 static int nand_exec_prog_page_op(struct nand_chip *chip, unsigned int page,
1316 unsigned int offset_in_page, const void *buf,
1317 unsigned int len, bool prog)
1318 {
1319 const struct nand_sdr_timings *sdr =
1320 nand_get_sdr_timings(nand_get_interface_config(chip));
1321 struct mtd_info *mtd = nand_to_mtd(chip);
1322 u8 addrs[5] = {};
1323 struct nand_op_instr instrs[] = {
1324 /*
1325 * The first instruction will be dropped if we're dealing
1326 * with a large page NAND and adjusted if we're dealing
1327 * with a small page NAND and the page offset is > 255.
1328 */
1329 NAND_OP_CMD(NAND_CMD_READ0, 0),
1330 NAND_OP_CMD(NAND_CMD_SEQIN, 0),
1331 NAND_OP_ADDR(0, addrs, PSEC_TO_NSEC(sdr->tADL_min)),
1332 NAND_OP_DATA_OUT(len, buf, 0),
1333 NAND_OP_CMD(NAND_CMD_PAGEPROG, PSEC_TO_NSEC(sdr->tWB_max)),
1334 NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tPROG_max), 0),
1335 };
1336 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1337 int naddrs = nand_fill_column_cycles(chip, addrs, offset_in_page);
1338
1339 if (naddrs < 0)
1340 return naddrs;
1341
1342 addrs[naddrs++] = page;
1343 addrs[naddrs++] = page >> 8;
1344 if (chip->options & NAND_ROW_ADDR_3)
1345 addrs[naddrs++] = page >> 16;
1346
1347 instrs[2].ctx.addr.naddrs = naddrs;
1348
1349 /* Drop the last two instructions if we're not programming the page. */
1350 if (!prog) {
1351 op.ninstrs -= 2;
1352 /* Also drop the DATA_OUT instruction if empty. */
1353 if (!len)
1354 op.ninstrs--;
1355 }
1356
1357 if (mtd->writesize <= 512) {
1358 /*
1359 * Small pages need some more tweaking: we have to adjust the
1360 * first instruction depending on the page offset we're trying
1361 * to access.
1362 */
1363 if (offset_in_page >= mtd->writesize)
1364 instrs[0].ctx.cmd.opcode = NAND_CMD_READOOB;
1365 else if (offset_in_page >= 256 &&
1366 !(chip->options & NAND_BUSWIDTH_16))
1367 instrs[0].ctx.cmd.opcode = NAND_CMD_READ1;
1368 } else {
1369 /*
1370 * Drop the first command if we're dealing with a large page
1371 * NAND.
1372 */
1373 op.instrs++;
1374 op.ninstrs--;
1375 }
1376
1377 return nand_exec_op(chip, &op);
1378 }
1379
1380 /**
1381 * nand_prog_page_begin_op - starts a PROG PAGE operation
1382 * @chip: The NAND chip
1383 * @page: page to write
1384 * @offset_in_page: offset within the page
1385 * @buf: buffer containing the data to write to the page
1386 * @len: length of the buffer
1387 *
1388 * This function issues the first half of a PROG PAGE operation.
1389 * This function does not select/unselect the CS line.
1390 *
1391 * Returns 0 on success, a negative error code otherwise.
1392 */
nand_prog_page_begin_op(struct nand_chip * chip,unsigned int page,unsigned int offset_in_page,const void * buf,unsigned int len)1393 int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page,
1394 unsigned int offset_in_page, const void *buf,
1395 unsigned int len)
1396 {
1397 struct mtd_info *mtd = nand_to_mtd(chip);
1398
1399 if (len && !buf)
1400 return -EINVAL;
1401
1402 if (offset_in_page + len > mtd->writesize + mtd->oobsize)
1403 return -EINVAL;
1404
1405 if (nand_has_exec_op(chip))
1406 return nand_exec_prog_page_op(chip, page, offset_in_page, buf,
1407 len, false);
1408
1409 chip->legacy.cmdfunc(chip, NAND_CMD_SEQIN, offset_in_page, page);
1410
1411 if (buf)
1412 chip->legacy.write_buf(chip, buf, len);
1413
1414 return 0;
1415 }
1416 EXPORT_SYMBOL_GPL(nand_prog_page_begin_op);
1417
1418 /**
1419 * nand_prog_page_end_op - ends a PROG PAGE operation
1420 * @chip: The NAND chip
1421 *
1422 * This function issues the second half of a PROG PAGE operation.
1423 * This function does not select/unselect the CS line.
1424 *
1425 * Returns 0 on success, a negative error code otherwise.
1426 */
nand_prog_page_end_op(struct nand_chip * chip)1427 int nand_prog_page_end_op(struct nand_chip *chip)
1428 {
1429 int ret;
1430 u8 status;
1431
1432 if (nand_has_exec_op(chip)) {
1433 const struct nand_sdr_timings *sdr =
1434 nand_get_sdr_timings(nand_get_interface_config(chip));
1435 struct nand_op_instr instrs[] = {
1436 NAND_OP_CMD(NAND_CMD_PAGEPROG,
1437 PSEC_TO_NSEC(sdr->tWB_max)),
1438 NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tPROG_max), 0),
1439 };
1440 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1441
1442 ret = nand_exec_op(chip, &op);
1443 if (ret)
1444 return ret;
1445
1446 ret = nand_status_op(chip, &status);
1447 if (ret)
1448 return ret;
1449 } else {
1450 chip->legacy.cmdfunc(chip, NAND_CMD_PAGEPROG, -1, -1);
1451 ret = chip->legacy.waitfunc(chip);
1452 if (ret < 0)
1453 return ret;
1454
1455 status = ret;
1456 }
1457
1458 if (status & NAND_STATUS_FAIL)
1459 return -EIO;
1460
1461 return 0;
1462 }
1463 EXPORT_SYMBOL_GPL(nand_prog_page_end_op);
1464
1465 /**
1466 * nand_prog_page_op - Do a full PROG PAGE operation
1467 * @chip: The NAND chip
1468 * @page: page to write
1469 * @offset_in_page: offset within the page
1470 * @buf: buffer containing the data to write to the page
1471 * @len: length of the buffer
1472 *
1473 * This function issues a full PROG PAGE operation.
1474 * This function does not select/unselect the CS line.
1475 *
1476 * Returns 0 on success, a negative error code otherwise.
1477 */
nand_prog_page_op(struct nand_chip * chip,unsigned int page,unsigned int offset_in_page,const void * buf,unsigned int len)1478 int nand_prog_page_op(struct nand_chip *chip, unsigned int page,
1479 unsigned int offset_in_page, const void *buf,
1480 unsigned int len)
1481 {
1482 struct mtd_info *mtd = nand_to_mtd(chip);
1483 u8 status;
1484 int ret;
1485
1486 if (!len || !buf)
1487 return -EINVAL;
1488
1489 if (offset_in_page + len > mtd->writesize + mtd->oobsize)
1490 return -EINVAL;
1491
1492 if (nand_has_exec_op(chip)) {
1493 ret = nand_exec_prog_page_op(chip, page, offset_in_page, buf,
1494 len, true);
1495 if (ret)
1496 return ret;
1497
1498 ret = nand_status_op(chip, &status);
1499 if (ret)
1500 return ret;
1501 } else {
1502 chip->legacy.cmdfunc(chip, NAND_CMD_SEQIN, offset_in_page,
1503 page);
1504 chip->legacy.write_buf(chip, buf, len);
1505 chip->legacy.cmdfunc(chip, NAND_CMD_PAGEPROG, -1, -1);
1506 ret = chip->legacy.waitfunc(chip);
1507 if (ret < 0)
1508 return ret;
1509
1510 status = ret;
1511 }
1512
1513 if (status & NAND_STATUS_FAIL)
1514 return -EIO;
1515
1516 return 0;
1517 }
1518 EXPORT_SYMBOL_GPL(nand_prog_page_op);
1519
1520 /**
1521 * nand_change_write_column_op - Do a CHANGE WRITE COLUMN operation
1522 * @chip: The NAND chip
1523 * @offset_in_page: offset within the page
1524 * @buf: buffer containing the data to send to the NAND
1525 * @len: length of the buffer
1526 * @force_8bit: force 8-bit bus access
1527 *
1528 * This function issues a CHANGE WRITE COLUMN operation.
1529 * This function does not select/unselect the CS line.
1530 *
1531 * Returns 0 on success, a negative error code otherwise.
1532 */
nand_change_write_column_op(struct nand_chip * chip,unsigned int offset_in_page,const void * buf,unsigned int len,bool force_8bit)1533 int nand_change_write_column_op(struct nand_chip *chip,
1534 unsigned int offset_in_page,
1535 const void *buf, unsigned int len,
1536 bool force_8bit)
1537 {
1538 struct mtd_info *mtd = nand_to_mtd(chip);
1539
1540 if (len && !buf)
1541 return -EINVAL;
1542
1543 if (offset_in_page + len > mtd->writesize + mtd->oobsize)
1544 return -EINVAL;
1545
1546 /* Small page NANDs do not support column change. */
1547 if (mtd->writesize <= 512)
1548 return -ENOTSUPP;
1549
1550 if (nand_has_exec_op(chip)) {
1551 const struct nand_sdr_timings *sdr =
1552 nand_get_sdr_timings(nand_get_interface_config(chip));
1553 u8 addrs[2];
1554 struct nand_op_instr instrs[] = {
1555 NAND_OP_CMD(NAND_CMD_RNDIN, 0),
1556 NAND_OP_ADDR(2, addrs, PSEC_TO_NSEC(sdr->tCCS_min)),
1557 NAND_OP_DATA_OUT(len, buf, 0),
1558 };
1559 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1560 int ret;
1561
1562 ret = nand_fill_column_cycles(chip, addrs, offset_in_page);
1563 if (ret < 0)
1564 return ret;
1565
1566 instrs[2].ctx.data.force_8bit = force_8bit;
1567
1568 /* Drop the DATA_OUT instruction if len is set to 0. */
1569 if (!len)
1570 op.ninstrs--;
1571
1572 return nand_exec_op(chip, &op);
1573 }
1574
1575 chip->legacy.cmdfunc(chip, NAND_CMD_RNDIN, offset_in_page, -1);
1576 if (len)
1577 chip->legacy.write_buf(chip, buf, len);
1578
1579 return 0;
1580 }
1581 EXPORT_SYMBOL_GPL(nand_change_write_column_op);
1582
1583 /**
1584 * nand_readid_op - Do a READID operation
1585 * @chip: The NAND chip
1586 * @addr: address cycle to pass after the READID command
1587 * @buf: buffer used to store the ID
1588 * @len: length of the buffer
1589 *
1590 * This function sends a READID command and reads back the ID returned by the
1591 * NAND.
1592 * This function does not select/unselect the CS line.
1593 *
1594 * Returns 0 on success, a negative error code otherwise.
1595 */
nand_readid_op(struct nand_chip * chip,u8 addr,void * buf,unsigned int len)1596 int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf,
1597 unsigned int len)
1598 {
1599 unsigned int i;
1600 u8 *id = buf;
1601
1602 if (len && !buf)
1603 return -EINVAL;
1604
1605 if (nand_has_exec_op(chip)) {
1606 const struct nand_sdr_timings *sdr =
1607 nand_get_sdr_timings(nand_get_interface_config(chip));
1608 struct nand_op_instr instrs[] = {
1609 NAND_OP_CMD(NAND_CMD_READID, 0),
1610 NAND_OP_ADDR(1, &addr, PSEC_TO_NSEC(sdr->tADL_min)),
1611 NAND_OP_8BIT_DATA_IN(len, buf, 0),
1612 };
1613 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1614
1615 /* Drop the DATA_IN instruction if len is set to 0. */
1616 if (!len)
1617 op.ninstrs--;
1618
1619 return nand_exec_op(chip, &op);
1620 }
1621
1622 chip->legacy.cmdfunc(chip, NAND_CMD_READID, addr, -1);
1623
1624 for (i = 0; i < len; i++)
1625 id[i] = chip->legacy.read_byte(chip);
1626
1627 return 0;
1628 }
1629 EXPORT_SYMBOL_GPL(nand_readid_op);
1630
1631 /**
1632 * nand_status_op - Do a STATUS operation
1633 * @chip: The NAND chip
1634 * @status: out variable to store the NAND status
1635 *
1636 * This function sends a STATUS command and reads back the status returned by
1637 * the NAND.
1638 * This function does not select/unselect the CS line.
1639 *
1640 * Returns 0 on success, a negative error code otherwise.
1641 */
nand_status_op(struct nand_chip * chip,u8 * status)1642 int nand_status_op(struct nand_chip *chip, u8 *status)
1643 {
1644 if (nand_has_exec_op(chip)) {
1645 const struct nand_sdr_timings *sdr =
1646 nand_get_sdr_timings(nand_get_interface_config(chip));
1647 struct nand_op_instr instrs[] = {
1648 NAND_OP_CMD(NAND_CMD_STATUS,
1649 PSEC_TO_NSEC(sdr->tADL_min)),
1650 NAND_OP_8BIT_DATA_IN(1, status, 0),
1651 };
1652 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1653
1654 if (!status)
1655 op.ninstrs--;
1656
1657 return nand_exec_op(chip, &op);
1658 }
1659
1660 chip->legacy.cmdfunc(chip, NAND_CMD_STATUS, -1, -1);
1661 if (status)
1662 *status = chip->legacy.read_byte(chip);
1663
1664 return 0;
1665 }
1666 EXPORT_SYMBOL_GPL(nand_status_op);
1667
1668 /**
1669 * nand_exit_status_op - Exit a STATUS operation
1670 * @chip: The NAND chip
1671 *
1672 * This function sends a READ0 command to cancel the effect of the STATUS
1673 * command to avoid reading only the status until a new read command is sent.
1674 *
1675 * This function does not select/unselect the CS line.
1676 *
1677 * Returns 0 on success, a negative error code otherwise.
1678 */
nand_exit_status_op(struct nand_chip * chip)1679 int nand_exit_status_op(struct nand_chip *chip)
1680 {
1681 if (nand_has_exec_op(chip)) {
1682 struct nand_op_instr instrs[] = {
1683 NAND_OP_CMD(NAND_CMD_READ0, 0),
1684 };
1685 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1686
1687 return nand_exec_op(chip, &op);
1688 }
1689
1690 chip->legacy.cmdfunc(chip, NAND_CMD_READ0, -1, -1);
1691
1692 return 0;
1693 }
1694
1695 /**
1696 * nand_erase_op - Do an erase operation
1697 * @chip: The NAND chip
1698 * @eraseblock: block to erase
1699 *
1700 * This function sends an ERASE command and waits for the NAND to be ready
1701 * before returning.
1702 * This function does not select/unselect the CS line.
1703 *
1704 * Returns 0 on success, a negative error code otherwise.
1705 */
nand_erase_op(struct nand_chip * chip,unsigned int eraseblock)1706 int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock)
1707 {
1708 unsigned int page = eraseblock <<
1709 (chip->phys_erase_shift - chip->page_shift);
1710 int ret;
1711 u8 status;
1712
1713 if (nand_has_exec_op(chip)) {
1714 const struct nand_sdr_timings *sdr =
1715 nand_get_sdr_timings(nand_get_interface_config(chip));
1716 u8 addrs[3] = { page, page >> 8, page >> 16 };
1717 struct nand_op_instr instrs[] = {
1718 NAND_OP_CMD(NAND_CMD_ERASE1, 0),
1719 NAND_OP_ADDR(2, addrs, 0),
1720 NAND_OP_CMD(NAND_CMD_ERASE2,
1721 PSEC_TO_MSEC(sdr->tWB_max)),
1722 NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tBERS_max), 0),
1723 };
1724 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1725
1726 if (chip->options & NAND_ROW_ADDR_3)
1727 instrs[1].ctx.addr.naddrs++;
1728
1729 ret = nand_exec_op(chip, &op);
1730 if (ret)
1731 return ret;
1732
1733 ret = nand_status_op(chip, &status);
1734 if (ret)
1735 return ret;
1736 } else {
1737 chip->legacy.cmdfunc(chip, NAND_CMD_ERASE1, -1, page);
1738 chip->legacy.cmdfunc(chip, NAND_CMD_ERASE2, -1, -1);
1739
1740 ret = chip->legacy.waitfunc(chip);
1741 if (ret < 0)
1742 return ret;
1743
1744 status = ret;
1745 }
1746
1747 if (status & NAND_STATUS_FAIL)
1748 return -EIO;
1749
1750 return 0;
1751 }
1752 EXPORT_SYMBOL_GPL(nand_erase_op);
1753
1754 /**
1755 * nand_set_features_op - Do a SET FEATURES operation
1756 * @chip: The NAND chip
1757 * @feature: feature id
1758 * @data: 4 bytes of data
1759 *
1760 * This function sends a SET FEATURES command and waits for the NAND to be
1761 * ready before returning.
1762 * This function does not select/unselect the CS line.
1763 *
1764 * Returns 0 on success, a negative error code otherwise.
1765 */
nand_set_features_op(struct nand_chip * chip,u8 feature,const void * data)1766 static int nand_set_features_op(struct nand_chip *chip, u8 feature,
1767 const void *data)
1768 {
1769 const u8 *params = data;
1770 int i, ret;
1771
1772 if (nand_has_exec_op(chip)) {
1773 const struct nand_sdr_timings *sdr =
1774 nand_get_sdr_timings(nand_get_interface_config(chip));
1775 struct nand_op_instr instrs[] = {
1776 NAND_OP_CMD(NAND_CMD_SET_FEATURES, 0),
1777 NAND_OP_ADDR(1, &feature, PSEC_TO_NSEC(sdr->tADL_min)),
1778 NAND_OP_8BIT_DATA_OUT(ONFI_SUBFEATURE_PARAM_LEN, data,
1779 PSEC_TO_NSEC(sdr->tWB_max)),
1780 NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tFEAT_max), 0),
1781 };
1782 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1783
1784 return nand_exec_op(chip, &op);
1785 }
1786
1787 chip->legacy.cmdfunc(chip, NAND_CMD_SET_FEATURES, feature, -1);
1788 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
1789 chip->legacy.write_byte(chip, params[i]);
1790
1791 ret = chip->legacy.waitfunc(chip);
1792 if (ret < 0)
1793 return ret;
1794
1795 if (ret & NAND_STATUS_FAIL)
1796 return -EIO;
1797
1798 return 0;
1799 }
1800
1801 /**
1802 * nand_get_features_op - Do a GET FEATURES operation
1803 * @chip: The NAND chip
1804 * @feature: feature id
1805 * @data: 4 bytes of data
1806 *
1807 * This function sends a GET FEATURES command and waits for the NAND to be
1808 * ready before returning.
1809 * This function does not select/unselect the CS line.
1810 *
1811 * Returns 0 on success, a negative error code otherwise.
1812 */
nand_get_features_op(struct nand_chip * chip,u8 feature,void * data)1813 static int nand_get_features_op(struct nand_chip *chip, u8 feature,
1814 void *data)
1815 {
1816 u8 *params = data;
1817 int i;
1818
1819 if (nand_has_exec_op(chip)) {
1820 const struct nand_sdr_timings *sdr =
1821 nand_get_sdr_timings(nand_get_interface_config(chip));
1822 struct nand_op_instr instrs[] = {
1823 NAND_OP_CMD(NAND_CMD_GET_FEATURES, 0),
1824 NAND_OP_ADDR(1, &feature, PSEC_TO_NSEC(sdr->tWB_max)),
1825 NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tFEAT_max),
1826 PSEC_TO_NSEC(sdr->tRR_min)),
1827 NAND_OP_8BIT_DATA_IN(ONFI_SUBFEATURE_PARAM_LEN,
1828 data, 0),
1829 };
1830 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1831
1832 return nand_exec_op(chip, &op);
1833 }
1834
1835 chip->legacy.cmdfunc(chip, NAND_CMD_GET_FEATURES, feature, -1);
1836 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
1837 params[i] = chip->legacy.read_byte(chip);
1838
1839 return 0;
1840 }
1841
nand_wait_rdy_op(struct nand_chip * chip,unsigned int timeout_ms,unsigned int delay_ns)1842 static int nand_wait_rdy_op(struct nand_chip *chip, unsigned int timeout_ms,
1843 unsigned int delay_ns)
1844 {
1845 if (nand_has_exec_op(chip)) {
1846 struct nand_op_instr instrs[] = {
1847 NAND_OP_WAIT_RDY(PSEC_TO_MSEC(timeout_ms),
1848 PSEC_TO_NSEC(delay_ns)),
1849 };
1850 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1851
1852 return nand_exec_op(chip, &op);
1853 }
1854
1855 /* Apply delay or wait for ready/busy pin */
1856 if (!chip->legacy.dev_ready)
1857 udelay(chip->legacy.chip_delay);
1858 else
1859 nand_wait_ready(chip);
1860
1861 return 0;
1862 }
1863
1864 /**
1865 * nand_reset_op - Do a reset operation
1866 * @chip: The NAND chip
1867 *
1868 * This function sends a RESET command and waits for the NAND to be ready
1869 * before returning.
1870 * This function does not select/unselect the CS line.
1871 *
1872 * Returns 0 on success, a negative error code otherwise.
1873 */
nand_reset_op(struct nand_chip * chip)1874 int nand_reset_op(struct nand_chip *chip)
1875 {
1876 if (nand_has_exec_op(chip)) {
1877 const struct nand_sdr_timings *sdr =
1878 nand_get_sdr_timings(nand_get_interface_config(chip));
1879 struct nand_op_instr instrs[] = {
1880 NAND_OP_CMD(NAND_CMD_RESET, PSEC_TO_NSEC(sdr->tWB_max)),
1881 NAND_OP_WAIT_RDY(PSEC_TO_MSEC(sdr->tRST_max), 0),
1882 };
1883 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1884
1885 return nand_exec_op(chip, &op);
1886 }
1887
1888 chip->legacy.cmdfunc(chip, NAND_CMD_RESET, -1, -1);
1889
1890 return 0;
1891 }
1892 EXPORT_SYMBOL_GPL(nand_reset_op);
1893
1894 /**
1895 * nand_read_data_op - Read data from the NAND
1896 * @chip: The NAND chip
1897 * @buf: buffer used to store the data
1898 * @len: length of the buffer
1899 * @force_8bit: force 8-bit bus access
1900 * @check_only: do not actually run the command, only checks if the
1901 * controller driver supports it
1902 *
1903 * This function does a raw data read on the bus. Usually used after launching
1904 * another NAND operation like nand_read_page_op().
1905 * This function does not select/unselect the CS line.
1906 *
1907 * Returns 0 on success, a negative error code otherwise.
1908 */
nand_read_data_op(struct nand_chip * chip,void * buf,unsigned int len,bool force_8bit,bool check_only)1909 int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len,
1910 bool force_8bit, bool check_only)
1911 {
1912 if (!len || !buf)
1913 return -EINVAL;
1914
1915 if (nand_has_exec_op(chip)) {
1916 struct nand_op_instr instrs[] = {
1917 NAND_OP_DATA_IN(len, buf, 0),
1918 };
1919 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1920
1921 instrs[0].ctx.data.force_8bit = force_8bit;
1922
1923 if (check_only)
1924 return nand_check_op(chip, &op);
1925
1926 return nand_exec_op(chip, &op);
1927 }
1928
1929 if (check_only)
1930 return 0;
1931
1932 if (force_8bit) {
1933 u8 *p = buf;
1934 unsigned int i;
1935
1936 for (i = 0; i < len; i++)
1937 p[i] = chip->legacy.read_byte(chip);
1938 } else {
1939 chip->legacy.read_buf(chip, buf, len);
1940 }
1941
1942 return 0;
1943 }
1944 EXPORT_SYMBOL_GPL(nand_read_data_op);
1945
1946 /**
1947 * nand_write_data_op - Write data from the NAND
1948 * @chip: The NAND chip
1949 * @buf: buffer containing the data to send on the bus
1950 * @len: length of the buffer
1951 * @force_8bit: force 8-bit bus access
1952 *
1953 * This function does a raw data write on the bus. Usually used after launching
1954 * another NAND operation like nand_write_page_begin_op().
1955 * This function does not select/unselect the CS line.
1956 *
1957 * Returns 0 on success, a negative error code otherwise.
1958 */
nand_write_data_op(struct nand_chip * chip,const void * buf,unsigned int len,bool force_8bit)1959 int nand_write_data_op(struct nand_chip *chip, const void *buf,
1960 unsigned int len, bool force_8bit)
1961 {
1962 if (!len || !buf)
1963 return -EINVAL;
1964
1965 if (nand_has_exec_op(chip)) {
1966 struct nand_op_instr instrs[] = {
1967 NAND_OP_DATA_OUT(len, buf, 0),
1968 };
1969 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1970
1971 instrs[0].ctx.data.force_8bit = force_8bit;
1972
1973 return nand_exec_op(chip, &op);
1974 }
1975
1976 if (force_8bit) {
1977 const u8 *p = buf;
1978 unsigned int i;
1979
1980 for (i = 0; i < len; i++)
1981 chip->legacy.write_byte(chip, p[i]);
1982 } else {
1983 chip->legacy.write_buf(chip, buf, len);
1984 }
1985
1986 return 0;
1987 }
1988 EXPORT_SYMBOL_GPL(nand_write_data_op);
1989
1990 /**
1991 * struct nand_op_parser_ctx - Context used by the parser
1992 * @instrs: array of all the instructions that must be addressed
1993 * @ninstrs: length of the @instrs array
1994 * @subop: Sub-operation to be passed to the NAND controller
1995 *
1996 * This structure is used by the core to split NAND operations into
1997 * sub-operations that can be handled by the NAND controller.
1998 */
1999 struct nand_op_parser_ctx {
2000 const struct nand_op_instr *instrs;
2001 unsigned int ninstrs;
2002 struct nand_subop subop;
2003 };
2004
2005 /**
2006 * nand_op_parser_must_split_instr - Checks if an instruction must be split
2007 * @pat: the parser pattern element that matches @instr
2008 * @instr: pointer to the instruction to check
2009 * @start_offset: this is an in/out parameter. If @instr has already been
2010 * split, then @start_offset is the offset from which to start
2011 * (either an address cycle or an offset in the data buffer).
2012 * Conversely, if the function returns true (ie. instr must be
2013 * split), this parameter is updated to point to the first
2014 * data/address cycle that has not been taken care of.
2015 *
2016 * Some NAND controllers are limited and cannot send X address cycles with a
2017 * unique operation, or cannot read/write more than Y bytes at the same time.
2018 * In this case, split the instruction that does not fit in a single
2019 * controller-operation into two or more chunks.
2020 *
2021 * Returns true if the instruction must be split, false otherwise.
2022 * The @start_offset parameter is also updated to the offset at which the next
2023 * bundle of instruction must start (if an address or a data instruction).
2024 */
2025 static bool
nand_op_parser_must_split_instr(const struct nand_op_parser_pattern_elem * pat,const struct nand_op_instr * instr,unsigned int * start_offset)2026 nand_op_parser_must_split_instr(const struct nand_op_parser_pattern_elem *pat,
2027 const struct nand_op_instr *instr,
2028 unsigned int *start_offset)
2029 {
2030 switch (pat->type) {
2031 case NAND_OP_ADDR_INSTR:
2032 if (!pat->ctx.addr.maxcycles)
2033 break;
2034
2035 if (instr->ctx.addr.naddrs - *start_offset >
2036 pat->ctx.addr.maxcycles) {
2037 *start_offset += pat->ctx.addr.maxcycles;
2038 return true;
2039 }
2040 break;
2041
2042 case NAND_OP_DATA_IN_INSTR:
2043 case NAND_OP_DATA_OUT_INSTR:
2044 if (!pat->ctx.data.maxlen)
2045 break;
2046
2047 if (instr->ctx.data.len - *start_offset >
2048 pat->ctx.data.maxlen) {
2049 *start_offset += pat->ctx.data.maxlen;
2050 return true;
2051 }
2052 break;
2053
2054 default:
2055 break;
2056 }
2057
2058 return false;
2059 }
2060
2061 /**
2062 * nand_op_parser_match_pat - Checks if a pattern matches the instructions
2063 * remaining in the parser context
2064 * @pat: the pattern to test
2065 * @ctx: the parser context structure to match with the pattern @pat
2066 *
2067 * Check if @pat matches the set or a sub-set of instructions remaining in @ctx.
2068 * Returns true if this is the case, false ortherwise. When true is returned,
2069 * @ctx->subop is updated with the set of instructions to be passed to the
2070 * controller driver.
2071 */
2072 static bool
nand_op_parser_match_pat(const struct nand_op_parser_pattern * pat,struct nand_op_parser_ctx * ctx)2073 nand_op_parser_match_pat(const struct nand_op_parser_pattern *pat,
2074 struct nand_op_parser_ctx *ctx)
2075 {
2076 unsigned int instr_offset = ctx->subop.first_instr_start_off;
2077 const struct nand_op_instr *end = ctx->instrs + ctx->ninstrs;
2078 const struct nand_op_instr *instr = ctx->subop.instrs;
2079 unsigned int i, ninstrs;
2080
2081 for (i = 0, ninstrs = 0; i < pat->nelems && instr < end; i++) {
2082 /*
2083 * The pattern instruction does not match the operation
2084 * instruction. If the instruction is marked optional in the
2085 * pattern definition, we skip the pattern element and continue
2086 * to the next one. If the element is mandatory, there's no
2087 * match and we can return false directly.
2088 */
2089 if (instr->type != pat->elems[i].type) {
2090 if (!pat->elems[i].optional)
2091 return false;
2092
2093 continue;
2094 }
2095
2096 /*
2097 * Now check the pattern element constraints. If the pattern is
2098 * not able to handle the whole instruction in a single step,
2099 * we have to split it.
2100 * The last_instr_end_off value comes back updated to point to
2101 * the position where we have to split the instruction (the
2102 * start of the next subop chunk).
2103 */
2104 if (nand_op_parser_must_split_instr(&pat->elems[i], instr,
2105 &instr_offset)) {
2106 ninstrs++;
2107 i++;
2108 break;
2109 }
2110
2111 instr++;
2112 ninstrs++;
2113 instr_offset = 0;
2114 }
2115
2116 /*
2117 * This can happen if all instructions of a pattern are optional.
2118 * Still, if there's not at least one instruction handled by this
2119 * pattern, this is not a match, and we should try the next one (if
2120 * any).
2121 */
2122 if (!ninstrs)
2123 return false;
2124
2125 /*
2126 * We had a match on the pattern head, but the pattern may be longer
2127 * than the instructions we're asked to execute. We need to make sure
2128 * there's no mandatory elements in the pattern tail.
2129 */
2130 for (; i < pat->nelems; i++) {
2131 if (!pat->elems[i].optional)
2132 return false;
2133 }
2134
2135 /*
2136 * We have a match: update the subop structure accordingly and return
2137 * true.
2138 */
2139 ctx->subop.ninstrs = ninstrs;
2140 ctx->subop.last_instr_end_off = instr_offset;
2141
2142 return true;
2143 }
2144
2145 #if IS_ENABLED(CONFIG_DYNAMIC_DEBUG) || defined(DEBUG)
nand_op_parser_trace(const struct nand_op_parser_ctx * ctx)2146 static void nand_op_parser_trace(const struct nand_op_parser_ctx *ctx)
2147 {
2148 const struct nand_op_instr *instr;
2149 char *prefix = " ";
2150 unsigned int i;
2151
2152 pr_debug("executing subop (CS%d):\n", ctx->subop.cs);
2153
2154 for (i = 0; i < ctx->ninstrs; i++) {
2155 instr = &ctx->instrs[i];
2156
2157 if (instr == &ctx->subop.instrs[0])
2158 prefix = " ->";
2159
2160 nand_op_trace(prefix, instr);
2161
2162 if (instr == &ctx->subop.instrs[ctx->subop.ninstrs - 1])
2163 prefix = " ";
2164 }
2165 }
2166 #else
nand_op_parser_trace(const struct nand_op_parser_ctx * ctx)2167 static void nand_op_parser_trace(const struct nand_op_parser_ctx *ctx)
2168 {
2169 /* NOP */
2170 }
2171 #endif
2172
nand_op_parser_cmp_ctx(const struct nand_op_parser_ctx * a,const struct nand_op_parser_ctx * b)2173 static int nand_op_parser_cmp_ctx(const struct nand_op_parser_ctx *a,
2174 const struct nand_op_parser_ctx *b)
2175 {
2176 if (a->subop.ninstrs < b->subop.ninstrs)
2177 return -1;
2178 else if (a->subop.ninstrs > b->subop.ninstrs)
2179 return 1;
2180
2181 if (a->subop.last_instr_end_off < b->subop.last_instr_end_off)
2182 return -1;
2183 else if (a->subop.last_instr_end_off > b->subop.last_instr_end_off)
2184 return 1;
2185
2186 return 0;
2187 }
2188
2189 /**
2190 * nand_op_parser_exec_op - exec_op parser
2191 * @chip: the NAND chip
2192 * @parser: patterns description provided by the controller driver
2193 * @op: the NAND operation to address
2194 * @check_only: when true, the function only checks if @op can be handled but
2195 * does not execute the operation
2196 *
2197 * Helper function designed to ease integration of NAND controller drivers that
2198 * only support a limited set of instruction sequences. The supported sequences
2199 * are described in @parser, and the framework takes care of splitting @op into
2200 * multiple sub-operations (if required) and pass them back to the ->exec()
2201 * callback of the matching pattern if @check_only is set to false.
2202 *
2203 * NAND controller drivers should call this function from their own ->exec_op()
2204 * implementation.
2205 *
2206 * Returns 0 on success, a negative error code otherwise. A failure can be
2207 * caused by an unsupported operation (none of the supported patterns is able
2208 * to handle the requested operation), or an error returned by one of the
2209 * matching pattern->exec() hook.
2210 */
nand_op_parser_exec_op(struct nand_chip * chip,const struct nand_op_parser * parser,const struct nand_operation * op,bool check_only)2211 int nand_op_parser_exec_op(struct nand_chip *chip,
2212 const struct nand_op_parser *parser,
2213 const struct nand_operation *op, bool check_only)
2214 {
2215 struct nand_op_parser_ctx ctx = {
2216 .subop.cs = op->cs,
2217 .subop.instrs = op->instrs,
2218 .instrs = op->instrs,
2219 .ninstrs = op->ninstrs,
2220 };
2221 unsigned int i;
2222
2223 while (ctx.subop.instrs < op->instrs + op->ninstrs) {
2224 const struct nand_op_parser_pattern *pattern;
2225 struct nand_op_parser_ctx best_ctx;
2226 int ret, best_pattern = -1;
2227
2228 for (i = 0; i < parser->npatterns; i++) {
2229 struct nand_op_parser_ctx test_ctx = ctx;
2230
2231 pattern = &parser->patterns[i];
2232 if (!nand_op_parser_match_pat(pattern, &test_ctx))
2233 continue;
2234
2235 if (best_pattern >= 0 &&
2236 nand_op_parser_cmp_ctx(&test_ctx, &best_ctx) <= 0)
2237 continue;
2238
2239 best_pattern = i;
2240 best_ctx = test_ctx;
2241 }
2242
2243 if (best_pattern < 0) {
2244 pr_debug("->exec_op() parser: pattern not found!\n");
2245 return -ENOTSUPP;
2246 }
2247
2248 ctx = best_ctx;
2249 nand_op_parser_trace(&ctx);
2250
2251 if (!check_only) {
2252 pattern = &parser->patterns[best_pattern];
2253 ret = pattern->exec(chip, &ctx.subop);
2254 if (ret)
2255 return ret;
2256 }
2257
2258 /*
2259 * Update the context structure by pointing to the start of the
2260 * next subop.
2261 */
2262 ctx.subop.instrs = ctx.subop.instrs + ctx.subop.ninstrs;
2263 if (ctx.subop.last_instr_end_off)
2264 ctx.subop.instrs -= 1;
2265
2266 ctx.subop.first_instr_start_off = ctx.subop.last_instr_end_off;
2267 }
2268
2269 return 0;
2270 }
2271 EXPORT_SYMBOL_GPL(nand_op_parser_exec_op);
2272
nand_instr_is_data(const struct nand_op_instr * instr)2273 static bool nand_instr_is_data(const struct nand_op_instr *instr)
2274 {
2275 return instr && (instr->type == NAND_OP_DATA_IN_INSTR ||
2276 instr->type == NAND_OP_DATA_OUT_INSTR);
2277 }
2278
nand_subop_instr_is_valid(const struct nand_subop * subop,unsigned int instr_idx)2279 static bool nand_subop_instr_is_valid(const struct nand_subop *subop,
2280 unsigned int instr_idx)
2281 {
2282 return subop && instr_idx < subop->ninstrs;
2283 }
2284
nand_subop_get_start_off(const struct nand_subop * subop,unsigned int instr_idx)2285 static unsigned int nand_subop_get_start_off(const struct nand_subop *subop,
2286 unsigned int instr_idx)
2287 {
2288 if (instr_idx)
2289 return 0;
2290
2291 return subop->first_instr_start_off;
2292 }
2293
2294 /**
2295 * nand_subop_get_addr_start_off - Get the start offset in an address array
2296 * @subop: The entire sub-operation
2297 * @instr_idx: Index of the instruction inside the sub-operation
2298 *
2299 * During driver development, one could be tempted to directly use the
2300 * ->addr.addrs field of address instructions. This is wrong as address
2301 * instructions might be split.
2302 *
2303 * Given an address instruction, returns the offset of the first cycle to issue.
2304 */
nand_subop_get_addr_start_off(const struct nand_subop * subop,unsigned int instr_idx)2305 unsigned int nand_subop_get_addr_start_off(const struct nand_subop *subop,
2306 unsigned int instr_idx)
2307 {
2308 if (WARN_ON(!nand_subop_instr_is_valid(subop, instr_idx) ||
2309 subop->instrs[instr_idx].type != NAND_OP_ADDR_INSTR))
2310 return 0;
2311
2312 return nand_subop_get_start_off(subop, instr_idx);
2313 }
2314 EXPORT_SYMBOL_GPL(nand_subop_get_addr_start_off);
2315
2316 /**
2317 * nand_subop_get_num_addr_cyc - Get the remaining address cycles to assert
2318 * @subop: The entire sub-operation
2319 * @instr_idx: Index of the instruction inside the sub-operation
2320 *
2321 * During driver development, one could be tempted to directly use the
2322 * ->addr->naddrs field of a data instruction. This is wrong as instructions
2323 * might be split.
2324 *
2325 * Given an address instruction, returns the number of address cycle to issue.
2326 */
nand_subop_get_num_addr_cyc(const struct nand_subop * subop,unsigned int instr_idx)2327 unsigned int nand_subop_get_num_addr_cyc(const struct nand_subop *subop,
2328 unsigned int instr_idx)
2329 {
2330 int start_off, end_off;
2331
2332 if (WARN_ON(!nand_subop_instr_is_valid(subop, instr_idx) ||
2333 subop->instrs[instr_idx].type != NAND_OP_ADDR_INSTR))
2334 return 0;
2335
2336 start_off = nand_subop_get_addr_start_off(subop, instr_idx);
2337
2338 if (instr_idx == subop->ninstrs - 1 &&
2339 subop->last_instr_end_off)
2340 end_off = subop->last_instr_end_off;
2341 else
2342 end_off = subop->instrs[instr_idx].ctx.addr.naddrs;
2343
2344 return end_off - start_off;
2345 }
2346 EXPORT_SYMBOL_GPL(nand_subop_get_num_addr_cyc);
2347
2348 /**
2349 * nand_subop_get_data_start_off - Get the start offset in a data array
2350 * @subop: The entire sub-operation
2351 * @instr_idx: Index of the instruction inside the sub-operation
2352 *
2353 * During driver development, one could be tempted to directly use the
2354 * ->data->buf.{in,out} field of data instructions. This is wrong as data
2355 * instructions might be split.
2356 *
2357 * Given a data instruction, returns the offset to start from.
2358 */
nand_subop_get_data_start_off(const struct nand_subop * subop,unsigned int instr_idx)2359 unsigned int nand_subop_get_data_start_off(const struct nand_subop *subop,
2360 unsigned int instr_idx)
2361 {
2362 if (WARN_ON(!nand_subop_instr_is_valid(subop, instr_idx) ||
2363 !nand_instr_is_data(&subop->instrs[instr_idx])))
2364 return 0;
2365
2366 return nand_subop_get_start_off(subop, instr_idx);
2367 }
2368 EXPORT_SYMBOL_GPL(nand_subop_get_data_start_off);
2369
2370 /**
2371 * nand_subop_get_data_len - Get the number of bytes to retrieve
2372 * @subop: The entire sub-operation
2373 * @instr_idx: Index of the instruction inside the sub-operation
2374 *
2375 * During driver development, one could be tempted to directly use the
2376 * ->data->len field of a data instruction. This is wrong as data instructions
2377 * might be split.
2378 *
2379 * Returns the length of the chunk of data to send/receive.
2380 */
nand_subop_get_data_len(const struct nand_subop * subop,unsigned int instr_idx)2381 unsigned int nand_subop_get_data_len(const struct nand_subop *subop,
2382 unsigned int instr_idx)
2383 {
2384 int start_off = 0, end_off;
2385
2386 if (WARN_ON(!nand_subop_instr_is_valid(subop, instr_idx) ||
2387 !nand_instr_is_data(&subop->instrs[instr_idx])))
2388 return 0;
2389
2390 start_off = nand_subop_get_data_start_off(subop, instr_idx);
2391
2392 if (instr_idx == subop->ninstrs - 1 &&
2393 subop->last_instr_end_off)
2394 end_off = subop->last_instr_end_off;
2395 else
2396 end_off = subop->instrs[instr_idx].ctx.data.len;
2397
2398 return end_off - start_off;
2399 }
2400 EXPORT_SYMBOL_GPL(nand_subop_get_data_len);
2401
2402 /**
2403 * nand_reset - Reset and initialize a NAND device
2404 * @chip: The NAND chip
2405 * @chipnr: Internal die id
2406 *
2407 * Save the timings data structure, then apply SDR timings mode 0 (see
2408 * nand_reset_interface for details), do the reset operation, and apply
2409 * back the previous timings.
2410 *
2411 * Returns 0 on success, a negative error code otherwise.
2412 */
nand_reset(struct nand_chip * chip,int chipnr)2413 int nand_reset(struct nand_chip *chip, int chipnr)
2414 {
2415 int ret;
2416
2417 ret = nand_reset_interface(chip, chipnr);
2418 if (ret)
2419 return ret;
2420
2421 /*
2422 * The CS line has to be released before we can apply the new NAND
2423 * interface settings, hence this weird nand_select_target()
2424 * nand_deselect_target() dance.
2425 */
2426 nand_select_target(chip, chipnr);
2427 ret = nand_reset_op(chip);
2428 nand_deselect_target(chip);
2429 if (ret)
2430 return ret;
2431
2432 ret = nand_setup_interface(chip, chipnr);
2433 if (ret)
2434 return ret;
2435
2436 return 0;
2437 }
2438 EXPORT_SYMBOL_GPL(nand_reset);
2439
2440 /**
2441 * nand_get_features - wrapper to perform a GET_FEATURE
2442 * @chip: NAND chip info structure
2443 * @addr: feature address
2444 * @subfeature_param: the subfeature parameters, a four bytes array
2445 *
2446 * Returns 0 for success, a negative error otherwise. Returns -ENOTSUPP if the
2447 * operation cannot be handled.
2448 */
nand_get_features(struct nand_chip * chip,int addr,u8 * subfeature_param)2449 int nand_get_features(struct nand_chip *chip, int addr,
2450 u8 *subfeature_param)
2451 {
2452 if (!nand_supports_get_features(chip, addr))
2453 return -ENOTSUPP;
2454
2455 if (chip->legacy.get_features)
2456 return chip->legacy.get_features(chip, addr, subfeature_param);
2457
2458 return nand_get_features_op(chip, addr, subfeature_param);
2459 }
2460
2461 /**
2462 * nand_set_features - wrapper to perform a SET_FEATURE
2463 * @chip: NAND chip info structure
2464 * @addr: feature address
2465 * @subfeature_param: the subfeature parameters, a four bytes array
2466 *
2467 * Returns 0 for success, a negative error otherwise. Returns -ENOTSUPP if the
2468 * operation cannot be handled.
2469 */
nand_set_features(struct nand_chip * chip,int addr,u8 * subfeature_param)2470 int nand_set_features(struct nand_chip *chip, int addr,
2471 u8 *subfeature_param)
2472 {
2473 if (!nand_supports_set_features(chip, addr))
2474 return -ENOTSUPP;
2475
2476 if (chip->legacy.set_features)
2477 return chip->legacy.set_features(chip, addr, subfeature_param);
2478
2479 return nand_set_features_op(chip, addr, subfeature_param);
2480 }
2481
2482 /**
2483 * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data
2484 * @buf: buffer to test
2485 * @len: buffer length
2486 * @bitflips_threshold: maximum number of bitflips
2487 *
2488 * Check if a buffer contains only 0xff, which means the underlying region
2489 * has been erased and is ready to be programmed.
2490 * The bitflips_threshold specify the maximum number of bitflips before
2491 * considering the region is not erased.
2492 * Note: The logic of this function has been extracted from the memweight
2493 * implementation, except that nand_check_erased_buf function exit before
2494 * testing the whole buffer if the number of bitflips exceed the
2495 * bitflips_threshold value.
2496 *
2497 * Returns a positive number of bitflips less than or equal to
2498 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
2499 * threshold.
2500 */
nand_check_erased_buf(void * buf,int len,int bitflips_threshold)2501 static int nand_check_erased_buf(void *buf, int len, int bitflips_threshold)
2502 {
2503 const unsigned char *bitmap = buf;
2504 int bitflips = 0;
2505 int weight;
2506
2507 for (; len && ((uintptr_t)bitmap) % sizeof(long);
2508 len--, bitmap++) {
2509 weight = hweight8(*bitmap);
2510 bitflips += BITS_PER_BYTE - weight;
2511 if (unlikely(bitflips > bitflips_threshold))
2512 return -EBADMSG;
2513 }
2514
2515 for (; len >= sizeof(long);
2516 len -= sizeof(long), bitmap += sizeof(long)) {
2517 unsigned long d = *((unsigned long *)bitmap);
2518 if (d == ~0UL)
2519 continue;
2520 weight = hweight_long(d);
2521 bitflips += BITS_PER_LONG - weight;
2522 if (unlikely(bitflips > bitflips_threshold))
2523 return -EBADMSG;
2524 }
2525
2526 for (; len > 0; len--, bitmap++) {
2527 weight = hweight8(*bitmap);
2528 bitflips += BITS_PER_BYTE - weight;
2529 if (unlikely(bitflips > bitflips_threshold))
2530 return -EBADMSG;
2531 }
2532
2533 return bitflips;
2534 }
2535
2536 /**
2537 * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only
2538 * 0xff data
2539 * @data: data buffer to test
2540 * @datalen: data length
2541 * @ecc: ECC buffer
2542 * @ecclen: ECC length
2543 * @extraoob: extra OOB buffer
2544 * @extraooblen: extra OOB length
2545 * @bitflips_threshold: maximum number of bitflips
2546 *
2547 * Check if a data buffer and its associated ECC and OOB data contains only
2548 * 0xff pattern, which means the underlying region has been erased and is
2549 * ready to be programmed.
2550 * The bitflips_threshold specify the maximum number of bitflips before
2551 * considering the region as not erased.
2552 *
2553 * Note:
2554 * 1/ ECC algorithms are working on pre-defined block sizes which are usually
2555 * different from the NAND page size. When fixing bitflips, ECC engines will
2556 * report the number of errors per chunk, and the NAND core infrastructure
2557 * expect you to return the maximum number of bitflips for the whole page.
2558 * This is why you should always use this function on a single chunk and
2559 * not on the whole page. After checking each chunk you should update your
2560 * max_bitflips value accordingly.
2561 * 2/ When checking for bitflips in erased pages you should not only check
2562 * the payload data but also their associated ECC data, because a user might
2563 * have programmed almost all bits to 1 but a few. In this case, we
2564 * shouldn't consider the chunk as erased, and checking ECC bytes prevent
2565 * this case.
2566 * 3/ The extraoob argument is optional, and should be used if some of your OOB
2567 * data are protected by the ECC engine.
2568 * It could also be used if you support subpages and want to attach some
2569 * extra OOB data to an ECC chunk.
2570 *
2571 * Returns a positive number of bitflips less than or equal to
2572 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
2573 * threshold. In case of success, the passed buffers are filled with 0xff.
2574 */
nand_check_erased_ecc_chunk(void * data,int datalen,void * ecc,int ecclen,void * extraoob,int extraooblen,int bitflips_threshold)2575 int nand_check_erased_ecc_chunk(void *data, int datalen,
2576 void *ecc, int ecclen,
2577 void *extraoob, int extraooblen,
2578 int bitflips_threshold)
2579 {
2580 int data_bitflips = 0, ecc_bitflips = 0, extraoob_bitflips = 0;
2581
2582 data_bitflips = nand_check_erased_buf(data, datalen,
2583 bitflips_threshold);
2584 if (data_bitflips < 0)
2585 return data_bitflips;
2586
2587 bitflips_threshold -= data_bitflips;
2588
2589 ecc_bitflips = nand_check_erased_buf(ecc, ecclen, bitflips_threshold);
2590 if (ecc_bitflips < 0)
2591 return ecc_bitflips;
2592
2593 bitflips_threshold -= ecc_bitflips;
2594
2595 extraoob_bitflips = nand_check_erased_buf(extraoob, extraooblen,
2596 bitflips_threshold);
2597 if (extraoob_bitflips < 0)
2598 return extraoob_bitflips;
2599
2600 if (data_bitflips)
2601 memset(data, 0xff, datalen);
2602
2603 if (ecc_bitflips)
2604 memset(ecc, 0xff, ecclen);
2605
2606 if (extraoob_bitflips)
2607 memset(extraoob, 0xff, extraooblen);
2608
2609 return data_bitflips + ecc_bitflips + extraoob_bitflips;
2610 }
2611 EXPORT_SYMBOL(nand_check_erased_ecc_chunk);
2612
2613 /**
2614 * nand_read_page_raw_notsupp - dummy read raw page function
2615 * @chip: nand chip info structure
2616 * @buf: buffer to store read data
2617 * @oob_required: caller requires OOB data read to chip->oob_poi
2618 * @page: page number to read
2619 *
2620 * Returns -ENOTSUPP unconditionally.
2621 */
nand_read_page_raw_notsupp(struct nand_chip * chip,u8 * buf,int oob_required,int page)2622 int nand_read_page_raw_notsupp(struct nand_chip *chip, u8 *buf,
2623 int oob_required, int page)
2624 {
2625 return -ENOTSUPP;
2626 }
2627
2628 /**
2629 * nand_read_page_raw - [INTERN] read raw page data without ecc
2630 * @chip: nand chip info structure
2631 * @buf: buffer to store read data
2632 * @oob_required: caller requires OOB data read to chip->oob_poi
2633 * @page: page number to read
2634 *
2635 * Not for syndrome calculating ECC controllers, which use a special oob layout.
2636 */
nand_read_page_raw(struct nand_chip * chip,uint8_t * buf,int oob_required,int page)2637 int nand_read_page_raw(struct nand_chip *chip, uint8_t *buf, int oob_required,
2638 int page)
2639 {
2640 struct mtd_info *mtd = nand_to_mtd(chip);
2641 int ret;
2642
2643 ret = nand_read_page_op(chip, page, 0, buf, mtd->writesize);
2644 if (ret)
2645 return ret;
2646
2647 if (oob_required) {
2648 ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize,
2649 false, false);
2650 if (ret)
2651 return ret;
2652 }
2653
2654 return 0;
2655 }
2656 EXPORT_SYMBOL(nand_read_page_raw);
2657
2658 /**
2659 * nand_monolithic_read_page_raw - Monolithic page read in raw mode
2660 * @chip: NAND chip info structure
2661 * @buf: buffer to store read data
2662 * @oob_required: caller requires OOB data read to chip->oob_poi
2663 * @page: page number to read
2664 *
2665 * This is a raw page read, ie. without any error detection/correction.
2666 * Monolithic means we are requesting all the relevant data (main plus
2667 * eventually OOB) to be loaded in the NAND cache and sent over the
2668 * bus (from the NAND chip to the NAND controller) in a single
2669 * operation. This is an alternative to nand_read_page_raw(), which
2670 * first reads the main data, and if the OOB data is requested too,
2671 * then reads more data on the bus.
2672 */
nand_monolithic_read_page_raw(struct nand_chip * chip,u8 * buf,int oob_required,int page)2673 int nand_monolithic_read_page_raw(struct nand_chip *chip, u8 *buf,
2674 int oob_required, int page)
2675 {
2676 struct mtd_info *mtd = nand_to_mtd(chip);
2677 unsigned int size = mtd->writesize;
2678 u8 *read_buf = buf;
2679 int ret;
2680
2681 if (oob_required) {
2682 size += mtd->oobsize;
2683
2684 if (buf != chip->data_buf)
2685 read_buf = nand_get_data_buf(chip);
2686 }
2687
2688 ret = nand_read_page_op(chip, page, 0, read_buf, size);
2689 if (ret)
2690 return ret;
2691
2692 if (buf != chip->data_buf)
2693 memcpy(buf, read_buf, mtd->writesize);
2694
2695 return 0;
2696 }
2697 EXPORT_SYMBOL(nand_monolithic_read_page_raw);
2698
2699 /**
2700 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
2701 * @chip: nand chip info structure
2702 * @buf: buffer to store read data
2703 * @oob_required: caller requires OOB data read to chip->oob_poi
2704 * @page: page number to read
2705 *
2706 * We need a special oob layout and handling even when OOB isn't used.
2707 */
nand_read_page_raw_syndrome(struct nand_chip * chip,uint8_t * buf,int oob_required,int page)2708 static int nand_read_page_raw_syndrome(struct nand_chip *chip, uint8_t *buf,
2709 int oob_required, int page)
2710 {
2711 struct mtd_info *mtd = nand_to_mtd(chip);
2712 int eccsize = chip->ecc.size;
2713 int eccbytes = chip->ecc.bytes;
2714 uint8_t *oob = chip->oob_poi;
2715 int steps, size, ret;
2716
2717 ret = nand_read_page_op(chip, page, 0, NULL, 0);
2718 if (ret)
2719 return ret;
2720
2721 for (steps = chip->ecc.steps; steps > 0; steps--) {
2722 ret = nand_read_data_op(chip, buf, eccsize, false, false);
2723 if (ret)
2724 return ret;
2725
2726 buf += eccsize;
2727
2728 if (chip->ecc.prepad) {
2729 ret = nand_read_data_op(chip, oob, chip->ecc.prepad,
2730 false, false);
2731 if (ret)
2732 return ret;
2733
2734 oob += chip->ecc.prepad;
2735 }
2736
2737 ret = nand_read_data_op(chip, oob, eccbytes, false, false);
2738 if (ret)
2739 return ret;
2740
2741 oob += eccbytes;
2742
2743 if (chip->ecc.postpad) {
2744 ret = nand_read_data_op(chip, oob, chip->ecc.postpad,
2745 false, false);
2746 if (ret)
2747 return ret;
2748
2749 oob += chip->ecc.postpad;
2750 }
2751 }
2752
2753 size = mtd->oobsize - (oob - chip->oob_poi);
2754 if (size) {
2755 ret = nand_read_data_op(chip, oob, size, false, false);
2756 if (ret)
2757 return ret;
2758 }
2759
2760 return 0;
2761 }
2762
2763 /**
2764 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
2765 * @chip: nand chip info structure
2766 * @buf: buffer to store read data
2767 * @oob_required: caller requires OOB data read to chip->oob_poi
2768 * @page: page number to read
2769 */
nand_read_page_swecc(struct nand_chip * chip,uint8_t * buf,int oob_required,int page)2770 static int nand_read_page_swecc(struct nand_chip *chip, uint8_t *buf,
2771 int oob_required, int page)
2772 {
2773 struct mtd_info *mtd = nand_to_mtd(chip);
2774 int i, eccsize = chip->ecc.size, ret;
2775 int eccbytes = chip->ecc.bytes;
2776 int eccsteps = chip->ecc.steps;
2777 uint8_t *p = buf;
2778 uint8_t *ecc_calc = chip->ecc.calc_buf;
2779 uint8_t *ecc_code = chip->ecc.code_buf;
2780 unsigned int max_bitflips = 0;
2781
2782 chip->ecc.read_page_raw(chip, buf, 1, page);
2783
2784 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
2785 chip->ecc.calculate(chip, p, &ecc_calc[i]);
2786
2787 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
2788 chip->ecc.total);
2789 if (ret)
2790 return ret;
2791
2792 eccsteps = chip->ecc.steps;
2793 p = buf;
2794
2795 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2796 int stat;
2797
2798 stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]);
2799 if (stat < 0) {
2800 mtd->ecc_stats.failed++;
2801 } else {
2802 mtd->ecc_stats.corrected += stat;
2803 max_bitflips = max_t(unsigned int, max_bitflips, stat);
2804 }
2805 }
2806 return max_bitflips;
2807 }
2808
2809 /**
2810 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
2811 * @chip: nand chip info structure
2812 * @data_offs: offset of requested data within the page
2813 * @readlen: data length
2814 * @bufpoi: buffer to store read data
2815 * @page: page number to read
2816 */
nand_read_subpage(struct nand_chip * chip,uint32_t data_offs,uint32_t readlen,uint8_t * bufpoi,int page)2817 static int nand_read_subpage(struct nand_chip *chip, uint32_t data_offs,
2818 uint32_t readlen, uint8_t *bufpoi, int page)
2819 {
2820 struct mtd_info *mtd = nand_to_mtd(chip);
2821 int start_step, end_step, num_steps, ret;
2822 uint8_t *p;
2823 int data_col_addr, i, gaps = 0;
2824 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
2825 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
2826 int index, section = 0;
2827 unsigned int max_bitflips = 0;
2828 struct mtd_oob_region oobregion = { };
2829
2830 /* Column address within the page aligned to ECC size (256bytes) */
2831 start_step = data_offs / chip->ecc.size;
2832 end_step = (data_offs + readlen - 1) / chip->ecc.size;
2833 num_steps = end_step - start_step + 1;
2834 index = start_step * chip->ecc.bytes;
2835
2836 /* Data size aligned to ECC ecc.size */
2837 datafrag_len = num_steps * chip->ecc.size;
2838 eccfrag_len = num_steps * chip->ecc.bytes;
2839
2840 data_col_addr = start_step * chip->ecc.size;
2841 /* If we read not a page aligned data */
2842 p = bufpoi + data_col_addr;
2843 ret = nand_read_page_op(chip, page, data_col_addr, p, datafrag_len);
2844 if (ret)
2845 return ret;
2846
2847 /* Calculate ECC */
2848 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
2849 chip->ecc.calculate(chip, p, &chip->ecc.calc_buf[i]);
2850
2851 /*
2852 * The performance is faster if we position offsets according to
2853 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
2854 */
2855 ret = mtd_ooblayout_find_eccregion(mtd, index, §ion, &oobregion);
2856 if (ret)
2857 return ret;
2858
2859 if (oobregion.length < eccfrag_len)
2860 gaps = 1;
2861
2862 if (gaps) {
2863 ret = nand_change_read_column_op(chip, mtd->writesize,
2864 chip->oob_poi, mtd->oobsize,
2865 false);
2866 if (ret)
2867 return ret;
2868 } else {
2869 /*
2870 * Send the command to read the particular ECC bytes take care
2871 * about buswidth alignment in read_buf.
2872 */
2873 aligned_pos = oobregion.offset & ~(busw - 1);
2874 aligned_len = eccfrag_len;
2875 if (oobregion.offset & (busw - 1))
2876 aligned_len++;
2877 if ((oobregion.offset + (num_steps * chip->ecc.bytes)) &
2878 (busw - 1))
2879 aligned_len++;
2880
2881 ret = nand_change_read_column_op(chip,
2882 mtd->writesize + aligned_pos,
2883 &chip->oob_poi[aligned_pos],
2884 aligned_len, false);
2885 if (ret)
2886 return ret;
2887 }
2888
2889 ret = mtd_ooblayout_get_eccbytes(mtd, chip->ecc.code_buf,
2890 chip->oob_poi, index, eccfrag_len);
2891 if (ret)
2892 return ret;
2893
2894 p = bufpoi + data_col_addr;
2895 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
2896 int stat;
2897
2898 stat = chip->ecc.correct(chip, p, &chip->ecc.code_buf[i],
2899 &chip->ecc.calc_buf[i]);
2900 if (stat == -EBADMSG &&
2901 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
2902 /* check for empty pages with bitflips */
2903 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
2904 &chip->ecc.code_buf[i],
2905 chip->ecc.bytes,
2906 NULL, 0,
2907 chip->ecc.strength);
2908 }
2909
2910 if (stat < 0) {
2911 mtd->ecc_stats.failed++;
2912 } else {
2913 mtd->ecc_stats.corrected += stat;
2914 max_bitflips = max_t(unsigned int, max_bitflips, stat);
2915 }
2916 }
2917 return max_bitflips;
2918 }
2919
2920 /**
2921 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
2922 * @chip: nand chip info structure
2923 * @buf: buffer to store read data
2924 * @oob_required: caller requires OOB data read to chip->oob_poi
2925 * @page: page number to read
2926 *
2927 * Not for syndrome calculating ECC controllers which need a special oob layout.
2928 */
nand_read_page_hwecc(struct nand_chip * chip,uint8_t * buf,int oob_required,int page)2929 static int nand_read_page_hwecc(struct nand_chip *chip, uint8_t *buf,
2930 int oob_required, int page)
2931 {
2932 struct mtd_info *mtd = nand_to_mtd(chip);
2933 int i, eccsize = chip->ecc.size, ret;
2934 int eccbytes = chip->ecc.bytes;
2935 int eccsteps = chip->ecc.steps;
2936 uint8_t *p = buf;
2937 uint8_t *ecc_calc = chip->ecc.calc_buf;
2938 uint8_t *ecc_code = chip->ecc.code_buf;
2939 unsigned int max_bitflips = 0;
2940
2941 ret = nand_read_page_op(chip, page, 0, NULL, 0);
2942 if (ret)
2943 return ret;
2944
2945 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2946 chip->ecc.hwctl(chip, NAND_ECC_READ);
2947
2948 ret = nand_read_data_op(chip, p, eccsize, false, false);
2949 if (ret)
2950 return ret;
2951
2952 chip->ecc.calculate(chip, p, &ecc_calc[i]);
2953 }
2954
2955 ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize, false,
2956 false);
2957 if (ret)
2958 return ret;
2959
2960 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
2961 chip->ecc.total);
2962 if (ret)
2963 return ret;
2964
2965 eccsteps = chip->ecc.steps;
2966 p = buf;
2967
2968 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2969 int stat;
2970
2971 stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]);
2972 if (stat == -EBADMSG &&
2973 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
2974 /* check for empty pages with bitflips */
2975 stat = nand_check_erased_ecc_chunk(p, eccsize,
2976 &ecc_code[i], eccbytes,
2977 NULL, 0,
2978 chip->ecc.strength);
2979 }
2980
2981 if (stat < 0) {
2982 mtd->ecc_stats.failed++;
2983 } else {
2984 mtd->ecc_stats.corrected += stat;
2985 max_bitflips = max_t(unsigned int, max_bitflips, stat);
2986 }
2987 }
2988 return max_bitflips;
2989 }
2990
2991 /**
2992 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
2993 * @chip: nand chip info structure
2994 * @buf: buffer to store read data
2995 * @oob_required: caller requires OOB data read to chip->oob_poi
2996 * @page: page number to read
2997 *
2998 * The hw generator calculates the error syndrome automatically. Therefore we
2999 * need a special oob layout and handling.
3000 */
nand_read_page_syndrome(struct nand_chip * chip,uint8_t * buf,int oob_required,int page)3001 static int nand_read_page_syndrome(struct nand_chip *chip, uint8_t *buf,
3002 int oob_required, int page)
3003 {
3004 struct mtd_info *mtd = nand_to_mtd(chip);
3005 int ret, i, eccsize = chip->ecc.size;
3006 int eccbytes = chip->ecc.bytes;
3007 int eccsteps = chip->ecc.steps;
3008 int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
3009 uint8_t *p = buf;
3010 uint8_t *oob = chip->oob_poi;
3011 unsigned int max_bitflips = 0;
3012
3013 ret = nand_read_page_op(chip, page, 0, NULL, 0);
3014 if (ret)
3015 return ret;
3016
3017 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
3018 int stat;
3019
3020 chip->ecc.hwctl(chip, NAND_ECC_READ);
3021
3022 ret = nand_read_data_op(chip, p, eccsize, false, false);
3023 if (ret)
3024 return ret;
3025
3026 if (chip->ecc.prepad) {
3027 ret = nand_read_data_op(chip, oob, chip->ecc.prepad,
3028 false, false);
3029 if (ret)
3030 return ret;
3031
3032 oob += chip->ecc.prepad;
3033 }
3034
3035 chip->ecc.hwctl(chip, NAND_ECC_READSYN);
3036
3037 ret = nand_read_data_op(chip, oob, eccbytes, false, false);
3038 if (ret)
3039 return ret;
3040
3041 stat = chip->ecc.correct(chip, p, oob, NULL);
3042
3043 oob += eccbytes;
3044
3045 if (chip->ecc.postpad) {
3046 ret = nand_read_data_op(chip, oob, chip->ecc.postpad,
3047 false, false);
3048 if (ret)
3049 return ret;
3050
3051 oob += chip->ecc.postpad;
3052 }
3053
3054 if (stat == -EBADMSG &&
3055 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
3056 /* check for empty pages with bitflips */
3057 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
3058 oob - eccpadbytes,
3059 eccpadbytes,
3060 NULL, 0,
3061 chip->ecc.strength);
3062 }
3063
3064 if (stat < 0) {
3065 mtd->ecc_stats.failed++;
3066 } else {
3067 mtd->ecc_stats.corrected += stat;
3068 max_bitflips = max_t(unsigned int, max_bitflips, stat);
3069 }
3070 }
3071
3072 /* Calculate remaining oob bytes */
3073 i = mtd->oobsize - (oob - chip->oob_poi);
3074 if (i) {
3075 ret = nand_read_data_op(chip, oob, i, false, false);
3076 if (ret)
3077 return ret;
3078 }
3079
3080 return max_bitflips;
3081 }
3082
3083 /**
3084 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
3085 * @chip: NAND chip object
3086 * @oob: oob destination address
3087 * @ops: oob ops structure
3088 * @len: size of oob to transfer
3089 */
nand_transfer_oob(struct nand_chip * chip,uint8_t * oob,struct mtd_oob_ops * ops,size_t len)3090 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
3091 struct mtd_oob_ops *ops, size_t len)
3092 {
3093 struct mtd_info *mtd = nand_to_mtd(chip);
3094 int ret;
3095
3096 switch (ops->mode) {
3097
3098 case MTD_OPS_PLACE_OOB:
3099 case MTD_OPS_RAW:
3100 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
3101 return oob + len;
3102
3103 case MTD_OPS_AUTO_OOB:
3104 ret = mtd_ooblayout_get_databytes(mtd, oob, chip->oob_poi,
3105 ops->ooboffs, len);
3106 BUG_ON(ret);
3107 return oob + len;
3108
3109 default:
3110 BUG();
3111 }
3112 return NULL;
3113 }
3114
3115 /**
3116 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
3117 * @chip: NAND chip object
3118 * @retry_mode: the retry mode to use
3119 *
3120 * Some vendors supply a special command to shift the Vt threshold, to be used
3121 * when there are too many bitflips in a page (i.e., ECC error). After setting
3122 * a new threshold, the host should retry reading the page.
3123 */
nand_setup_read_retry(struct nand_chip * chip,int retry_mode)3124 static int nand_setup_read_retry(struct nand_chip *chip, int retry_mode)
3125 {
3126 pr_debug("setting READ RETRY mode %d\n", retry_mode);
3127
3128 if (retry_mode >= chip->read_retries)
3129 return -EINVAL;
3130
3131 if (!chip->ops.setup_read_retry)
3132 return -EOPNOTSUPP;
3133
3134 return chip->ops.setup_read_retry(chip, retry_mode);
3135 }
3136
nand_wait_readrdy(struct nand_chip * chip)3137 static void nand_wait_readrdy(struct nand_chip *chip)
3138 {
3139 const struct nand_sdr_timings *sdr;
3140
3141 if (!(chip->options & NAND_NEED_READRDY))
3142 return;
3143
3144 sdr = nand_get_sdr_timings(nand_get_interface_config(chip));
3145 WARN_ON(nand_wait_rdy_op(chip, PSEC_TO_MSEC(sdr->tR_max), 0));
3146 }
3147
3148 /**
3149 * nand_do_read_ops - [INTERN] Read data with ECC
3150 * @chip: NAND chip object
3151 * @from: offset to read from
3152 * @ops: oob ops structure
3153 *
3154 * Internal function. Called with chip held.
3155 */
nand_do_read_ops(struct nand_chip * chip,loff_t from,struct mtd_oob_ops * ops)3156 static int nand_do_read_ops(struct nand_chip *chip, loff_t from,
3157 struct mtd_oob_ops *ops)
3158 {
3159 int chipnr, page, realpage, col, bytes, aligned, oob_required;
3160 struct mtd_info *mtd = nand_to_mtd(chip);
3161 int ret = 0;
3162 uint32_t readlen = ops->len;
3163 uint32_t oobreadlen = ops->ooblen;
3164 uint32_t max_oobsize = mtd_oobavail(mtd, ops);
3165
3166 uint8_t *bufpoi, *oob, *buf;
3167 int use_bounce_buf;
3168 unsigned int max_bitflips = 0;
3169 int retry_mode = 0;
3170 bool ecc_fail = false;
3171
3172 /* Check if the region is secured */
3173 if (nand_region_is_secured(chip, from, readlen))
3174 return -EIO;
3175
3176 chipnr = (int)(from >> chip->chip_shift);
3177 nand_select_target(chip, chipnr);
3178
3179 realpage = (int)(from >> chip->page_shift);
3180 page = realpage & chip->pagemask;
3181
3182 col = (int)(from & (mtd->writesize - 1));
3183
3184 buf = ops->datbuf;
3185 oob = ops->oobbuf;
3186 oob_required = oob ? 1 : 0;
3187
3188 while (1) {
3189 struct mtd_ecc_stats ecc_stats = mtd->ecc_stats;
3190
3191 bytes = min(mtd->writesize - col, readlen);
3192 aligned = (bytes == mtd->writesize);
3193
3194 if (!aligned)
3195 use_bounce_buf = 1;
3196 else if (chip->options & NAND_USES_DMA)
3197 use_bounce_buf = !virt_addr_valid(buf) ||
3198 !IS_ALIGNED((unsigned long)buf,
3199 chip->buf_align);
3200 else
3201 use_bounce_buf = 0;
3202
3203 /* Is the current page in the buffer? */
3204 if (realpage != chip->pagecache.page || oob) {
3205 bufpoi = use_bounce_buf ? chip->data_buf : buf;
3206
3207 if (use_bounce_buf && aligned)
3208 pr_debug("%s: using read bounce buffer for buf@%p\n",
3209 __func__, buf);
3210
3211 read_retry:
3212 /*
3213 * Now read the page into the buffer. Absent an error,
3214 * the read methods return max bitflips per ecc step.
3215 */
3216 if (unlikely(ops->mode == MTD_OPS_RAW))
3217 ret = chip->ecc.read_page_raw(chip, bufpoi,
3218 oob_required,
3219 page);
3220 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
3221 !oob)
3222 ret = chip->ecc.read_subpage(chip, col, bytes,
3223 bufpoi, page);
3224 else
3225 ret = chip->ecc.read_page(chip, bufpoi,
3226 oob_required, page);
3227 if (ret < 0) {
3228 if (use_bounce_buf)
3229 /* Invalidate page cache */
3230 chip->pagecache.page = -1;
3231 break;
3232 }
3233
3234 /*
3235 * Copy back the data in the initial buffer when reading
3236 * partial pages or when a bounce buffer is required.
3237 */
3238 if (use_bounce_buf) {
3239 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
3240 !(mtd->ecc_stats.failed - ecc_stats.failed) &&
3241 (ops->mode != MTD_OPS_RAW)) {
3242 chip->pagecache.page = realpage;
3243 chip->pagecache.bitflips = ret;
3244 } else {
3245 /* Invalidate page cache */
3246 chip->pagecache.page = -1;
3247 }
3248 memcpy(buf, bufpoi + col, bytes);
3249 }
3250
3251 if (unlikely(oob)) {
3252 int toread = min(oobreadlen, max_oobsize);
3253
3254 if (toread) {
3255 oob = nand_transfer_oob(chip, oob, ops,
3256 toread);
3257 oobreadlen -= toread;
3258 }
3259 }
3260
3261 nand_wait_readrdy(chip);
3262
3263 if (mtd->ecc_stats.failed - ecc_stats.failed) {
3264 if (retry_mode + 1 < chip->read_retries) {
3265 retry_mode++;
3266 ret = nand_setup_read_retry(chip,
3267 retry_mode);
3268 if (ret < 0)
3269 break;
3270
3271 /* Reset ecc_stats; retry */
3272 mtd->ecc_stats = ecc_stats;
3273 goto read_retry;
3274 } else {
3275 /* No more retry modes; real failure */
3276 ecc_fail = true;
3277 }
3278 }
3279
3280 buf += bytes;
3281 max_bitflips = max_t(unsigned int, max_bitflips, ret);
3282 } else {
3283 memcpy(buf, chip->data_buf + col, bytes);
3284 buf += bytes;
3285 max_bitflips = max_t(unsigned int, max_bitflips,
3286 chip->pagecache.bitflips);
3287 }
3288
3289 readlen -= bytes;
3290
3291 /* Reset to retry mode 0 */
3292 if (retry_mode) {
3293 ret = nand_setup_read_retry(chip, 0);
3294 if (ret < 0)
3295 break;
3296 retry_mode = 0;
3297 }
3298
3299 if (!readlen)
3300 break;
3301
3302 /* For subsequent reads align to page boundary */
3303 col = 0;
3304 /* Increment page address */
3305 realpage++;
3306
3307 page = realpage & chip->pagemask;
3308 /* Check, if we cross a chip boundary */
3309 if (!page) {
3310 chipnr++;
3311 nand_deselect_target(chip);
3312 nand_select_target(chip, chipnr);
3313 }
3314 }
3315 nand_deselect_target(chip);
3316
3317 ops->retlen = ops->len - (size_t) readlen;
3318 if (oob)
3319 ops->oobretlen = ops->ooblen - oobreadlen;
3320
3321 if (ret < 0)
3322 return ret;
3323
3324 if (ecc_fail)
3325 return -EBADMSG;
3326
3327 return max_bitflips;
3328 }
3329
3330 /**
3331 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
3332 * @chip: nand chip info structure
3333 * @page: page number to read
3334 */
nand_read_oob_std(struct nand_chip * chip,int page)3335 int nand_read_oob_std(struct nand_chip *chip, int page)
3336 {
3337 struct mtd_info *mtd = nand_to_mtd(chip);
3338
3339 return nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
3340 }
3341 EXPORT_SYMBOL(nand_read_oob_std);
3342
3343 /**
3344 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
3345 * with syndromes
3346 * @chip: nand chip info structure
3347 * @page: page number to read
3348 */
nand_read_oob_syndrome(struct nand_chip * chip,int page)3349 static int nand_read_oob_syndrome(struct nand_chip *chip, int page)
3350 {
3351 struct mtd_info *mtd = nand_to_mtd(chip);
3352 int length = mtd->oobsize;
3353 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
3354 int eccsize = chip->ecc.size;
3355 uint8_t *bufpoi = chip->oob_poi;
3356 int i, toread, sndrnd = 0, pos, ret;
3357
3358 ret = nand_read_page_op(chip, page, chip->ecc.size, NULL, 0);
3359 if (ret)
3360 return ret;
3361
3362 for (i = 0; i < chip->ecc.steps; i++) {
3363 if (sndrnd) {
3364 int ret;
3365
3366 pos = eccsize + i * (eccsize + chunk);
3367 if (mtd->writesize > 512)
3368 ret = nand_change_read_column_op(chip, pos,
3369 NULL, 0,
3370 false);
3371 else
3372 ret = nand_read_page_op(chip, page, pos, NULL,
3373 0);
3374
3375 if (ret)
3376 return ret;
3377 } else
3378 sndrnd = 1;
3379 toread = min_t(int, length, chunk);
3380
3381 ret = nand_read_data_op(chip, bufpoi, toread, false, false);
3382 if (ret)
3383 return ret;
3384
3385 bufpoi += toread;
3386 length -= toread;
3387 }
3388 if (length > 0) {
3389 ret = nand_read_data_op(chip, bufpoi, length, false, false);
3390 if (ret)
3391 return ret;
3392 }
3393
3394 return 0;
3395 }
3396
3397 /**
3398 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
3399 * @chip: nand chip info structure
3400 * @page: page number to write
3401 */
nand_write_oob_std(struct nand_chip * chip,int page)3402 int nand_write_oob_std(struct nand_chip *chip, int page)
3403 {
3404 struct mtd_info *mtd = nand_to_mtd(chip);
3405
3406 return nand_prog_page_op(chip, page, mtd->writesize, chip->oob_poi,
3407 mtd->oobsize);
3408 }
3409 EXPORT_SYMBOL(nand_write_oob_std);
3410
3411 /**
3412 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
3413 * with syndrome - only for large page flash
3414 * @chip: nand chip info structure
3415 * @page: page number to write
3416 */
nand_write_oob_syndrome(struct nand_chip * chip,int page)3417 static int nand_write_oob_syndrome(struct nand_chip *chip, int page)
3418 {
3419 struct mtd_info *mtd = nand_to_mtd(chip);
3420 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
3421 int eccsize = chip->ecc.size, length = mtd->oobsize;
3422 int ret, i, len, pos, sndcmd = 0, steps = chip->ecc.steps;
3423 const uint8_t *bufpoi = chip->oob_poi;
3424
3425 /*
3426 * data-ecc-data-ecc ... ecc-oob
3427 * or
3428 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
3429 */
3430 if (!chip->ecc.prepad && !chip->ecc.postpad) {
3431 pos = steps * (eccsize + chunk);
3432 steps = 0;
3433 } else
3434 pos = eccsize;
3435
3436 ret = nand_prog_page_begin_op(chip, page, pos, NULL, 0);
3437 if (ret)
3438 return ret;
3439
3440 for (i = 0; i < steps; i++) {
3441 if (sndcmd) {
3442 if (mtd->writesize <= 512) {
3443 uint32_t fill = 0xFFFFFFFF;
3444
3445 len = eccsize;
3446 while (len > 0) {
3447 int num = min_t(int, len, 4);
3448
3449 ret = nand_write_data_op(chip, &fill,
3450 num, false);
3451 if (ret)
3452 return ret;
3453
3454 len -= num;
3455 }
3456 } else {
3457 pos = eccsize + i * (eccsize + chunk);
3458 ret = nand_change_write_column_op(chip, pos,
3459 NULL, 0,
3460 false);
3461 if (ret)
3462 return ret;
3463 }
3464 } else
3465 sndcmd = 1;
3466 len = min_t(int, length, chunk);
3467
3468 ret = nand_write_data_op(chip, bufpoi, len, false);
3469 if (ret)
3470 return ret;
3471
3472 bufpoi += len;
3473 length -= len;
3474 }
3475 if (length > 0) {
3476 ret = nand_write_data_op(chip, bufpoi, length, false);
3477 if (ret)
3478 return ret;
3479 }
3480
3481 return nand_prog_page_end_op(chip);
3482 }
3483
3484 /**
3485 * nand_do_read_oob - [INTERN] NAND read out-of-band
3486 * @chip: NAND chip object
3487 * @from: offset to read from
3488 * @ops: oob operations description structure
3489 *
3490 * NAND read out-of-band data from the spare area.
3491 */
nand_do_read_oob(struct nand_chip * chip,loff_t from,struct mtd_oob_ops * ops)3492 static int nand_do_read_oob(struct nand_chip *chip, loff_t from,
3493 struct mtd_oob_ops *ops)
3494 {
3495 struct mtd_info *mtd = nand_to_mtd(chip);
3496 unsigned int max_bitflips = 0;
3497 int page, realpage, chipnr;
3498 struct mtd_ecc_stats stats;
3499 int readlen = ops->ooblen;
3500 int len;
3501 uint8_t *buf = ops->oobbuf;
3502 int ret = 0;
3503
3504 pr_debug("%s: from = 0x%08Lx, len = %i\n",
3505 __func__, (unsigned long long)from, readlen);
3506
3507 /* Check if the region is secured */
3508 if (nand_region_is_secured(chip, from, readlen))
3509 return -EIO;
3510
3511 stats = mtd->ecc_stats;
3512
3513 len = mtd_oobavail(mtd, ops);
3514
3515 chipnr = (int)(from >> chip->chip_shift);
3516 nand_select_target(chip, chipnr);
3517
3518 /* Shift to get page */
3519 realpage = (int)(from >> chip->page_shift);
3520 page = realpage & chip->pagemask;
3521
3522 while (1) {
3523 if (ops->mode == MTD_OPS_RAW)
3524 ret = chip->ecc.read_oob_raw(chip, page);
3525 else
3526 ret = chip->ecc.read_oob(chip, page);
3527
3528 if (ret < 0)
3529 break;
3530
3531 len = min(len, readlen);
3532 buf = nand_transfer_oob(chip, buf, ops, len);
3533
3534 nand_wait_readrdy(chip);
3535
3536 max_bitflips = max_t(unsigned int, max_bitflips, ret);
3537
3538 readlen -= len;
3539 if (!readlen)
3540 break;
3541
3542 /* Increment page address */
3543 realpage++;
3544
3545 page = realpage & chip->pagemask;
3546 /* Check, if we cross a chip boundary */
3547 if (!page) {
3548 chipnr++;
3549 nand_deselect_target(chip);
3550 nand_select_target(chip, chipnr);
3551 }
3552 }
3553 nand_deselect_target(chip);
3554
3555 ops->oobretlen = ops->ooblen - readlen;
3556
3557 if (ret < 0)
3558 return ret;
3559
3560 if (mtd->ecc_stats.failed - stats.failed)
3561 return -EBADMSG;
3562
3563 return max_bitflips;
3564 }
3565
3566 /**
3567 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
3568 * @mtd: MTD device structure
3569 * @from: offset to read from
3570 * @ops: oob operation description structure
3571 *
3572 * NAND read data and/or out-of-band data.
3573 */
nand_read_oob(struct mtd_info * mtd,loff_t from,struct mtd_oob_ops * ops)3574 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
3575 struct mtd_oob_ops *ops)
3576 {
3577 struct nand_chip *chip = mtd_to_nand(mtd);
3578 int ret;
3579
3580 ops->retlen = 0;
3581
3582 if (ops->mode != MTD_OPS_PLACE_OOB &&
3583 ops->mode != MTD_OPS_AUTO_OOB &&
3584 ops->mode != MTD_OPS_RAW)
3585 return -ENOTSUPP;
3586
3587 ret = nand_get_device(chip);
3588 if (ret)
3589 return ret;
3590
3591 if (!ops->datbuf)
3592 ret = nand_do_read_oob(chip, from, ops);
3593 else
3594 ret = nand_do_read_ops(chip, from, ops);
3595
3596 nand_release_device(chip);
3597 return ret;
3598 }
3599
3600 /**
3601 * nand_write_page_raw_notsupp - dummy raw page write function
3602 * @chip: nand chip info structure
3603 * @buf: data buffer
3604 * @oob_required: must write chip->oob_poi to OOB
3605 * @page: page number to write
3606 *
3607 * Returns -ENOTSUPP unconditionally.
3608 */
nand_write_page_raw_notsupp(struct nand_chip * chip,const u8 * buf,int oob_required,int page)3609 int nand_write_page_raw_notsupp(struct nand_chip *chip, const u8 *buf,
3610 int oob_required, int page)
3611 {
3612 return -ENOTSUPP;
3613 }
3614
3615 /**
3616 * nand_write_page_raw - [INTERN] raw page write function
3617 * @chip: nand chip info structure
3618 * @buf: data buffer
3619 * @oob_required: must write chip->oob_poi to OOB
3620 * @page: page number to write
3621 *
3622 * Not for syndrome calculating ECC controllers, which use a special oob layout.
3623 */
nand_write_page_raw(struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)3624 int nand_write_page_raw(struct nand_chip *chip, const uint8_t *buf,
3625 int oob_required, int page)
3626 {
3627 struct mtd_info *mtd = nand_to_mtd(chip);
3628 int ret;
3629
3630 ret = nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize);
3631 if (ret)
3632 return ret;
3633
3634 if (oob_required) {
3635 ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize,
3636 false);
3637 if (ret)
3638 return ret;
3639 }
3640
3641 return nand_prog_page_end_op(chip);
3642 }
3643 EXPORT_SYMBOL(nand_write_page_raw);
3644
3645 /**
3646 * nand_monolithic_write_page_raw - Monolithic page write in raw mode
3647 * @chip: NAND chip info structure
3648 * @buf: data buffer to write
3649 * @oob_required: must write chip->oob_poi to OOB
3650 * @page: page number to write
3651 *
3652 * This is a raw page write, ie. without any error detection/correction.
3653 * Monolithic means we are requesting all the relevant data (main plus
3654 * eventually OOB) to be sent over the bus and effectively programmed
3655 * into the NAND chip arrays in a single operation. This is an
3656 * alternative to nand_write_page_raw(), which first sends the main
3657 * data, then eventually send the OOB data by latching more data
3658 * cycles on the NAND bus, and finally sends the program command to
3659 * synchronyze the NAND chip cache.
3660 */
nand_monolithic_write_page_raw(struct nand_chip * chip,const u8 * buf,int oob_required,int page)3661 int nand_monolithic_write_page_raw(struct nand_chip *chip, const u8 *buf,
3662 int oob_required, int page)
3663 {
3664 struct mtd_info *mtd = nand_to_mtd(chip);
3665 unsigned int size = mtd->writesize;
3666 u8 *write_buf = (u8 *)buf;
3667
3668 if (oob_required) {
3669 size += mtd->oobsize;
3670
3671 if (buf != chip->data_buf) {
3672 write_buf = nand_get_data_buf(chip);
3673 memcpy(write_buf, buf, mtd->writesize);
3674 }
3675 }
3676
3677 return nand_prog_page_op(chip, page, 0, write_buf, size);
3678 }
3679 EXPORT_SYMBOL(nand_monolithic_write_page_raw);
3680
3681 /**
3682 * nand_write_page_raw_syndrome - [INTERN] raw page write function
3683 * @chip: nand chip info structure
3684 * @buf: data buffer
3685 * @oob_required: must write chip->oob_poi to OOB
3686 * @page: page number to write
3687 *
3688 * We need a special oob layout and handling even when ECC isn't checked.
3689 */
nand_write_page_raw_syndrome(struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)3690 static int nand_write_page_raw_syndrome(struct nand_chip *chip,
3691 const uint8_t *buf, int oob_required,
3692 int page)
3693 {
3694 struct mtd_info *mtd = nand_to_mtd(chip);
3695 int eccsize = chip->ecc.size;
3696 int eccbytes = chip->ecc.bytes;
3697 uint8_t *oob = chip->oob_poi;
3698 int steps, size, ret;
3699
3700 ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0);
3701 if (ret)
3702 return ret;
3703
3704 for (steps = chip->ecc.steps; steps > 0; steps--) {
3705 ret = nand_write_data_op(chip, buf, eccsize, false);
3706 if (ret)
3707 return ret;
3708
3709 buf += eccsize;
3710
3711 if (chip->ecc.prepad) {
3712 ret = nand_write_data_op(chip, oob, chip->ecc.prepad,
3713 false);
3714 if (ret)
3715 return ret;
3716
3717 oob += chip->ecc.prepad;
3718 }
3719
3720 ret = nand_write_data_op(chip, oob, eccbytes, false);
3721 if (ret)
3722 return ret;
3723
3724 oob += eccbytes;
3725
3726 if (chip->ecc.postpad) {
3727 ret = nand_write_data_op(chip, oob, chip->ecc.postpad,
3728 false);
3729 if (ret)
3730 return ret;
3731
3732 oob += chip->ecc.postpad;
3733 }
3734 }
3735
3736 size = mtd->oobsize - (oob - chip->oob_poi);
3737 if (size) {
3738 ret = nand_write_data_op(chip, oob, size, false);
3739 if (ret)
3740 return ret;
3741 }
3742
3743 return nand_prog_page_end_op(chip);
3744 }
3745 /**
3746 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
3747 * @chip: nand chip info structure
3748 * @buf: data buffer
3749 * @oob_required: must write chip->oob_poi to OOB
3750 * @page: page number to write
3751 */
nand_write_page_swecc(struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)3752 static int nand_write_page_swecc(struct nand_chip *chip, const uint8_t *buf,
3753 int oob_required, int page)
3754 {
3755 struct mtd_info *mtd = nand_to_mtd(chip);
3756 int i, eccsize = chip->ecc.size, ret;
3757 int eccbytes = chip->ecc.bytes;
3758 int eccsteps = chip->ecc.steps;
3759 uint8_t *ecc_calc = chip->ecc.calc_buf;
3760 const uint8_t *p = buf;
3761
3762 /* Software ECC calculation */
3763 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
3764 chip->ecc.calculate(chip, p, &ecc_calc[i]);
3765
3766 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,
3767 chip->ecc.total);
3768 if (ret)
3769 return ret;
3770
3771 return chip->ecc.write_page_raw(chip, buf, 1, page);
3772 }
3773
3774 /**
3775 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
3776 * @chip: nand chip info structure
3777 * @buf: data buffer
3778 * @oob_required: must write chip->oob_poi to OOB
3779 * @page: page number to write
3780 */
nand_write_page_hwecc(struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)3781 static int nand_write_page_hwecc(struct nand_chip *chip, const uint8_t *buf,
3782 int oob_required, int page)
3783 {
3784 struct mtd_info *mtd = nand_to_mtd(chip);
3785 int i, eccsize = chip->ecc.size, ret;
3786 int eccbytes = chip->ecc.bytes;
3787 int eccsteps = chip->ecc.steps;
3788 uint8_t *ecc_calc = chip->ecc.calc_buf;
3789 const uint8_t *p = buf;
3790
3791 ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0);
3792 if (ret)
3793 return ret;
3794
3795 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
3796 chip->ecc.hwctl(chip, NAND_ECC_WRITE);
3797
3798 ret = nand_write_data_op(chip, p, eccsize, false);
3799 if (ret)
3800 return ret;
3801
3802 chip->ecc.calculate(chip, p, &ecc_calc[i]);
3803 }
3804
3805 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,
3806 chip->ecc.total);
3807 if (ret)
3808 return ret;
3809
3810 ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false);
3811 if (ret)
3812 return ret;
3813
3814 return nand_prog_page_end_op(chip);
3815 }
3816
3817
3818 /**
3819 * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write
3820 * @chip: nand chip info structure
3821 * @offset: column address of subpage within the page
3822 * @data_len: data length
3823 * @buf: data buffer
3824 * @oob_required: must write chip->oob_poi to OOB
3825 * @page: page number to write
3826 */
nand_write_subpage_hwecc(struct nand_chip * chip,uint32_t offset,uint32_t data_len,const uint8_t * buf,int oob_required,int page)3827 static int nand_write_subpage_hwecc(struct nand_chip *chip, uint32_t offset,
3828 uint32_t data_len, const uint8_t *buf,
3829 int oob_required, int page)
3830 {
3831 struct mtd_info *mtd = nand_to_mtd(chip);
3832 uint8_t *oob_buf = chip->oob_poi;
3833 uint8_t *ecc_calc = chip->ecc.calc_buf;
3834 int ecc_size = chip->ecc.size;
3835 int ecc_bytes = chip->ecc.bytes;
3836 int ecc_steps = chip->ecc.steps;
3837 uint32_t start_step = offset / ecc_size;
3838 uint32_t end_step = (offset + data_len - 1) / ecc_size;
3839 int oob_bytes = mtd->oobsize / ecc_steps;
3840 int step, ret;
3841
3842 ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0);
3843 if (ret)
3844 return ret;
3845
3846 for (step = 0; step < ecc_steps; step++) {
3847 /* configure controller for WRITE access */
3848 chip->ecc.hwctl(chip, NAND_ECC_WRITE);
3849
3850 /* write data (untouched subpages already masked by 0xFF) */
3851 ret = nand_write_data_op(chip, buf, ecc_size, false);
3852 if (ret)
3853 return ret;
3854
3855 /* mask ECC of un-touched subpages by padding 0xFF */
3856 if ((step < start_step) || (step > end_step))
3857 memset(ecc_calc, 0xff, ecc_bytes);
3858 else
3859 chip->ecc.calculate(chip, buf, ecc_calc);
3860
3861 /* mask OOB of un-touched subpages by padding 0xFF */
3862 /* if oob_required, preserve OOB metadata of written subpage */
3863 if (!oob_required || (step < start_step) || (step > end_step))
3864 memset(oob_buf, 0xff, oob_bytes);
3865
3866 buf += ecc_size;
3867 ecc_calc += ecc_bytes;
3868 oob_buf += oob_bytes;
3869 }
3870
3871 /* copy calculated ECC for whole page to chip->buffer->oob */
3872 /* this include masked-value(0xFF) for unwritten subpages */
3873 ecc_calc = chip->ecc.calc_buf;
3874 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,
3875 chip->ecc.total);
3876 if (ret)
3877 return ret;
3878
3879 /* write OOB buffer to NAND device */
3880 ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false);
3881 if (ret)
3882 return ret;
3883
3884 return nand_prog_page_end_op(chip);
3885 }
3886
3887
3888 /**
3889 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
3890 * @chip: nand chip info structure
3891 * @buf: data buffer
3892 * @oob_required: must write chip->oob_poi to OOB
3893 * @page: page number to write
3894 *
3895 * The hw generator calculates the error syndrome automatically. Therefore we
3896 * need a special oob layout and handling.
3897 */
nand_write_page_syndrome(struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)3898 static int nand_write_page_syndrome(struct nand_chip *chip, const uint8_t *buf,
3899 int oob_required, int page)
3900 {
3901 struct mtd_info *mtd = nand_to_mtd(chip);
3902 int i, eccsize = chip->ecc.size;
3903 int eccbytes = chip->ecc.bytes;
3904 int eccsteps = chip->ecc.steps;
3905 const uint8_t *p = buf;
3906 uint8_t *oob = chip->oob_poi;
3907 int ret;
3908
3909 ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0);
3910 if (ret)
3911 return ret;
3912
3913 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
3914 chip->ecc.hwctl(chip, NAND_ECC_WRITE);
3915
3916 ret = nand_write_data_op(chip, p, eccsize, false);
3917 if (ret)
3918 return ret;
3919
3920 if (chip->ecc.prepad) {
3921 ret = nand_write_data_op(chip, oob, chip->ecc.prepad,
3922 false);
3923 if (ret)
3924 return ret;
3925
3926 oob += chip->ecc.prepad;
3927 }
3928
3929 chip->ecc.calculate(chip, p, oob);
3930
3931 ret = nand_write_data_op(chip, oob, eccbytes, false);
3932 if (ret)
3933 return ret;
3934
3935 oob += eccbytes;
3936
3937 if (chip->ecc.postpad) {
3938 ret = nand_write_data_op(chip, oob, chip->ecc.postpad,
3939 false);
3940 if (ret)
3941 return ret;
3942
3943 oob += chip->ecc.postpad;
3944 }
3945 }
3946
3947 /* Calculate remaining oob bytes */
3948 i = mtd->oobsize - (oob - chip->oob_poi);
3949 if (i) {
3950 ret = nand_write_data_op(chip, oob, i, false);
3951 if (ret)
3952 return ret;
3953 }
3954
3955 return nand_prog_page_end_op(chip);
3956 }
3957
3958 /**
3959 * nand_write_page - write one page
3960 * @chip: NAND chip descriptor
3961 * @offset: address offset within the page
3962 * @data_len: length of actual data to be written
3963 * @buf: the data to write
3964 * @oob_required: must write chip->oob_poi to OOB
3965 * @page: page number to write
3966 * @raw: use _raw version of write_page
3967 */
nand_write_page(struct nand_chip * chip,uint32_t offset,int data_len,const uint8_t * buf,int oob_required,int page,int raw)3968 static int nand_write_page(struct nand_chip *chip, uint32_t offset,
3969 int data_len, const uint8_t *buf, int oob_required,
3970 int page, int raw)
3971 {
3972 struct mtd_info *mtd = nand_to_mtd(chip);
3973 int status, subpage;
3974
3975 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3976 chip->ecc.write_subpage)
3977 subpage = offset || (data_len < mtd->writesize);
3978 else
3979 subpage = 0;
3980
3981 if (unlikely(raw))
3982 status = chip->ecc.write_page_raw(chip, buf, oob_required,
3983 page);
3984 else if (subpage)
3985 status = chip->ecc.write_subpage(chip, offset, data_len, buf,
3986 oob_required, page);
3987 else
3988 status = chip->ecc.write_page(chip, buf, oob_required, page);
3989
3990 if (status < 0)
3991 return status;
3992
3993 return 0;
3994 }
3995
3996 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
3997
3998 /**
3999 * nand_do_write_ops - [INTERN] NAND write with ECC
4000 * @chip: NAND chip object
4001 * @to: offset to write to
4002 * @ops: oob operations description structure
4003 *
4004 * NAND write with ECC.
4005 */
nand_do_write_ops(struct nand_chip * chip,loff_t to,struct mtd_oob_ops * ops)4006 static int nand_do_write_ops(struct nand_chip *chip, loff_t to,
4007 struct mtd_oob_ops *ops)
4008 {
4009 struct mtd_info *mtd = nand_to_mtd(chip);
4010 int chipnr, realpage, page, column;
4011 uint32_t writelen = ops->len;
4012
4013 uint32_t oobwritelen = ops->ooblen;
4014 uint32_t oobmaxlen = mtd_oobavail(mtd, ops);
4015
4016 uint8_t *oob = ops->oobbuf;
4017 uint8_t *buf = ops->datbuf;
4018 int ret;
4019 int oob_required = oob ? 1 : 0;
4020
4021 ops->retlen = 0;
4022 if (!writelen)
4023 return 0;
4024
4025 /* Reject writes, which are not page aligned */
4026 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
4027 pr_notice("%s: attempt to write non page aligned data\n",
4028 __func__);
4029 return -EINVAL;
4030 }
4031
4032 /* Check if the region is secured */
4033 if (nand_region_is_secured(chip, to, writelen))
4034 return -EIO;
4035
4036 column = to & (mtd->writesize - 1);
4037
4038 chipnr = (int)(to >> chip->chip_shift);
4039 nand_select_target(chip, chipnr);
4040
4041 /* Check, if it is write protected */
4042 if (nand_check_wp(chip)) {
4043 ret = -EIO;
4044 goto err_out;
4045 }
4046
4047 realpage = (int)(to >> chip->page_shift);
4048 page = realpage & chip->pagemask;
4049
4050 /* Invalidate the page cache, when we write to the cached page */
4051 if (to <= ((loff_t)chip->pagecache.page << chip->page_shift) &&
4052 ((loff_t)chip->pagecache.page << chip->page_shift) < (to + ops->len))
4053 chip->pagecache.page = -1;
4054
4055 /* Don't allow multipage oob writes with offset */
4056 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
4057 ret = -EINVAL;
4058 goto err_out;
4059 }
4060
4061 while (1) {
4062 int bytes = mtd->writesize;
4063 uint8_t *wbuf = buf;
4064 int use_bounce_buf;
4065 int part_pagewr = (column || writelen < mtd->writesize);
4066
4067 if (part_pagewr)
4068 use_bounce_buf = 1;
4069 else if (chip->options & NAND_USES_DMA)
4070 use_bounce_buf = !virt_addr_valid(buf) ||
4071 !IS_ALIGNED((unsigned long)buf,
4072 chip->buf_align);
4073 else
4074 use_bounce_buf = 0;
4075
4076 /*
4077 * Copy the data from the initial buffer when doing partial page
4078 * writes or when a bounce buffer is required.
4079 */
4080 if (use_bounce_buf) {
4081 pr_debug("%s: using write bounce buffer for buf@%p\n",
4082 __func__, buf);
4083 if (part_pagewr)
4084 bytes = min_t(int, bytes - column, writelen);
4085 wbuf = nand_get_data_buf(chip);
4086 memset(wbuf, 0xff, mtd->writesize);
4087 memcpy(&wbuf[column], buf, bytes);
4088 }
4089
4090 if (unlikely(oob)) {
4091 size_t len = min(oobwritelen, oobmaxlen);
4092 oob = nand_fill_oob(chip, oob, len, ops);
4093 oobwritelen -= len;
4094 } else {
4095 /* We still need to erase leftover OOB data */
4096 memset(chip->oob_poi, 0xff, mtd->oobsize);
4097 }
4098
4099 ret = nand_write_page(chip, column, bytes, wbuf,
4100 oob_required, page,
4101 (ops->mode == MTD_OPS_RAW));
4102 if (ret)
4103 break;
4104
4105 writelen -= bytes;
4106 if (!writelen)
4107 break;
4108
4109 column = 0;
4110 buf += bytes;
4111 realpage++;
4112
4113 page = realpage & chip->pagemask;
4114 /* Check, if we cross a chip boundary */
4115 if (!page) {
4116 chipnr++;
4117 nand_deselect_target(chip);
4118 nand_select_target(chip, chipnr);
4119 }
4120 }
4121
4122 ops->retlen = ops->len - writelen;
4123 if (unlikely(oob))
4124 ops->oobretlen = ops->ooblen;
4125
4126 err_out:
4127 nand_deselect_target(chip);
4128 return ret;
4129 }
4130
4131 /**
4132 * panic_nand_write - [MTD Interface] NAND write with ECC
4133 * @mtd: MTD device structure
4134 * @to: offset to write to
4135 * @len: number of bytes to write
4136 * @retlen: pointer to variable to store the number of written bytes
4137 * @buf: the data to write
4138 *
4139 * NAND write with ECC. Used when performing writes in interrupt context, this
4140 * may for example be called by mtdoops when writing an oops while in panic.
4141 */
panic_nand_write(struct mtd_info * mtd,loff_t to,size_t len,size_t * retlen,const uint8_t * buf)4142 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
4143 size_t *retlen, const uint8_t *buf)
4144 {
4145 struct nand_chip *chip = mtd_to_nand(mtd);
4146 int chipnr = (int)(to >> chip->chip_shift);
4147 struct mtd_oob_ops ops;
4148 int ret;
4149
4150 nand_select_target(chip, chipnr);
4151
4152 /* Wait for the device to get ready */
4153 panic_nand_wait(chip, 400);
4154
4155 memset(&ops, 0, sizeof(ops));
4156 ops.len = len;
4157 ops.datbuf = (uint8_t *)buf;
4158 ops.mode = MTD_OPS_PLACE_OOB;
4159
4160 ret = nand_do_write_ops(chip, to, &ops);
4161
4162 *retlen = ops.retlen;
4163 return ret;
4164 }
4165
4166 /**
4167 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
4168 * @mtd: MTD device structure
4169 * @to: offset to write to
4170 * @ops: oob operation description structure
4171 */
nand_write_oob(struct mtd_info * mtd,loff_t to,struct mtd_oob_ops * ops)4172 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
4173 struct mtd_oob_ops *ops)
4174 {
4175 struct nand_chip *chip = mtd_to_nand(mtd);
4176 int ret;
4177
4178 ops->retlen = 0;
4179
4180 ret = nand_get_device(chip);
4181 if (ret)
4182 return ret;
4183
4184 switch (ops->mode) {
4185 case MTD_OPS_PLACE_OOB:
4186 case MTD_OPS_AUTO_OOB:
4187 case MTD_OPS_RAW:
4188 break;
4189
4190 default:
4191 goto out;
4192 }
4193
4194 if (!ops->datbuf)
4195 ret = nand_do_write_oob(chip, to, ops);
4196 else
4197 ret = nand_do_write_ops(chip, to, ops);
4198
4199 out:
4200 nand_release_device(chip);
4201 return ret;
4202 }
4203
4204 /**
4205 * nand_erase - [MTD Interface] erase block(s)
4206 * @mtd: MTD device structure
4207 * @instr: erase instruction
4208 *
4209 * Erase one ore more blocks.
4210 */
nand_erase(struct mtd_info * mtd,struct erase_info * instr)4211 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
4212 {
4213 return nand_erase_nand(mtd_to_nand(mtd), instr, 0);
4214 }
4215
4216 /**
4217 * nand_erase_nand - [INTERN] erase block(s)
4218 * @chip: NAND chip object
4219 * @instr: erase instruction
4220 * @allowbbt: allow erasing the bbt area
4221 *
4222 * Erase one ore more blocks.
4223 */
nand_erase_nand(struct nand_chip * chip,struct erase_info * instr,int allowbbt)4224 int nand_erase_nand(struct nand_chip *chip, struct erase_info *instr,
4225 int allowbbt)
4226 {
4227 int page, pages_per_block, ret, chipnr;
4228 loff_t len;
4229
4230 pr_debug("%s: start = 0x%012llx, len = %llu\n",
4231 __func__, (unsigned long long)instr->addr,
4232 (unsigned long long)instr->len);
4233
4234 if (check_offs_len(chip, instr->addr, instr->len))
4235 return -EINVAL;
4236
4237 /* Check if the region is secured */
4238 if (nand_region_is_secured(chip, instr->addr, instr->len))
4239 return -EIO;
4240
4241 /* Grab the lock and see if the device is available */
4242 ret = nand_get_device(chip);
4243 if (ret)
4244 return ret;
4245
4246 /* Shift to get first page */
4247 page = (int)(instr->addr >> chip->page_shift);
4248 chipnr = (int)(instr->addr >> chip->chip_shift);
4249
4250 /* Calculate pages in each block */
4251 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
4252
4253 /* Select the NAND device */
4254 nand_select_target(chip, chipnr);
4255
4256 /* Check, if it is write protected */
4257 if (nand_check_wp(chip)) {
4258 pr_debug("%s: device is write protected!\n",
4259 __func__);
4260 ret = -EIO;
4261 goto erase_exit;
4262 }
4263
4264 /* Loop through the pages */
4265 len = instr->len;
4266
4267 while (len) {
4268 /* Check if we have a bad block, we do not erase bad blocks! */
4269 if (nand_block_checkbad(chip, ((loff_t) page) <<
4270 chip->page_shift, allowbbt)) {
4271 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
4272 __func__, page);
4273 ret = -EIO;
4274 goto erase_exit;
4275 }
4276
4277 /*
4278 * Invalidate the page cache, if we erase the block which
4279 * contains the current cached page.
4280 */
4281 if (page <= chip->pagecache.page && chip->pagecache.page <
4282 (page + pages_per_block))
4283 chip->pagecache.page = -1;
4284
4285 ret = nand_erase_op(chip, (page & chip->pagemask) >>
4286 (chip->phys_erase_shift - chip->page_shift));
4287 if (ret) {
4288 pr_debug("%s: failed erase, page 0x%08x\n",
4289 __func__, page);
4290 instr->fail_addr =
4291 ((loff_t)page << chip->page_shift);
4292 goto erase_exit;
4293 }
4294
4295 /* Increment page address and decrement length */
4296 len -= (1ULL << chip->phys_erase_shift);
4297 page += pages_per_block;
4298
4299 /* Check, if we cross a chip boundary */
4300 if (len && !(page & chip->pagemask)) {
4301 chipnr++;
4302 nand_deselect_target(chip);
4303 nand_select_target(chip, chipnr);
4304 }
4305 }
4306
4307 ret = 0;
4308 erase_exit:
4309
4310 /* Deselect and wake up anyone waiting on the device */
4311 nand_deselect_target(chip);
4312 nand_release_device(chip);
4313
4314 /* Return more or less happy */
4315 return ret;
4316 }
4317
4318 /**
4319 * nand_sync - [MTD Interface] sync
4320 * @mtd: MTD device structure
4321 *
4322 * Sync is actually a wait for chip ready function.
4323 */
nand_sync(struct mtd_info * mtd)4324 static void nand_sync(struct mtd_info *mtd)
4325 {
4326 struct nand_chip *chip = mtd_to_nand(mtd);
4327
4328 pr_debug("%s: called\n", __func__);
4329
4330 /* Grab the lock and see if the device is available */
4331 WARN_ON(nand_get_device(chip));
4332 /* Release it and go back */
4333 nand_release_device(chip);
4334 }
4335
4336 /**
4337 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
4338 * @mtd: MTD device structure
4339 * @offs: offset relative to mtd start
4340 */
nand_block_isbad(struct mtd_info * mtd,loff_t offs)4341 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
4342 {
4343 struct nand_chip *chip = mtd_to_nand(mtd);
4344 int chipnr = (int)(offs >> chip->chip_shift);
4345 int ret;
4346
4347 /* Select the NAND device */
4348 ret = nand_get_device(chip);
4349 if (ret)
4350 return ret;
4351
4352 nand_select_target(chip, chipnr);
4353
4354 ret = nand_block_checkbad(chip, offs, 0);
4355
4356 nand_deselect_target(chip);
4357 nand_release_device(chip);
4358
4359 return ret;
4360 }
4361
4362 /**
4363 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
4364 * @mtd: MTD device structure
4365 * @ofs: offset relative to mtd start
4366 */
nand_block_markbad(struct mtd_info * mtd,loff_t ofs)4367 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
4368 {
4369 int ret;
4370
4371 ret = nand_block_isbad(mtd, ofs);
4372 if (ret) {
4373 /* If it was bad already, return success and do nothing */
4374 if (ret > 0)
4375 return 0;
4376 return ret;
4377 }
4378
4379 return nand_block_markbad_lowlevel(mtd_to_nand(mtd), ofs);
4380 }
4381
4382 /**
4383 * nand_suspend - [MTD Interface] Suspend the NAND flash
4384 * @mtd: MTD device structure
4385 *
4386 * Returns 0 for success or negative error code otherwise.
4387 */
nand_suspend(struct mtd_info * mtd)4388 static int nand_suspend(struct mtd_info *mtd)
4389 {
4390 struct nand_chip *chip = mtd_to_nand(mtd);
4391 int ret = 0;
4392
4393 mutex_lock(&chip->lock);
4394 if (chip->ops.suspend)
4395 ret = chip->ops.suspend(chip);
4396 if (!ret)
4397 chip->suspended = 1;
4398 mutex_unlock(&chip->lock);
4399
4400 return ret;
4401 }
4402
4403 /**
4404 * nand_resume - [MTD Interface] Resume the NAND flash
4405 * @mtd: MTD device structure
4406 */
nand_resume(struct mtd_info * mtd)4407 static void nand_resume(struct mtd_info *mtd)
4408 {
4409 struct nand_chip *chip = mtd_to_nand(mtd);
4410
4411 mutex_lock(&chip->lock);
4412 if (chip->suspended) {
4413 if (chip->ops.resume)
4414 chip->ops.resume(chip);
4415 chip->suspended = 0;
4416 } else {
4417 pr_err("%s called for a chip which is not in suspended state\n",
4418 __func__);
4419 }
4420 mutex_unlock(&chip->lock);
4421 }
4422
4423 /**
4424 * nand_shutdown - [MTD Interface] Finish the current NAND operation and
4425 * prevent further operations
4426 * @mtd: MTD device structure
4427 */
nand_shutdown(struct mtd_info * mtd)4428 static void nand_shutdown(struct mtd_info *mtd)
4429 {
4430 nand_suspend(mtd);
4431 }
4432
4433 /**
4434 * nand_lock - [MTD Interface] Lock the NAND flash
4435 * @mtd: MTD device structure
4436 * @ofs: offset byte address
4437 * @len: number of bytes to lock (must be a multiple of block/page size)
4438 */
nand_lock(struct mtd_info * mtd,loff_t ofs,uint64_t len)4439 static int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
4440 {
4441 struct nand_chip *chip = mtd_to_nand(mtd);
4442
4443 if (!chip->ops.lock_area)
4444 return -ENOTSUPP;
4445
4446 return chip->ops.lock_area(chip, ofs, len);
4447 }
4448
4449 /**
4450 * nand_unlock - [MTD Interface] Unlock the NAND flash
4451 * @mtd: MTD device structure
4452 * @ofs: offset byte address
4453 * @len: number of bytes to unlock (must be a multiple of block/page size)
4454 */
nand_unlock(struct mtd_info * mtd,loff_t ofs,uint64_t len)4455 static int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
4456 {
4457 struct nand_chip *chip = mtd_to_nand(mtd);
4458
4459 if (!chip->ops.unlock_area)
4460 return -ENOTSUPP;
4461
4462 return chip->ops.unlock_area(chip, ofs, len);
4463 }
4464
4465 /* Set default functions */
nand_set_defaults(struct nand_chip * chip)4466 static void nand_set_defaults(struct nand_chip *chip)
4467 {
4468 /* If no controller is provided, use the dummy, legacy one. */
4469 if (!chip->controller) {
4470 chip->controller = &chip->legacy.dummy_controller;
4471 nand_controller_init(chip->controller);
4472 }
4473
4474 nand_legacy_set_defaults(chip);
4475
4476 if (!chip->buf_align)
4477 chip->buf_align = 1;
4478 }
4479
4480 /* Sanitize ONFI strings so we can safely print them */
sanitize_string(uint8_t * s,size_t len)4481 void sanitize_string(uint8_t *s, size_t len)
4482 {
4483 ssize_t i;
4484
4485 /* Null terminate */
4486 s[len - 1] = 0;
4487
4488 /* Remove non printable chars */
4489 for (i = 0; i < len - 1; i++) {
4490 if (s[i] < ' ' || s[i] > 127)
4491 s[i] = '?';
4492 }
4493
4494 /* Remove trailing spaces */
4495 strim(s);
4496 }
4497
4498 /*
4499 * nand_id_has_period - Check if an ID string has a given wraparound period
4500 * @id_data: the ID string
4501 * @arrlen: the length of the @id_data array
4502 * @period: the period of repitition
4503 *
4504 * Check if an ID string is repeated within a given sequence of bytes at
4505 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
4506 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
4507 * if the repetition has a period of @period; otherwise, returns zero.
4508 */
nand_id_has_period(u8 * id_data,int arrlen,int period)4509 static int nand_id_has_period(u8 *id_data, int arrlen, int period)
4510 {
4511 int i, j;
4512 for (i = 0; i < period; i++)
4513 for (j = i + period; j < arrlen; j += period)
4514 if (id_data[i] != id_data[j])
4515 return 0;
4516 return 1;
4517 }
4518
4519 /*
4520 * nand_id_len - Get the length of an ID string returned by CMD_READID
4521 * @id_data: the ID string
4522 * @arrlen: the length of the @id_data array
4523
4524 * Returns the length of the ID string, according to known wraparound/trailing
4525 * zero patterns. If no pattern exists, returns the length of the array.
4526 */
nand_id_len(u8 * id_data,int arrlen)4527 static int nand_id_len(u8 *id_data, int arrlen)
4528 {
4529 int last_nonzero, period;
4530
4531 /* Find last non-zero byte */
4532 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
4533 if (id_data[last_nonzero])
4534 break;
4535
4536 /* All zeros */
4537 if (last_nonzero < 0)
4538 return 0;
4539
4540 /* Calculate wraparound period */
4541 for (period = 1; period < arrlen; period++)
4542 if (nand_id_has_period(id_data, arrlen, period))
4543 break;
4544
4545 /* There's a repeated pattern */
4546 if (period < arrlen)
4547 return period;
4548
4549 /* There are trailing zeros */
4550 if (last_nonzero < arrlen - 1)
4551 return last_nonzero + 1;
4552
4553 /* No pattern detected */
4554 return arrlen;
4555 }
4556
4557 /* Extract the bits of per cell from the 3rd byte of the extended ID */
nand_get_bits_per_cell(u8 cellinfo)4558 static int nand_get_bits_per_cell(u8 cellinfo)
4559 {
4560 int bits;
4561
4562 bits = cellinfo & NAND_CI_CELLTYPE_MSK;
4563 bits >>= NAND_CI_CELLTYPE_SHIFT;
4564 return bits + 1;
4565 }
4566
4567 /*
4568 * Many new NAND share similar device ID codes, which represent the size of the
4569 * chip. The rest of the parameters must be decoded according to generic or
4570 * manufacturer-specific "extended ID" decoding patterns.
4571 */
nand_decode_ext_id(struct nand_chip * chip)4572 void nand_decode_ext_id(struct nand_chip *chip)
4573 {
4574 struct nand_memory_organization *memorg;
4575 struct mtd_info *mtd = nand_to_mtd(chip);
4576 int extid;
4577 u8 *id_data = chip->id.data;
4578
4579 memorg = nanddev_get_memorg(&chip->base);
4580
4581 /* The 3rd id byte holds MLC / multichip data */
4582 memorg->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
4583 /* The 4th id byte is the important one */
4584 extid = id_data[3];
4585
4586 /* Calc pagesize */
4587 memorg->pagesize = 1024 << (extid & 0x03);
4588 mtd->writesize = memorg->pagesize;
4589 extid >>= 2;
4590 /* Calc oobsize */
4591 memorg->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
4592 mtd->oobsize = memorg->oobsize;
4593 extid >>= 2;
4594 /* Calc blocksize. Blocksize is multiples of 64KiB */
4595 memorg->pages_per_eraseblock = ((64 * 1024) << (extid & 0x03)) /
4596 memorg->pagesize;
4597 mtd->erasesize = (64 * 1024) << (extid & 0x03);
4598 extid >>= 2;
4599 /* Get buswidth information */
4600 if (extid & 0x1)
4601 chip->options |= NAND_BUSWIDTH_16;
4602 }
4603 EXPORT_SYMBOL_GPL(nand_decode_ext_id);
4604
4605 /*
4606 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
4607 * decodes a matching ID table entry and assigns the MTD size parameters for
4608 * the chip.
4609 */
nand_decode_id(struct nand_chip * chip,struct nand_flash_dev * type)4610 static void nand_decode_id(struct nand_chip *chip, struct nand_flash_dev *type)
4611 {
4612 struct mtd_info *mtd = nand_to_mtd(chip);
4613 struct nand_memory_organization *memorg;
4614
4615 memorg = nanddev_get_memorg(&chip->base);
4616
4617 memorg->pages_per_eraseblock = type->erasesize / type->pagesize;
4618 mtd->erasesize = type->erasesize;
4619 memorg->pagesize = type->pagesize;
4620 mtd->writesize = memorg->pagesize;
4621 memorg->oobsize = memorg->pagesize / 32;
4622 mtd->oobsize = memorg->oobsize;
4623
4624 /* All legacy ID NAND are small-page, SLC */
4625 memorg->bits_per_cell = 1;
4626 }
4627
4628 /*
4629 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
4630 * heuristic patterns using various detected parameters (e.g., manufacturer,
4631 * page size, cell-type information).
4632 */
nand_decode_bbm_options(struct nand_chip * chip)4633 static void nand_decode_bbm_options(struct nand_chip *chip)
4634 {
4635 struct mtd_info *mtd = nand_to_mtd(chip);
4636
4637 /* Set the bad block position */
4638 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
4639 chip->badblockpos = NAND_BBM_POS_LARGE;
4640 else
4641 chip->badblockpos = NAND_BBM_POS_SMALL;
4642 }
4643
is_full_id_nand(struct nand_flash_dev * type)4644 static inline bool is_full_id_nand(struct nand_flash_dev *type)
4645 {
4646 return type->id_len;
4647 }
4648
find_full_id_nand(struct nand_chip * chip,struct nand_flash_dev * type)4649 static bool find_full_id_nand(struct nand_chip *chip,
4650 struct nand_flash_dev *type)
4651 {
4652 struct nand_device *base = &chip->base;
4653 struct nand_ecc_props requirements;
4654 struct mtd_info *mtd = nand_to_mtd(chip);
4655 struct nand_memory_organization *memorg;
4656 u8 *id_data = chip->id.data;
4657
4658 memorg = nanddev_get_memorg(&chip->base);
4659
4660 if (!strncmp(type->id, id_data, type->id_len)) {
4661 memorg->pagesize = type->pagesize;
4662 mtd->writesize = memorg->pagesize;
4663 memorg->pages_per_eraseblock = type->erasesize /
4664 type->pagesize;
4665 mtd->erasesize = type->erasesize;
4666 memorg->oobsize = type->oobsize;
4667 mtd->oobsize = memorg->oobsize;
4668
4669 memorg->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
4670 memorg->eraseblocks_per_lun =
4671 DIV_ROUND_DOWN_ULL((u64)type->chipsize << 20,
4672 memorg->pagesize *
4673 memorg->pages_per_eraseblock);
4674 chip->options |= type->options;
4675 requirements.strength = NAND_ECC_STRENGTH(type);
4676 requirements.step_size = NAND_ECC_STEP(type);
4677 nanddev_set_ecc_requirements(base, &requirements);
4678
4679 chip->parameters.model = kstrdup(type->name, GFP_KERNEL);
4680 if (!chip->parameters.model)
4681 return false;
4682
4683 return true;
4684 }
4685 return false;
4686 }
4687
4688 /*
4689 * Manufacturer detection. Only used when the NAND is not ONFI or JEDEC
4690 * compliant and does not have a full-id or legacy-id entry in the nand_ids
4691 * table.
4692 */
nand_manufacturer_detect(struct nand_chip * chip)4693 static void nand_manufacturer_detect(struct nand_chip *chip)
4694 {
4695 /*
4696 * Try manufacturer detection if available and use
4697 * nand_decode_ext_id() otherwise.
4698 */
4699 if (chip->manufacturer.desc && chip->manufacturer.desc->ops &&
4700 chip->manufacturer.desc->ops->detect) {
4701 struct nand_memory_organization *memorg;
4702
4703 memorg = nanddev_get_memorg(&chip->base);
4704
4705 /* The 3rd id byte holds MLC / multichip data */
4706 memorg->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]);
4707 chip->manufacturer.desc->ops->detect(chip);
4708 } else {
4709 nand_decode_ext_id(chip);
4710 }
4711 }
4712
4713 /*
4714 * Manufacturer initialization. This function is called for all NANDs including
4715 * ONFI and JEDEC compliant ones.
4716 * Manufacturer drivers should put all their specific initialization code in
4717 * their ->init() hook.
4718 */
nand_manufacturer_init(struct nand_chip * chip)4719 static int nand_manufacturer_init(struct nand_chip *chip)
4720 {
4721 if (!chip->manufacturer.desc || !chip->manufacturer.desc->ops ||
4722 !chip->manufacturer.desc->ops->init)
4723 return 0;
4724
4725 return chip->manufacturer.desc->ops->init(chip);
4726 }
4727
4728 /*
4729 * Manufacturer cleanup. This function is called for all NANDs including
4730 * ONFI and JEDEC compliant ones.
4731 * Manufacturer drivers should put all their specific cleanup code in their
4732 * ->cleanup() hook.
4733 */
nand_manufacturer_cleanup(struct nand_chip * chip)4734 static void nand_manufacturer_cleanup(struct nand_chip *chip)
4735 {
4736 /* Release manufacturer private data */
4737 if (chip->manufacturer.desc && chip->manufacturer.desc->ops &&
4738 chip->manufacturer.desc->ops->cleanup)
4739 chip->manufacturer.desc->ops->cleanup(chip);
4740 }
4741
4742 static const char *
nand_manufacturer_name(const struct nand_manufacturer_desc * manufacturer_desc)4743 nand_manufacturer_name(const struct nand_manufacturer_desc *manufacturer_desc)
4744 {
4745 return manufacturer_desc ? manufacturer_desc->name : "Unknown";
4746 }
4747
4748 /*
4749 * Get the flash and manufacturer id and lookup if the type is supported.
4750 */
nand_detect(struct nand_chip * chip,struct nand_flash_dev * type)4751 static int nand_detect(struct nand_chip *chip, struct nand_flash_dev *type)
4752 {
4753 const struct nand_manufacturer_desc *manufacturer_desc;
4754 struct mtd_info *mtd = nand_to_mtd(chip);
4755 struct nand_memory_organization *memorg;
4756 int busw, ret;
4757 u8 *id_data = chip->id.data;
4758 u8 maf_id, dev_id;
4759 u64 targetsize;
4760
4761 /*
4762 * Let's start by initializing memorg fields that might be left
4763 * unassigned by the ID-based detection logic.
4764 */
4765 memorg = nanddev_get_memorg(&chip->base);
4766 memorg->planes_per_lun = 1;
4767 memorg->luns_per_target = 1;
4768
4769 /*
4770 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
4771 * after power-up.
4772 */
4773 ret = nand_reset(chip, 0);
4774 if (ret)
4775 return ret;
4776
4777 /* Select the device */
4778 nand_select_target(chip, 0);
4779
4780 /* Send the command for reading device ID */
4781 ret = nand_readid_op(chip, 0, id_data, 2);
4782 if (ret)
4783 return ret;
4784
4785 /* Read manufacturer and device IDs */
4786 maf_id = id_data[0];
4787 dev_id = id_data[1];
4788
4789 /*
4790 * Try again to make sure, as some systems the bus-hold or other
4791 * interface concerns can cause random data which looks like a
4792 * possibly credible NAND flash to appear. If the two results do
4793 * not match, ignore the device completely.
4794 */
4795
4796 /* Read entire ID string */
4797 ret = nand_readid_op(chip, 0, id_data, sizeof(chip->id.data));
4798 if (ret)
4799 return ret;
4800
4801 if (id_data[0] != maf_id || id_data[1] != dev_id) {
4802 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
4803 maf_id, dev_id, id_data[0], id_data[1]);
4804 return -ENODEV;
4805 }
4806
4807 chip->id.len = nand_id_len(id_data, ARRAY_SIZE(chip->id.data));
4808
4809 /* Try to identify manufacturer */
4810 manufacturer_desc = nand_get_manufacturer_desc(maf_id);
4811 chip->manufacturer.desc = manufacturer_desc;
4812
4813 if (!type)
4814 type = nand_flash_ids;
4815
4816 /*
4817 * Save the NAND_BUSWIDTH_16 flag before letting auto-detection logic
4818 * override it.
4819 * This is required to make sure initial NAND bus width set by the
4820 * NAND controller driver is coherent with the real NAND bus width
4821 * (extracted by auto-detection code).
4822 */
4823 busw = chip->options & NAND_BUSWIDTH_16;
4824
4825 /*
4826 * The flag is only set (never cleared), reset it to its default value
4827 * before starting auto-detection.
4828 */
4829 chip->options &= ~NAND_BUSWIDTH_16;
4830
4831 for (; type->name != NULL; type++) {
4832 if (is_full_id_nand(type)) {
4833 if (find_full_id_nand(chip, type))
4834 goto ident_done;
4835 } else if (dev_id == type->dev_id) {
4836 break;
4837 }
4838 }
4839
4840 if (!type->name || !type->pagesize) {
4841 /* Check if the chip is ONFI compliant */
4842 ret = nand_onfi_detect(chip);
4843 if (ret < 0)
4844 return ret;
4845 else if (ret)
4846 goto ident_done;
4847
4848 /* Check if the chip is JEDEC compliant */
4849 ret = nand_jedec_detect(chip);
4850 if (ret < 0)
4851 return ret;
4852 else if (ret)
4853 goto ident_done;
4854 }
4855
4856 if (!type->name)
4857 return -ENODEV;
4858
4859 chip->parameters.model = kstrdup(type->name, GFP_KERNEL);
4860 if (!chip->parameters.model)
4861 return -ENOMEM;
4862
4863 if (!type->pagesize)
4864 nand_manufacturer_detect(chip);
4865 else
4866 nand_decode_id(chip, type);
4867
4868 /* Get chip options */
4869 chip->options |= type->options;
4870
4871 memorg->eraseblocks_per_lun =
4872 DIV_ROUND_DOWN_ULL((u64)type->chipsize << 20,
4873 memorg->pagesize *
4874 memorg->pages_per_eraseblock);
4875
4876 ident_done:
4877 if (!mtd->name)
4878 mtd->name = chip->parameters.model;
4879
4880 if (chip->options & NAND_BUSWIDTH_AUTO) {
4881 WARN_ON(busw & NAND_BUSWIDTH_16);
4882 nand_set_defaults(chip);
4883 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
4884 /*
4885 * Check, if buswidth is correct. Hardware drivers should set
4886 * chip correct!
4887 */
4888 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
4889 maf_id, dev_id);
4890 pr_info("%s %s\n", nand_manufacturer_name(manufacturer_desc),
4891 mtd->name);
4892 pr_warn("bus width %d instead of %d bits\n", busw ? 16 : 8,
4893 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8);
4894 ret = -EINVAL;
4895
4896 goto free_detect_allocation;
4897 }
4898
4899 nand_decode_bbm_options(chip);
4900
4901 /* Calculate the address shift from the page size */
4902 chip->page_shift = ffs(mtd->writesize) - 1;
4903 /* Convert chipsize to number of pages per chip -1 */
4904 targetsize = nanddev_target_size(&chip->base);
4905 chip->pagemask = (targetsize >> chip->page_shift) - 1;
4906
4907 chip->bbt_erase_shift = chip->phys_erase_shift =
4908 ffs(mtd->erasesize) - 1;
4909 if (targetsize & 0xffffffff)
4910 chip->chip_shift = ffs((unsigned)targetsize) - 1;
4911 else {
4912 chip->chip_shift = ffs((unsigned)(targetsize >> 32));
4913 chip->chip_shift += 32 - 1;
4914 }
4915
4916 if (chip->chip_shift - chip->page_shift > 16)
4917 chip->options |= NAND_ROW_ADDR_3;
4918
4919 chip->badblockbits = 8;
4920
4921 nand_legacy_adjust_cmdfunc(chip);
4922
4923 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
4924 maf_id, dev_id);
4925 pr_info("%s %s\n", nand_manufacturer_name(manufacturer_desc),
4926 chip->parameters.model);
4927 pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",
4928 (int)(targetsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
4929 mtd->erasesize >> 10, mtd->writesize, mtd->oobsize);
4930 return 0;
4931
4932 free_detect_allocation:
4933 kfree(chip->parameters.model);
4934
4935 return ret;
4936 }
4937
4938 static enum nand_ecc_engine_type
of_get_rawnand_ecc_engine_type_legacy(struct device_node * np)4939 of_get_rawnand_ecc_engine_type_legacy(struct device_node *np)
4940 {
4941 enum nand_ecc_legacy_mode {
4942 NAND_ECC_INVALID,
4943 NAND_ECC_NONE,
4944 NAND_ECC_SOFT,
4945 NAND_ECC_SOFT_BCH,
4946 NAND_ECC_HW,
4947 NAND_ECC_HW_SYNDROME,
4948 NAND_ECC_ON_DIE,
4949 };
4950 const char * const nand_ecc_legacy_modes[] = {
4951 [NAND_ECC_NONE] = "none",
4952 [NAND_ECC_SOFT] = "soft",
4953 [NAND_ECC_SOFT_BCH] = "soft_bch",
4954 [NAND_ECC_HW] = "hw",
4955 [NAND_ECC_HW_SYNDROME] = "hw_syndrome",
4956 [NAND_ECC_ON_DIE] = "on-die",
4957 };
4958 enum nand_ecc_legacy_mode eng_type;
4959 const char *pm;
4960 int err;
4961
4962 err = of_property_read_string(np, "nand-ecc-mode", &pm);
4963 if (err)
4964 return NAND_ECC_ENGINE_TYPE_INVALID;
4965
4966 for (eng_type = NAND_ECC_NONE;
4967 eng_type < ARRAY_SIZE(nand_ecc_legacy_modes); eng_type++) {
4968 if (!strcasecmp(pm, nand_ecc_legacy_modes[eng_type])) {
4969 switch (eng_type) {
4970 case NAND_ECC_NONE:
4971 return NAND_ECC_ENGINE_TYPE_NONE;
4972 case NAND_ECC_SOFT:
4973 case NAND_ECC_SOFT_BCH:
4974 return NAND_ECC_ENGINE_TYPE_SOFT;
4975 case NAND_ECC_HW:
4976 case NAND_ECC_HW_SYNDROME:
4977 return NAND_ECC_ENGINE_TYPE_ON_HOST;
4978 case NAND_ECC_ON_DIE:
4979 return NAND_ECC_ENGINE_TYPE_ON_DIE;
4980 default:
4981 break;
4982 }
4983 }
4984 }
4985
4986 return NAND_ECC_ENGINE_TYPE_INVALID;
4987 }
4988
4989 static enum nand_ecc_placement
of_get_rawnand_ecc_placement_legacy(struct device_node * np)4990 of_get_rawnand_ecc_placement_legacy(struct device_node *np)
4991 {
4992 const char *pm;
4993 int err;
4994
4995 err = of_property_read_string(np, "nand-ecc-mode", &pm);
4996 if (!err) {
4997 if (!strcasecmp(pm, "hw_syndrome"))
4998 return NAND_ECC_PLACEMENT_INTERLEAVED;
4999 }
5000
5001 return NAND_ECC_PLACEMENT_UNKNOWN;
5002 }
5003
of_get_rawnand_ecc_algo_legacy(struct device_node * np)5004 static enum nand_ecc_algo of_get_rawnand_ecc_algo_legacy(struct device_node *np)
5005 {
5006 const char *pm;
5007 int err;
5008
5009 err = of_property_read_string(np, "nand-ecc-mode", &pm);
5010 if (!err) {
5011 if (!strcasecmp(pm, "soft"))
5012 return NAND_ECC_ALGO_HAMMING;
5013 else if (!strcasecmp(pm, "soft_bch"))
5014 return NAND_ECC_ALGO_BCH;
5015 }
5016
5017 return NAND_ECC_ALGO_UNKNOWN;
5018 }
5019
of_get_nand_ecc_legacy_user_config(struct nand_chip * chip)5020 static void of_get_nand_ecc_legacy_user_config(struct nand_chip *chip)
5021 {
5022 struct device_node *dn = nand_get_flash_node(chip);
5023 struct nand_ecc_props *user_conf = &chip->base.ecc.user_conf;
5024
5025 if (user_conf->engine_type == NAND_ECC_ENGINE_TYPE_INVALID)
5026 user_conf->engine_type = of_get_rawnand_ecc_engine_type_legacy(dn);
5027
5028 if (user_conf->algo == NAND_ECC_ALGO_UNKNOWN)
5029 user_conf->algo = of_get_rawnand_ecc_algo_legacy(dn);
5030
5031 if (user_conf->placement == NAND_ECC_PLACEMENT_UNKNOWN)
5032 user_conf->placement = of_get_rawnand_ecc_placement_legacy(dn);
5033 }
5034
of_get_nand_bus_width(struct device_node * np)5035 static int of_get_nand_bus_width(struct device_node *np)
5036 {
5037 u32 val;
5038
5039 if (of_property_read_u32(np, "nand-bus-width", &val))
5040 return 8;
5041
5042 switch (val) {
5043 case 8:
5044 case 16:
5045 return val;
5046 default:
5047 return -EIO;
5048 }
5049 }
5050
of_get_nand_on_flash_bbt(struct device_node * np)5051 static bool of_get_nand_on_flash_bbt(struct device_node *np)
5052 {
5053 return of_property_read_bool(np, "nand-on-flash-bbt");
5054 }
5055
of_get_nand_secure_regions(struct nand_chip * chip)5056 static int of_get_nand_secure_regions(struct nand_chip *chip)
5057 {
5058 struct device_node *dn = nand_get_flash_node(chip);
5059 int nr_elem, i, j;
5060
5061 nr_elem = of_property_count_elems_of_size(dn, "secure-regions", sizeof(u64));
5062 if (!nr_elem)
5063 return 0;
5064
5065 chip->nr_secure_regions = nr_elem / 2;
5066 chip->secure_regions = kcalloc(chip->nr_secure_regions, sizeof(*chip->secure_regions),
5067 GFP_KERNEL);
5068 if (!chip->secure_regions)
5069 return -ENOMEM;
5070
5071 for (i = 0, j = 0; i < chip->nr_secure_regions; i++, j += 2) {
5072 of_property_read_u64_index(dn, "secure-regions", j,
5073 &chip->secure_regions[i].offset);
5074 of_property_read_u64_index(dn, "secure-regions", j + 1,
5075 &chip->secure_regions[i].size);
5076 }
5077
5078 return 0;
5079 }
5080
rawnand_dt_init(struct nand_chip * chip)5081 static int rawnand_dt_init(struct nand_chip *chip)
5082 {
5083 struct nand_device *nand = mtd_to_nanddev(nand_to_mtd(chip));
5084 struct device_node *dn = nand_get_flash_node(chip);
5085
5086 if (!dn)
5087 return 0;
5088
5089 if (of_get_nand_bus_width(dn) == 16)
5090 chip->options |= NAND_BUSWIDTH_16;
5091
5092 if (of_property_read_bool(dn, "nand-is-boot-medium"))
5093 chip->options |= NAND_IS_BOOT_MEDIUM;
5094
5095 if (of_get_nand_on_flash_bbt(dn))
5096 chip->bbt_options |= NAND_BBT_USE_FLASH;
5097
5098 of_get_nand_ecc_user_config(nand);
5099 of_get_nand_ecc_legacy_user_config(chip);
5100
5101 /*
5102 * If neither the user nor the NAND controller have requested a specific
5103 * ECC engine type, we will default to NAND_ECC_ENGINE_TYPE_ON_HOST.
5104 */
5105 nand->ecc.defaults.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
5106
5107 /*
5108 * Use the user requested engine type, unless there is none, in this
5109 * case default to the NAND controller choice, otherwise fallback to
5110 * the raw NAND default one.
5111 */
5112 if (nand->ecc.user_conf.engine_type != NAND_ECC_ENGINE_TYPE_INVALID)
5113 chip->ecc.engine_type = nand->ecc.user_conf.engine_type;
5114 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_INVALID)
5115 chip->ecc.engine_type = nand->ecc.defaults.engine_type;
5116
5117 chip->ecc.placement = nand->ecc.user_conf.placement;
5118 chip->ecc.algo = nand->ecc.user_conf.algo;
5119 chip->ecc.strength = nand->ecc.user_conf.strength;
5120 chip->ecc.size = nand->ecc.user_conf.step_size;
5121
5122 return 0;
5123 }
5124
5125 /**
5126 * nand_scan_ident - Scan for the NAND device
5127 * @chip: NAND chip object
5128 * @maxchips: number of chips to scan for
5129 * @table: alternative NAND ID table
5130 *
5131 * This is the first phase of the normal nand_scan() function. It reads the
5132 * flash ID and sets up MTD fields accordingly.
5133 *
5134 * This helper used to be called directly from controller drivers that needed
5135 * to tweak some ECC-related parameters before nand_scan_tail(). This separation
5136 * prevented dynamic allocations during this phase which was unconvenient and
5137 * as been banned for the benefit of the ->init_ecc()/cleanup_ecc() hooks.
5138 */
nand_scan_ident(struct nand_chip * chip,unsigned int maxchips,struct nand_flash_dev * table)5139 static int nand_scan_ident(struct nand_chip *chip, unsigned int maxchips,
5140 struct nand_flash_dev *table)
5141 {
5142 struct mtd_info *mtd = nand_to_mtd(chip);
5143 struct nand_memory_organization *memorg;
5144 int nand_maf_id, nand_dev_id;
5145 unsigned int i;
5146 int ret;
5147
5148 memorg = nanddev_get_memorg(&chip->base);
5149
5150 /* Assume all dies are deselected when we enter nand_scan_ident(). */
5151 chip->cur_cs = -1;
5152
5153 mutex_init(&chip->lock);
5154
5155 /* Enforce the right timings for reset/detection */
5156 chip->current_interface_config = nand_get_reset_interface_config();
5157
5158 ret = rawnand_dt_init(chip);
5159 if (ret)
5160 return ret;
5161
5162 if (!mtd->name && mtd->dev.parent)
5163 mtd->name = dev_name(mtd->dev.parent);
5164
5165 /* Set the default functions */
5166 nand_set_defaults(chip);
5167
5168 ret = nand_legacy_check_hooks(chip);
5169 if (ret)
5170 return ret;
5171
5172 memorg->ntargets = maxchips;
5173
5174 /* Read the flash type */
5175 ret = nand_detect(chip, table);
5176 if (ret) {
5177 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
5178 pr_warn("No NAND device found\n");
5179 nand_deselect_target(chip);
5180 return ret;
5181 }
5182
5183 nand_maf_id = chip->id.data[0];
5184 nand_dev_id = chip->id.data[1];
5185
5186 nand_deselect_target(chip);
5187
5188 /* Check for a chip array */
5189 for (i = 1; i < maxchips; i++) {
5190 u8 id[2];
5191
5192 /* See comment in nand_get_flash_type for reset */
5193 ret = nand_reset(chip, i);
5194 if (ret)
5195 break;
5196
5197 nand_select_target(chip, i);
5198 /* Send the command for reading device ID */
5199 ret = nand_readid_op(chip, 0, id, sizeof(id));
5200 if (ret)
5201 break;
5202 /* Read manufacturer and device IDs */
5203 if (nand_maf_id != id[0] || nand_dev_id != id[1]) {
5204 nand_deselect_target(chip);
5205 break;
5206 }
5207 nand_deselect_target(chip);
5208 }
5209 if (i > 1)
5210 pr_info("%d chips detected\n", i);
5211
5212 /* Store the number of chips and calc total size for mtd */
5213 memorg->ntargets = i;
5214 mtd->size = i * nanddev_target_size(&chip->base);
5215
5216 return 0;
5217 }
5218
nand_scan_ident_cleanup(struct nand_chip * chip)5219 static void nand_scan_ident_cleanup(struct nand_chip *chip)
5220 {
5221 kfree(chip->parameters.model);
5222 kfree(chip->parameters.onfi);
5223 }
5224
rawnand_sw_hamming_init(struct nand_chip * chip)5225 int rawnand_sw_hamming_init(struct nand_chip *chip)
5226 {
5227 struct nand_ecc_sw_hamming_conf *engine_conf;
5228 struct nand_device *base = &chip->base;
5229 int ret;
5230
5231 base->ecc.user_conf.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
5232 base->ecc.user_conf.algo = NAND_ECC_ALGO_HAMMING;
5233 base->ecc.user_conf.strength = chip->ecc.strength;
5234 base->ecc.user_conf.step_size = chip->ecc.size;
5235
5236 ret = nand_ecc_sw_hamming_init_ctx(base);
5237 if (ret)
5238 return ret;
5239
5240 engine_conf = base->ecc.ctx.priv;
5241
5242 if (chip->ecc.options & NAND_ECC_SOFT_HAMMING_SM_ORDER)
5243 engine_conf->sm_order = true;
5244
5245 chip->ecc.size = base->ecc.ctx.conf.step_size;
5246 chip->ecc.strength = base->ecc.ctx.conf.strength;
5247 chip->ecc.total = base->ecc.ctx.total;
5248 chip->ecc.steps = nanddev_get_ecc_nsteps(base);
5249 chip->ecc.bytes = base->ecc.ctx.total / nanddev_get_ecc_nsteps(base);
5250
5251 return 0;
5252 }
5253 EXPORT_SYMBOL(rawnand_sw_hamming_init);
5254
rawnand_sw_hamming_calculate(struct nand_chip * chip,const unsigned char * buf,unsigned char * code)5255 int rawnand_sw_hamming_calculate(struct nand_chip *chip,
5256 const unsigned char *buf,
5257 unsigned char *code)
5258 {
5259 struct nand_device *base = &chip->base;
5260
5261 return nand_ecc_sw_hamming_calculate(base, buf, code);
5262 }
5263 EXPORT_SYMBOL(rawnand_sw_hamming_calculate);
5264
rawnand_sw_hamming_correct(struct nand_chip * chip,unsigned char * buf,unsigned char * read_ecc,unsigned char * calc_ecc)5265 int rawnand_sw_hamming_correct(struct nand_chip *chip,
5266 unsigned char *buf,
5267 unsigned char *read_ecc,
5268 unsigned char *calc_ecc)
5269 {
5270 struct nand_device *base = &chip->base;
5271
5272 return nand_ecc_sw_hamming_correct(base, buf, read_ecc, calc_ecc);
5273 }
5274 EXPORT_SYMBOL(rawnand_sw_hamming_correct);
5275
rawnand_sw_hamming_cleanup(struct nand_chip * chip)5276 void rawnand_sw_hamming_cleanup(struct nand_chip *chip)
5277 {
5278 struct nand_device *base = &chip->base;
5279
5280 nand_ecc_sw_hamming_cleanup_ctx(base);
5281 }
5282 EXPORT_SYMBOL(rawnand_sw_hamming_cleanup);
5283
rawnand_sw_bch_init(struct nand_chip * chip)5284 int rawnand_sw_bch_init(struct nand_chip *chip)
5285 {
5286 struct nand_device *base = &chip->base;
5287 const struct nand_ecc_props *ecc_conf = nanddev_get_ecc_conf(base);
5288 int ret;
5289
5290 base->ecc.user_conf.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
5291 base->ecc.user_conf.algo = NAND_ECC_ALGO_BCH;
5292 base->ecc.user_conf.step_size = chip->ecc.size;
5293 base->ecc.user_conf.strength = chip->ecc.strength;
5294
5295 ret = nand_ecc_sw_bch_init_ctx(base);
5296 if (ret)
5297 return ret;
5298
5299 chip->ecc.size = ecc_conf->step_size;
5300 chip->ecc.strength = ecc_conf->strength;
5301 chip->ecc.total = base->ecc.ctx.total;
5302 chip->ecc.steps = nanddev_get_ecc_nsteps(base);
5303 chip->ecc.bytes = base->ecc.ctx.total / nanddev_get_ecc_nsteps(base);
5304
5305 return 0;
5306 }
5307 EXPORT_SYMBOL(rawnand_sw_bch_init);
5308
rawnand_sw_bch_calculate(struct nand_chip * chip,const unsigned char * buf,unsigned char * code)5309 static int rawnand_sw_bch_calculate(struct nand_chip *chip,
5310 const unsigned char *buf,
5311 unsigned char *code)
5312 {
5313 struct nand_device *base = &chip->base;
5314
5315 return nand_ecc_sw_bch_calculate(base, buf, code);
5316 }
5317
rawnand_sw_bch_correct(struct nand_chip * chip,unsigned char * buf,unsigned char * read_ecc,unsigned char * calc_ecc)5318 int rawnand_sw_bch_correct(struct nand_chip *chip, unsigned char *buf,
5319 unsigned char *read_ecc, unsigned char *calc_ecc)
5320 {
5321 struct nand_device *base = &chip->base;
5322
5323 return nand_ecc_sw_bch_correct(base, buf, read_ecc, calc_ecc);
5324 }
5325 EXPORT_SYMBOL(rawnand_sw_bch_correct);
5326
rawnand_sw_bch_cleanup(struct nand_chip * chip)5327 void rawnand_sw_bch_cleanup(struct nand_chip *chip)
5328 {
5329 struct nand_device *base = &chip->base;
5330
5331 nand_ecc_sw_bch_cleanup_ctx(base);
5332 }
5333 EXPORT_SYMBOL(rawnand_sw_bch_cleanup);
5334
nand_set_ecc_on_host_ops(struct nand_chip * chip)5335 static int nand_set_ecc_on_host_ops(struct nand_chip *chip)
5336 {
5337 struct nand_ecc_ctrl *ecc = &chip->ecc;
5338
5339 switch (ecc->placement) {
5340 case NAND_ECC_PLACEMENT_UNKNOWN:
5341 case NAND_ECC_PLACEMENT_OOB:
5342 /* Use standard hwecc read page function? */
5343 if (!ecc->read_page)
5344 ecc->read_page = nand_read_page_hwecc;
5345 if (!ecc->write_page)
5346 ecc->write_page = nand_write_page_hwecc;
5347 if (!ecc->read_page_raw)
5348 ecc->read_page_raw = nand_read_page_raw;
5349 if (!ecc->write_page_raw)
5350 ecc->write_page_raw = nand_write_page_raw;
5351 if (!ecc->read_oob)
5352 ecc->read_oob = nand_read_oob_std;
5353 if (!ecc->write_oob)
5354 ecc->write_oob = nand_write_oob_std;
5355 if (!ecc->read_subpage)
5356 ecc->read_subpage = nand_read_subpage;
5357 if (!ecc->write_subpage && ecc->hwctl && ecc->calculate)
5358 ecc->write_subpage = nand_write_subpage_hwecc;
5359 fallthrough;
5360
5361 case NAND_ECC_PLACEMENT_INTERLEAVED:
5362 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
5363 (!ecc->read_page ||
5364 ecc->read_page == nand_read_page_hwecc ||
5365 !ecc->write_page ||
5366 ecc->write_page == nand_write_page_hwecc)) {
5367 WARN(1, "No ECC functions supplied; hardware ECC not possible\n");
5368 return -EINVAL;
5369 }
5370 /* Use standard syndrome read/write page function? */
5371 if (!ecc->read_page)
5372 ecc->read_page = nand_read_page_syndrome;
5373 if (!ecc->write_page)
5374 ecc->write_page = nand_write_page_syndrome;
5375 if (!ecc->read_page_raw)
5376 ecc->read_page_raw = nand_read_page_raw_syndrome;
5377 if (!ecc->write_page_raw)
5378 ecc->write_page_raw = nand_write_page_raw_syndrome;
5379 if (!ecc->read_oob)
5380 ecc->read_oob = nand_read_oob_syndrome;
5381 if (!ecc->write_oob)
5382 ecc->write_oob = nand_write_oob_syndrome;
5383 break;
5384
5385 default:
5386 pr_warn("Invalid NAND_ECC_PLACEMENT %d\n",
5387 ecc->placement);
5388 return -EINVAL;
5389 }
5390
5391 return 0;
5392 }
5393
nand_set_ecc_soft_ops(struct nand_chip * chip)5394 static int nand_set_ecc_soft_ops(struct nand_chip *chip)
5395 {
5396 struct mtd_info *mtd = nand_to_mtd(chip);
5397 struct nand_device *nanddev = mtd_to_nanddev(mtd);
5398 struct nand_ecc_ctrl *ecc = &chip->ecc;
5399 int ret;
5400
5401 if (WARN_ON(ecc->engine_type != NAND_ECC_ENGINE_TYPE_SOFT))
5402 return -EINVAL;
5403
5404 switch (ecc->algo) {
5405 case NAND_ECC_ALGO_HAMMING:
5406 ecc->calculate = rawnand_sw_hamming_calculate;
5407 ecc->correct = rawnand_sw_hamming_correct;
5408 ecc->read_page = nand_read_page_swecc;
5409 ecc->read_subpage = nand_read_subpage;
5410 ecc->write_page = nand_write_page_swecc;
5411 if (!ecc->read_page_raw)
5412 ecc->read_page_raw = nand_read_page_raw;
5413 if (!ecc->write_page_raw)
5414 ecc->write_page_raw = nand_write_page_raw;
5415 ecc->read_oob = nand_read_oob_std;
5416 ecc->write_oob = nand_write_oob_std;
5417 if (!ecc->size)
5418 ecc->size = 256;
5419 ecc->bytes = 3;
5420 ecc->strength = 1;
5421
5422 if (IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC))
5423 ecc->options |= NAND_ECC_SOFT_HAMMING_SM_ORDER;
5424
5425 ret = rawnand_sw_hamming_init(chip);
5426 if (ret) {
5427 WARN(1, "Hamming ECC initialization failed!\n");
5428 return ret;
5429 }
5430
5431 return 0;
5432 case NAND_ECC_ALGO_BCH:
5433 if (!IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_BCH)) {
5434 WARN(1, "CONFIG_MTD_NAND_ECC_SW_BCH not enabled\n");
5435 return -EINVAL;
5436 }
5437 ecc->calculate = rawnand_sw_bch_calculate;
5438 ecc->correct = rawnand_sw_bch_correct;
5439 ecc->read_page = nand_read_page_swecc;
5440 ecc->read_subpage = nand_read_subpage;
5441 ecc->write_page = nand_write_page_swecc;
5442 if (!ecc->read_page_raw)
5443 ecc->read_page_raw = nand_read_page_raw;
5444 if (!ecc->write_page_raw)
5445 ecc->write_page_raw = nand_write_page_raw;
5446 ecc->read_oob = nand_read_oob_std;
5447 ecc->write_oob = nand_write_oob_std;
5448
5449 /*
5450 * We can only maximize ECC config when the default layout is
5451 * used, otherwise we don't know how many bytes can really be
5452 * used.
5453 */
5454 if (nanddev->ecc.user_conf.flags & NAND_ECC_MAXIMIZE_STRENGTH &&
5455 mtd->ooblayout != nand_get_large_page_ooblayout())
5456 nanddev->ecc.user_conf.flags &= ~NAND_ECC_MAXIMIZE_STRENGTH;
5457
5458 ret = rawnand_sw_bch_init(chip);
5459 if (ret) {
5460 WARN(1, "BCH ECC initialization failed!\n");
5461 return ret;
5462 }
5463
5464 return 0;
5465 default:
5466 WARN(1, "Unsupported ECC algorithm!\n");
5467 return -EINVAL;
5468 }
5469 }
5470
5471 /**
5472 * nand_check_ecc_caps - check the sanity of preset ECC settings
5473 * @chip: nand chip info structure
5474 * @caps: ECC caps info structure
5475 * @oobavail: OOB size that the ECC engine can use
5476 *
5477 * When ECC step size and strength are already set, check if they are supported
5478 * by the controller and the calculated ECC bytes fit within the chip's OOB.
5479 * On success, the calculated ECC bytes is set.
5480 */
5481 static int
nand_check_ecc_caps(struct nand_chip * chip,const struct nand_ecc_caps * caps,int oobavail)5482 nand_check_ecc_caps(struct nand_chip *chip,
5483 const struct nand_ecc_caps *caps, int oobavail)
5484 {
5485 struct mtd_info *mtd = nand_to_mtd(chip);
5486 const struct nand_ecc_step_info *stepinfo;
5487 int preset_step = chip->ecc.size;
5488 int preset_strength = chip->ecc.strength;
5489 int ecc_bytes, nsteps = mtd->writesize / preset_step;
5490 int i, j;
5491
5492 for (i = 0; i < caps->nstepinfos; i++) {
5493 stepinfo = &caps->stepinfos[i];
5494
5495 if (stepinfo->stepsize != preset_step)
5496 continue;
5497
5498 for (j = 0; j < stepinfo->nstrengths; j++) {
5499 if (stepinfo->strengths[j] != preset_strength)
5500 continue;
5501
5502 ecc_bytes = caps->calc_ecc_bytes(preset_step,
5503 preset_strength);
5504 if (WARN_ON_ONCE(ecc_bytes < 0))
5505 return ecc_bytes;
5506
5507 if (ecc_bytes * nsteps > oobavail) {
5508 pr_err("ECC (step, strength) = (%d, %d) does not fit in OOB",
5509 preset_step, preset_strength);
5510 return -ENOSPC;
5511 }
5512
5513 chip->ecc.bytes = ecc_bytes;
5514
5515 return 0;
5516 }
5517 }
5518
5519 pr_err("ECC (step, strength) = (%d, %d) not supported on this controller",
5520 preset_step, preset_strength);
5521
5522 return -ENOTSUPP;
5523 }
5524
5525 /**
5526 * nand_match_ecc_req - meet the chip's requirement with least ECC bytes
5527 * @chip: nand chip info structure
5528 * @caps: ECC engine caps info structure
5529 * @oobavail: OOB size that the ECC engine can use
5530 *
5531 * If a chip's ECC requirement is provided, try to meet it with the least
5532 * number of ECC bytes (i.e. with the largest number of OOB-free bytes).
5533 * On success, the chosen ECC settings are set.
5534 */
5535 static int
nand_match_ecc_req(struct nand_chip * chip,const struct nand_ecc_caps * caps,int oobavail)5536 nand_match_ecc_req(struct nand_chip *chip,
5537 const struct nand_ecc_caps *caps, int oobavail)
5538 {
5539 const struct nand_ecc_props *requirements =
5540 nanddev_get_ecc_requirements(&chip->base);
5541 struct mtd_info *mtd = nand_to_mtd(chip);
5542 const struct nand_ecc_step_info *stepinfo;
5543 int req_step = requirements->step_size;
5544 int req_strength = requirements->strength;
5545 int req_corr, step_size, strength, nsteps, ecc_bytes, ecc_bytes_total;
5546 int best_step, best_strength, best_ecc_bytes;
5547 int best_ecc_bytes_total = INT_MAX;
5548 int i, j;
5549
5550 /* No information provided by the NAND chip */
5551 if (!req_step || !req_strength)
5552 return -ENOTSUPP;
5553
5554 /* number of correctable bits the chip requires in a page */
5555 req_corr = mtd->writesize / req_step * req_strength;
5556
5557 for (i = 0; i < caps->nstepinfos; i++) {
5558 stepinfo = &caps->stepinfos[i];
5559 step_size = stepinfo->stepsize;
5560
5561 for (j = 0; j < stepinfo->nstrengths; j++) {
5562 strength = stepinfo->strengths[j];
5563
5564 /*
5565 * If both step size and strength are smaller than the
5566 * chip's requirement, it is not easy to compare the
5567 * resulted reliability.
5568 */
5569 if (step_size < req_step && strength < req_strength)
5570 continue;
5571
5572 if (mtd->writesize % step_size)
5573 continue;
5574
5575 nsteps = mtd->writesize / step_size;
5576
5577 ecc_bytes = caps->calc_ecc_bytes(step_size, strength);
5578 if (WARN_ON_ONCE(ecc_bytes < 0))
5579 continue;
5580 ecc_bytes_total = ecc_bytes * nsteps;
5581
5582 if (ecc_bytes_total > oobavail ||
5583 strength * nsteps < req_corr)
5584 continue;
5585
5586 /*
5587 * We assume the best is to meet the chip's requrement
5588 * with the least number of ECC bytes.
5589 */
5590 if (ecc_bytes_total < best_ecc_bytes_total) {
5591 best_ecc_bytes_total = ecc_bytes_total;
5592 best_step = step_size;
5593 best_strength = strength;
5594 best_ecc_bytes = ecc_bytes;
5595 }
5596 }
5597 }
5598
5599 if (best_ecc_bytes_total == INT_MAX)
5600 return -ENOTSUPP;
5601
5602 chip->ecc.size = best_step;
5603 chip->ecc.strength = best_strength;
5604 chip->ecc.bytes = best_ecc_bytes;
5605
5606 return 0;
5607 }
5608
5609 /**
5610 * nand_maximize_ecc - choose the max ECC strength available
5611 * @chip: nand chip info structure
5612 * @caps: ECC engine caps info structure
5613 * @oobavail: OOB size that the ECC engine can use
5614 *
5615 * Choose the max ECC strength that is supported on the controller, and can fit
5616 * within the chip's OOB. On success, the chosen ECC settings are set.
5617 */
5618 static int
nand_maximize_ecc(struct nand_chip * chip,const struct nand_ecc_caps * caps,int oobavail)5619 nand_maximize_ecc(struct nand_chip *chip,
5620 const struct nand_ecc_caps *caps, int oobavail)
5621 {
5622 struct mtd_info *mtd = nand_to_mtd(chip);
5623 const struct nand_ecc_step_info *stepinfo;
5624 int step_size, strength, nsteps, ecc_bytes, corr;
5625 int best_corr = 0;
5626 int best_step = 0;
5627 int best_strength, best_ecc_bytes;
5628 int i, j;
5629
5630 for (i = 0; i < caps->nstepinfos; i++) {
5631 stepinfo = &caps->stepinfos[i];
5632 step_size = stepinfo->stepsize;
5633
5634 /* If chip->ecc.size is already set, respect it */
5635 if (chip->ecc.size && step_size != chip->ecc.size)
5636 continue;
5637
5638 for (j = 0; j < stepinfo->nstrengths; j++) {
5639 strength = stepinfo->strengths[j];
5640
5641 if (mtd->writesize % step_size)
5642 continue;
5643
5644 nsteps = mtd->writesize / step_size;
5645
5646 ecc_bytes = caps->calc_ecc_bytes(step_size, strength);
5647 if (WARN_ON_ONCE(ecc_bytes < 0))
5648 continue;
5649
5650 if (ecc_bytes * nsteps > oobavail)
5651 continue;
5652
5653 corr = strength * nsteps;
5654
5655 /*
5656 * If the number of correctable bits is the same,
5657 * bigger step_size has more reliability.
5658 */
5659 if (corr > best_corr ||
5660 (corr == best_corr && step_size > best_step)) {
5661 best_corr = corr;
5662 best_step = step_size;
5663 best_strength = strength;
5664 best_ecc_bytes = ecc_bytes;
5665 }
5666 }
5667 }
5668
5669 if (!best_corr)
5670 return -ENOTSUPP;
5671
5672 chip->ecc.size = best_step;
5673 chip->ecc.strength = best_strength;
5674 chip->ecc.bytes = best_ecc_bytes;
5675
5676 return 0;
5677 }
5678
5679 /**
5680 * nand_ecc_choose_conf - Set the ECC strength and ECC step size
5681 * @chip: nand chip info structure
5682 * @caps: ECC engine caps info structure
5683 * @oobavail: OOB size that the ECC engine can use
5684 *
5685 * Choose the ECC configuration according to following logic.
5686 *
5687 * 1. If both ECC step size and ECC strength are already set (usually by DT)
5688 * then check if it is supported by this controller.
5689 * 2. If the user provided the nand-ecc-maximize property, then select maximum
5690 * ECC strength.
5691 * 3. Otherwise, try to match the ECC step size and ECC strength closest
5692 * to the chip's requirement. If available OOB size can't fit the chip
5693 * requirement then fallback to the maximum ECC step size and ECC strength.
5694 *
5695 * On success, the chosen ECC settings are set.
5696 */
nand_ecc_choose_conf(struct nand_chip * chip,const struct nand_ecc_caps * caps,int oobavail)5697 int nand_ecc_choose_conf(struct nand_chip *chip,
5698 const struct nand_ecc_caps *caps, int oobavail)
5699 {
5700 struct mtd_info *mtd = nand_to_mtd(chip);
5701 struct nand_device *nanddev = mtd_to_nanddev(mtd);
5702
5703 if (WARN_ON(oobavail < 0 || oobavail > mtd->oobsize))
5704 return -EINVAL;
5705
5706 if (chip->ecc.size && chip->ecc.strength)
5707 return nand_check_ecc_caps(chip, caps, oobavail);
5708
5709 if (nanddev->ecc.user_conf.flags & NAND_ECC_MAXIMIZE_STRENGTH)
5710 return nand_maximize_ecc(chip, caps, oobavail);
5711
5712 if (!nand_match_ecc_req(chip, caps, oobavail))
5713 return 0;
5714
5715 return nand_maximize_ecc(chip, caps, oobavail);
5716 }
5717 EXPORT_SYMBOL_GPL(nand_ecc_choose_conf);
5718
rawnand_erase(struct nand_device * nand,const struct nand_pos * pos)5719 static int rawnand_erase(struct nand_device *nand, const struct nand_pos *pos)
5720 {
5721 struct nand_chip *chip = container_of(nand, struct nand_chip,
5722 base);
5723 unsigned int eb = nanddev_pos_to_row(nand, pos);
5724 int ret;
5725
5726 eb >>= nand->rowconv.eraseblock_addr_shift;
5727
5728 nand_select_target(chip, pos->target);
5729 ret = nand_erase_op(chip, eb);
5730 nand_deselect_target(chip);
5731
5732 return ret;
5733 }
5734
rawnand_markbad(struct nand_device * nand,const struct nand_pos * pos)5735 static int rawnand_markbad(struct nand_device *nand,
5736 const struct nand_pos *pos)
5737 {
5738 struct nand_chip *chip = container_of(nand, struct nand_chip,
5739 base);
5740
5741 return nand_markbad_bbm(chip, nanddev_pos_to_offs(nand, pos));
5742 }
5743
rawnand_isbad(struct nand_device * nand,const struct nand_pos * pos)5744 static bool rawnand_isbad(struct nand_device *nand, const struct nand_pos *pos)
5745 {
5746 struct nand_chip *chip = container_of(nand, struct nand_chip,
5747 base);
5748 int ret;
5749
5750 nand_select_target(chip, pos->target);
5751 ret = nand_isbad_bbm(chip, nanddev_pos_to_offs(nand, pos));
5752 nand_deselect_target(chip);
5753
5754 return ret;
5755 }
5756
5757 static const struct nand_ops rawnand_ops = {
5758 .erase = rawnand_erase,
5759 .markbad = rawnand_markbad,
5760 .isbad = rawnand_isbad,
5761 };
5762
5763 /**
5764 * nand_scan_tail - Scan for the NAND device
5765 * @chip: NAND chip object
5766 *
5767 * This is the second phase of the normal nand_scan() function. It fills out
5768 * all the uninitialized function pointers with the defaults and scans for a
5769 * bad block table if appropriate.
5770 */
nand_scan_tail(struct nand_chip * chip)5771 static int nand_scan_tail(struct nand_chip *chip)
5772 {
5773 struct mtd_info *mtd = nand_to_mtd(chip);
5774 struct nand_ecc_ctrl *ecc = &chip->ecc;
5775 int ret, i;
5776
5777 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
5778 if (WARN_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
5779 !(chip->bbt_options & NAND_BBT_USE_FLASH))) {
5780 return -EINVAL;
5781 }
5782
5783 chip->data_buf = kmalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL);
5784 if (!chip->data_buf)
5785 return -ENOMEM;
5786
5787 /*
5788 * FIXME: some NAND manufacturer drivers expect the first die to be
5789 * selected when manufacturer->init() is called. They should be fixed
5790 * to explictly select the relevant die when interacting with the NAND
5791 * chip.
5792 */
5793 nand_select_target(chip, 0);
5794 ret = nand_manufacturer_init(chip);
5795 nand_deselect_target(chip);
5796 if (ret)
5797 goto err_free_buf;
5798
5799 /* Set the internal oob buffer location, just after the page data */
5800 chip->oob_poi = chip->data_buf + mtd->writesize;
5801
5802 /*
5803 * If no default placement scheme is given, select an appropriate one.
5804 */
5805 if (!mtd->ooblayout &&
5806 !(ecc->engine_type == NAND_ECC_ENGINE_TYPE_SOFT &&
5807 ecc->algo == NAND_ECC_ALGO_BCH) &&
5808 !(ecc->engine_type == NAND_ECC_ENGINE_TYPE_SOFT &&
5809 ecc->algo == NAND_ECC_ALGO_HAMMING)) {
5810 switch (mtd->oobsize) {
5811 case 8:
5812 case 16:
5813 mtd_set_ooblayout(mtd, nand_get_small_page_ooblayout());
5814 break;
5815 case 64:
5816 case 128:
5817 mtd_set_ooblayout(mtd,
5818 nand_get_large_page_hamming_ooblayout());
5819 break;
5820 default:
5821 /*
5822 * Expose the whole OOB area to users if ECC_NONE
5823 * is passed. We could do that for all kind of
5824 * ->oobsize, but we must keep the old large/small
5825 * page with ECC layout when ->oobsize <= 128 for
5826 * compatibility reasons.
5827 */
5828 if (ecc->engine_type == NAND_ECC_ENGINE_TYPE_NONE) {
5829 mtd_set_ooblayout(mtd,
5830 nand_get_large_page_ooblayout());
5831 break;
5832 }
5833
5834 WARN(1, "No oob scheme defined for oobsize %d\n",
5835 mtd->oobsize);
5836 ret = -EINVAL;
5837 goto err_nand_manuf_cleanup;
5838 }
5839 }
5840
5841 /*
5842 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
5843 * selected and we have 256 byte pagesize fallback to software ECC
5844 */
5845
5846 switch (ecc->engine_type) {
5847 case NAND_ECC_ENGINE_TYPE_ON_HOST:
5848 ret = nand_set_ecc_on_host_ops(chip);
5849 if (ret)
5850 goto err_nand_manuf_cleanup;
5851
5852 if (mtd->writesize >= ecc->size) {
5853 if (!ecc->strength) {
5854 WARN(1, "Driver must set ecc.strength when using hardware ECC\n");
5855 ret = -EINVAL;
5856 goto err_nand_manuf_cleanup;
5857 }
5858 break;
5859 }
5860 pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
5861 ecc->size, mtd->writesize);
5862 ecc->engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
5863 ecc->algo = NAND_ECC_ALGO_HAMMING;
5864 fallthrough;
5865
5866 case NAND_ECC_ENGINE_TYPE_SOFT:
5867 ret = nand_set_ecc_soft_ops(chip);
5868 if (ret)
5869 goto err_nand_manuf_cleanup;
5870 break;
5871
5872 case NAND_ECC_ENGINE_TYPE_ON_DIE:
5873 if (!ecc->read_page || !ecc->write_page) {
5874 WARN(1, "No ECC functions supplied; on-die ECC not possible\n");
5875 ret = -EINVAL;
5876 goto err_nand_manuf_cleanup;
5877 }
5878 if (!ecc->read_oob)
5879 ecc->read_oob = nand_read_oob_std;
5880 if (!ecc->write_oob)
5881 ecc->write_oob = nand_write_oob_std;
5882 break;
5883
5884 case NAND_ECC_ENGINE_TYPE_NONE:
5885 pr_warn("NAND_ECC_ENGINE_TYPE_NONE selected by board driver. This is not recommended!\n");
5886 ecc->read_page = nand_read_page_raw;
5887 ecc->write_page = nand_write_page_raw;
5888 ecc->read_oob = nand_read_oob_std;
5889 ecc->read_page_raw = nand_read_page_raw;
5890 ecc->write_page_raw = nand_write_page_raw;
5891 ecc->write_oob = nand_write_oob_std;
5892 ecc->size = mtd->writesize;
5893 ecc->bytes = 0;
5894 ecc->strength = 0;
5895 break;
5896
5897 default:
5898 WARN(1, "Invalid NAND_ECC_MODE %d\n", ecc->engine_type);
5899 ret = -EINVAL;
5900 goto err_nand_manuf_cleanup;
5901 }
5902
5903 if (ecc->correct || ecc->calculate) {
5904 ecc->calc_buf = kmalloc(mtd->oobsize, GFP_KERNEL);
5905 ecc->code_buf = kmalloc(mtd->oobsize, GFP_KERNEL);
5906 if (!ecc->calc_buf || !ecc->code_buf) {
5907 ret = -ENOMEM;
5908 goto err_nand_manuf_cleanup;
5909 }
5910 }
5911
5912 /* For many systems, the standard OOB write also works for raw */
5913 if (!ecc->read_oob_raw)
5914 ecc->read_oob_raw = ecc->read_oob;
5915 if (!ecc->write_oob_raw)
5916 ecc->write_oob_raw = ecc->write_oob;
5917
5918 /* propagate ecc info to mtd_info */
5919 mtd->ecc_strength = ecc->strength;
5920 mtd->ecc_step_size = ecc->size;
5921
5922 /*
5923 * Set the number of read / write steps for one page depending on ECC
5924 * mode.
5925 */
5926 if (!ecc->steps)
5927 ecc->steps = mtd->writesize / ecc->size;
5928 if (ecc->steps * ecc->size != mtd->writesize) {
5929 WARN(1, "Invalid ECC parameters\n");
5930 ret = -EINVAL;
5931 goto err_nand_manuf_cleanup;
5932 }
5933
5934 if (!ecc->total) {
5935 ecc->total = ecc->steps * ecc->bytes;
5936 chip->base.ecc.ctx.total = ecc->total;
5937 }
5938
5939 if (ecc->total > mtd->oobsize) {
5940 WARN(1, "Total number of ECC bytes exceeded oobsize\n");
5941 ret = -EINVAL;
5942 goto err_nand_manuf_cleanup;
5943 }
5944
5945 /*
5946 * The number of bytes available for a client to place data into
5947 * the out of band area.
5948 */
5949 ret = mtd_ooblayout_count_freebytes(mtd);
5950 if (ret < 0)
5951 ret = 0;
5952
5953 mtd->oobavail = ret;
5954
5955 /* ECC sanity check: warn if it's too weak */
5956 if (!nand_ecc_is_strong_enough(&chip->base))
5957 pr_warn("WARNING: %s: the ECC used on your system (%db/%dB) is too weak compared to the one required by the NAND chip (%db/%dB)\n",
5958 mtd->name, chip->ecc.strength, chip->ecc.size,
5959 nanddev_get_ecc_requirements(&chip->base)->strength,
5960 nanddev_get_ecc_requirements(&chip->base)->step_size);
5961
5962 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
5963 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
5964 switch (ecc->steps) {
5965 case 2:
5966 mtd->subpage_sft = 1;
5967 break;
5968 case 4:
5969 case 8:
5970 case 16:
5971 mtd->subpage_sft = 2;
5972 break;
5973 }
5974 }
5975 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
5976
5977 /* Invalidate the pagebuffer reference */
5978 chip->pagecache.page = -1;
5979
5980 /* Large page NAND with SOFT_ECC should support subpage reads */
5981 switch (ecc->engine_type) {
5982 case NAND_ECC_ENGINE_TYPE_SOFT:
5983 if (chip->page_shift > 9)
5984 chip->options |= NAND_SUBPAGE_READ;
5985 break;
5986
5987 default:
5988 break;
5989 }
5990
5991 ret = nanddev_init(&chip->base, &rawnand_ops, mtd->owner);
5992 if (ret)
5993 goto err_nand_manuf_cleanup;
5994
5995 /* Adjust the MTD_CAP_ flags when NAND_ROM is set. */
5996 if (chip->options & NAND_ROM)
5997 mtd->flags = MTD_CAP_ROM;
5998
5999 /* Fill in remaining MTD driver data */
6000 mtd->_erase = nand_erase;
6001 mtd->_point = NULL;
6002 mtd->_unpoint = NULL;
6003 mtd->_panic_write = panic_nand_write;
6004 mtd->_read_oob = nand_read_oob;
6005 mtd->_write_oob = nand_write_oob;
6006 mtd->_sync = nand_sync;
6007 mtd->_lock = nand_lock;
6008 mtd->_unlock = nand_unlock;
6009 mtd->_suspend = nand_suspend;
6010 mtd->_resume = nand_resume;
6011 mtd->_reboot = nand_shutdown;
6012 mtd->_block_isreserved = nand_block_isreserved;
6013 mtd->_block_isbad = nand_block_isbad;
6014 mtd->_block_markbad = nand_block_markbad;
6015 mtd->_max_bad_blocks = nanddev_mtd_max_bad_blocks;
6016
6017 /*
6018 * Initialize bitflip_threshold to its default prior scan_bbt() call.
6019 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
6020 * properly set.
6021 */
6022 if (!mtd->bitflip_threshold)
6023 mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4);
6024
6025 /* Find the fastest data interface for this chip */
6026 ret = nand_choose_interface_config(chip);
6027 if (ret)
6028 goto err_nanddev_cleanup;
6029
6030 /* Enter fastest possible mode on all dies. */
6031 for (i = 0; i < nanddev_ntargets(&chip->base); i++) {
6032 ret = nand_setup_interface(chip, i);
6033 if (ret)
6034 goto err_free_interface_config;
6035 }
6036
6037 /*
6038 * Look for secure regions in the NAND chip. These regions are supposed
6039 * to be protected by a secure element like Trustzone. So the read/write
6040 * accesses to these regions will be blocked in the runtime by this
6041 * driver.
6042 */
6043 ret = of_get_nand_secure_regions(chip);
6044 if (ret)
6045 goto err_free_interface_config;
6046
6047 /* Check, if we should skip the bad block table scan */
6048 if (chip->options & NAND_SKIP_BBTSCAN)
6049 return 0;
6050
6051 /* Build bad block table */
6052 ret = nand_create_bbt(chip);
6053 if (ret)
6054 goto err_free_secure_regions;
6055
6056 return 0;
6057
6058 err_free_secure_regions:
6059 kfree(chip->secure_regions);
6060
6061 err_free_interface_config:
6062 kfree(chip->best_interface_config);
6063
6064 err_nanddev_cleanup:
6065 nanddev_cleanup(&chip->base);
6066
6067 err_nand_manuf_cleanup:
6068 nand_manufacturer_cleanup(chip);
6069
6070 err_free_buf:
6071 kfree(chip->data_buf);
6072 kfree(ecc->code_buf);
6073 kfree(ecc->calc_buf);
6074
6075 return ret;
6076 }
6077
nand_attach(struct nand_chip * chip)6078 static int nand_attach(struct nand_chip *chip)
6079 {
6080 if (chip->controller->ops && chip->controller->ops->attach_chip)
6081 return chip->controller->ops->attach_chip(chip);
6082
6083 return 0;
6084 }
6085
nand_detach(struct nand_chip * chip)6086 static void nand_detach(struct nand_chip *chip)
6087 {
6088 if (chip->controller->ops && chip->controller->ops->detach_chip)
6089 chip->controller->ops->detach_chip(chip);
6090 }
6091
6092 /**
6093 * nand_scan_with_ids - [NAND Interface] Scan for the NAND device
6094 * @chip: NAND chip object
6095 * @maxchips: number of chips to scan for.
6096 * @ids: optional flash IDs table
6097 *
6098 * This fills out all the uninitialized function pointers with the defaults.
6099 * The flash ID is read and the mtd/chip structures are filled with the
6100 * appropriate values.
6101 */
nand_scan_with_ids(struct nand_chip * chip,unsigned int maxchips,struct nand_flash_dev * ids)6102 int nand_scan_with_ids(struct nand_chip *chip, unsigned int maxchips,
6103 struct nand_flash_dev *ids)
6104 {
6105 int ret;
6106
6107 if (!maxchips)
6108 return -EINVAL;
6109
6110 ret = nand_scan_ident(chip, maxchips, ids);
6111 if (ret)
6112 return ret;
6113
6114 ret = nand_attach(chip);
6115 if (ret)
6116 goto cleanup_ident;
6117
6118 ret = nand_scan_tail(chip);
6119 if (ret)
6120 goto detach_chip;
6121
6122 return 0;
6123
6124 detach_chip:
6125 nand_detach(chip);
6126 cleanup_ident:
6127 nand_scan_ident_cleanup(chip);
6128
6129 return ret;
6130 }
6131 EXPORT_SYMBOL(nand_scan_with_ids);
6132
6133 /**
6134 * nand_cleanup - [NAND Interface] Free resources held by the NAND device
6135 * @chip: NAND chip object
6136 */
nand_cleanup(struct nand_chip * chip)6137 void nand_cleanup(struct nand_chip *chip)
6138 {
6139 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT) {
6140 if (chip->ecc.algo == NAND_ECC_ALGO_HAMMING)
6141 rawnand_sw_hamming_cleanup(chip);
6142 else if (chip->ecc.algo == NAND_ECC_ALGO_BCH)
6143 rawnand_sw_bch_cleanup(chip);
6144 }
6145
6146 nanddev_cleanup(&chip->base);
6147
6148 /* Free secure regions data */
6149 kfree(chip->secure_regions);
6150
6151 /* Free bad block table memory */
6152 kfree(chip->bbt);
6153 kfree(chip->data_buf);
6154 kfree(chip->ecc.code_buf);
6155 kfree(chip->ecc.calc_buf);
6156
6157 /* Free bad block descriptor memory */
6158 if (chip->badblock_pattern && chip->badblock_pattern->options
6159 & NAND_BBT_DYNAMICSTRUCT)
6160 kfree(chip->badblock_pattern);
6161
6162 /* Free the data interface */
6163 kfree(chip->best_interface_config);
6164
6165 /* Free manufacturer priv data. */
6166 nand_manufacturer_cleanup(chip);
6167
6168 /* Free controller specific allocations after chip identification */
6169 nand_detach(chip);
6170
6171 /* Free identification phase allocations */
6172 nand_scan_ident_cleanup(chip);
6173 }
6174
6175 EXPORT_SYMBOL_GPL(nand_cleanup);
6176
6177 MODULE_LICENSE("GPL");
6178 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
6179 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
6180 MODULE_DESCRIPTION("Generic NAND flash driver code");
6181