1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Broadcom Starfighter 2 DSA switch driver
4 *
5 * Copyright (C) 2014, Broadcom Corporation
6 */
7
8 #include <linux/list.h>
9 #include <linux/module.h>
10 #include <linux/netdevice.h>
11 #include <linux/interrupt.h>
12 #include <linux/platform_device.h>
13 #include <linux/phy.h>
14 #include <linux/phy_fixed.h>
15 #include <linux/phylink.h>
16 #include <linux/mii.h>
17 #include <linux/clk.h>
18 #include <linux/of.h>
19 #include <linux/of_irq.h>
20 #include <linux/of_address.h>
21 #include <linux/of_net.h>
22 #include <linux/of_mdio.h>
23 #include <net/dsa.h>
24 #include <linux/ethtool.h>
25 #include <linux/if_bridge.h>
26 #include <linux/brcmphy.h>
27 #include <linux/etherdevice.h>
28 #include <linux/platform_data/b53.h>
29
30 #include "bcm_sf2.h"
31 #include "bcm_sf2_regs.h"
32 #include "b53/b53_priv.h"
33 #include "b53/b53_regs.h"
34
bcm_sf2_reg_rgmii_cntrl(struct bcm_sf2_priv * priv,int port)35 static u16 bcm_sf2_reg_rgmii_cntrl(struct bcm_sf2_priv *priv, int port)
36 {
37 switch (priv->type) {
38 case BCM4908_DEVICE_ID:
39 switch (port) {
40 case 7:
41 return REG_RGMII_11_CNTRL;
42 default:
43 break;
44 }
45 break;
46 default:
47 switch (port) {
48 case 0:
49 return REG_RGMII_0_CNTRL;
50 case 1:
51 return REG_RGMII_1_CNTRL;
52 case 2:
53 return REG_RGMII_2_CNTRL;
54 default:
55 break;
56 }
57 }
58
59 WARN_ONCE(1, "Unsupported port %d\n", port);
60
61 /* RO fallback reg */
62 return REG_SWITCH_STATUS;
63 }
64
65 /* Return the number of active ports, not counting the IMP (CPU) port */
bcm_sf2_num_active_ports(struct dsa_switch * ds)66 static unsigned int bcm_sf2_num_active_ports(struct dsa_switch *ds)
67 {
68 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
69 unsigned int port, count = 0;
70
71 for (port = 0; port < ARRAY_SIZE(priv->port_sts); port++) {
72 if (dsa_is_cpu_port(ds, port))
73 continue;
74 if (priv->port_sts[port].enabled)
75 count++;
76 }
77
78 return count;
79 }
80
bcm_sf2_recalc_clock(struct dsa_switch * ds)81 static void bcm_sf2_recalc_clock(struct dsa_switch *ds)
82 {
83 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
84 unsigned long new_rate;
85 unsigned int ports_active;
86 /* Frequenty in Mhz */
87 static const unsigned long rate_table[] = {
88 59220000,
89 60820000,
90 62500000,
91 62500000,
92 };
93
94 ports_active = bcm_sf2_num_active_ports(ds);
95 if (ports_active == 0 || !priv->clk_mdiv)
96 return;
97
98 /* If we overflow our table, just use the recommended operational
99 * frequency
100 */
101 if (ports_active > ARRAY_SIZE(rate_table))
102 new_rate = 90000000;
103 else
104 new_rate = rate_table[ports_active - 1];
105 clk_set_rate(priv->clk_mdiv, new_rate);
106 }
107
bcm_sf2_imp_setup(struct dsa_switch * ds,int port)108 static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
109 {
110 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
111 unsigned int i;
112 u32 reg, offset;
113
114 /* Enable the port memories */
115 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
116 reg &= ~P_TXQ_PSM_VDD(port);
117 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
118
119 /* Enable forwarding */
120 core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
121
122 /* Enable IMP port in dumb mode */
123 reg = core_readl(priv, CORE_SWITCH_CTRL);
124 reg |= MII_DUMB_FWDG_EN;
125 core_writel(priv, reg, CORE_SWITCH_CTRL);
126
127 /* Configure Traffic Class to QoS mapping, allow each priority to map
128 * to a different queue number
129 */
130 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
131 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
132 reg |= i << (PRT_TO_QID_SHIFT * i);
133 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
134
135 b53_brcm_hdr_setup(ds, port);
136
137 if (port == 8) {
138 if (priv->type == BCM4908_DEVICE_ID ||
139 priv->type == BCM7445_DEVICE_ID)
140 offset = CORE_STS_OVERRIDE_IMP;
141 else
142 offset = CORE_STS_OVERRIDE_IMP2;
143
144 /* Force link status for IMP port */
145 reg = core_readl(priv, offset);
146 reg |= (MII_SW_OR | LINK_STS);
147 if (priv->type == BCM4908_DEVICE_ID)
148 reg |= GMII_SPEED_UP_2G;
149 else
150 reg &= ~GMII_SPEED_UP_2G;
151 core_writel(priv, reg, offset);
152
153 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
154 reg = core_readl(priv, CORE_IMP_CTL);
155 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
156 reg &= ~(RX_DIS | TX_DIS);
157 core_writel(priv, reg, CORE_IMP_CTL);
158 } else {
159 reg = core_readl(priv, CORE_G_PCTL_PORT(port));
160 reg &= ~(RX_DIS | TX_DIS);
161 core_writel(priv, reg, CORE_G_PCTL_PORT(port));
162 }
163
164 priv->port_sts[port].enabled = true;
165 }
166
bcm_sf2_gphy_enable_set(struct dsa_switch * ds,bool enable)167 static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
168 {
169 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
170 u32 reg;
171
172 reg = reg_readl(priv, REG_SPHY_CNTRL);
173 if (enable) {
174 reg |= PHY_RESET;
175 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS);
176 reg_writel(priv, reg, REG_SPHY_CNTRL);
177 udelay(21);
178 reg = reg_readl(priv, REG_SPHY_CNTRL);
179 reg &= ~PHY_RESET;
180 } else {
181 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
182 reg_writel(priv, reg, REG_SPHY_CNTRL);
183 mdelay(1);
184 reg |= CK25_DIS;
185 }
186 reg_writel(priv, reg, REG_SPHY_CNTRL);
187
188 /* Use PHY-driven LED signaling */
189 if (!enable) {
190 reg = reg_readl(priv, REG_LED_CNTRL(0));
191 reg |= SPDLNK_SRC_SEL;
192 reg_writel(priv, reg, REG_LED_CNTRL(0));
193 }
194 }
195
bcm_sf2_port_intr_enable(struct bcm_sf2_priv * priv,int port)196 static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv,
197 int port)
198 {
199 unsigned int off;
200
201 switch (port) {
202 case 7:
203 off = P7_IRQ_OFF;
204 break;
205 case 0:
206 /* Port 0 interrupts are located on the first bank */
207 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF));
208 return;
209 default:
210 off = P_IRQ_OFF(port);
211 break;
212 }
213
214 intrl2_1_mask_clear(priv, P_IRQ_MASK(off));
215 }
216
bcm_sf2_port_intr_disable(struct bcm_sf2_priv * priv,int port)217 static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv,
218 int port)
219 {
220 unsigned int off;
221
222 switch (port) {
223 case 7:
224 off = P7_IRQ_OFF;
225 break;
226 case 0:
227 /* Port 0 interrupts are located on the first bank */
228 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF));
229 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR);
230 return;
231 default:
232 off = P_IRQ_OFF(port);
233 break;
234 }
235
236 intrl2_1_mask_set(priv, P_IRQ_MASK(off));
237 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR);
238 }
239
bcm_sf2_port_setup(struct dsa_switch * ds,int port,struct phy_device * phy)240 static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
241 struct phy_device *phy)
242 {
243 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
244 unsigned int i;
245 u32 reg;
246
247 if (!dsa_is_user_port(ds, port))
248 return 0;
249
250 priv->port_sts[port].enabled = true;
251
252 bcm_sf2_recalc_clock(ds);
253
254 /* Clear the memory power down */
255 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
256 reg &= ~P_TXQ_PSM_VDD(port);
257 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
258
259 /* Enable Broadcom tags for that port if requested */
260 if (priv->brcm_tag_mask & BIT(port))
261 b53_brcm_hdr_setup(ds, port);
262
263 /* Configure Traffic Class to QoS mapping, allow each priority to map
264 * to a different queue number
265 */
266 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
267 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
268 reg |= i << (PRT_TO_QID_SHIFT * i);
269 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
270
271 /* Re-enable the GPHY and re-apply workarounds */
272 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) {
273 bcm_sf2_gphy_enable_set(ds, true);
274 if (phy) {
275 /* if phy_stop() has been called before, phy
276 * will be in halted state, and phy_start()
277 * will call resume.
278 *
279 * the resume path does not configure back
280 * autoneg settings, and since we hard reset
281 * the phy manually here, we need to reset the
282 * state machine also.
283 */
284 phy->state = PHY_READY;
285 phy_init_hw(phy);
286 }
287 }
288
289 /* Enable MoCA port interrupts to get notified */
290 if (port == priv->moca_port)
291 bcm_sf2_port_intr_enable(priv, port);
292
293 /* Set per-queue pause threshold to 32 */
294 core_writel(priv, 32, CORE_TXQ_THD_PAUSE_QN_PORT(port));
295
296 /* Set ACB threshold to 24 */
297 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) {
298 reg = acb_readl(priv, ACB_QUEUE_CFG(port *
299 SF2_NUM_EGRESS_QUEUES + i));
300 reg &= ~XOFF_THRESHOLD_MASK;
301 reg |= 24;
302 acb_writel(priv, reg, ACB_QUEUE_CFG(port *
303 SF2_NUM_EGRESS_QUEUES + i));
304 }
305
306 return b53_enable_port(ds, port, phy);
307 }
308
bcm_sf2_port_disable(struct dsa_switch * ds,int port)309 static void bcm_sf2_port_disable(struct dsa_switch *ds, int port)
310 {
311 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
312 u32 reg;
313
314 /* Disable learning while in WoL mode */
315 if (priv->wol_ports_mask & (1 << port)) {
316 reg = core_readl(priv, CORE_DIS_LEARN);
317 reg |= BIT(port);
318 core_writel(priv, reg, CORE_DIS_LEARN);
319 return;
320 }
321
322 if (port == priv->moca_port)
323 bcm_sf2_port_intr_disable(priv, port);
324
325 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1)
326 bcm_sf2_gphy_enable_set(ds, false);
327
328 b53_disable_port(ds, port);
329
330 /* Power down the port memory */
331 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
332 reg |= P_TXQ_PSM_VDD(port);
333 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
334
335 priv->port_sts[port].enabled = false;
336
337 bcm_sf2_recalc_clock(ds);
338 }
339
340
bcm_sf2_sw_indir_rw(struct bcm_sf2_priv * priv,int op,int addr,int regnum,u16 val)341 static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr,
342 int regnum, u16 val)
343 {
344 int ret = 0;
345 u32 reg;
346
347 reg = reg_readl(priv, REG_SWITCH_CNTRL);
348 reg |= MDIO_MASTER_SEL;
349 reg_writel(priv, reg, REG_SWITCH_CNTRL);
350
351 /* Page << 8 | offset */
352 reg = 0x70;
353 reg <<= 2;
354 core_writel(priv, addr, reg);
355
356 /* Page << 8 | offset */
357 reg = 0x80 << 8 | regnum << 1;
358 reg <<= 2;
359
360 if (op)
361 ret = core_readl(priv, reg);
362 else
363 core_writel(priv, val, reg);
364
365 reg = reg_readl(priv, REG_SWITCH_CNTRL);
366 reg &= ~MDIO_MASTER_SEL;
367 reg_writel(priv, reg, REG_SWITCH_CNTRL);
368
369 return ret & 0xffff;
370 }
371
bcm_sf2_sw_mdio_read(struct mii_bus * bus,int addr,int regnum)372 static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
373 {
374 struct bcm_sf2_priv *priv = bus->priv;
375
376 /* Intercept reads from Broadcom pseudo-PHY address, else, send
377 * them to our master MDIO bus controller
378 */
379 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
380 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0);
381 else
382 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum);
383 }
384
bcm_sf2_sw_mdio_write(struct mii_bus * bus,int addr,int regnum,u16 val)385 static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
386 u16 val)
387 {
388 struct bcm_sf2_priv *priv = bus->priv;
389
390 /* Intercept writes to the Broadcom pseudo-PHY address, else,
391 * send them to our master MDIO bus controller
392 */
393 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
394 return bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val);
395 else
396 return mdiobus_write_nested(priv->master_mii_bus, addr,
397 regnum, val);
398 }
399
bcm_sf2_switch_0_isr(int irq,void * dev_id)400 static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
401 {
402 struct dsa_switch *ds = dev_id;
403 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
404
405 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
406 ~priv->irq0_mask;
407 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
408
409 return IRQ_HANDLED;
410 }
411
bcm_sf2_switch_1_isr(int irq,void * dev_id)412 static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
413 {
414 struct dsa_switch *ds = dev_id;
415 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
416
417 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
418 ~priv->irq1_mask;
419 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
420
421 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) {
422 priv->port_sts[7].link = true;
423 dsa_port_phylink_mac_change(ds, 7, true);
424 }
425 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) {
426 priv->port_sts[7].link = false;
427 dsa_port_phylink_mac_change(ds, 7, false);
428 }
429
430 return IRQ_HANDLED;
431 }
432
bcm_sf2_sw_rst(struct bcm_sf2_priv * priv)433 static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
434 {
435 unsigned int timeout = 1000;
436 u32 reg;
437 int ret;
438
439 /* The watchdog reset does not work on 7278, we need to hit the
440 * "external" reset line through the reset controller.
441 */
442 if (priv->type == BCM7278_DEVICE_ID) {
443 ret = reset_control_assert(priv->rcdev);
444 if (ret)
445 return ret;
446
447 return reset_control_deassert(priv->rcdev);
448 }
449
450 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
451 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
452 core_writel(priv, reg, CORE_WATCHDOG_CTRL);
453
454 do {
455 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
456 if (!(reg & SOFTWARE_RESET))
457 break;
458
459 usleep_range(1000, 2000);
460 } while (timeout-- > 0);
461
462 if (timeout == 0)
463 return -ETIMEDOUT;
464
465 return 0;
466 }
467
bcm_sf2_crossbar_setup(struct bcm_sf2_priv * priv)468 static void bcm_sf2_crossbar_setup(struct bcm_sf2_priv *priv)
469 {
470 struct device *dev = priv->dev->ds->dev;
471 int shift;
472 u32 mask;
473 u32 reg;
474 int i;
475
476 mask = BIT(priv->num_crossbar_int_ports) - 1;
477
478 reg = reg_readl(priv, REG_CROSSBAR);
479 switch (priv->type) {
480 case BCM4908_DEVICE_ID:
481 shift = CROSSBAR_BCM4908_INT_P7 * priv->num_crossbar_int_ports;
482 reg &= ~(mask << shift);
483 if (0) /* FIXME */
484 reg |= CROSSBAR_BCM4908_EXT_SERDES << shift;
485 else if (priv->int_phy_mask & BIT(7))
486 reg |= CROSSBAR_BCM4908_EXT_GPHY4 << shift;
487 else if (phy_interface_mode_is_rgmii(priv->port_sts[7].mode))
488 reg |= CROSSBAR_BCM4908_EXT_RGMII << shift;
489 else if (WARN(1, "Invalid port mode\n"))
490 return;
491 break;
492 default:
493 return;
494 }
495 reg_writel(priv, reg, REG_CROSSBAR);
496
497 reg = reg_readl(priv, REG_CROSSBAR);
498 for (i = 0; i < priv->num_crossbar_int_ports; i++) {
499 shift = i * priv->num_crossbar_int_ports;
500
501 dev_dbg(dev, "crossbar int port #%d - ext port #%d\n", i,
502 (reg >> shift) & mask);
503 }
504 }
505
bcm_sf2_intr_disable(struct bcm_sf2_priv * priv)506 static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
507 {
508 intrl2_0_mask_set(priv, 0xffffffff);
509 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
510 intrl2_1_mask_set(priv, 0xffffffff);
511 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
512 }
513
bcm_sf2_identify_ports(struct bcm_sf2_priv * priv,struct device_node * dn)514 static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv,
515 struct device_node *dn)
516 {
517 struct device *dev = priv->dev->ds->dev;
518 struct bcm_sf2_port_status *port_st;
519 struct device_node *port;
520 unsigned int port_num;
521 struct property *prop;
522 int err;
523
524 priv->moca_port = -1;
525
526 for_each_available_child_of_node(dn, port) {
527 if (of_property_read_u32(port, "reg", &port_num))
528 continue;
529
530 if (port_num >= DSA_MAX_PORTS) {
531 dev_err(dev, "Invalid port number %d\n", port_num);
532 continue;
533 }
534
535 port_st = &priv->port_sts[port_num];
536
537 /* Internal PHYs get assigned a specific 'phy-mode' property
538 * value: "internal" to help flag them before MDIO probing
539 * has completed, since they might be turned off at that
540 * time
541 */
542 err = of_get_phy_mode(port, &port_st->mode);
543 if (err)
544 continue;
545
546 if (port_st->mode == PHY_INTERFACE_MODE_INTERNAL)
547 priv->int_phy_mask |= 1 << port_num;
548
549 if (port_st->mode == PHY_INTERFACE_MODE_MOCA)
550 priv->moca_port = port_num;
551
552 if (of_property_read_bool(port, "brcm,use-bcm-hdr"))
553 priv->brcm_tag_mask |= 1 << port_num;
554
555 /* Ensure that port 5 is not picked up as a DSA CPU port
556 * flavour but a regular port instead. We should be using
557 * devlink to be able to set the port flavour.
558 */
559 if (port_num == 5 && priv->type == BCM7278_DEVICE_ID) {
560 prop = of_find_property(port, "ethernet", NULL);
561 if (prop)
562 of_remove_property(port, prop);
563 }
564 }
565 }
566
bcm_sf2_mdio_register(struct dsa_switch * ds)567 static int bcm_sf2_mdio_register(struct dsa_switch *ds)
568 {
569 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
570 struct device_node *dn, *child;
571 struct phy_device *phydev;
572 struct property *prop;
573 static int index;
574 int err, reg;
575
576 /* Find our integrated MDIO bus node */
577 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio");
578 priv->master_mii_bus = of_mdio_find_bus(dn);
579 if (!priv->master_mii_bus) {
580 of_node_put(dn);
581 return -EPROBE_DEFER;
582 }
583
584 get_device(&priv->master_mii_bus->dev);
585 priv->master_mii_dn = dn;
586
587 priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev);
588 if (!priv->slave_mii_bus) {
589 of_node_put(dn);
590 return -ENOMEM;
591 }
592
593 priv->slave_mii_bus->priv = priv;
594 priv->slave_mii_bus->name = "sf2 slave mii";
595 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read;
596 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write;
597 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d",
598 index++);
599 priv->slave_mii_bus->dev.of_node = dn;
600
601 /* Include the pseudo-PHY address to divert reads towards our
602 * workaround. This is only required for 7445D0, since 7445E0
603 * disconnects the internal switch pseudo-PHY such that we can use the
604 * regular SWITCH_MDIO master controller instead.
605 *
606 * Here we flag the pseudo PHY as needing special treatment and would
607 * otherwise make all other PHY read/writes go to the master MDIO bus
608 * controller that comes with this switch backed by the "mdio-unimac"
609 * driver.
610 */
611 if (of_machine_is_compatible("brcm,bcm7445d0"))
612 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR) | (1 << 0);
613 else
614 priv->indir_phy_mask = 0;
615
616 ds->phys_mii_mask = priv->indir_phy_mask;
617 ds->slave_mii_bus = priv->slave_mii_bus;
618 priv->slave_mii_bus->parent = ds->dev->parent;
619 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask;
620
621 /* We need to make sure that of_phy_connect() will not work by
622 * removing the 'phandle' and 'linux,phandle' properties and
623 * unregister the existing PHY device that was already registered.
624 */
625 for_each_available_child_of_node(dn, child) {
626 if (of_property_read_u32(child, "reg", ®) ||
627 reg >= PHY_MAX_ADDR)
628 continue;
629
630 if (!(priv->indir_phy_mask & BIT(reg)))
631 continue;
632
633 prop = of_find_property(child, "phandle", NULL);
634 if (prop)
635 of_remove_property(child, prop);
636
637 prop = of_find_property(child, "linux,phandle", NULL);
638 if (prop)
639 of_remove_property(child, prop);
640
641 phydev = of_phy_find_device(child);
642 if (phydev)
643 phy_device_remove(phydev);
644 }
645
646 err = mdiobus_register(priv->slave_mii_bus);
647 if (err && dn)
648 of_node_put(dn);
649
650 return err;
651 }
652
bcm_sf2_mdio_unregister(struct bcm_sf2_priv * priv)653 static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv)
654 {
655 mdiobus_unregister(priv->slave_mii_bus);
656 of_node_put(priv->master_mii_dn);
657 }
658
bcm_sf2_sw_get_phy_flags(struct dsa_switch * ds,int port)659 static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
660 {
661 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
662
663 /* The BCM7xxx PHY driver expects to find the integrated PHY revision
664 * in bits 15:8 and the patch level in bits 7:0 which is exactly what
665 * the REG_PHY_REVISION register layout is.
666 */
667 if (priv->int_phy_mask & BIT(port))
668 return priv->hw_params.gphy_rev;
669 else
670 return 0;
671 }
672
bcm_sf2_sw_validate(struct dsa_switch * ds,int port,unsigned long * supported,struct phylink_link_state * state)673 static void bcm_sf2_sw_validate(struct dsa_switch *ds, int port,
674 unsigned long *supported,
675 struct phylink_link_state *state)
676 {
677 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
678 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
679
680 if (!phy_interface_mode_is_rgmii(state->interface) &&
681 state->interface != PHY_INTERFACE_MODE_MII &&
682 state->interface != PHY_INTERFACE_MODE_REVMII &&
683 state->interface != PHY_INTERFACE_MODE_GMII &&
684 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
685 state->interface != PHY_INTERFACE_MODE_MOCA) {
686 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
687 if (port != core_readl(priv, CORE_IMP0_PRT_ID))
688 dev_err(ds->dev,
689 "Unsupported interface: %d for port %d\n",
690 state->interface, port);
691 return;
692 }
693
694 /* Allow all the expected bits */
695 phylink_set(mask, Autoneg);
696 phylink_set_port_modes(mask);
697 phylink_set(mask, Pause);
698 phylink_set(mask, Asym_Pause);
699
700 /* With the exclusion of MII and Reverse MII, we support Gigabit,
701 * including Half duplex
702 */
703 if (state->interface != PHY_INTERFACE_MODE_MII &&
704 state->interface != PHY_INTERFACE_MODE_REVMII) {
705 phylink_set(mask, 1000baseT_Full);
706 phylink_set(mask, 1000baseT_Half);
707 }
708
709 phylink_set(mask, 10baseT_Half);
710 phylink_set(mask, 10baseT_Full);
711 phylink_set(mask, 100baseT_Half);
712 phylink_set(mask, 100baseT_Full);
713
714 bitmap_and(supported, supported, mask,
715 __ETHTOOL_LINK_MODE_MASK_NBITS);
716 bitmap_and(state->advertising, state->advertising, mask,
717 __ETHTOOL_LINK_MODE_MASK_NBITS);
718 }
719
bcm_sf2_sw_mac_config(struct dsa_switch * ds,int port,unsigned int mode,const struct phylink_link_state * state)720 static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port,
721 unsigned int mode,
722 const struct phylink_link_state *state)
723 {
724 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
725 u32 id_mode_dis = 0, port_mode;
726 u32 reg_rgmii_ctrl;
727 u32 reg;
728
729 if (port == core_readl(priv, CORE_IMP0_PRT_ID))
730 return;
731
732 switch (state->interface) {
733 case PHY_INTERFACE_MODE_RGMII:
734 id_mode_dis = 1;
735 fallthrough;
736 case PHY_INTERFACE_MODE_RGMII_TXID:
737 port_mode = EXT_GPHY;
738 break;
739 case PHY_INTERFACE_MODE_MII:
740 port_mode = EXT_EPHY;
741 break;
742 case PHY_INTERFACE_MODE_REVMII:
743 port_mode = EXT_REVMII;
744 break;
745 default:
746 /* Nothing required for all other PHYs: internal and MoCA */
747 return;
748 }
749
750 reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port);
751
752 /* Clear id_mode_dis bit, and the existing port mode, let
753 * RGMII_MODE_EN bet set by mac_link_{up,down}
754 */
755 reg = reg_readl(priv, reg_rgmii_ctrl);
756 reg &= ~ID_MODE_DIS;
757 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
758
759 reg |= port_mode;
760 if (id_mode_dis)
761 reg |= ID_MODE_DIS;
762
763 reg_writel(priv, reg, reg_rgmii_ctrl);
764 }
765
bcm_sf2_sw_mac_link_set(struct dsa_switch * ds,int port,phy_interface_t interface,bool link)766 static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port,
767 phy_interface_t interface, bool link)
768 {
769 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
770 u32 reg_rgmii_ctrl;
771 u32 reg;
772
773 if (!phy_interface_mode_is_rgmii(interface) &&
774 interface != PHY_INTERFACE_MODE_MII &&
775 interface != PHY_INTERFACE_MODE_REVMII)
776 return;
777
778 reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port);
779
780 /* If the link is down, just disable the interface to conserve power */
781 reg = reg_readl(priv, reg_rgmii_ctrl);
782 if (link)
783 reg |= RGMII_MODE_EN;
784 else
785 reg &= ~RGMII_MODE_EN;
786 reg_writel(priv, reg, reg_rgmii_ctrl);
787 }
788
bcm_sf2_sw_mac_link_down(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface)789 static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port,
790 unsigned int mode,
791 phy_interface_t interface)
792 {
793 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
794 u32 reg, offset;
795
796 if (port != core_readl(priv, CORE_IMP0_PRT_ID)) {
797 if (priv->type == BCM4908_DEVICE_ID ||
798 priv->type == BCM7445_DEVICE_ID)
799 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
800 else
801 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
802
803 reg = core_readl(priv, offset);
804 reg &= ~LINK_STS;
805 core_writel(priv, reg, offset);
806 }
807
808 bcm_sf2_sw_mac_link_set(ds, port, interface, false);
809 }
810
bcm_sf2_sw_mac_link_up(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface,struct phy_device * phydev,int speed,int duplex,bool tx_pause,bool rx_pause)811 static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port,
812 unsigned int mode,
813 phy_interface_t interface,
814 struct phy_device *phydev,
815 int speed, int duplex,
816 bool tx_pause, bool rx_pause)
817 {
818 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
819 struct ethtool_eee *p = &priv->dev->ports[port].eee;
820
821 bcm_sf2_sw_mac_link_set(ds, port, interface, true);
822
823 if (port != core_readl(priv, CORE_IMP0_PRT_ID)) {
824 u32 reg_rgmii_ctrl;
825 u32 reg, offset;
826
827 reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port);
828
829 if (priv->type == BCM4908_DEVICE_ID ||
830 priv->type == BCM7445_DEVICE_ID)
831 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
832 else
833 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
834
835 if (interface == PHY_INTERFACE_MODE_RGMII ||
836 interface == PHY_INTERFACE_MODE_RGMII_TXID ||
837 interface == PHY_INTERFACE_MODE_MII ||
838 interface == PHY_INTERFACE_MODE_REVMII) {
839 reg = reg_readl(priv, reg_rgmii_ctrl);
840 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
841
842 if (tx_pause)
843 reg |= TX_PAUSE_EN;
844 if (rx_pause)
845 reg |= RX_PAUSE_EN;
846
847 reg_writel(priv, reg, reg_rgmii_ctrl);
848 }
849
850 reg = SW_OVERRIDE | LINK_STS;
851 switch (speed) {
852 case SPEED_1000:
853 reg |= SPDSTS_1000 << SPEED_SHIFT;
854 break;
855 case SPEED_100:
856 reg |= SPDSTS_100 << SPEED_SHIFT;
857 break;
858 }
859
860 if (duplex == DUPLEX_FULL)
861 reg |= DUPLX_MODE;
862
863 core_writel(priv, reg, offset);
864 }
865
866 if (mode == MLO_AN_PHY && phydev)
867 p->eee_enabled = b53_eee_init(ds, port, phydev);
868 }
869
bcm_sf2_sw_fixed_state(struct dsa_switch * ds,int port,struct phylink_link_state * status)870 static void bcm_sf2_sw_fixed_state(struct dsa_switch *ds, int port,
871 struct phylink_link_state *status)
872 {
873 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
874
875 status->link = false;
876
877 /* MoCA port is special as we do not get link status from CORE_LNKSTS,
878 * which means that we need to force the link at the port override
879 * level to get the data to flow. We do use what the interrupt handler
880 * did determine before.
881 *
882 * For the other ports, we just force the link status, since this is
883 * a fixed PHY device.
884 */
885 if (port == priv->moca_port) {
886 status->link = priv->port_sts[port].link;
887 /* For MoCA interfaces, also force a link down notification
888 * since some version of the user-space daemon (mocad) use
889 * cmd->autoneg to force the link, which messes up the PHY
890 * state machine and make it go in PHY_FORCING state instead.
891 */
892 if (!status->link)
893 netif_carrier_off(dsa_to_port(ds, port)->slave);
894 status->duplex = DUPLEX_FULL;
895 } else {
896 status->link = true;
897 }
898 }
899
bcm_sf2_enable_acb(struct dsa_switch * ds)900 static void bcm_sf2_enable_acb(struct dsa_switch *ds)
901 {
902 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
903 u32 reg;
904
905 /* Enable ACB globally */
906 reg = acb_readl(priv, ACB_CONTROL);
907 reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
908 acb_writel(priv, reg, ACB_CONTROL);
909 reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
910 reg |= ACB_EN | ACB_ALGORITHM;
911 acb_writel(priv, reg, ACB_CONTROL);
912 }
913
bcm_sf2_sw_suspend(struct dsa_switch * ds)914 static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
915 {
916 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
917 unsigned int port;
918
919 bcm_sf2_intr_disable(priv);
920
921 /* Disable all ports physically present including the IMP
922 * port, the other ones have already been disabled during
923 * bcm_sf2_sw_setup
924 */
925 for (port = 0; port < ds->num_ports; port++) {
926 if (dsa_is_user_port(ds, port) || dsa_is_cpu_port(ds, port))
927 bcm_sf2_port_disable(ds, port);
928 }
929
930 if (!priv->wol_ports_mask)
931 clk_disable_unprepare(priv->clk);
932
933 return 0;
934 }
935
bcm_sf2_sw_resume(struct dsa_switch * ds)936 static int bcm_sf2_sw_resume(struct dsa_switch *ds)
937 {
938 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
939 int ret;
940
941 if (!priv->wol_ports_mask)
942 clk_prepare_enable(priv->clk);
943
944 ret = bcm_sf2_sw_rst(priv);
945 if (ret) {
946 pr_err("%s: failed to software reset switch\n", __func__);
947 return ret;
948 }
949
950 bcm_sf2_crossbar_setup(priv);
951
952 ret = bcm_sf2_cfp_resume(ds);
953 if (ret)
954 return ret;
955
956 if (priv->hw_params.num_gphy == 1)
957 bcm_sf2_gphy_enable_set(ds, true);
958
959 ds->ops->setup(ds);
960
961 return 0;
962 }
963
bcm_sf2_sw_get_wol(struct dsa_switch * ds,int port,struct ethtool_wolinfo * wol)964 static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port,
965 struct ethtool_wolinfo *wol)
966 {
967 struct net_device *p = dsa_to_port(ds, port)->cpu_dp->master;
968 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
969 struct ethtool_wolinfo pwol = { };
970
971 /* Get the parent device WoL settings */
972 if (p->ethtool_ops->get_wol)
973 p->ethtool_ops->get_wol(p, &pwol);
974
975 /* Advertise the parent device supported settings */
976 wol->supported = pwol.supported;
977 memset(&wol->sopass, 0, sizeof(wol->sopass));
978
979 if (pwol.wolopts & WAKE_MAGICSECURE)
980 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass));
981
982 if (priv->wol_ports_mask & (1 << port))
983 wol->wolopts = pwol.wolopts;
984 else
985 wol->wolopts = 0;
986 }
987
bcm_sf2_sw_set_wol(struct dsa_switch * ds,int port,struct ethtool_wolinfo * wol)988 static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port,
989 struct ethtool_wolinfo *wol)
990 {
991 struct net_device *p = dsa_to_port(ds, port)->cpu_dp->master;
992 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
993 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
994 struct ethtool_wolinfo pwol = { };
995
996 if (p->ethtool_ops->get_wol)
997 p->ethtool_ops->get_wol(p, &pwol);
998 if (wol->wolopts & ~pwol.supported)
999 return -EINVAL;
1000
1001 if (wol->wolopts)
1002 priv->wol_ports_mask |= (1 << port);
1003 else
1004 priv->wol_ports_mask &= ~(1 << port);
1005
1006 /* If we have at least one port enabled, make sure the CPU port
1007 * is also enabled. If the CPU port is the last one enabled, we disable
1008 * it since this configuration does not make sense.
1009 */
1010 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port))
1011 priv->wol_ports_mask |= (1 << cpu_port);
1012 else
1013 priv->wol_ports_mask &= ~(1 << cpu_port);
1014
1015 return p->ethtool_ops->set_wol(p, wol);
1016 }
1017
bcm_sf2_sw_setup(struct dsa_switch * ds)1018 static int bcm_sf2_sw_setup(struct dsa_switch *ds)
1019 {
1020 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
1021 unsigned int port;
1022
1023 /* Enable all valid ports and disable those unused */
1024 for (port = 0; port < priv->hw_params.num_ports; port++) {
1025 /* IMP port receives special treatment */
1026 if (dsa_is_user_port(ds, port))
1027 bcm_sf2_port_setup(ds, port, NULL);
1028 else if (dsa_is_cpu_port(ds, port))
1029 bcm_sf2_imp_setup(ds, port);
1030 else
1031 bcm_sf2_port_disable(ds, port);
1032 }
1033
1034 b53_configure_vlan(ds);
1035 bcm_sf2_enable_acb(ds);
1036
1037 return b53_setup_devlink_resources(ds);
1038 }
1039
bcm_sf2_sw_teardown(struct dsa_switch * ds)1040 static void bcm_sf2_sw_teardown(struct dsa_switch *ds)
1041 {
1042 dsa_devlink_resources_unregister(ds);
1043 }
1044
1045 /* The SWITCH_CORE register space is managed by b53 but operates on a page +
1046 * register basis so we need to translate that into an address that the
1047 * bus-glue understands.
1048 */
1049 #define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2)
1050
bcm_sf2_core_read8(struct b53_device * dev,u8 page,u8 reg,u8 * val)1051 static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg,
1052 u8 *val)
1053 {
1054 struct bcm_sf2_priv *priv = dev->priv;
1055
1056 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
1057
1058 return 0;
1059 }
1060
bcm_sf2_core_read16(struct b53_device * dev,u8 page,u8 reg,u16 * val)1061 static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg,
1062 u16 *val)
1063 {
1064 struct bcm_sf2_priv *priv = dev->priv;
1065
1066 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
1067
1068 return 0;
1069 }
1070
bcm_sf2_core_read32(struct b53_device * dev,u8 page,u8 reg,u32 * val)1071 static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg,
1072 u32 *val)
1073 {
1074 struct bcm_sf2_priv *priv = dev->priv;
1075
1076 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
1077
1078 return 0;
1079 }
1080
bcm_sf2_core_read64(struct b53_device * dev,u8 page,u8 reg,u64 * val)1081 static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg,
1082 u64 *val)
1083 {
1084 struct bcm_sf2_priv *priv = dev->priv;
1085
1086 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg));
1087
1088 return 0;
1089 }
1090
bcm_sf2_core_write8(struct b53_device * dev,u8 page,u8 reg,u8 value)1091 static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg,
1092 u8 value)
1093 {
1094 struct bcm_sf2_priv *priv = dev->priv;
1095
1096 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
1097
1098 return 0;
1099 }
1100
bcm_sf2_core_write16(struct b53_device * dev,u8 page,u8 reg,u16 value)1101 static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg,
1102 u16 value)
1103 {
1104 struct bcm_sf2_priv *priv = dev->priv;
1105
1106 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
1107
1108 return 0;
1109 }
1110
bcm_sf2_core_write32(struct b53_device * dev,u8 page,u8 reg,u32 value)1111 static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg,
1112 u32 value)
1113 {
1114 struct bcm_sf2_priv *priv = dev->priv;
1115
1116 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
1117
1118 return 0;
1119 }
1120
bcm_sf2_core_write64(struct b53_device * dev,u8 page,u8 reg,u64 value)1121 static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg,
1122 u64 value)
1123 {
1124 struct bcm_sf2_priv *priv = dev->priv;
1125
1126 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
1127
1128 return 0;
1129 }
1130
1131 static const struct b53_io_ops bcm_sf2_io_ops = {
1132 .read8 = bcm_sf2_core_read8,
1133 .read16 = bcm_sf2_core_read16,
1134 .read32 = bcm_sf2_core_read32,
1135 .read48 = bcm_sf2_core_read64,
1136 .read64 = bcm_sf2_core_read64,
1137 .write8 = bcm_sf2_core_write8,
1138 .write16 = bcm_sf2_core_write16,
1139 .write32 = bcm_sf2_core_write32,
1140 .write48 = bcm_sf2_core_write64,
1141 .write64 = bcm_sf2_core_write64,
1142 };
1143
bcm_sf2_sw_get_strings(struct dsa_switch * ds,int port,u32 stringset,uint8_t * data)1144 static void bcm_sf2_sw_get_strings(struct dsa_switch *ds, int port,
1145 u32 stringset, uint8_t *data)
1146 {
1147 int cnt = b53_get_sset_count(ds, port, stringset);
1148
1149 b53_get_strings(ds, port, stringset, data);
1150 bcm_sf2_cfp_get_strings(ds, port, stringset,
1151 data + cnt * ETH_GSTRING_LEN);
1152 }
1153
bcm_sf2_sw_get_ethtool_stats(struct dsa_switch * ds,int port,uint64_t * data)1154 static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds, int port,
1155 uint64_t *data)
1156 {
1157 int cnt = b53_get_sset_count(ds, port, ETH_SS_STATS);
1158
1159 b53_get_ethtool_stats(ds, port, data);
1160 bcm_sf2_cfp_get_ethtool_stats(ds, port, data + cnt);
1161 }
1162
bcm_sf2_sw_get_sset_count(struct dsa_switch * ds,int port,int sset)1163 static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds, int port,
1164 int sset)
1165 {
1166 int cnt = b53_get_sset_count(ds, port, sset);
1167
1168 if (cnt < 0)
1169 return cnt;
1170
1171 cnt += bcm_sf2_cfp_get_sset_count(ds, port, sset);
1172
1173 return cnt;
1174 }
1175
1176 static const struct dsa_switch_ops bcm_sf2_ops = {
1177 .get_tag_protocol = b53_get_tag_protocol,
1178 .setup = bcm_sf2_sw_setup,
1179 .teardown = bcm_sf2_sw_teardown,
1180 .get_strings = bcm_sf2_sw_get_strings,
1181 .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats,
1182 .get_sset_count = bcm_sf2_sw_get_sset_count,
1183 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats,
1184 .get_phy_flags = bcm_sf2_sw_get_phy_flags,
1185 .phylink_validate = bcm_sf2_sw_validate,
1186 .phylink_mac_config = bcm_sf2_sw_mac_config,
1187 .phylink_mac_link_down = bcm_sf2_sw_mac_link_down,
1188 .phylink_mac_link_up = bcm_sf2_sw_mac_link_up,
1189 .phylink_fixed_state = bcm_sf2_sw_fixed_state,
1190 .suspend = bcm_sf2_sw_suspend,
1191 .resume = bcm_sf2_sw_resume,
1192 .get_wol = bcm_sf2_sw_get_wol,
1193 .set_wol = bcm_sf2_sw_set_wol,
1194 .port_enable = bcm_sf2_port_setup,
1195 .port_disable = bcm_sf2_port_disable,
1196 .get_mac_eee = b53_get_mac_eee,
1197 .set_mac_eee = b53_set_mac_eee,
1198 .port_bridge_join = b53_br_join,
1199 .port_bridge_leave = b53_br_leave,
1200 .port_pre_bridge_flags = b53_br_flags_pre,
1201 .port_bridge_flags = b53_br_flags,
1202 .port_stp_state_set = b53_br_set_stp_state,
1203 .port_set_mrouter = b53_set_mrouter,
1204 .port_fast_age = b53_br_fast_age,
1205 .port_vlan_filtering = b53_vlan_filtering,
1206 .port_vlan_add = b53_vlan_add,
1207 .port_vlan_del = b53_vlan_del,
1208 .port_fdb_dump = b53_fdb_dump,
1209 .port_fdb_add = b53_fdb_add,
1210 .port_fdb_del = b53_fdb_del,
1211 .get_rxnfc = bcm_sf2_get_rxnfc,
1212 .set_rxnfc = bcm_sf2_set_rxnfc,
1213 .port_mirror_add = b53_mirror_add,
1214 .port_mirror_del = b53_mirror_del,
1215 .port_mdb_add = b53_mdb_add,
1216 .port_mdb_del = b53_mdb_del,
1217 };
1218
1219 struct bcm_sf2_of_data {
1220 u32 type;
1221 const u16 *reg_offsets;
1222 unsigned int core_reg_align;
1223 unsigned int num_cfp_rules;
1224 unsigned int num_crossbar_int_ports;
1225 };
1226
1227 static const u16 bcm_sf2_4908_reg_offsets[] = {
1228 [REG_SWITCH_CNTRL] = 0x00,
1229 [REG_SWITCH_STATUS] = 0x04,
1230 [REG_DIR_DATA_WRITE] = 0x08,
1231 [REG_DIR_DATA_READ] = 0x0c,
1232 [REG_SWITCH_REVISION] = 0x10,
1233 [REG_PHY_REVISION] = 0x14,
1234 [REG_SPHY_CNTRL] = 0x24,
1235 [REG_CROSSBAR] = 0xc8,
1236 [REG_RGMII_11_CNTRL] = 0x014c,
1237 [REG_LED_0_CNTRL] = 0x40,
1238 [REG_LED_1_CNTRL] = 0x4c,
1239 [REG_LED_2_CNTRL] = 0x58,
1240 };
1241
1242 static const struct bcm_sf2_of_data bcm_sf2_4908_data = {
1243 .type = BCM4908_DEVICE_ID,
1244 .core_reg_align = 0,
1245 .reg_offsets = bcm_sf2_4908_reg_offsets,
1246 .num_cfp_rules = 256,
1247 .num_crossbar_int_ports = 2,
1248 };
1249
1250 /* Register offsets for the SWITCH_REG_* block */
1251 static const u16 bcm_sf2_7445_reg_offsets[] = {
1252 [REG_SWITCH_CNTRL] = 0x00,
1253 [REG_SWITCH_STATUS] = 0x04,
1254 [REG_DIR_DATA_WRITE] = 0x08,
1255 [REG_DIR_DATA_READ] = 0x0C,
1256 [REG_SWITCH_REVISION] = 0x18,
1257 [REG_PHY_REVISION] = 0x1C,
1258 [REG_SPHY_CNTRL] = 0x2C,
1259 [REG_RGMII_0_CNTRL] = 0x34,
1260 [REG_RGMII_1_CNTRL] = 0x40,
1261 [REG_RGMII_2_CNTRL] = 0x4c,
1262 [REG_LED_0_CNTRL] = 0x90,
1263 [REG_LED_1_CNTRL] = 0x94,
1264 [REG_LED_2_CNTRL] = 0x98,
1265 };
1266
1267 static const struct bcm_sf2_of_data bcm_sf2_7445_data = {
1268 .type = BCM7445_DEVICE_ID,
1269 .core_reg_align = 0,
1270 .reg_offsets = bcm_sf2_7445_reg_offsets,
1271 .num_cfp_rules = 256,
1272 };
1273
1274 static const u16 bcm_sf2_7278_reg_offsets[] = {
1275 [REG_SWITCH_CNTRL] = 0x00,
1276 [REG_SWITCH_STATUS] = 0x04,
1277 [REG_DIR_DATA_WRITE] = 0x08,
1278 [REG_DIR_DATA_READ] = 0x0c,
1279 [REG_SWITCH_REVISION] = 0x10,
1280 [REG_PHY_REVISION] = 0x14,
1281 [REG_SPHY_CNTRL] = 0x24,
1282 [REG_RGMII_0_CNTRL] = 0xe0,
1283 [REG_RGMII_1_CNTRL] = 0xec,
1284 [REG_RGMII_2_CNTRL] = 0xf8,
1285 [REG_LED_0_CNTRL] = 0x40,
1286 [REG_LED_1_CNTRL] = 0x4c,
1287 [REG_LED_2_CNTRL] = 0x58,
1288 };
1289
1290 static const struct bcm_sf2_of_data bcm_sf2_7278_data = {
1291 .type = BCM7278_DEVICE_ID,
1292 .core_reg_align = 1,
1293 .reg_offsets = bcm_sf2_7278_reg_offsets,
1294 .num_cfp_rules = 128,
1295 };
1296
1297 static const struct of_device_id bcm_sf2_of_match[] = {
1298 { .compatible = "brcm,bcm4908-switch",
1299 .data = &bcm_sf2_4908_data
1300 },
1301 { .compatible = "brcm,bcm7445-switch-v4.0",
1302 .data = &bcm_sf2_7445_data
1303 },
1304 { .compatible = "brcm,bcm7278-switch-v4.0",
1305 .data = &bcm_sf2_7278_data
1306 },
1307 { .compatible = "brcm,bcm7278-switch-v4.8",
1308 .data = &bcm_sf2_7278_data
1309 },
1310 { /* sentinel */ },
1311 };
1312 MODULE_DEVICE_TABLE(of, bcm_sf2_of_match);
1313
bcm_sf2_sw_probe(struct platform_device * pdev)1314 static int bcm_sf2_sw_probe(struct platform_device *pdev)
1315 {
1316 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
1317 struct device_node *dn = pdev->dev.of_node;
1318 const struct of_device_id *of_id = NULL;
1319 const struct bcm_sf2_of_data *data;
1320 struct b53_platform_data *pdata;
1321 struct dsa_switch_ops *ops;
1322 struct device_node *ports;
1323 struct bcm_sf2_priv *priv;
1324 struct b53_device *dev;
1325 struct dsa_switch *ds;
1326 void __iomem **base;
1327 unsigned int i;
1328 u32 reg, rev;
1329 int ret;
1330
1331 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1332 if (!priv)
1333 return -ENOMEM;
1334
1335 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL);
1336 if (!ops)
1337 return -ENOMEM;
1338
1339 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv);
1340 if (!dev)
1341 return -ENOMEM;
1342
1343 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1344 if (!pdata)
1345 return -ENOMEM;
1346
1347 of_id = of_match_node(bcm_sf2_of_match, dn);
1348 if (!of_id || !of_id->data)
1349 return -EINVAL;
1350
1351 data = of_id->data;
1352
1353 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */
1354 priv->type = data->type;
1355 priv->reg_offsets = data->reg_offsets;
1356 priv->core_reg_align = data->core_reg_align;
1357 priv->num_cfp_rules = data->num_cfp_rules;
1358 priv->num_crossbar_int_ports = data->num_crossbar_int_ports;
1359
1360 priv->rcdev = devm_reset_control_get_optional_exclusive(&pdev->dev,
1361 "switch");
1362 if (IS_ERR(priv->rcdev))
1363 return PTR_ERR(priv->rcdev);
1364
1365 /* Auto-detection using standard registers will not work, so
1366 * provide an indication of what kind of device we are for
1367 * b53_common to work with
1368 */
1369 pdata->chip_id = priv->type;
1370 dev->pdata = pdata;
1371
1372 priv->dev = dev;
1373 ds = dev->ds;
1374 ds->ops = &bcm_sf2_ops;
1375
1376 /* Advertise the 8 egress queues */
1377 ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES;
1378
1379 dev_set_drvdata(&pdev->dev, priv);
1380
1381 spin_lock_init(&priv->indir_lock);
1382 mutex_init(&priv->cfp.lock);
1383 INIT_LIST_HEAD(&priv->cfp.rules_list);
1384
1385 /* CFP rule #0 cannot be used for specific classifications, flag it as
1386 * permanently used
1387 */
1388 set_bit(0, priv->cfp.used);
1389 set_bit(0, priv->cfp.unique);
1390
1391 /* Balance of_node_put() done by of_find_node_by_name() */
1392 of_node_get(dn);
1393 ports = of_find_node_by_name(dn, "ports");
1394 if (ports) {
1395 bcm_sf2_identify_ports(priv, ports);
1396 of_node_put(ports);
1397 }
1398
1399 priv->irq0 = irq_of_parse_and_map(dn, 0);
1400 priv->irq1 = irq_of_parse_and_map(dn, 1);
1401
1402 base = &priv->core;
1403 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
1404 *base = devm_platform_ioremap_resource(pdev, i);
1405 if (IS_ERR(*base)) {
1406 pr_err("unable to find register: %s\n", reg_names[i]);
1407 return PTR_ERR(*base);
1408 }
1409 base++;
1410 }
1411
1412 priv->clk = devm_clk_get_optional(&pdev->dev, "sw_switch");
1413 if (IS_ERR(priv->clk))
1414 return PTR_ERR(priv->clk);
1415
1416 clk_prepare_enable(priv->clk);
1417
1418 priv->clk_mdiv = devm_clk_get_optional(&pdev->dev, "sw_switch_mdiv");
1419 if (IS_ERR(priv->clk_mdiv)) {
1420 ret = PTR_ERR(priv->clk_mdiv);
1421 goto out_clk;
1422 }
1423
1424 clk_prepare_enable(priv->clk_mdiv);
1425
1426 ret = bcm_sf2_sw_rst(priv);
1427 if (ret) {
1428 pr_err("unable to software reset switch: %d\n", ret);
1429 goto out_clk_mdiv;
1430 }
1431
1432 bcm_sf2_crossbar_setup(priv);
1433
1434 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1435
1436 ret = bcm_sf2_mdio_register(ds);
1437 if (ret) {
1438 pr_err("failed to register MDIO bus\n");
1439 goto out_clk_mdiv;
1440 }
1441
1442 bcm_sf2_gphy_enable_set(priv->dev->ds, false);
1443
1444 ret = bcm_sf2_cfp_rst(priv);
1445 if (ret) {
1446 pr_err("failed to reset CFP\n");
1447 goto out_mdio;
1448 }
1449
1450 /* Disable all interrupts and request them */
1451 bcm_sf2_intr_disable(priv);
1452
1453 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0,
1454 "switch_0", ds);
1455 if (ret < 0) {
1456 pr_err("failed to request switch_0 IRQ\n");
1457 goto out_mdio;
1458 }
1459
1460 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0,
1461 "switch_1", ds);
1462 if (ret < 0) {
1463 pr_err("failed to request switch_1 IRQ\n");
1464 goto out_mdio;
1465 }
1466
1467 /* Reset the MIB counters */
1468 reg = core_readl(priv, CORE_GMNCFGCFG);
1469 reg |= RST_MIB_CNT;
1470 core_writel(priv, reg, CORE_GMNCFGCFG);
1471 reg &= ~RST_MIB_CNT;
1472 core_writel(priv, reg, CORE_GMNCFGCFG);
1473
1474 /* Get the maximum number of ports for this switch */
1475 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
1476 if (priv->hw_params.num_ports > DSA_MAX_PORTS)
1477 priv->hw_params.num_ports = DSA_MAX_PORTS;
1478
1479 /* Assume a single GPHY setup if we can't read that property */
1480 if (of_property_read_u32(dn, "brcm,num-gphy",
1481 &priv->hw_params.num_gphy))
1482 priv->hw_params.num_gphy = 1;
1483
1484 rev = reg_readl(priv, REG_SWITCH_REVISION);
1485 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
1486 SWITCH_TOP_REV_MASK;
1487 priv->hw_params.core_rev = (rev & SF2_REV_MASK);
1488
1489 rev = reg_readl(priv, REG_PHY_REVISION);
1490 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
1491
1492 ret = b53_switch_register(dev);
1493 if (ret)
1494 goto out_mdio;
1495
1496 dev_info(&pdev->dev,
1497 "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n",
1498 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
1499 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
1500 priv->irq0, priv->irq1);
1501
1502 return 0;
1503
1504 out_mdio:
1505 bcm_sf2_mdio_unregister(priv);
1506 out_clk_mdiv:
1507 clk_disable_unprepare(priv->clk_mdiv);
1508 out_clk:
1509 clk_disable_unprepare(priv->clk);
1510 return ret;
1511 }
1512
bcm_sf2_sw_remove(struct platform_device * pdev)1513 static int bcm_sf2_sw_remove(struct platform_device *pdev)
1514 {
1515 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1516
1517 priv->wol_ports_mask = 0;
1518 /* Disable interrupts */
1519 bcm_sf2_intr_disable(priv);
1520 dsa_unregister_switch(priv->dev->ds);
1521 bcm_sf2_cfp_exit(priv->dev->ds);
1522 bcm_sf2_mdio_unregister(priv);
1523 clk_disable_unprepare(priv->clk_mdiv);
1524 clk_disable_unprepare(priv->clk);
1525 if (priv->type == BCM7278_DEVICE_ID)
1526 reset_control_assert(priv->rcdev);
1527
1528 return 0;
1529 }
1530
bcm_sf2_sw_shutdown(struct platform_device * pdev)1531 static void bcm_sf2_sw_shutdown(struct platform_device *pdev)
1532 {
1533 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1534
1535 /* For a kernel about to be kexec'd we want to keep the GPHY on for a
1536 * successful MDIO bus scan to occur. If we did turn off the GPHY
1537 * before (e.g: port_disable), this will also power it back on.
1538 *
1539 * Do not rely on kexec_in_progress, just power the PHY on.
1540 */
1541 if (priv->hw_params.num_gphy == 1)
1542 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1543 }
1544
1545 #ifdef CONFIG_PM_SLEEP
bcm_sf2_suspend(struct device * dev)1546 static int bcm_sf2_suspend(struct device *dev)
1547 {
1548 struct bcm_sf2_priv *priv = dev_get_drvdata(dev);
1549
1550 return dsa_switch_suspend(priv->dev->ds);
1551 }
1552
bcm_sf2_resume(struct device * dev)1553 static int bcm_sf2_resume(struct device *dev)
1554 {
1555 struct bcm_sf2_priv *priv = dev_get_drvdata(dev);
1556
1557 return dsa_switch_resume(priv->dev->ds);
1558 }
1559 #endif /* CONFIG_PM_SLEEP */
1560
1561 static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops,
1562 bcm_sf2_suspend, bcm_sf2_resume);
1563
1564
1565 static struct platform_driver bcm_sf2_driver = {
1566 .probe = bcm_sf2_sw_probe,
1567 .remove = bcm_sf2_sw_remove,
1568 .shutdown = bcm_sf2_sw_shutdown,
1569 .driver = {
1570 .name = "brcm-sf2",
1571 .of_match_table = bcm_sf2_of_match,
1572 .pm = &bcm_sf2_pm_ops,
1573 },
1574 };
1575 module_platform_driver(bcm_sf2_driver);
1576
1577 MODULE_AUTHOR("Broadcom Corporation");
1578 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
1579 MODULE_LICENSE("GPL");
1580 MODULE_ALIAS("platform:brcm-sf2");
1581