1 /*
2 * Copyright (c) 2018 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34 #ifndef __MLX5_FPGA_TLS_H__
35 #define __MLX5_FPGA_TLS_H__
36
37 #include <linux/mlx5/driver.h>
38
39 #include <net/tls.h>
40 #include "fpga/core.h"
41
42 struct mlx5_fpga_tls {
43 struct list_head pending_cmds;
44 spinlock_t pending_cmds_lock; /* Protects pending_cmds */
45 u32 caps;
46 struct mlx5_fpga_conn *conn;
47
48 struct idr tx_idr;
49 struct idr rx_idr;
50 spinlock_t tx_idr_spinlock; /* protects the IDR */
51 spinlock_t rx_idr_spinlock; /* protects the IDR */
52 };
53
54 int mlx5_fpga_tls_add_flow(struct mlx5_core_dev *mdev, void *flow,
55 struct tls_crypto_info *crypto_info,
56 u32 start_offload_tcp_sn, u32 *p_swid,
57 bool direction_sx);
58
59 void mlx5_fpga_tls_del_flow(struct mlx5_core_dev *mdev, u32 swid,
60 gfp_t flags, bool direction_sx);
61
62 bool mlx5_fpga_is_tls_device(struct mlx5_core_dev *mdev);
63 int mlx5_fpga_tls_init(struct mlx5_core_dev *mdev);
64 void mlx5_fpga_tls_cleanup(struct mlx5_core_dev *mdev);
65
mlx5_fpga_tls_device_caps(struct mlx5_core_dev * mdev)66 static inline u32 mlx5_fpga_tls_device_caps(struct mlx5_core_dev *mdev)
67 {
68 return mdev->fpga->tls->caps;
69 }
70
71 int mlx5_fpga_tls_resync_rx(struct mlx5_core_dev *mdev, __be32 handle,
72 u32 seq, __be64 rcd_sn);
73
74 #endif /* __MLX5_FPGA_TLS_H__ */
75